mpc8568mds.dts 11 KB

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  1. /*
  2. * MPC8568E MDS Device Tree Source
  3. *
  4. * Copyright 2007 Freescale Semiconductor Inc.
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License as published by the
  8. * Free Software Foundation; either version 2 of the License, or (at your
  9. * option) any later version.
  10. */
  11. /*
  12. /memreserve/ 00000000 1000000;
  13. */
  14. / {
  15. model = "MPC8568EMDS";
  16. compatible = "MPC8568EMDS", "MPC85xxMDS";
  17. #address-cells = <1>;
  18. #size-cells = <1>;
  19. cpus {
  20. #address-cells = <1>;
  21. #size-cells = <0>;
  22. PowerPC,8568@0 {
  23. device_type = "cpu";
  24. reg = <0>;
  25. d-cache-line-size = <20>; // 32 bytes
  26. i-cache-line-size = <20>; // 32 bytes
  27. d-cache-size = <8000>; // L1, 32K
  28. i-cache-size = <8000>; // L1, 32K
  29. timebase-frequency = <0>;
  30. bus-frequency = <0>;
  31. clock-frequency = <0>;
  32. };
  33. };
  34. memory {
  35. device_type = "memory";
  36. reg = <00000000 10000000>;
  37. };
  38. bcsr@f8000000 {
  39. device_type = "board-control";
  40. reg = <f8000000 8000>;
  41. };
  42. soc8568@e0000000 {
  43. #address-cells = <1>;
  44. #size-cells = <1>;
  45. device_type = "soc";
  46. ranges = <0 e0000000 00100000>;
  47. reg = <e0000000 00001000>;
  48. bus-frequency = <0>;
  49. memory-controller@2000 {
  50. compatible = "fsl,8568-memory-controller";
  51. reg = <2000 1000>;
  52. interrupt-parent = <&mpic>;
  53. interrupts = <12 2>;
  54. };
  55. l2-cache-controller@20000 {
  56. compatible = "fsl,8568-l2-cache-controller";
  57. reg = <20000 1000>;
  58. cache-line-size = <20>; // 32 bytes
  59. cache-size = <80000>; // L2, 512K
  60. interrupt-parent = <&mpic>;
  61. interrupts = <10 2>;
  62. };
  63. i2c@3000 {
  64. #address-cells = <1>;
  65. #size-cells = <0>;
  66. device_type = "i2c";
  67. compatible = "fsl-i2c";
  68. reg = <3000 100>;
  69. interrupts = <2b 2>;
  70. interrupt-parent = <&mpic>;
  71. dfsrr;
  72. rtc@68 {
  73. compatible = "dallas,ds1374";
  74. reg = <68>;
  75. };
  76. };
  77. i2c@3100 {
  78. #address-cells = <1>;
  79. #size-cells = <0>;
  80. device_type = "i2c";
  81. compatible = "fsl-i2c";
  82. reg = <3100 100>;
  83. interrupts = <2b 2>;
  84. interrupt-parent = <&mpic>;
  85. dfsrr;
  86. };
  87. mdio@24520 {
  88. #address-cells = <1>;
  89. #size-cells = <0>;
  90. device_type = "mdio";
  91. compatible = "gianfar";
  92. reg = <24520 20>;
  93. phy0: ethernet-phy@7 {
  94. interrupt-parent = <&mpic>;
  95. interrupts = <1 1>;
  96. reg = <7>;
  97. device_type = "ethernet-phy";
  98. };
  99. phy1: ethernet-phy@1 {
  100. interrupt-parent = <&mpic>;
  101. interrupts = <2 1>;
  102. reg = <1>;
  103. device_type = "ethernet-phy";
  104. };
  105. phy2: ethernet-phy@2 {
  106. interrupt-parent = <&mpic>;
  107. interrupts = <1 1>;
  108. reg = <2>;
  109. device_type = "ethernet-phy";
  110. };
  111. phy3: ethernet-phy@3 {
  112. interrupt-parent = <&mpic>;
  113. interrupts = <2 1>;
  114. reg = <3>;
  115. device_type = "ethernet-phy";
  116. };
  117. };
  118. ethernet@24000 {
  119. #address-cells = <1>;
  120. #size-cells = <0>;
  121. device_type = "network";
  122. model = "eTSEC";
  123. compatible = "gianfar";
  124. reg = <24000 1000>;
  125. /*
  126. * mac-address is deprecated and will be removed
  127. * in 2.6.25. Only recent versions of
  128. * U-Boot support local-mac-address, however.
  129. */
  130. mac-address = [ 00 00 00 00 00 00 ];
  131. local-mac-address = [ 00 00 00 00 00 00 ];
  132. interrupts = <1d 2 1e 2 22 2>;
  133. interrupt-parent = <&mpic>;
  134. phy-handle = <&phy2>;
  135. };
  136. ethernet@25000 {
  137. #address-cells = <1>;
  138. #size-cells = <0>;
  139. device_type = "network";
  140. model = "eTSEC";
  141. compatible = "gianfar";
  142. reg = <25000 1000>;
  143. /*
  144. * mac-address is deprecated and will be removed
  145. * in 2.6.25. Only recent versions of
  146. * U-Boot support local-mac-address, however.
  147. */
  148. mac-address = [ 00 00 00 00 00 00 ];
  149. local-mac-address = [ 00 00 00 00 00 00 ];
  150. interrupts = <23 2 24 2 28 2>;
  151. interrupt-parent = <&mpic>;
  152. phy-handle = <&phy3>;
  153. };
  154. serial@4500 {
  155. device_type = "serial";
  156. compatible = "ns16550";
  157. reg = <4500 100>;
  158. clock-frequency = <0>;
  159. interrupts = <2a 2>;
  160. interrupt-parent = <&mpic>;
  161. };
  162. global-utilities@e0000 { //global utilities block
  163. compatible = "fsl,mpc8548-guts";
  164. reg = <e0000 1000>;
  165. fsl,has-rstcr;
  166. };
  167. serial@4600 {
  168. device_type = "serial";
  169. compatible = "ns16550";
  170. reg = <4600 100>;
  171. clock-frequency = <0>;
  172. interrupts = <2a 2>;
  173. interrupt-parent = <&mpic>;
  174. };
  175. crypto@30000 {
  176. device_type = "crypto";
  177. model = "SEC2";
  178. compatible = "talitos";
  179. reg = <30000 f000>;
  180. interrupts = <2d 2>;
  181. interrupt-parent = <&mpic>;
  182. num-channels = <4>;
  183. channel-fifo-len = <18>;
  184. exec-units-mask = <000000fe>;
  185. descriptor-types-mask = <012b0ebf>;
  186. };
  187. mpic: pic@40000 {
  188. clock-frequency = <0>;
  189. interrupt-controller;
  190. #address-cells = <0>;
  191. #interrupt-cells = <2>;
  192. reg = <40000 40000>;
  193. compatible = "chrp,open-pic";
  194. device_type = "open-pic";
  195. big-endian;
  196. };
  197. par_io@e0100 {
  198. reg = <e0100 100>;
  199. device_type = "par_io";
  200. num-ports = <7>;
  201. pio1: ucc_pin@01 {
  202. pio-map = <
  203. /* port pin dir open_drain assignment has_irq */
  204. 4 0a 1 0 2 0 /* TxD0 */
  205. 4 09 1 0 2 0 /* TxD1 */
  206. 4 08 1 0 2 0 /* TxD2 */
  207. 4 07 1 0 2 0 /* TxD3 */
  208. 4 17 1 0 2 0 /* TxD4 */
  209. 4 16 1 0 2 0 /* TxD5 */
  210. 4 15 1 0 2 0 /* TxD6 */
  211. 4 14 1 0 2 0 /* TxD7 */
  212. 4 0f 2 0 2 0 /* RxD0 */
  213. 4 0e 2 0 2 0 /* RxD1 */
  214. 4 0d 2 0 2 0 /* RxD2 */
  215. 4 0c 2 0 2 0 /* RxD3 */
  216. 4 1d 2 0 2 0 /* RxD4 */
  217. 4 1c 2 0 2 0 /* RxD5 */
  218. 4 1b 2 0 2 0 /* RxD6 */
  219. 4 1a 2 0 2 0 /* RxD7 */
  220. 4 0b 1 0 2 0 /* TX_EN */
  221. 4 18 1 0 2 0 /* TX_ER */
  222. 4 10 2 0 2 0 /* RX_DV */
  223. 4 1e 2 0 2 0 /* RX_ER */
  224. 4 11 2 0 2 0 /* RX_CLK */
  225. 4 13 1 0 2 0 /* GTX_CLK */
  226. 1 1f 2 0 3 0>; /* GTX125 */
  227. };
  228. pio2: ucc_pin@02 {
  229. pio-map = <
  230. /* port pin dir open_drain assignment has_irq */
  231. 5 0a 1 0 2 0 /* TxD0 */
  232. 5 09 1 0 2 0 /* TxD1 */
  233. 5 08 1 0 2 0 /* TxD2 */
  234. 5 07 1 0 2 0 /* TxD3 */
  235. 5 17 1 0 2 0 /* TxD4 */
  236. 5 16 1 0 2 0 /* TxD5 */
  237. 5 15 1 0 2 0 /* TxD6 */
  238. 5 14 1 0 2 0 /* TxD7 */
  239. 5 0f 2 0 2 0 /* RxD0 */
  240. 5 0e 2 0 2 0 /* RxD1 */
  241. 5 0d 2 0 2 0 /* RxD2 */
  242. 5 0c 2 0 2 0 /* RxD3 */
  243. 5 1d 2 0 2 0 /* RxD4 */
  244. 5 1c 2 0 2 0 /* RxD5 */
  245. 5 1b 2 0 2 0 /* RxD6 */
  246. 5 1a 2 0 2 0 /* RxD7 */
  247. 5 0b 1 0 2 0 /* TX_EN */
  248. 5 18 1 0 2 0 /* TX_ER */
  249. 5 10 2 0 2 0 /* RX_DV */
  250. 5 1e 2 0 2 0 /* RX_ER */
  251. 5 11 2 0 2 0 /* RX_CLK */
  252. 5 13 1 0 2 0 /* GTX_CLK */
  253. 1 1f 2 0 3 0 /* GTX125 */
  254. 4 06 3 0 2 0 /* MDIO */
  255. 4 05 1 0 2 0>; /* MDC */
  256. };
  257. };
  258. };
  259. qe@e0080000 {
  260. #address-cells = <1>;
  261. #size-cells = <1>;
  262. device_type = "qe";
  263. model = "QE";
  264. ranges = <0 e0080000 00040000>;
  265. reg = <e0080000 480>;
  266. brg-frequency = <0>;
  267. bus-frequency = <179A7B00>;
  268. muram@10000 {
  269. device_type = "muram";
  270. ranges = <0 00010000 0000c000>;
  271. data-only@0{
  272. reg = <0 c000>;
  273. };
  274. };
  275. spi@4c0 {
  276. device_type = "spi";
  277. compatible = "fsl_spi";
  278. reg = <4c0 40>;
  279. interrupts = <2>;
  280. interrupt-parent = <&qeic>;
  281. mode = "cpu";
  282. };
  283. spi@500 {
  284. device_type = "spi";
  285. compatible = "fsl_spi";
  286. reg = <500 40>;
  287. interrupts = <1>;
  288. interrupt-parent = <&qeic>;
  289. mode = "cpu";
  290. };
  291. ucc@2000 {
  292. device_type = "network";
  293. compatible = "ucc_geth";
  294. model = "UCC";
  295. device-id = <1>;
  296. reg = <2000 200>;
  297. interrupts = <20>;
  298. interrupt-parent = <&qeic>;
  299. /*
  300. * mac-address is deprecated and will be removed
  301. * in 2.6.25. Only recent versions of
  302. * U-Boot support local-mac-address, however.
  303. */
  304. mac-address = [ 00 00 00 00 00 00 ];
  305. local-mac-address = [ 00 00 00 00 00 00 ];
  306. rx-clock = <0>;
  307. tx-clock = <20>;
  308. pio-handle = <&pio1>;
  309. phy-handle = <&phy0>;
  310. phy-connection-type = "rgmii-id";
  311. };
  312. ucc@3000 {
  313. device_type = "network";
  314. compatible = "ucc_geth";
  315. model = "UCC";
  316. device-id = <2>;
  317. reg = <3000 200>;
  318. interrupts = <21>;
  319. interrupt-parent = <&qeic>;
  320. /*
  321. * mac-address is deprecated and will be removed
  322. * in 2.6.25. Only recent versions of
  323. * U-Boot support local-mac-address, however.
  324. */
  325. mac-address = [ 00 00 00 00 00 00 ];
  326. local-mac-address = [ 00 00 00 00 00 00 ];
  327. rx-clock = <0>;
  328. tx-clock = <20>;
  329. pio-handle = <&pio2>;
  330. phy-handle = <&phy1>;
  331. phy-connection-type = "rgmii-id";
  332. };
  333. mdio@2120 {
  334. #address-cells = <1>;
  335. #size-cells = <0>;
  336. reg = <2120 18>;
  337. device_type = "mdio";
  338. compatible = "ucc_geth_phy";
  339. /* These are the same PHYs as on
  340. * gianfar's MDIO bus */
  341. qe_phy0: ethernet-phy@07 {
  342. interrupt-parent = <&mpic>;
  343. interrupts = <1 1>;
  344. reg = <7>;
  345. device_type = "ethernet-phy";
  346. };
  347. qe_phy1: ethernet-phy@01 {
  348. interrupt-parent = <&mpic>;
  349. interrupts = <2 1>;
  350. reg = <1>;
  351. device_type = "ethernet-phy";
  352. };
  353. qe_phy2: ethernet-phy@02 {
  354. interrupt-parent = <&mpic>;
  355. interrupts = <1 1>;
  356. reg = <2>;
  357. device_type = "ethernet-phy";
  358. };
  359. qe_phy3: ethernet-phy@03 {
  360. interrupt-parent = <&mpic>;
  361. interrupts = <2 1>;
  362. reg = <3>;
  363. device_type = "ethernet-phy";
  364. };
  365. };
  366. qeic: qeic@80 {
  367. interrupt-controller;
  368. device_type = "qeic";
  369. #address-cells = <0>;
  370. #interrupt-cells = <1>;
  371. reg = <80 80>;
  372. big-endian;
  373. interrupts = <2e 2 2e 2>; //high:30 low:30
  374. interrupt-parent = <&mpic>;
  375. };
  376. };
  377. pci@e0008000 {
  378. interrupt-map-mask = <f800 0 0 7>;
  379. interrupt-map = <
  380. /* IDSEL 0x12 AD18 */
  381. 9000 0 0 1 &mpic 5 1
  382. 9000 0 0 2 &mpic 6 1
  383. 9000 0 0 3 &mpic 7 1
  384. 9000 0 0 4 &mpic 4 1
  385. /* IDSEL 0x13 AD19 */
  386. 9800 0 0 1 &mpic 6 1
  387. 9800 0 0 2 &mpic 7 1
  388. 9800 0 0 3 &mpic 4 1
  389. 9800 0 0 4 &mpic 5 1>;
  390. interrupt-parent = <&mpic>;
  391. interrupts = <18 2>;
  392. bus-range = <0 ff>;
  393. ranges = <02000000 0 80000000 80000000 0 20000000
  394. 01000000 0 00000000 e2000000 0 00800000>;
  395. clock-frequency = <3f940aa>;
  396. #interrupt-cells = <1>;
  397. #size-cells = <2>;
  398. #address-cells = <3>;
  399. reg = <e0008000 1000>;
  400. compatible = "fsl,mpc8540-pci";
  401. device_type = "pci";
  402. };
  403. /* PCI Express */
  404. pcie@e000a000 {
  405. interrupt-map-mask = <f800 0 0 7>;
  406. interrupt-map = <
  407. /* IDSEL 0x0 (PEX) */
  408. 00000 0 0 1 &mpic 0 1
  409. 00000 0 0 2 &mpic 1 1
  410. 00000 0 0 3 &mpic 2 1
  411. 00000 0 0 4 &mpic 3 1>;
  412. interrupt-parent = <&mpic>;
  413. interrupts = <1a 2>;
  414. bus-range = <0 ff>;
  415. ranges = <02000000 0 a0000000 a0000000 0 10000000
  416. 01000000 0 00000000 e2800000 0 00800000>;
  417. clock-frequency = <1fca055>;
  418. #interrupt-cells = <1>;
  419. #size-cells = <2>;
  420. #address-cells = <3>;
  421. reg = <e000a000 1000>;
  422. compatible = "fsl,mpc8548-pcie";
  423. device_type = "pci";
  424. pcie@0 {
  425. reg = <0 0 0 0 0>;
  426. #size-cells = <2>;
  427. #address-cells = <3>;
  428. device_type = "pci";
  429. ranges = <02000000 0 a0000000
  430. 02000000 0 a0000000
  431. 0 10000000
  432. 01000000 0 00000000
  433. 01000000 0 00000000
  434. 0 00800000>;
  435. };
  436. };
  437. };