mpc8540ads.dts 6.1 KB

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  1. /*
  2. * MPC8540 ADS Device Tree Source
  3. *
  4. * Copyright 2006 Freescale Semiconductor Inc.
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License as published by the
  8. * Free Software Foundation; either version 2 of the License, or (at your
  9. * option) any later version.
  10. */
  11. / {
  12. model = "MPC8540ADS";
  13. compatible = "MPC8540ADS", "MPC85xxADS";
  14. #address-cells = <1>;
  15. #size-cells = <1>;
  16. cpus {
  17. #address-cells = <1>;
  18. #size-cells = <0>;
  19. PowerPC,8540@0 {
  20. device_type = "cpu";
  21. reg = <0>;
  22. d-cache-line-size = <20>; // 32 bytes
  23. i-cache-line-size = <20>; // 32 bytes
  24. d-cache-size = <8000>; // L1, 32K
  25. i-cache-size = <8000>; // L1, 32K
  26. timebase-frequency = <0>; // 33 MHz, from uboot
  27. bus-frequency = <0>; // 166 MHz
  28. clock-frequency = <0>; // 825 MHz, from uboot
  29. };
  30. };
  31. memory {
  32. device_type = "memory";
  33. reg = <00000000 08000000>; // 128M at 0x0
  34. };
  35. soc8540@e0000000 {
  36. #address-cells = <1>;
  37. #size-cells = <1>;
  38. device_type = "soc";
  39. ranges = <0 e0000000 00100000>;
  40. reg = <e0000000 00100000>; // CCSRBAR 1M
  41. bus-frequency = <0>;
  42. memory-controller@2000 {
  43. compatible = "fsl,8540-memory-controller";
  44. reg = <2000 1000>;
  45. interrupt-parent = <&mpic>;
  46. interrupts = <12 2>;
  47. };
  48. l2-cache-controller@20000 {
  49. compatible = "fsl,8540-l2-cache-controller";
  50. reg = <20000 1000>;
  51. cache-line-size = <20>; // 32 bytes
  52. cache-size = <40000>; // L2, 256K
  53. interrupt-parent = <&mpic>;
  54. interrupts = <10 2>;
  55. };
  56. i2c@3000 {
  57. device_type = "i2c";
  58. compatible = "fsl-i2c";
  59. reg = <3000 100>;
  60. interrupts = <2b 2>;
  61. interrupt-parent = <&mpic>;
  62. dfsrr;
  63. };
  64. mdio@24520 {
  65. #address-cells = <1>;
  66. #size-cells = <0>;
  67. device_type = "mdio";
  68. compatible = "gianfar";
  69. reg = <24520 20>;
  70. phy0: ethernet-phy@0 {
  71. interrupt-parent = <&mpic>;
  72. interrupts = <5 1>;
  73. reg = <0>;
  74. device_type = "ethernet-phy";
  75. };
  76. phy1: ethernet-phy@1 {
  77. interrupt-parent = <&mpic>;
  78. interrupts = <5 1>;
  79. reg = <1>;
  80. device_type = "ethernet-phy";
  81. };
  82. phy3: ethernet-phy@3 {
  83. interrupt-parent = <&mpic>;
  84. interrupts = <7 1>;
  85. reg = <3>;
  86. device_type = "ethernet-phy";
  87. };
  88. };
  89. ethernet@24000 {
  90. #address-cells = <1>;
  91. #size-cells = <0>;
  92. device_type = "network";
  93. model = "TSEC";
  94. compatible = "gianfar";
  95. reg = <24000 1000>;
  96. /*
  97. * address is deprecated and will be removed
  98. * in 2.6.25. Only recent versions of
  99. * U-Boot support local-mac-address, however.
  100. */
  101. address = [ 00 00 00 00 00 00 ];
  102. local-mac-address = [ 00 00 00 00 00 00 ];
  103. interrupts = <1d 2 1e 2 22 2>;
  104. interrupt-parent = <&mpic>;
  105. phy-handle = <&phy0>;
  106. };
  107. ethernet@25000 {
  108. #address-cells = <1>;
  109. #size-cells = <0>;
  110. device_type = "network";
  111. model = "TSEC";
  112. compatible = "gianfar";
  113. reg = <25000 1000>;
  114. /*
  115. * address is deprecated and will be removed
  116. * in 2.6.25. Only recent versions of
  117. * U-Boot support local-mac-address, however.
  118. */
  119. address = [ 00 00 00 00 00 00 ];
  120. local-mac-address = [ 00 00 00 00 00 00 ];
  121. interrupts = <23 2 24 2 28 2>;
  122. interrupt-parent = <&mpic>;
  123. phy-handle = <&phy1>;
  124. };
  125. ethernet@26000 {
  126. #address-cells = <1>;
  127. #size-cells = <0>;
  128. device_type = "network";
  129. model = "FEC";
  130. compatible = "gianfar";
  131. reg = <26000 1000>;
  132. /*
  133. * address is deprecated and will be removed
  134. * in 2.6.25. Only recent versions of
  135. * U-Boot support local-mac-address, however.
  136. */
  137. address = [ 00 00 00 00 00 00 ];
  138. local-mac-address = [ 00 00 00 00 00 00 ];
  139. interrupts = <29 2>;
  140. interrupt-parent = <&mpic>;
  141. phy-handle = <&phy3>;
  142. };
  143. serial@4500 {
  144. device_type = "serial";
  145. compatible = "ns16550";
  146. reg = <4500 100>; // reg base, size
  147. clock-frequency = <0>; // should we fill in in uboot?
  148. interrupts = <2a 2>;
  149. interrupt-parent = <&mpic>;
  150. };
  151. serial@4600 {
  152. device_type = "serial";
  153. compatible = "ns16550";
  154. reg = <4600 100>; // reg base, size
  155. clock-frequency = <0>; // should we fill in in uboot?
  156. interrupts = <2a 2>;
  157. interrupt-parent = <&mpic>;
  158. };
  159. mpic: pic@40000 {
  160. clock-frequency = <0>;
  161. interrupt-controller;
  162. #address-cells = <0>;
  163. #interrupt-cells = <2>;
  164. reg = <40000 40000>;
  165. compatible = "chrp,open-pic";
  166. device_type = "open-pic";
  167. big-endian;
  168. };
  169. };
  170. pci@e0008000 {
  171. interrupt-map-mask = <f800 0 0 7>;
  172. interrupt-map = <
  173. /* IDSEL 0x02 */
  174. 1000 0 0 1 &mpic 1 1
  175. 1000 0 0 2 &mpic 2 1
  176. 1000 0 0 3 &mpic 3 1
  177. 1000 0 0 4 &mpic 4 1
  178. /* IDSEL 0x03 */
  179. 1800 0 0 1 &mpic 4 1
  180. 1800 0 0 2 &mpic 1 1
  181. 1800 0 0 3 &mpic 2 1
  182. 1800 0 0 4 &mpic 3 1
  183. /* IDSEL 0x04 */
  184. 2000 0 0 1 &mpic 3 1
  185. 2000 0 0 2 &mpic 4 1
  186. 2000 0 0 3 &mpic 1 1
  187. 2000 0 0 4 &mpic 2 1
  188. /* IDSEL 0x05 */
  189. 2800 0 0 1 &mpic 2 1
  190. 2800 0 0 2 &mpic 3 1
  191. 2800 0 0 3 &mpic 4 1
  192. 2800 0 0 4 &mpic 1 1
  193. /* IDSEL 0x0c */
  194. 6000 0 0 1 &mpic 1 1
  195. 6000 0 0 2 &mpic 2 1
  196. 6000 0 0 3 &mpic 3 1
  197. 6000 0 0 4 &mpic 4 1
  198. /* IDSEL 0x0d */
  199. 6800 0 0 1 &mpic 4 1
  200. 6800 0 0 2 &mpic 1 1
  201. 6800 0 0 3 &mpic 2 1
  202. 6800 0 0 4 &mpic 3 1
  203. /* IDSEL 0x0e */
  204. 7000 0 0 1 &mpic 3 1
  205. 7000 0 0 2 &mpic 4 1
  206. 7000 0 0 3 &mpic 1 1
  207. 7000 0 0 4 &mpic 2 1
  208. /* IDSEL 0x0f */
  209. 7800 0 0 1 &mpic 2 1
  210. 7800 0 0 2 &mpic 3 1
  211. 7800 0 0 3 &mpic 4 1
  212. 7800 0 0 4 &mpic 1 1
  213. /* IDSEL 0x12 */
  214. 9000 0 0 1 &mpic 1 1
  215. 9000 0 0 2 &mpic 2 1
  216. 9000 0 0 3 &mpic 3 1
  217. 9000 0 0 4 &mpic 4 1
  218. /* IDSEL 0x13 */
  219. 9800 0 0 1 &mpic 4 1
  220. 9800 0 0 2 &mpic 1 1
  221. 9800 0 0 3 &mpic 2 1
  222. 9800 0 0 4 &mpic 3 1
  223. /* IDSEL 0x14 */
  224. a000 0 0 1 &mpic 3 1
  225. a000 0 0 2 &mpic 4 1
  226. a000 0 0 3 &mpic 1 1
  227. a000 0 0 4 &mpic 2 1
  228. /* IDSEL 0x15 */
  229. a800 0 0 1 &mpic 2 1
  230. a800 0 0 2 &mpic 3 1
  231. a800 0 0 3 &mpic 4 1
  232. a800 0 0 4 &mpic 1 1>;
  233. interrupt-parent = <&mpic>;
  234. interrupts = <18 2>;
  235. bus-range = <0 0>;
  236. ranges = <02000000 0 80000000 80000000 0 20000000
  237. 01000000 0 00000000 e2000000 0 00100000>;
  238. clock-frequency = <3f940aa>;
  239. #interrupt-cells = <1>;
  240. #size-cells = <2>;
  241. #address-cells = <3>;
  242. reg = <e0008000 1000>;
  243. compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
  244. device_type = "pci";
  245. };
  246. };