mpc836x_mds.dts 8.5 KB

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  1. /*
  2. * MPC8360E EMDS Device Tree Source
  3. *
  4. * Copyright 2006 Freescale Semiconductor Inc.
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License as published by the
  8. * Free Software Foundation; either version 2 of the License, or (at your
  9. * option) any later version.
  10. */
  11. /*
  12. /memreserve/ 00000000 1000000;
  13. */
  14. / {
  15. model = "MPC8360MDS";
  16. compatible = "MPC8360EMDS", "MPC836xMDS", "MPC83xxMDS";
  17. #address-cells = <1>;
  18. #size-cells = <1>;
  19. cpus {
  20. #address-cells = <1>;
  21. #size-cells = <0>;
  22. PowerPC,8360@0 {
  23. device_type = "cpu";
  24. reg = <0>;
  25. d-cache-line-size = <20>; // 32 bytes
  26. i-cache-line-size = <20>; // 32 bytes
  27. d-cache-size = <8000>; // L1, 32K
  28. i-cache-size = <8000>; // L1, 32K
  29. timebase-frequency = <3EF1480>;
  30. bus-frequency = <FBC5200>;
  31. clock-frequency = <1F78A400>;
  32. };
  33. };
  34. memory {
  35. device_type = "memory";
  36. reg = <00000000 10000000>;
  37. };
  38. bcsr@f8000000 {
  39. device_type = "board-control";
  40. reg = <f8000000 8000>;
  41. };
  42. soc8360@e0000000 {
  43. #address-cells = <1>;
  44. #size-cells = <1>;
  45. device_type = "soc";
  46. ranges = <0 e0000000 00100000>;
  47. reg = <e0000000 00000200>;
  48. bus-frequency = <FBC5200>;
  49. wdt@200 {
  50. device_type = "watchdog";
  51. compatible = "mpc83xx_wdt";
  52. reg = <200 100>;
  53. };
  54. i2c@3000 {
  55. #address-cells = <1>;
  56. #size-cells = <0>;
  57. device_type = "i2c";
  58. compatible = "fsl-i2c";
  59. reg = <3000 100>;
  60. interrupts = <e 8>;
  61. interrupt-parent = < &ipic >;
  62. dfsrr;
  63. rtc@68 {
  64. compatible = "dallas,ds1374";
  65. reg = <68>;
  66. };
  67. };
  68. i2c@3100 {
  69. #address-cells = <1>;
  70. #size-cells = <0>;
  71. device_type = "i2c";
  72. compatible = "fsl-i2c";
  73. reg = <3100 100>;
  74. interrupts = <f 8>;
  75. interrupt-parent = < &ipic >;
  76. dfsrr;
  77. };
  78. serial@4500 {
  79. device_type = "serial";
  80. compatible = "ns16550";
  81. reg = <4500 100>;
  82. clock-frequency = <FBC5200>;
  83. interrupts = <9 8>;
  84. interrupt-parent = < &ipic >;
  85. };
  86. serial@4600 {
  87. device_type = "serial";
  88. compatible = "ns16550";
  89. reg = <4600 100>;
  90. clock-frequency = <FBC5200>;
  91. interrupts = <a 8>;
  92. interrupt-parent = < &ipic >;
  93. };
  94. crypto@30000 {
  95. device_type = "crypto";
  96. model = "SEC2";
  97. compatible = "talitos";
  98. reg = <30000 10000>;
  99. interrupts = <b 8>;
  100. interrupt-parent = < &ipic >;
  101. num-channels = <4>;
  102. channel-fifo-len = <18>;
  103. exec-units-mask = <0000007e>;
  104. /* desc mask is for rev1.x, we need runtime fixup for >=2.x */
  105. descriptor-types-mask = <01010ebf>;
  106. };
  107. ipic: pic@700 {
  108. interrupt-controller;
  109. #address-cells = <0>;
  110. #interrupt-cells = <2>;
  111. reg = <700 100>;
  112. device_type = "ipic";
  113. };
  114. par_io@1400 {
  115. reg = <1400 100>;
  116. device_type = "par_io";
  117. num-ports = <7>;
  118. pio1: ucc_pin@01 {
  119. pio-map = <
  120. /* port pin dir open_drain assignment has_irq */
  121. 0 3 1 0 1 0 /* TxD0 */
  122. 0 4 1 0 1 0 /* TxD1 */
  123. 0 5 1 0 1 0 /* TxD2 */
  124. 0 6 1 0 1 0 /* TxD3 */
  125. 1 6 1 0 3 0 /* TxD4 */
  126. 1 7 1 0 1 0 /* TxD5 */
  127. 1 9 1 0 2 0 /* TxD6 */
  128. 1 a 1 0 2 0 /* TxD7 */
  129. 0 9 2 0 1 0 /* RxD0 */
  130. 0 a 2 0 1 0 /* RxD1 */
  131. 0 b 2 0 1 0 /* RxD2 */
  132. 0 c 2 0 1 0 /* RxD3 */
  133. 0 d 2 0 1 0 /* RxD4 */
  134. 1 1 2 0 2 0 /* RxD5 */
  135. 1 0 2 0 2 0 /* RxD6 */
  136. 1 4 2 0 2 0 /* RxD7 */
  137. 0 7 1 0 1 0 /* TX_EN */
  138. 0 8 1 0 1 0 /* TX_ER */
  139. 0 f 2 0 1 0 /* RX_DV */
  140. 0 10 2 0 1 0 /* RX_ER */
  141. 0 0 2 0 1 0 /* RX_CLK */
  142. 2 9 1 0 3 0 /* GTX_CLK - CLK10 */
  143. 2 8 2 0 1 0>; /* GTX125 - CLK9 */
  144. };
  145. pio2: ucc_pin@02 {
  146. pio-map = <
  147. /* port pin dir open_drain assignment has_irq */
  148. 0 11 1 0 1 0 /* TxD0 */
  149. 0 12 1 0 1 0 /* TxD1 */
  150. 0 13 1 0 1 0 /* TxD2 */
  151. 0 14 1 0 1 0 /* TxD3 */
  152. 1 2 1 0 1 0 /* TxD4 */
  153. 1 3 1 0 2 0 /* TxD5 */
  154. 1 5 1 0 3 0 /* TxD6 */
  155. 1 8 1 0 3 0 /* TxD7 */
  156. 0 17 2 0 1 0 /* RxD0 */
  157. 0 18 2 0 1 0 /* RxD1 */
  158. 0 19 2 0 1 0 /* RxD2 */
  159. 0 1a 2 0 1 0 /* RxD3 */
  160. 0 1b 2 0 1 0 /* RxD4 */
  161. 1 c 2 0 2 0 /* RxD5 */
  162. 1 d 2 0 3 0 /* RxD6 */
  163. 1 b 2 0 2 0 /* RxD7 */
  164. 0 15 1 0 1 0 /* TX_EN */
  165. 0 16 1 0 1 0 /* TX_ER */
  166. 0 1d 2 0 1 0 /* RX_DV */
  167. 0 1e 2 0 1 0 /* RX_ER */
  168. 0 1f 2 0 1 0 /* RX_CLK */
  169. 2 2 1 0 2 0 /* GTX_CLK - CLK10 */
  170. 2 3 2 0 1 0 /* GTX125 - CLK4 */
  171. 0 1 3 0 2 0 /* MDIO */
  172. 0 2 1 0 1 0>; /* MDC */
  173. };
  174. };
  175. };
  176. qe@e0100000 {
  177. #address-cells = <1>;
  178. #size-cells = <1>;
  179. device_type = "qe";
  180. model = "QE";
  181. ranges = <0 e0100000 00100000>;
  182. reg = <e0100000 480>;
  183. brg-frequency = <0>;
  184. bus-frequency = <179A7B00>;
  185. muram@10000 {
  186. device_type = "muram";
  187. ranges = <0 00010000 0000c000>;
  188. data-only@0{
  189. reg = <0 c000>;
  190. };
  191. };
  192. spi@4c0 {
  193. device_type = "spi";
  194. compatible = "fsl_spi";
  195. reg = <4c0 40>;
  196. interrupts = <2>;
  197. interrupt-parent = < &qeic >;
  198. mode = "cpu";
  199. };
  200. spi@500 {
  201. device_type = "spi";
  202. compatible = "fsl_spi";
  203. reg = <500 40>;
  204. interrupts = <1>;
  205. interrupt-parent = < &qeic >;
  206. mode = "cpu";
  207. };
  208. usb@6c0 {
  209. device_type = "usb";
  210. compatible = "qe_udc";
  211. reg = <6c0 40 8B00 100>;
  212. interrupts = <b>;
  213. interrupt-parent = < &qeic >;
  214. mode = "slave";
  215. };
  216. ucc@2000 {
  217. device_type = "network";
  218. compatible = "ucc_geth";
  219. model = "UCC";
  220. device-id = <1>;
  221. reg = <2000 200>;
  222. interrupts = <20>;
  223. interrupt-parent = < &qeic >;
  224. /*
  225. * mac-address is deprecated and will be removed
  226. * in 2.6.25. Only recent versions of
  227. * U-Boot support local-mac-address, however.
  228. */
  229. mac-address = [ 00 00 00 00 00 00 ];
  230. local-mac-address = [ 00 00 00 00 00 00 ];
  231. rx-clock = <0>;
  232. tx-clock = <19>;
  233. phy-handle = < &phy0 >;
  234. phy-connection-type = "rgmii-id";
  235. pio-handle = < &pio1 >;
  236. };
  237. ucc@3000 {
  238. device_type = "network";
  239. compatible = "ucc_geth";
  240. model = "UCC";
  241. device-id = <2>;
  242. reg = <3000 200>;
  243. interrupts = <21>;
  244. interrupt-parent = < &qeic >;
  245. /*
  246. * mac-address is deprecated and will be removed
  247. * in 2.6.25. Only recent versions of
  248. * U-Boot support local-mac-address, however.
  249. */
  250. mac-address = [ 00 00 00 00 00 00 ];
  251. local-mac-address = [ 00 00 00 00 00 00 ];
  252. rx-clock = <0>;
  253. tx-clock = <14>;
  254. phy-handle = < &phy1 >;
  255. phy-connection-type = "rgmii-id";
  256. pio-handle = < &pio2 >;
  257. };
  258. mdio@2120 {
  259. #address-cells = <1>;
  260. #size-cells = <0>;
  261. reg = <2120 18>;
  262. device_type = "mdio";
  263. compatible = "ucc_geth_phy";
  264. phy0: ethernet-phy@00 {
  265. interrupt-parent = < &ipic >;
  266. interrupts = <11 8>;
  267. reg = <0>;
  268. device_type = "ethernet-phy";
  269. };
  270. phy1: ethernet-phy@01 {
  271. interrupt-parent = < &ipic >;
  272. interrupts = <12 8>;
  273. reg = <1>;
  274. device_type = "ethernet-phy";
  275. };
  276. };
  277. qeic: qeic@80 {
  278. interrupt-controller;
  279. device_type = "qeic";
  280. #address-cells = <0>;
  281. #interrupt-cells = <1>;
  282. reg = <80 80>;
  283. big-endian;
  284. interrupts = <20 8 21 8>; //high:32 low:33
  285. interrupt-parent = < &ipic >;
  286. };
  287. };
  288. pci@e0008500 {
  289. interrupt-map-mask = <f800 0 0 7>;
  290. interrupt-map = <
  291. /* IDSEL 0x11 AD17 */
  292. 8800 0 0 1 &ipic 14 8
  293. 8800 0 0 2 &ipic 15 8
  294. 8800 0 0 3 &ipic 16 8
  295. 8800 0 0 4 &ipic 17 8
  296. /* IDSEL 0x12 AD18 */
  297. 9000 0 0 1 &ipic 16 8
  298. 9000 0 0 2 &ipic 17 8
  299. 9000 0 0 3 &ipic 14 8
  300. 9000 0 0 4 &ipic 15 8
  301. /* IDSEL 0x13 AD19 */
  302. 9800 0 0 1 &ipic 17 8
  303. 9800 0 0 2 &ipic 14 8
  304. 9800 0 0 3 &ipic 15 8
  305. 9800 0 0 4 &ipic 16 8
  306. /* IDSEL 0x15 AD21*/
  307. a800 0 0 1 &ipic 14 8
  308. a800 0 0 2 &ipic 15 8
  309. a800 0 0 3 &ipic 16 8
  310. a800 0 0 4 &ipic 17 8
  311. /* IDSEL 0x16 AD22*/
  312. b000 0 0 1 &ipic 17 8
  313. b000 0 0 2 &ipic 14 8
  314. b000 0 0 3 &ipic 15 8
  315. b000 0 0 4 &ipic 16 8
  316. /* IDSEL 0x17 AD23*/
  317. b800 0 0 1 &ipic 16 8
  318. b800 0 0 2 &ipic 17 8
  319. b800 0 0 3 &ipic 14 8
  320. b800 0 0 4 &ipic 15 8
  321. /* IDSEL 0x18 AD24*/
  322. c000 0 0 1 &ipic 15 8
  323. c000 0 0 2 &ipic 16 8
  324. c000 0 0 3 &ipic 17 8
  325. c000 0 0 4 &ipic 14 8>;
  326. interrupt-parent = < &ipic >;
  327. interrupts = <42 8>;
  328. bus-range = <0 0>;
  329. ranges = <02000000 0 a0000000 a0000000 0 10000000
  330. 42000000 0 80000000 80000000 0 10000000
  331. 01000000 0 00000000 e2000000 0 00100000>;
  332. clock-frequency = <3f940aa>;
  333. #interrupt-cells = <1>;
  334. #size-cells = <2>;
  335. #address-cells = <3>;
  336. reg = <e0008500 100>;
  337. compatible = "fsl,mpc8349-pci";
  338. device_type = "pci";
  339. };
  340. };