mpc832x_rdb.dts 6.7 KB

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  1. /*
  2. * MPC832x RDB Device Tree Source
  3. *
  4. * Copyright 2007 Freescale Semiconductor Inc.
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License as published by the
  8. * Free Software Foundation; either version 2 of the License, or (at your
  9. * option) any later version.
  10. */
  11. / {
  12. model = "MPC8323ERDB";
  13. compatible = "MPC8323ERDB", "MPC832xRDB", "MPC83xxRDB";
  14. #address-cells = <1>;
  15. #size-cells = <1>;
  16. cpus {
  17. #address-cells = <1>;
  18. #size-cells = <0>;
  19. PowerPC,8323@0 {
  20. device_type = "cpu";
  21. reg = <0>;
  22. d-cache-line-size = <20>; // 32 bytes
  23. i-cache-line-size = <20>; // 32 bytes
  24. d-cache-size = <4000>; // L1, 16K
  25. i-cache-size = <4000>; // L1, 16K
  26. timebase-frequency = <0>;
  27. bus-frequency = <0>;
  28. clock-frequency = <0>;
  29. };
  30. };
  31. memory {
  32. device_type = "memory";
  33. reg = <00000000 04000000>;
  34. };
  35. soc8323@e0000000 {
  36. #address-cells = <1>;
  37. #size-cells = <1>;
  38. device_type = "soc";
  39. ranges = <0 e0000000 00100000>;
  40. reg = <e0000000 00000200>;
  41. bus-frequency = <0>;
  42. wdt@200 {
  43. device_type = "watchdog";
  44. compatible = "mpc83xx_wdt";
  45. reg = <200 100>;
  46. };
  47. i2c@3000 {
  48. device_type = "i2c";
  49. compatible = "fsl-i2c";
  50. reg = <3000 100>;
  51. interrupts = <e 8>;
  52. interrupt-parent = <&pic>;
  53. dfsrr;
  54. };
  55. serial@4500 {
  56. device_type = "serial";
  57. compatible = "ns16550";
  58. reg = <4500 100>;
  59. clock-frequency = <0>;
  60. interrupts = <9 8>;
  61. interrupt-parent = <&pic>;
  62. };
  63. serial@4600 {
  64. device_type = "serial";
  65. compatible = "ns16550";
  66. reg = <4600 100>;
  67. clock-frequency = <0>;
  68. interrupts = <a 8>;
  69. interrupt-parent = <&pic>;
  70. };
  71. crypto@30000 {
  72. device_type = "crypto";
  73. model = "SEC2";
  74. compatible = "talitos";
  75. reg = <30000 7000>;
  76. interrupts = <b 8>;
  77. interrupt-parent = <&pic>;
  78. /* Rev. 2.2 */
  79. num-channels = <1>;
  80. channel-fifo-len = <18>;
  81. exec-units-mask = <0000004c>;
  82. descriptor-types-mask = <0122003f>;
  83. };
  84. pic:pic@700 {
  85. interrupt-controller;
  86. #address-cells = <0>;
  87. #interrupt-cells = <2>;
  88. reg = <700 100>;
  89. device_type = "ipic";
  90. };
  91. par_io@1400 {
  92. reg = <1400 100>;
  93. device_type = "par_io";
  94. num-ports = <7>;
  95. ucc2pio:ucc_pin@02 {
  96. pio-map = <
  97. /* port pin dir open_drain assignment has_irq */
  98. 3 4 3 0 2 0 /* MDIO */
  99. 3 5 1 0 2 0 /* MDC */
  100. 3 15 2 0 1 0 /* RX_CLK (CLK16) */
  101. 3 17 2 0 1 0 /* TX_CLK (CLK3) */
  102. 0 12 1 0 1 0 /* TxD0 */
  103. 0 13 1 0 1 0 /* TxD1 */
  104. 0 14 1 0 1 0 /* TxD2 */
  105. 0 15 1 0 1 0 /* TxD3 */
  106. 0 16 2 0 1 0 /* RxD0 */
  107. 0 17 2 0 1 0 /* RxD1 */
  108. 0 18 2 0 1 0 /* RxD2 */
  109. 0 19 2 0 1 0 /* RxD3 */
  110. 0 1a 2 0 1 0 /* RX_ER */
  111. 0 1b 1 0 1 0 /* TX_ER */
  112. 0 1c 2 0 1 0 /* RX_DV */
  113. 0 1d 2 0 1 0 /* COL */
  114. 0 1e 1 0 1 0 /* TX_EN */
  115. 0 1f 2 0 1 0>; /* CRS */
  116. };
  117. ucc3pio:ucc_pin@03 {
  118. pio-map = <
  119. /* port pin dir open_drain assignment has_irq */
  120. 0 d 2 0 1 0 /* RX_CLK (CLK9) */
  121. 3 18 2 0 1 0 /* TX_CLK (CLK10) */
  122. 1 0 1 0 1 0 /* TxD0 */
  123. 1 1 1 0 1 0 /* TxD1 */
  124. 1 2 1 0 1 0 /* TxD2 */
  125. 1 3 1 0 1 0 /* TxD3 */
  126. 1 4 2 0 1 0 /* RxD0 */
  127. 1 5 2 0 1 0 /* RxD1 */
  128. 1 6 2 0 1 0 /* RxD2 */
  129. 1 7 2 0 1 0 /* RxD3 */
  130. 1 8 2 0 1 0 /* RX_ER */
  131. 1 9 1 0 1 0 /* TX_ER */
  132. 1 a 2 0 1 0 /* RX_DV */
  133. 1 b 2 0 1 0 /* COL */
  134. 1 c 1 0 1 0 /* TX_EN */
  135. 1 d 2 0 1 0>; /* CRS */
  136. };
  137. };
  138. };
  139. qe@e0100000 {
  140. #address-cells = <1>;
  141. #size-cells = <1>;
  142. device_type = "qe";
  143. model = "QE";
  144. ranges = <0 e0100000 00100000>;
  145. reg = <e0100000 480>;
  146. brg-frequency = <0>;
  147. bus-frequency = <BCD3D80>;
  148. muram@10000 {
  149. device_type = "muram";
  150. ranges = <0 00010000 00004000>;
  151. data-only@0 {
  152. reg = <0 4000>;
  153. };
  154. };
  155. spi@4c0 {
  156. device_type = "spi";
  157. compatible = "fsl_spi";
  158. reg = <4c0 40>;
  159. interrupts = <2>;
  160. interrupt-parent = <&qeic>;
  161. mode = "cpu-qe";
  162. };
  163. spi@500 {
  164. device_type = "spi";
  165. compatible = "fsl_spi";
  166. reg = <500 40>;
  167. interrupts = <1>;
  168. interrupt-parent = <&qeic>;
  169. mode = "cpu";
  170. };
  171. ucc@3000 {
  172. device_type = "network";
  173. compatible = "ucc_geth";
  174. model = "UCC";
  175. device-id = <2>;
  176. reg = <3000 200>;
  177. interrupts = <21>;
  178. interrupt-parent = <&qeic>;
  179. /*
  180. * mac-address is deprecated and will be removed
  181. * in 2.6.25. Only recent versions of
  182. * U-Boot support local-mac-address, however.
  183. */
  184. mac-address = [ 00 00 00 00 00 00 ];
  185. local-mac-address = [ 00 00 00 00 00 00 ];
  186. rx-clock = <20>;
  187. tx-clock = <13>;
  188. phy-handle = <&phy00>;
  189. pio-handle = <&ucc2pio>;
  190. };
  191. ucc@2200 {
  192. device_type = "network";
  193. compatible = "ucc_geth";
  194. model = "UCC";
  195. device-id = <3>;
  196. reg = <2200 200>;
  197. interrupts = <22>;
  198. interrupt-parent = <&qeic>;
  199. /*
  200. * mac-address is deprecated and will be removed
  201. * in 2.6.25. Only recent versions of
  202. * U-Boot support local-mac-address, however.
  203. */
  204. mac-address = [ 00 00 00 00 00 00 ];
  205. local-mac-address = [ 00 00 00 00 00 00 ];
  206. rx-clock = <19>;
  207. tx-clock = <1a>;
  208. phy-handle = <&phy04>;
  209. pio-handle = <&ucc3pio>;
  210. };
  211. mdio@3120 {
  212. #address-cells = <1>;
  213. #size-cells = <0>;
  214. reg = <3120 18>;
  215. device_type = "mdio";
  216. compatible = "ucc_geth_phy";
  217. phy00:ethernet-phy@00 {
  218. interrupt-parent = <&pic>;
  219. interrupts = <0>;
  220. reg = <0>;
  221. device_type = "ethernet-phy";
  222. };
  223. phy04:ethernet-phy@04 {
  224. interrupt-parent = <&pic>;
  225. interrupts = <0>;
  226. reg = <4>;
  227. device_type = "ethernet-phy";
  228. };
  229. };
  230. qeic:qeic@80 {
  231. interrupt-controller;
  232. device_type = "qeic";
  233. #address-cells = <0>;
  234. #interrupt-cells = <1>;
  235. reg = <80 80>;
  236. big-endian;
  237. interrupts = <20 8 21 8>; //high:32 low:33
  238. interrupt-parent = <&pic>;
  239. };
  240. };
  241. pci@e0008500 {
  242. interrupt-map-mask = <f800 0 0 7>;
  243. interrupt-map = <
  244. /* IDSEL 0x10 AD16 (USB) */
  245. 8000 0 0 1 &pic 11 8
  246. /* IDSEL 0x11 AD17 (Mini1)*/
  247. 8800 0 0 1 &pic 12 8
  248. 8800 0 0 2 &pic 13 8
  249. 8800 0 0 3 &pic 14 8
  250. 8800 0 0 4 &pic 30 8
  251. /* IDSEL 0x12 AD18 (PCI/Mini2) */
  252. 9000 0 0 1 &pic 13 8
  253. 9000 0 0 2 &pic 14 8
  254. 9000 0 0 3 &pic 30 8
  255. 9000 0 0 4 &pic 11 8>;
  256. interrupt-parent = <&pic>;
  257. interrupts = <42 8>;
  258. bus-range = <0 0>;
  259. ranges = <42000000 0 80000000 80000000 0 10000000
  260. 02000000 0 90000000 90000000 0 10000000
  261. 01000000 0 d0000000 d0000000 0 04000000>;
  262. clock-frequency = <0>;
  263. #interrupt-cells = <1>;
  264. #size-cells = <2>;
  265. #address-cells = <3>;
  266. reg = <e0008500 100>;
  267. compatible = "fsl,mpc8349-pci";
  268. device_type = "pci";
  269. };
  270. };