mpc832x_mds.dts 7.6 KB

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  1. /*
  2. * MPC8323E EMDS Device Tree Source
  3. *
  4. * Copyright 2006 Freescale Semiconductor Inc.
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License as published by the
  8. * Free Software Foundation; either version 2 of the License, or (at your
  9. * option) any later version.
  10. */
  11. / {
  12. model = "MPC8323EMDS";
  13. compatible = "MPC8323EMDS", "MPC832xMDS", "MPC83xxMDS";
  14. #address-cells = <1>;
  15. #size-cells = <1>;
  16. cpus {
  17. #address-cells = <1>;
  18. #size-cells = <0>;
  19. PowerPC,8323@0 {
  20. device_type = "cpu";
  21. reg = <0>;
  22. d-cache-line-size = <20>; // 32 bytes
  23. i-cache-line-size = <20>; // 32 bytes
  24. d-cache-size = <4000>; // L1, 16K
  25. i-cache-size = <4000>; // L1, 16K
  26. timebase-frequency = <0>;
  27. bus-frequency = <0>;
  28. clock-frequency = <0>;
  29. };
  30. };
  31. memory {
  32. device_type = "memory";
  33. reg = <00000000 08000000>;
  34. };
  35. bcsr@f8000000 {
  36. device_type = "board-control";
  37. reg = <f8000000 8000>;
  38. };
  39. soc8323@e0000000 {
  40. #address-cells = <1>;
  41. #size-cells = <1>;
  42. device_type = "soc";
  43. ranges = <0 e0000000 00100000>;
  44. reg = <e0000000 00000200>;
  45. bus-frequency = <7DE2900>;
  46. wdt@200 {
  47. device_type = "watchdog";
  48. compatible = "mpc83xx_wdt";
  49. reg = <200 100>;
  50. };
  51. i2c@3000 {
  52. #address-cells = <1>;
  53. #size-cells = <0>;
  54. device_type = "i2c";
  55. compatible = "fsl-i2c";
  56. reg = <3000 100>;
  57. interrupts = <e 8>;
  58. interrupt-parent = < &ipic >;
  59. dfsrr;
  60. rtc@68 {
  61. compatible = "dallas,ds1374";
  62. reg = <68>;
  63. };
  64. };
  65. serial@4500 {
  66. device_type = "serial";
  67. compatible = "ns16550";
  68. reg = <4500 100>;
  69. clock-frequency = <0>;
  70. interrupts = <9 8>;
  71. interrupt-parent = < &ipic >;
  72. };
  73. serial@4600 {
  74. device_type = "serial";
  75. compatible = "ns16550";
  76. reg = <4600 100>;
  77. clock-frequency = <0>;
  78. interrupts = <a 8>;
  79. interrupt-parent = < &ipic >;
  80. };
  81. crypto@30000 {
  82. device_type = "crypto";
  83. model = "SEC2";
  84. compatible = "talitos";
  85. reg = <30000 7000>;
  86. interrupts = <b 8>;
  87. interrupt-parent = < &ipic >;
  88. /* Rev. 2.2 */
  89. num-channels = <1>;
  90. channel-fifo-len = <18>;
  91. exec-units-mask = <0000004c>;
  92. descriptor-types-mask = <0122003f>;
  93. };
  94. ipic: pic@700 {
  95. interrupt-controller;
  96. #address-cells = <0>;
  97. #interrupt-cells = <2>;
  98. reg = <700 100>;
  99. device_type = "ipic";
  100. };
  101. par_io@1400 {
  102. reg = <1400 100>;
  103. device_type = "par_io";
  104. num-ports = <7>;
  105. pio3: ucc_pin@03 {
  106. pio-map = <
  107. /* port pin dir open_drain assignment has_irq */
  108. 3 4 3 0 2 0 /* MDIO */
  109. 3 5 1 0 2 0 /* MDC */
  110. 0 d 2 0 1 0 /* RX_CLK (CLK9) */
  111. 3 18 2 0 1 0 /* TX_CLK (CLK10) */
  112. 1 0 1 0 1 0 /* TxD0 */
  113. 1 1 1 0 1 0 /* TxD1 */
  114. 1 2 1 0 1 0 /* TxD2 */
  115. 1 3 1 0 1 0 /* TxD3 */
  116. 1 4 2 0 1 0 /* RxD0 */
  117. 1 5 2 0 1 0 /* RxD1 */
  118. 1 6 2 0 1 0 /* RxD2 */
  119. 1 7 2 0 1 0 /* RxD3 */
  120. 1 8 2 0 1 0 /* RX_ER */
  121. 1 9 1 0 1 0 /* TX_ER */
  122. 1 a 2 0 1 0 /* RX_DV */
  123. 1 b 2 0 1 0 /* COL */
  124. 1 c 1 0 1 0 /* TX_EN */
  125. 1 d 2 0 1 0>;/* CRS */
  126. };
  127. pio4: ucc_pin@04 {
  128. pio-map = <
  129. /* port pin dir open_drain assignment has_irq */
  130. 3 1f 2 0 1 0 /* RX_CLK (CLK7) */
  131. 3 6 2 0 1 0 /* TX_CLK (CLK8) */
  132. 1 12 1 0 1 0 /* TxD0 */
  133. 1 13 1 0 1 0 /* TxD1 */
  134. 1 14 1 0 1 0 /* TxD2 */
  135. 1 15 1 0 1 0 /* TxD3 */
  136. 1 16 2 0 1 0 /* RxD0 */
  137. 1 17 2 0 1 0 /* RxD1 */
  138. 1 18 2 0 1 0 /* RxD2 */
  139. 1 19 2 0 1 0 /* RxD3 */
  140. 1 1a 2 0 1 0 /* RX_ER */
  141. 1 1b 1 0 1 0 /* TX_ER */
  142. 1 1c 2 0 1 0 /* RX_DV */
  143. 1 1d 2 0 1 0 /* COL */
  144. 1 1e 1 0 1 0 /* TX_EN */
  145. 1 1f 2 0 1 0>;/* CRS */
  146. };
  147. };
  148. };
  149. qe@e0100000 {
  150. #address-cells = <1>;
  151. #size-cells = <1>;
  152. device_type = "qe";
  153. model = "QE";
  154. ranges = <0 e0100000 00100000>;
  155. reg = <e0100000 480>;
  156. brg-frequency = <0>;
  157. bus-frequency = <BCD3D80>;
  158. muram@10000 {
  159. device_type = "muram";
  160. ranges = <0 00010000 00004000>;
  161. data-only@0 {
  162. reg = <0 4000>;
  163. };
  164. };
  165. spi@4c0 {
  166. device_type = "spi";
  167. compatible = "fsl_spi";
  168. reg = <4c0 40>;
  169. interrupts = <2>;
  170. interrupt-parent = < &qeic >;
  171. mode = "cpu";
  172. };
  173. spi@500 {
  174. device_type = "spi";
  175. compatible = "fsl_spi";
  176. reg = <500 40>;
  177. interrupts = <1>;
  178. interrupt-parent = < &qeic >;
  179. mode = "cpu";
  180. };
  181. usb@6c0 {
  182. device_type = "usb";
  183. compatible = "qe_udc";
  184. reg = <6c0 40 8B00 100>;
  185. interrupts = <b>;
  186. interrupt-parent = < &qeic >;
  187. mode = "slave";
  188. };
  189. ucc@2200 {
  190. device_type = "network";
  191. compatible = "ucc_geth";
  192. model = "UCC";
  193. device-id = <3>;
  194. reg = <2200 200>;
  195. interrupts = <22>;
  196. interrupt-parent = < &qeic >;
  197. /*
  198. * mac-address is deprecated and will be removed
  199. * in 2.6.25. Only recent versions of
  200. * U-Boot support local-mac-address, however.
  201. */
  202. mac-address = [ 00 00 00 00 00 00 ];
  203. local-mac-address = [ 00 00 00 00 00 00 ];
  204. rx-clock = <19>;
  205. tx-clock = <1a>;
  206. phy-handle = < &phy3 >;
  207. pio-handle = < &pio3 >;
  208. };
  209. ucc@3200 {
  210. device_type = "network";
  211. compatible = "ucc_geth";
  212. model = "UCC";
  213. device-id = <4>;
  214. reg = <3200 200>;
  215. interrupts = <23>;
  216. interrupt-parent = < &qeic >;
  217. /*
  218. * mac-address is deprecated and will be removed
  219. * in 2.6.25. Only recent versions of
  220. * U-Boot support local-mac-address, however.
  221. */
  222. mac-address = [ 00 00 00 00 00 00 ];
  223. local-mac-address = [ 00 00 00 00 00 00 ];
  224. rx-clock = <17>;
  225. tx-clock = <18>;
  226. phy-handle = < &phy4 >;
  227. pio-handle = < &pio4 >;
  228. };
  229. mdio@2320 {
  230. #address-cells = <1>;
  231. #size-cells = <0>;
  232. reg = <2320 18>;
  233. device_type = "mdio";
  234. compatible = "ucc_geth_phy";
  235. phy3: ethernet-phy@03 {
  236. interrupt-parent = < &ipic >;
  237. interrupts = <11 8>;
  238. reg = <3>;
  239. device_type = "ethernet-phy";
  240. };
  241. phy4: ethernet-phy@04 {
  242. interrupt-parent = < &ipic >;
  243. interrupts = <12 8>;
  244. reg = <4>;
  245. device_type = "ethernet-phy";
  246. };
  247. };
  248. qeic: qeic@80 {
  249. interrupt-controller;
  250. device_type = "qeic";
  251. #address-cells = <0>;
  252. #interrupt-cells = <1>;
  253. reg = <80 80>;
  254. big-endian;
  255. interrupts = <20 8 21 8>; //high:32 low:33
  256. interrupt-parent = < &ipic >;
  257. };
  258. };
  259. pci@e0008500 {
  260. interrupt-map-mask = <f800 0 0 7>;
  261. interrupt-map = <
  262. /* IDSEL 0x11 AD17 */
  263. 8800 0 0 1 &ipic 14 8
  264. 8800 0 0 2 &ipic 15 8
  265. 8800 0 0 3 &ipic 16 8
  266. 8800 0 0 4 &ipic 17 8
  267. /* IDSEL 0x12 AD18 */
  268. 9000 0 0 1 &ipic 16 8
  269. 9000 0 0 2 &ipic 17 8
  270. 9000 0 0 3 &ipic 14 8
  271. 9000 0 0 4 &ipic 15 8
  272. /* IDSEL 0x13 AD19 */
  273. 9800 0 0 1 &ipic 17 8
  274. 9800 0 0 2 &ipic 14 8
  275. 9800 0 0 3 &ipic 15 8
  276. 9800 0 0 4 &ipic 16 8
  277. /* IDSEL 0x15 AD21*/
  278. a800 0 0 1 &ipic 14 8
  279. a800 0 0 2 &ipic 15 8
  280. a800 0 0 3 &ipic 16 8
  281. a800 0 0 4 &ipic 17 8
  282. /* IDSEL 0x16 AD22*/
  283. b000 0 0 1 &ipic 17 8
  284. b000 0 0 2 &ipic 14 8
  285. b000 0 0 3 &ipic 15 8
  286. b000 0 0 4 &ipic 16 8
  287. /* IDSEL 0x17 AD23*/
  288. b800 0 0 1 &ipic 16 8
  289. b800 0 0 2 &ipic 17 8
  290. b800 0 0 3 &ipic 14 8
  291. b800 0 0 4 &ipic 15 8
  292. /* IDSEL 0x18 AD24*/
  293. c000 0 0 1 &ipic 15 8
  294. c000 0 0 2 &ipic 16 8
  295. c000 0 0 3 &ipic 17 8
  296. c000 0 0 4 &ipic 14 8>;
  297. interrupt-parent = < &ipic >;
  298. interrupts = <42 8>;
  299. bus-range = <0 0>;
  300. ranges = <02000000 0 90000000 90000000 0 10000000
  301. 42000000 0 80000000 80000000 0 10000000
  302. 01000000 0 00000000 d0000000 0 00100000>;
  303. clock-frequency = <0>;
  304. #interrupt-cells = <1>;
  305. #size-cells = <2>;
  306. #address-cells = <3>;
  307. reg = <e0008500 100>;
  308. compatible = "fsl,mpc8349-pci";
  309. device_type = "pci";
  310. };
  311. };