interrupt.c 3.5 KB

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  1. /*
  2. * Carsten Langgaard, carstenl@mips.com
  3. * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
  4. *
  5. * This program is free software; you can distribute it and/or modify it
  6. * under the terms of the GNU General Public License (Version 2) as
  7. * published by the Free Software Foundation.
  8. *
  9. * This program is distributed in the hope it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  12. * for more details.
  13. *
  14. * You should have received a copy of the GNU General Public License along
  15. * with this program; if not, write to the Free Software Foundation, Inc.,
  16. * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
  17. *
  18. * Routines for generic manipulation of the interrupts found on the
  19. * Lasat boards.
  20. */
  21. #include <linux/init.h>
  22. #include <linux/interrupt.h>
  23. #include <linux/irq.h>
  24. #include <asm/bootinfo.h>
  25. #include <asm/irq_cpu.h>
  26. #include <asm/lasat/lasatint.h>
  27. #include <irq.h>
  28. static volatile int *lasat_int_status;
  29. static volatile int *lasat_int_mask;
  30. static volatile int lasat_int_mask_shift;
  31. void disable_lasat_irq(unsigned int irq_nr)
  32. {
  33. *lasat_int_mask &= ~(1 << irq_nr) << lasat_int_mask_shift;
  34. }
  35. void enable_lasat_irq(unsigned int irq_nr)
  36. {
  37. *lasat_int_mask |= (1 << irq_nr) << lasat_int_mask_shift;
  38. }
  39. static struct irq_chip lasat_irq_type = {
  40. .name = "Lasat",
  41. .ack = disable_lasat_irq,
  42. .mask = disable_lasat_irq,
  43. .mask_ack = disable_lasat_irq,
  44. .unmask = enable_lasat_irq,
  45. };
  46. static inline int ls1bit32(unsigned int x)
  47. {
  48. int b = 31, s;
  49. s = 16; if (x << 16 == 0) s = 0; b -= s; x <<= s;
  50. s = 8; if (x << 8 == 0) s = 0; b -= s; x <<= s;
  51. s = 4; if (x << 4 == 0) s = 0; b -= s; x <<= s;
  52. s = 2; if (x << 2 == 0) s = 0; b -= s; x <<= s;
  53. s = 1; if (x << 1 == 0) s = 0; b -= s;
  54. return b;
  55. }
  56. static unsigned long (*get_int_status)(void);
  57. static unsigned long get_int_status_100(void)
  58. {
  59. return *lasat_int_status & *lasat_int_mask;
  60. }
  61. static unsigned long get_int_status_200(void)
  62. {
  63. unsigned long int_status;
  64. int_status = *lasat_int_status;
  65. int_status &= (int_status >> LASATINT_MASK_SHIFT_200) & 0xffff;
  66. return int_status;
  67. }
  68. asmlinkage void plat_irq_dispatch(void)
  69. {
  70. unsigned long int_status;
  71. unsigned int cause = read_c0_cause();
  72. int irq;
  73. if (cause & CAUSEF_IP7) { /* R4000 count / compare IRQ */
  74. do_IRQ(7);
  75. return;
  76. }
  77. int_status = get_int_status();
  78. /* if int_status == 0, then the interrupt has already been cleared */
  79. if (int_status) {
  80. irq = LASAT_IRQ_BASE + ls1bit32(int_status);
  81. do_IRQ(irq);
  82. }
  83. }
  84. static struct irqaction cascade = {
  85. .handler = no_action,
  86. .mask = CPU_MASK_NONE,
  87. .name = "cascade",
  88. };
  89. void __init arch_init_irq(void)
  90. {
  91. int i;
  92. switch (mips_machtype) {
  93. case MACH_LASAT_100:
  94. lasat_int_status = (void *)LASAT_INT_STATUS_REG_100;
  95. lasat_int_mask = (void *)LASAT_INT_MASK_REG_100;
  96. lasat_int_mask_shift = LASATINT_MASK_SHIFT_100;
  97. get_int_status = get_int_status_100;
  98. *lasat_int_mask = 0;
  99. break;
  100. case MACH_LASAT_200:
  101. lasat_int_status = (void *)LASAT_INT_STATUS_REG_200;
  102. lasat_int_mask = (void *)LASAT_INT_MASK_REG_200;
  103. lasat_int_mask_shift = LASATINT_MASK_SHIFT_200;
  104. get_int_status = get_int_status_200;
  105. *lasat_int_mask &= 0xffff;
  106. break;
  107. default:
  108. panic("arch_init_irq: mips_machtype incorrect");
  109. }
  110. mips_cpu_irq_init();
  111. for (i = LASAT_IRQ_BASE; i <= LASAT_IRQ_END; i++)
  112. set_irq_chip_and_handler(i, &lasat_irq_type, handle_level_irq);
  113. setup_irq(LASAT_CASCADE_IRQ, &cascade);
  114. }