omap_hwmod_44xx_data.c 153 KB

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  1. /*
  2. * Hardware modules present on the OMAP44xx chips
  3. *
  4. * Copyright (C) 2009-2012 Texas Instruments, Inc.
  5. * Copyright (C) 2009-2010 Nokia Corporation
  6. *
  7. * Paul Walmsley
  8. * Benoit Cousson
  9. *
  10. * This file is automatically generated from the OMAP hardware databases.
  11. * We respectfully ask that any modifications to this file be coordinated
  12. * with the public linux-omap@vger.kernel.org mailing list and the
  13. * authors above to ensure that the autogeneration scripts are kept
  14. * up-to-date with the file contents.
  15. *
  16. * This program is free software; you can redistribute it and/or modify
  17. * it under the terms of the GNU General Public License version 2 as
  18. * published by the Free Software Foundation.
  19. */
  20. #include <linux/io.h>
  21. #include <plat/omap_hwmod.h>
  22. #include <plat/cpu.h>
  23. #include <plat/i2c.h>
  24. #include <plat/gpio.h>
  25. #include <plat/dma.h>
  26. #include <plat/mcspi.h>
  27. #include <plat/mcbsp.h>
  28. #include <plat/mmc.h>
  29. #include <plat/dmtimer.h>
  30. #include <plat/common.h>
  31. #include "omap_hwmod_common_data.h"
  32. #include "smartreflex.h"
  33. #include "cm1_44xx.h"
  34. #include "cm2_44xx.h"
  35. #include "prm44xx.h"
  36. #include "prm-regbits-44xx.h"
  37. #include "wd_timer.h"
  38. /* Base offset for all OMAP4 interrupts external to MPUSS */
  39. #define OMAP44XX_IRQ_GIC_START 32
  40. /* Base offset for all OMAP4 dma requests */
  41. #define OMAP44XX_DMA_REQ_START 1
  42. /*
  43. * IP blocks
  44. */
  45. /*
  46. * 'c2c_target_fw' class
  47. * instance(s): c2c_target_fw
  48. */
  49. static struct omap_hwmod_class omap44xx_c2c_target_fw_hwmod_class = {
  50. .name = "c2c_target_fw",
  51. };
  52. /* c2c_target_fw */
  53. static struct omap_hwmod omap44xx_c2c_target_fw_hwmod = {
  54. .name = "c2c_target_fw",
  55. .class = &omap44xx_c2c_target_fw_hwmod_class,
  56. .clkdm_name = "d2d_clkdm",
  57. .prcm = {
  58. .omap4 = {
  59. .clkctrl_offs = OMAP4_CM_D2D_SAD2D_FW_CLKCTRL_OFFSET,
  60. .context_offs = OMAP4_RM_D2D_SAD2D_FW_CONTEXT_OFFSET,
  61. },
  62. },
  63. };
  64. /*
  65. * 'dmm' class
  66. * instance(s): dmm
  67. */
  68. static struct omap_hwmod_class omap44xx_dmm_hwmod_class = {
  69. .name = "dmm",
  70. };
  71. /* dmm */
  72. static struct omap_hwmod_irq_info omap44xx_dmm_irqs[] = {
  73. { .irq = 113 + OMAP44XX_IRQ_GIC_START },
  74. { .irq = -1 }
  75. };
  76. static struct omap_hwmod omap44xx_dmm_hwmod = {
  77. .name = "dmm",
  78. .class = &omap44xx_dmm_hwmod_class,
  79. .clkdm_name = "l3_emif_clkdm",
  80. .mpu_irqs = omap44xx_dmm_irqs,
  81. .prcm = {
  82. .omap4 = {
  83. .clkctrl_offs = OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET,
  84. .context_offs = OMAP4_RM_MEMIF_DMM_CONTEXT_OFFSET,
  85. },
  86. },
  87. };
  88. /*
  89. * 'emif_fw' class
  90. * instance(s): emif_fw
  91. */
  92. static struct omap_hwmod_class omap44xx_emif_fw_hwmod_class = {
  93. .name = "emif_fw",
  94. };
  95. /* emif_fw */
  96. static struct omap_hwmod omap44xx_emif_fw_hwmod = {
  97. .name = "emif_fw",
  98. .class = &omap44xx_emif_fw_hwmod_class,
  99. .clkdm_name = "l3_emif_clkdm",
  100. .prcm = {
  101. .omap4 = {
  102. .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_FW_CLKCTRL_OFFSET,
  103. .context_offs = OMAP4_RM_MEMIF_EMIF_FW_CONTEXT_OFFSET,
  104. },
  105. },
  106. };
  107. /*
  108. * 'l3' class
  109. * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
  110. */
  111. static struct omap_hwmod_class omap44xx_l3_hwmod_class = {
  112. .name = "l3",
  113. };
  114. /* l3_instr */
  115. static struct omap_hwmod omap44xx_l3_instr_hwmod = {
  116. .name = "l3_instr",
  117. .class = &omap44xx_l3_hwmod_class,
  118. .clkdm_name = "l3_instr_clkdm",
  119. .prcm = {
  120. .omap4 = {
  121. .clkctrl_offs = OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
  122. .context_offs = OMAP4_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
  123. .modulemode = MODULEMODE_HWCTRL,
  124. },
  125. },
  126. };
  127. /* l3_main_1 */
  128. static struct omap_hwmod_irq_info omap44xx_l3_main_1_irqs[] = {
  129. { .name = "dbg_err", .irq = 9 + OMAP44XX_IRQ_GIC_START },
  130. { .name = "app_err", .irq = 10 + OMAP44XX_IRQ_GIC_START },
  131. { .irq = -1 }
  132. };
  133. static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
  134. .name = "l3_main_1",
  135. .class = &omap44xx_l3_hwmod_class,
  136. .clkdm_name = "l3_1_clkdm",
  137. .mpu_irqs = omap44xx_l3_main_1_irqs,
  138. .prcm = {
  139. .omap4 = {
  140. .clkctrl_offs = OMAP4_CM_L3_1_L3_1_CLKCTRL_OFFSET,
  141. .context_offs = OMAP4_RM_L3_1_L3_1_CONTEXT_OFFSET,
  142. },
  143. },
  144. };
  145. /* l3_main_2 */
  146. static struct omap_hwmod omap44xx_l3_main_2_hwmod = {
  147. .name = "l3_main_2",
  148. .class = &omap44xx_l3_hwmod_class,
  149. .clkdm_name = "l3_2_clkdm",
  150. .prcm = {
  151. .omap4 = {
  152. .clkctrl_offs = OMAP4_CM_L3_2_L3_2_CLKCTRL_OFFSET,
  153. .context_offs = OMAP4_RM_L3_2_L3_2_CONTEXT_OFFSET,
  154. },
  155. },
  156. };
  157. /* l3_main_3 */
  158. static struct omap_hwmod omap44xx_l3_main_3_hwmod = {
  159. .name = "l3_main_3",
  160. .class = &omap44xx_l3_hwmod_class,
  161. .clkdm_name = "l3_instr_clkdm",
  162. .prcm = {
  163. .omap4 = {
  164. .clkctrl_offs = OMAP4_CM_L3INSTR_L3_3_CLKCTRL_OFFSET,
  165. .context_offs = OMAP4_RM_L3INSTR_L3_3_CONTEXT_OFFSET,
  166. .modulemode = MODULEMODE_HWCTRL,
  167. },
  168. },
  169. };
  170. /*
  171. * 'l4' class
  172. * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
  173. */
  174. static struct omap_hwmod_class omap44xx_l4_hwmod_class = {
  175. .name = "l4",
  176. };
  177. /* l4_abe */
  178. static struct omap_hwmod omap44xx_l4_abe_hwmod = {
  179. .name = "l4_abe",
  180. .class = &omap44xx_l4_hwmod_class,
  181. .clkdm_name = "abe_clkdm",
  182. .prcm = {
  183. .omap4 = {
  184. .clkctrl_offs = OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET,
  185. },
  186. },
  187. };
  188. /* l4_cfg */
  189. static struct omap_hwmod omap44xx_l4_cfg_hwmod = {
  190. .name = "l4_cfg",
  191. .class = &omap44xx_l4_hwmod_class,
  192. .clkdm_name = "l4_cfg_clkdm",
  193. .prcm = {
  194. .omap4 = {
  195. .clkctrl_offs = OMAP4_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
  196. .context_offs = OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
  197. },
  198. },
  199. };
  200. /* l4_per */
  201. static struct omap_hwmod omap44xx_l4_per_hwmod = {
  202. .name = "l4_per",
  203. .class = &omap44xx_l4_hwmod_class,
  204. .clkdm_name = "l4_per_clkdm",
  205. .prcm = {
  206. .omap4 = {
  207. .clkctrl_offs = OMAP4_CM_L4PER_L4PER_CLKCTRL_OFFSET,
  208. .context_offs = OMAP4_RM_L4PER_L4_PER_CONTEXT_OFFSET,
  209. },
  210. },
  211. };
  212. /* l4_wkup */
  213. static struct omap_hwmod omap44xx_l4_wkup_hwmod = {
  214. .name = "l4_wkup",
  215. .class = &omap44xx_l4_hwmod_class,
  216. .clkdm_name = "l4_wkup_clkdm",
  217. .prcm = {
  218. .omap4 = {
  219. .clkctrl_offs = OMAP4_CM_WKUP_L4WKUP_CLKCTRL_OFFSET,
  220. .context_offs = OMAP4_RM_WKUP_L4WKUP_CONTEXT_OFFSET,
  221. },
  222. },
  223. };
  224. /*
  225. * 'mpu_bus' class
  226. * instance(s): mpu_private
  227. */
  228. static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = {
  229. .name = "mpu_bus",
  230. };
  231. /* mpu_private */
  232. static struct omap_hwmod omap44xx_mpu_private_hwmod = {
  233. .name = "mpu_private",
  234. .class = &omap44xx_mpu_bus_hwmod_class,
  235. .clkdm_name = "mpuss_clkdm",
  236. };
  237. /*
  238. * 'ocp_wp_noc' class
  239. * instance(s): ocp_wp_noc
  240. */
  241. static struct omap_hwmod_class omap44xx_ocp_wp_noc_hwmod_class = {
  242. .name = "ocp_wp_noc",
  243. };
  244. /* ocp_wp_noc */
  245. static struct omap_hwmod omap44xx_ocp_wp_noc_hwmod = {
  246. .name = "ocp_wp_noc",
  247. .class = &omap44xx_ocp_wp_noc_hwmod_class,
  248. .clkdm_name = "l3_instr_clkdm",
  249. .prcm = {
  250. .omap4 = {
  251. .clkctrl_offs = OMAP4_CM_L3INSTR_OCP_WP1_CLKCTRL_OFFSET,
  252. .context_offs = OMAP4_RM_L3INSTR_OCP_WP1_CONTEXT_OFFSET,
  253. .modulemode = MODULEMODE_HWCTRL,
  254. },
  255. },
  256. };
  257. /*
  258. * Modules omap_hwmod structures
  259. *
  260. * The following IPs are excluded for the moment because:
  261. * - They do not need an explicit SW control using omap_hwmod API.
  262. * - They still need to be validated with the driver
  263. * properly adapted to omap_hwmod / omap_device
  264. *
  265. * debugss
  266. * efuse_ctrl_cust
  267. * efuse_ctrl_std
  268. * mpu_c0
  269. * mpu_c1
  270. * usb_phy_cm
  271. * usim
  272. */
  273. /*
  274. * 'aess' class
  275. * audio engine sub system
  276. */
  277. static struct omap_hwmod_class_sysconfig omap44xx_aess_sysc = {
  278. .rev_offs = 0x0000,
  279. .sysc_offs = 0x0010,
  280. .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
  281. .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
  282. MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART |
  283. MSTANDBY_SMART_WKUP),
  284. .sysc_fields = &omap_hwmod_sysc_type2,
  285. };
  286. static struct omap_hwmod_class omap44xx_aess_hwmod_class = {
  287. .name = "aess",
  288. .sysc = &omap44xx_aess_sysc,
  289. };
  290. /* aess */
  291. static struct omap_hwmod_irq_info omap44xx_aess_irqs[] = {
  292. { .irq = 99 + OMAP44XX_IRQ_GIC_START },
  293. { .irq = -1 }
  294. };
  295. static struct omap_hwmod_dma_info omap44xx_aess_sdma_reqs[] = {
  296. { .name = "fifo0", .dma_req = 100 + OMAP44XX_DMA_REQ_START },
  297. { .name = "fifo1", .dma_req = 101 + OMAP44XX_DMA_REQ_START },
  298. { .name = "fifo2", .dma_req = 102 + OMAP44XX_DMA_REQ_START },
  299. { .name = "fifo3", .dma_req = 103 + OMAP44XX_DMA_REQ_START },
  300. { .name = "fifo4", .dma_req = 104 + OMAP44XX_DMA_REQ_START },
  301. { .name = "fifo5", .dma_req = 105 + OMAP44XX_DMA_REQ_START },
  302. { .name = "fifo6", .dma_req = 106 + OMAP44XX_DMA_REQ_START },
  303. { .name = "fifo7", .dma_req = 107 + OMAP44XX_DMA_REQ_START },
  304. { .dma_req = -1 }
  305. };
  306. static struct omap_hwmod omap44xx_aess_hwmod = {
  307. .name = "aess",
  308. .class = &omap44xx_aess_hwmod_class,
  309. .clkdm_name = "abe_clkdm",
  310. .mpu_irqs = omap44xx_aess_irqs,
  311. .sdma_reqs = omap44xx_aess_sdma_reqs,
  312. .main_clk = "aess_fck",
  313. .prcm = {
  314. .omap4 = {
  315. .clkctrl_offs = OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET,
  316. .context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET,
  317. .modulemode = MODULEMODE_SWCTRL,
  318. },
  319. },
  320. };
  321. /*
  322. * 'c2c' class
  323. * chip 2 chip interface used to plug the ape soc (omap) with an external modem
  324. * soc
  325. */
  326. static struct omap_hwmod_class omap44xx_c2c_hwmod_class = {
  327. .name = "c2c",
  328. };
  329. /* c2c */
  330. static struct omap_hwmod_irq_info omap44xx_c2c_irqs[] = {
  331. { .irq = 88 + OMAP44XX_IRQ_GIC_START },
  332. { .irq = -1 }
  333. };
  334. static struct omap_hwmod_dma_info omap44xx_c2c_sdma_reqs[] = {
  335. { .dma_req = 68 + OMAP44XX_DMA_REQ_START },
  336. { .dma_req = -1 }
  337. };
  338. static struct omap_hwmod omap44xx_c2c_hwmod = {
  339. .name = "c2c",
  340. .class = &omap44xx_c2c_hwmod_class,
  341. .clkdm_name = "d2d_clkdm",
  342. .mpu_irqs = omap44xx_c2c_irqs,
  343. .sdma_reqs = omap44xx_c2c_sdma_reqs,
  344. .prcm = {
  345. .omap4 = {
  346. .clkctrl_offs = OMAP4_CM_D2D_SAD2D_CLKCTRL_OFFSET,
  347. .context_offs = OMAP4_RM_D2D_SAD2D_CONTEXT_OFFSET,
  348. },
  349. },
  350. };
  351. /*
  352. * 'counter' class
  353. * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
  354. */
  355. static struct omap_hwmod_class_sysconfig omap44xx_counter_sysc = {
  356. .rev_offs = 0x0000,
  357. .sysc_offs = 0x0004,
  358. .sysc_flags = SYSC_HAS_SIDLEMODE,
  359. .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
  360. SIDLE_SMART_WKUP),
  361. .sysc_fields = &omap_hwmod_sysc_type1,
  362. };
  363. static struct omap_hwmod_class omap44xx_counter_hwmod_class = {
  364. .name = "counter",
  365. .sysc = &omap44xx_counter_sysc,
  366. };
  367. /* counter_32k */
  368. static struct omap_hwmod omap44xx_counter_32k_hwmod = {
  369. .name = "counter_32k",
  370. .class = &omap44xx_counter_hwmod_class,
  371. .clkdm_name = "l4_wkup_clkdm",
  372. .flags = HWMOD_SWSUP_SIDLE,
  373. .main_clk = "sys_32k_ck",
  374. .prcm = {
  375. .omap4 = {
  376. .clkctrl_offs = OMAP4_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET,
  377. .context_offs = OMAP4_RM_WKUP_SYNCTIMER_CONTEXT_OFFSET,
  378. },
  379. },
  380. };
  381. /*
  382. * 'ctrl_module' class
  383. * attila core control module + core pad control module + wkup pad control
  384. * module + attila wkup control module
  385. */
  386. static struct omap_hwmod_class_sysconfig omap44xx_ctrl_module_sysc = {
  387. .rev_offs = 0x0000,
  388. .sysc_offs = 0x0010,
  389. .sysc_flags = SYSC_HAS_SIDLEMODE,
  390. .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
  391. SIDLE_SMART_WKUP),
  392. .sysc_fields = &omap_hwmod_sysc_type2,
  393. };
  394. static struct omap_hwmod_class omap44xx_ctrl_module_hwmod_class = {
  395. .name = "ctrl_module",
  396. .sysc = &omap44xx_ctrl_module_sysc,
  397. };
  398. /* ctrl_module_core */
  399. static struct omap_hwmod_irq_info omap44xx_ctrl_module_core_irqs[] = {
  400. { .irq = 8 + OMAP44XX_IRQ_GIC_START },
  401. { .irq = -1 }
  402. };
  403. static struct omap_hwmod omap44xx_ctrl_module_core_hwmod = {
  404. .name = "ctrl_module_core",
  405. .class = &omap44xx_ctrl_module_hwmod_class,
  406. .clkdm_name = "l4_cfg_clkdm",
  407. .mpu_irqs = omap44xx_ctrl_module_core_irqs,
  408. };
  409. /* ctrl_module_pad_core */
  410. static struct omap_hwmod omap44xx_ctrl_module_pad_core_hwmod = {
  411. .name = "ctrl_module_pad_core",
  412. .class = &omap44xx_ctrl_module_hwmod_class,
  413. .clkdm_name = "l4_cfg_clkdm",
  414. };
  415. /* ctrl_module_wkup */
  416. static struct omap_hwmod omap44xx_ctrl_module_wkup_hwmod = {
  417. .name = "ctrl_module_wkup",
  418. .class = &omap44xx_ctrl_module_hwmod_class,
  419. .clkdm_name = "l4_wkup_clkdm",
  420. };
  421. /* ctrl_module_pad_wkup */
  422. static struct omap_hwmod omap44xx_ctrl_module_pad_wkup_hwmod = {
  423. .name = "ctrl_module_pad_wkup",
  424. .class = &omap44xx_ctrl_module_hwmod_class,
  425. .clkdm_name = "l4_wkup_clkdm",
  426. };
  427. /*
  428. * 'dma' class
  429. * dma controller for data exchange between memory to memory (i.e. internal or
  430. * external memory) and gp peripherals to memory or memory to gp peripherals
  431. */
  432. static struct omap_hwmod_class_sysconfig omap44xx_dma_sysc = {
  433. .rev_offs = 0x0000,
  434. .sysc_offs = 0x002c,
  435. .syss_offs = 0x0028,
  436. .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
  437. SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
  438. SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
  439. SYSS_HAS_RESET_STATUS),
  440. .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
  441. MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
  442. .sysc_fields = &omap_hwmod_sysc_type1,
  443. };
  444. static struct omap_hwmod_class omap44xx_dma_hwmod_class = {
  445. .name = "dma",
  446. .sysc = &omap44xx_dma_sysc,
  447. };
  448. /* dma dev_attr */
  449. static struct omap_dma_dev_attr dma_dev_attr = {
  450. .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
  451. IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
  452. .lch_count = 32,
  453. };
  454. /* dma_system */
  455. static struct omap_hwmod_irq_info omap44xx_dma_system_irqs[] = {
  456. { .name = "0", .irq = 12 + OMAP44XX_IRQ_GIC_START },
  457. { .name = "1", .irq = 13 + OMAP44XX_IRQ_GIC_START },
  458. { .name = "2", .irq = 14 + OMAP44XX_IRQ_GIC_START },
  459. { .name = "3", .irq = 15 + OMAP44XX_IRQ_GIC_START },
  460. { .irq = -1 }
  461. };
  462. static struct omap_hwmod omap44xx_dma_system_hwmod = {
  463. .name = "dma_system",
  464. .class = &omap44xx_dma_hwmod_class,
  465. .clkdm_name = "l3_dma_clkdm",
  466. .mpu_irqs = omap44xx_dma_system_irqs,
  467. .main_clk = "l3_div_ck",
  468. .prcm = {
  469. .omap4 = {
  470. .clkctrl_offs = OMAP4_CM_SDMA_SDMA_CLKCTRL_OFFSET,
  471. .context_offs = OMAP4_RM_SDMA_SDMA_CONTEXT_OFFSET,
  472. },
  473. },
  474. .dev_attr = &dma_dev_attr,
  475. };
  476. /*
  477. * 'dmic' class
  478. * digital microphone controller
  479. */
  480. static struct omap_hwmod_class_sysconfig omap44xx_dmic_sysc = {
  481. .rev_offs = 0x0000,
  482. .sysc_offs = 0x0010,
  483. .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
  484. SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
  485. .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
  486. SIDLE_SMART_WKUP),
  487. .sysc_fields = &omap_hwmod_sysc_type2,
  488. };
  489. static struct omap_hwmod_class omap44xx_dmic_hwmod_class = {
  490. .name = "dmic",
  491. .sysc = &omap44xx_dmic_sysc,
  492. };
  493. /* dmic */
  494. static struct omap_hwmod_irq_info omap44xx_dmic_irqs[] = {
  495. { .irq = 114 + OMAP44XX_IRQ_GIC_START },
  496. { .irq = -1 }
  497. };
  498. static struct omap_hwmod_dma_info omap44xx_dmic_sdma_reqs[] = {
  499. { .dma_req = 66 + OMAP44XX_DMA_REQ_START },
  500. { .dma_req = -1 }
  501. };
  502. static struct omap_hwmod omap44xx_dmic_hwmod = {
  503. .name = "dmic",
  504. .class = &omap44xx_dmic_hwmod_class,
  505. .clkdm_name = "abe_clkdm",
  506. .mpu_irqs = omap44xx_dmic_irqs,
  507. .sdma_reqs = omap44xx_dmic_sdma_reqs,
  508. .main_clk = "dmic_fck",
  509. .prcm = {
  510. .omap4 = {
  511. .clkctrl_offs = OMAP4_CM1_ABE_DMIC_CLKCTRL_OFFSET,
  512. .context_offs = OMAP4_RM_ABE_DMIC_CONTEXT_OFFSET,
  513. .modulemode = MODULEMODE_SWCTRL,
  514. },
  515. },
  516. };
  517. /*
  518. * 'dsp' class
  519. * dsp sub-system
  520. */
  521. static struct omap_hwmod_class omap44xx_dsp_hwmod_class = {
  522. .name = "dsp",
  523. };
  524. /* dsp */
  525. static struct omap_hwmod_irq_info omap44xx_dsp_irqs[] = {
  526. { .irq = 28 + OMAP44XX_IRQ_GIC_START },
  527. { .irq = -1 }
  528. };
  529. static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = {
  530. { .name = "dsp", .rst_shift = 0 },
  531. { .name = "mmu_cache", .rst_shift = 1 },
  532. };
  533. static struct omap_hwmod omap44xx_dsp_hwmod = {
  534. .name = "dsp",
  535. .class = &omap44xx_dsp_hwmod_class,
  536. .clkdm_name = "tesla_clkdm",
  537. .mpu_irqs = omap44xx_dsp_irqs,
  538. .rst_lines = omap44xx_dsp_resets,
  539. .rst_lines_cnt = ARRAY_SIZE(omap44xx_dsp_resets),
  540. .main_clk = "dsp_fck",
  541. .prcm = {
  542. .omap4 = {
  543. .clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET,
  544. .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
  545. .context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET,
  546. .modulemode = MODULEMODE_HWCTRL,
  547. },
  548. },
  549. };
  550. /*
  551. * 'dss' class
  552. * display sub-system
  553. */
  554. static struct omap_hwmod_class_sysconfig omap44xx_dss_sysc = {
  555. .rev_offs = 0x0000,
  556. .syss_offs = 0x0014,
  557. .sysc_flags = SYSS_HAS_RESET_STATUS,
  558. };
  559. static struct omap_hwmod_class omap44xx_dss_hwmod_class = {
  560. .name = "dss",
  561. .sysc = &omap44xx_dss_sysc,
  562. .reset = omap_dss_reset,
  563. };
  564. /* dss */
  565. static struct omap_hwmod_opt_clk dss_opt_clks[] = {
  566. { .role = "sys_clk", .clk = "dss_sys_clk" },
  567. { .role = "tv_clk", .clk = "dss_tv_clk" },
  568. { .role = "hdmi_clk", .clk = "dss_48mhz_clk" },
  569. };
  570. static struct omap_hwmod omap44xx_dss_hwmod = {
  571. .name = "dss_core",
  572. .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
  573. .class = &omap44xx_dss_hwmod_class,
  574. .clkdm_name = "l3_dss_clkdm",
  575. .main_clk = "dss_dss_clk",
  576. .prcm = {
  577. .omap4 = {
  578. .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
  579. .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
  580. },
  581. },
  582. .opt_clks = dss_opt_clks,
  583. .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
  584. };
  585. /*
  586. * 'dispc' class
  587. * display controller
  588. */
  589. static struct omap_hwmod_class_sysconfig omap44xx_dispc_sysc = {
  590. .rev_offs = 0x0000,
  591. .sysc_offs = 0x0010,
  592. .syss_offs = 0x0014,
  593. .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
  594. SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
  595. SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
  596. SYSS_HAS_RESET_STATUS),
  597. .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
  598. MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
  599. .sysc_fields = &omap_hwmod_sysc_type1,
  600. };
  601. static struct omap_hwmod_class omap44xx_dispc_hwmod_class = {
  602. .name = "dispc",
  603. .sysc = &omap44xx_dispc_sysc,
  604. };
  605. /* dss_dispc */
  606. static struct omap_hwmod_irq_info omap44xx_dss_dispc_irqs[] = {
  607. { .irq = 25 + OMAP44XX_IRQ_GIC_START },
  608. { .irq = -1 }
  609. };
  610. static struct omap_hwmod_dma_info omap44xx_dss_dispc_sdma_reqs[] = {
  611. { .dma_req = 5 + OMAP44XX_DMA_REQ_START },
  612. { .dma_req = -1 }
  613. };
  614. static struct omap_dss_dispc_dev_attr omap44xx_dss_dispc_dev_attr = {
  615. .manager_count = 3,
  616. .has_framedonetv_irq = 1
  617. };
  618. static struct omap_hwmod omap44xx_dss_dispc_hwmod = {
  619. .name = "dss_dispc",
  620. .class = &omap44xx_dispc_hwmod_class,
  621. .clkdm_name = "l3_dss_clkdm",
  622. .mpu_irqs = omap44xx_dss_dispc_irqs,
  623. .sdma_reqs = omap44xx_dss_dispc_sdma_reqs,
  624. .main_clk = "dss_dss_clk",
  625. .prcm = {
  626. .omap4 = {
  627. .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
  628. .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
  629. },
  630. },
  631. .dev_attr = &omap44xx_dss_dispc_dev_attr
  632. };
  633. /*
  634. * 'dsi' class
  635. * display serial interface controller
  636. */
  637. static struct omap_hwmod_class_sysconfig omap44xx_dsi_sysc = {
  638. .rev_offs = 0x0000,
  639. .sysc_offs = 0x0010,
  640. .syss_offs = 0x0014,
  641. .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
  642. SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
  643. SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
  644. .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
  645. .sysc_fields = &omap_hwmod_sysc_type1,
  646. };
  647. static struct omap_hwmod_class omap44xx_dsi_hwmod_class = {
  648. .name = "dsi",
  649. .sysc = &omap44xx_dsi_sysc,
  650. };
  651. /* dss_dsi1 */
  652. static struct omap_hwmod_irq_info omap44xx_dss_dsi1_irqs[] = {
  653. { .irq = 53 + OMAP44XX_IRQ_GIC_START },
  654. { .irq = -1 }
  655. };
  656. static struct omap_hwmod_dma_info omap44xx_dss_dsi1_sdma_reqs[] = {
  657. { .dma_req = 74 + OMAP44XX_DMA_REQ_START },
  658. { .dma_req = -1 }
  659. };
  660. static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
  661. { .role = "sys_clk", .clk = "dss_sys_clk" },
  662. };
  663. static struct omap_hwmod omap44xx_dss_dsi1_hwmod = {
  664. .name = "dss_dsi1",
  665. .class = &omap44xx_dsi_hwmod_class,
  666. .clkdm_name = "l3_dss_clkdm",
  667. .mpu_irqs = omap44xx_dss_dsi1_irqs,
  668. .sdma_reqs = omap44xx_dss_dsi1_sdma_reqs,
  669. .main_clk = "dss_dss_clk",
  670. .prcm = {
  671. .omap4 = {
  672. .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
  673. .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
  674. },
  675. },
  676. .opt_clks = dss_dsi1_opt_clks,
  677. .opt_clks_cnt = ARRAY_SIZE(dss_dsi1_opt_clks),
  678. };
  679. /* dss_dsi2 */
  680. static struct omap_hwmod_irq_info omap44xx_dss_dsi2_irqs[] = {
  681. { .irq = 84 + OMAP44XX_IRQ_GIC_START },
  682. { .irq = -1 }
  683. };
  684. static struct omap_hwmod_dma_info omap44xx_dss_dsi2_sdma_reqs[] = {
  685. { .dma_req = 83 + OMAP44XX_DMA_REQ_START },
  686. { .dma_req = -1 }
  687. };
  688. static struct omap_hwmod_opt_clk dss_dsi2_opt_clks[] = {
  689. { .role = "sys_clk", .clk = "dss_sys_clk" },
  690. };
  691. static struct omap_hwmod omap44xx_dss_dsi2_hwmod = {
  692. .name = "dss_dsi2",
  693. .class = &omap44xx_dsi_hwmod_class,
  694. .clkdm_name = "l3_dss_clkdm",
  695. .mpu_irqs = omap44xx_dss_dsi2_irqs,
  696. .sdma_reqs = omap44xx_dss_dsi2_sdma_reqs,
  697. .main_clk = "dss_dss_clk",
  698. .prcm = {
  699. .omap4 = {
  700. .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
  701. .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
  702. },
  703. },
  704. .opt_clks = dss_dsi2_opt_clks,
  705. .opt_clks_cnt = ARRAY_SIZE(dss_dsi2_opt_clks),
  706. };
  707. /*
  708. * 'hdmi' class
  709. * hdmi controller
  710. */
  711. static struct omap_hwmod_class_sysconfig omap44xx_hdmi_sysc = {
  712. .rev_offs = 0x0000,
  713. .sysc_offs = 0x0010,
  714. .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
  715. SYSC_HAS_SOFTRESET),
  716. .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
  717. SIDLE_SMART_WKUP),
  718. .sysc_fields = &omap_hwmod_sysc_type2,
  719. };
  720. static struct omap_hwmod_class omap44xx_hdmi_hwmod_class = {
  721. .name = "hdmi",
  722. .sysc = &omap44xx_hdmi_sysc,
  723. };
  724. /* dss_hdmi */
  725. static struct omap_hwmod_irq_info omap44xx_dss_hdmi_irqs[] = {
  726. { .irq = 101 + OMAP44XX_IRQ_GIC_START },
  727. { .irq = -1 }
  728. };
  729. static struct omap_hwmod_dma_info omap44xx_dss_hdmi_sdma_reqs[] = {
  730. { .dma_req = 75 + OMAP44XX_DMA_REQ_START },
  731. { .dma_req = -1 }
  732. };
  733. static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
  734. { .role = "sys_clk", .clk = "dss_sys_clk" },
  735. };
  736. static struct omap_hwmod omap44xx_dss_hdmi_hwmod = {
  737. .name = "dss_hdmi",
  738. .class = &omap44xx_hdmi_hwmod_class,
  739. .clkdm_name = "l3_dss_clkdm",
  740. .mpu_irqs = omap44xx_dss_hdmi_irqs,
  741. .sdma_reqs = omap44xx_dss_hdmi_sdma_reqs,
  742. .main_clk = "dss_48mhz_clk",
  743. .prcm = {
  744. .omap4 = {
  745. .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
  746. .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
  747. },
  748. },
  749. .opt_clks = dss_hdmi_opt_clks,
  750. .opt_clks_cnt = ARRAY_SIZE(dss_hdmi_opt_clks),
  751. };
  752. /*
  753. * 'rfbi' class
  754. * remote frame buffer interface
  755. */
  756. static struct omap_hwmod_class_sysconfig omap44xx_rfbi_sysc = {
  757. .rev_offs = 0x0000,
  758. .sysc_offs = 0x0010,
  759. .syss_offs = 0x0014,
  760. .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
  761. SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
  762. .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
  763. .sysc_fields = &omap_hwmod_sysc_type1,
  764. };
  765. static struct omap_hwmod_class omap44xx_rfbi_hwmod_class = {
  766. .name = "rfbi",
  767. .sysc = &omap44xx_rfbi_sysc,
  768. };
  769. /* dss_rfbi */
  770. static struct omap_hwmod_dma_info omap44xx_dss_rfbi_sdma_reqs[] = {
  771. { .dma_req = 13 + OMAP44XX_DMA_REQ_START },
  772. { .dma_req = -1 }
  773. };
  774. static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
  775. { .role = "ick", .clk = "dss_fck" },
  776. };
  777. static struct omap_hwmod omap44xx_dss_rfbi_hwmod = {
  778. .name = "dss_rfbi",
  779. .class = &omap44xx_rfbi_hwmod_class,
  780. .clkdm_name = "l3_dss_clkdm",
  781. .sdma_reqs = omap44xx_dss_rfbi_sdma_reqs,
  782. .main_clk = "dss_dss_clk",
  783. .prcm = {
  784. .omap4 = {
  785. .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
  786. .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
  787. },
  788. },
  789. .opt_clks = dss_rfbi_opt_clks,
  790. .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks),
  791. };
  792. /*
  793. * 'venc' class
  794. * video encoder
  795. */
  796. static struct omap_hwmod_class omap44xx_venc_hwmod_class = {
  797. .name = "venc",
  798. };
  799. /* dss_venc */
  800. static struct omap_hwmod omap44xx_dss_venc_hwmod = {
  801. .name = "dss_venc",
  802. .class = &omap44xx_venc_hwmod_class,
  803. .clkdm_name = "l3_dss_clkdm",
  804. .main_clk = "dss_tv_clk",
  805. .prcm = {
  806. .omap4 = {
  807. .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
  808. .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
  809. },
  810. },
  811. };
  812. /*
  813. * 'elm' class
  814. * bch error location module
  815. */
  816. static struct omap_hwmod_class_sysconfig omap44xx_elm_sysc = {
  817. .rev_offs = 0x0000,
  818. .sysc_offs = 0x0010,
  819. .syss_offs = 0x0014,
  820. .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
  821. SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
  822. SYSS_HAS_RESET_STATUS),
  823. .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
  824. .sysc_fields = &omap_hwmod_sysc_type1,
  825. };
  826. static struct omap_hwmod_class omap44xx_elm_hwmod_class = {
  827. .name = "elm",
  828. .sysc = &omap44xx_elm_sysc,
  829. };
  830. /* elm */
  831. static struct omap_hwmod_irq_info omap44xx_elm_irqs[] = {
  832. { .irq = 4 + OMAP44XX_IRQ_GIC_START },
  833. { .irq = -1 }
  834. };
  835. static struct omap_hwmod omap44xx_elm_hwmod = {
  836. .name = "elm",
  837. .class = &omap44xx_elm_hwmod_class,
  838. .clkdm_name = "l4_per_clkdm",
  839. .mpu_irqs = omap44xx_elm_irqs,
  840. .prcm = {
  841. .omap4 = {
  842. .clkctrl_offs = OMAP4_CM_L4PER_ELM_CLKCTRL_OFFSET,
  843. .context_offs = OMAP4_RM_L4PER_ELM_CONTEXT_OFFSET,
  844. },
  845. },
  846. };
  847. /*
  848. * 'emif' class
  849. * external memory interface no1
  850. */
  851. static struct omap_hwmod_class_sysconfig omap44xx_emif_sysc = {
  852. .rev_offs = 0x0000,
  853. };
  854. static struct omap_hwmod_class omap44xx_emif_hwmod_class = {
  855. .name = "emif",
  856. .sysc = &omap44xx_emif_sysc,
  857. };
  858. /* emif1 */
  859. static struct omap_hwmod_irq_info omap44xx_emif1_irqs[] = {
  860. { .irq = 110 + OMAP44XX_IRQ_GIC_START },
  861. { .irq = -1 }
  862. };
  863. static struct omap_hwmod omap44xx_emif1_hwmod = {
  864. .name = "emif1",
  865. .class = &omap44xx_emif_hwmod_class,
  866. .clkdm_name = "l3_emif_clkdm",
  867. .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
  868. .mpu_irqs = omap44xx_emif1_irqs,
  869. .main_clk = "ddrphy_ck",
  870. .prcm = {
  871. .omap4 = {
  872. .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_1_CLKCTRL_OFFSET,
  873. .context_offs = OMAP4_RM_MEMIF_EMIF_1_CONTEXT_OFFSET,
  874. .modulemode = MODULEMODE_HWCTRL,
  875. },
  876. },
  877. };
  878. /* emif2 */
  879. static struct omap_hwmod_irq_info omap44xx_emif2_irqs[] = {
  880. { .irq = 111 + OMAP44XX_IRQ_GIC_START },
  881. { .irq = -1 }
  882. };
  883. static struct omap_hwmod omap44xx_emif2_hwmod = {
  884. .name = "emif2",
  885. .class = &omap44xx_emif_hwmod_class,
  886. .clkdm_name = "l3_emif_clkdm",
  887. .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
  888. .mpu_irqs = omap44xx_emif2_irqs,
  889. .main_clk = "ddrphy_ck",
  890. .prcm = {
  891. .omap4 = {
  892. .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_2_CLKCTRL_OFFSET,
  893. .context_offs = OMAP4_RM_MEMIF_EMIF_2_CONTEXT_OFFSET,
  894. .modulemode = MODULEMODE_HWCTRL,
  895. },
  896. },
  897. };
  898. /*
  899. * 'fdif' class
  900. * face detection hw accelerator module
  901. */
  902. static struct omap_hwmod_class_sysconfig omap44xx_fdif_sysc = {
  903. .rev_offs = 0x0000,
  904. .sysc_offs = 0x0010,
  905. /*
  906. * FDIF needs 100 OCP clk cycles delay after a softreset before
  907. * accessing sysconfig again.
  908. * The lowest frequency at the moment for L3 bus is 100 MHz, so
  909. * 1usec delay is needed. Add an x2 margin to be safe (2 usecs).
  910. *
  911. * TODO: Indicate errata when available.
  912. */
  913. .srst_udelay = 2,
  914. .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
  915. SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
  916. .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
  917. MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
  918. .sysc_fields = &omap_hwmod_sysc_type2,
  919. };
  920. static struct omap_hwmod_class omap44xx_fdif_hwmod_class = {
  921. .name = "fdif",
  922. .sysc = &omap44xx_fdif_sysc,
  923. };
  924. /* fdif */
  925. static struct omap_hwmod_irq_info omap44xx_fdif_irqs[] = {
  926. { .irq = 69 + OMAP44XX_IRQ_GIC_START },
  927. { .irq = -1 }
  928. };
  929. static struct omap_hwmod omap44xx_fdif_hwmod = {
  930. .name = "fdif",
  931. .class = &omap44xx_fdif_hwmod_class,
  932. .clkdm_name = "iss_clkdm",
  933. .mpu_irqs = omap44xx_fdif_irqs,
  934. .main_clk = "fdif_fck",
  935. .prcm = {
  936. .omap4 = {
  937. .clkctrl_offs = OMAP4_CM_CAM_FDIF_CLKCTRL_OFFSET,
  938. .context_offs = OMAP4_RM_CAM_FDIF_CONTEXT_OFFSET,
  939. .modulemode = MODULEMODE_SWCTRL,
  940. },
  941. },
  942. };
  943. /*
  944. * 'gpio' class
  945. * general purpose io module
  946. */
  947. static struct omap_hwmod_class_sysconfig omap44xx_gpio_sysc = {
  948. .rev_offs = 0x0000,
  949. .sysc_offs = 0x0010,
  950. .syss_offs = 0x0114,
  951. .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
  952. SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
  953. SYSS_HAS_RESET_STATUS),
  954. .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
  955. SIDLE_SMART_WKUP),
  956. .sysc_fields = &omap_hwmod_sysc_type1,
  957. };
  958. static struct omap_hwmod_class omap44xx_gpio_hwmod_class = {
  959. .name = "gpio",
  960. .sysc = &omap44xx_gpio_sysc,
  961. .rev = 2,
  962. };
  963. /* gpio dev_attr */
  964. static struct omap_gpio_dev_attr gpio_dev_attr = {
  965. .bank_width = 32,
  966. .dbck_flag = true,
  967. };
  968. /* gpio1 */
  969. static struct omap_hwmod_irq_info omap44xx_gpio1_irqs[] = {
  970. { .irq = 29 + OMAP44XX_IRQ_GIC_START },
  971. { .irq = -1 }
  972. };
  973. static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
  974. { .role = "dbclk", .clk = "gpio1_dbclk" },
  975. };
  976. static struct omap_hwmod omap44xx_gpio1_hwmod = {
  977. .name = "gpio1",
  978. .class = &omap44xx_gpio_hwmod_class,
  979. .clkdm_name = "l4_wkup_clkdm",
  980. .mpu_irqs = omap44xx_gpio1_irqs,
  981. .main_clk = "gpio1_ick",
  982. .prcm = {
  983. .omap4 = {
  984. .clkctrl_offs = OMAP4_CM_WKUP_GPIO1_CLKCTRL_OFFSET,
  985. .context_offs = OMAP4_RM_WKUP_GPIO1_CONTEXT_OFFSET,
  986. .modulemode = MODULEMODE_HWCTRL,
  987. },
  988. },
  989. .opt_clks = gpio1_opt_clks,
  990. .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
  991. .dev_attr = &gpio_dev_attr,
  992. };
  993. /* gpio2 */
  994. static struct omap_hwmod_irq_info omap44xx_gpio2_irqs[] = {
  995. { .irq = 30 + OMAP44XX_IRQ_GIC_START },
  996. { .irq = -1 }
  997. };
  998. static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
  999. { .role = "dbclk", .clk = "gpio2_dbclk" },
  1000. };
  1001. static struct omap_hwmod omap44xx_gpio2_hwmod = {
  1002. .name = "gpio2",
  1003. .class = &omap44xx_gpio_hwmod_class,
  1004. .clkdm_name = "l4_per_clkdm",
  1005. .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
  1006. .mpu_irqs = omap44xx_gpio2_irqs,
  1007. .main_clk = "gpio2_ick",
  1008. .prcm = {
  1009. .omap4 = {
  1010. .clkctrl_offs = OMAP4_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
  1011. .context_offs = OMAP4_RM_L4PER_GPIO2_CONTEXT_OFFSET,
  1012. .modulemode = MODULEMODE_HWCTRL,
  1013. },
  1014. },
  1015. .opt_clks = gpio2_opt_clks,
  1016. .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
  1017. .dev_attr = &gpio_dev_attr,
  1018. };
  1019. /* gpio3 */
  1020. static struct omap_hwmod_irq_info omap44xx_gpio3_irqs[] = {
  1021. { .irq = 31 + OMAP44XX_IRQ_GIC_START },
  1022. { .irq = -1 }
  1023. };
  1024. static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
  1025. { .role = "dbclk", .clk = "gpio3_dbclk" },
  1026. };
  1027. static struct omap_hwmod omap44xx_gpio3_hwmod = {
  1028. .name = "gpio3",
  1029. .class = &omap44xx_gpio_hwmod_class,
  1030. .clkdm_name = "l4_per_clkdm",
  1031. .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
  1032. .mpu_irqs = omap44xx_gpio3_irqs,
  1033. .main_clk = "gpio3_ick",
  1034. .prcm = {
  1035. .omap4 = {
  1036. .clkctrl_offs = OMAP4_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
  1037. .context_offs = OMAP4_RM_L4PER_GPIO3_CONTEXT_OFFSET,
  1038. .modulemode = MODULEMODE_HWCTRL,
  1039. },
  1040. },
  1041. .opt_clks = gpio3_opt_clks,
  1042. .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
  1043. .dev_attr = &gpio_dev_attr,
  1044. };
  1045. /* gpio4 */
  1046. static struct omap_hwmod_irq_info omap44xx_gpio4_irqs[] = {
  1047. { .irq = 32 + OMAP44XX_IRQ_GIC_START },
  1048. { .irq = -1 }
  1049. };
  1050. static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
  1051. { .role = "dbclk", .clk = "gpio4_dbclk" },
  1052. };
  1053. static struct omap_hwmod omap44xx_gpio4_hwmod = {
  1054. .name = "gpio4",
  1055. .class = &omap44xx_gpio_hwmod_class,
  1056. .clkdm_name = "l4_per_clkdm",
  1057. .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
  1058. .mpu_irqs = omap44xx_gpio4_irqs,
  1059. .main_clk = "gpio4_ick",
  1060. .prcm = {
  1061. .omap4 = {
  1062. .clkctrl_offs = OMAP4_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
  1063. .context_offs = OMAP4_RM_L4PER_GPIO4_CONTEXT_OFFSET,
  1064. .modulemode = MODULEMODE_HWCTRL,
  1065. },
  1066. },
  1067. .opt_clks = gpio4_opt_clks,
  1068. .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
  1069. .dev_attr = &gpio_dev_attr,
  1070. };
  1071. /* gpio5 */
  1072. static struct omap_hwmod_irq_info omap44xx_gpio5_irqs[] = {
  1073. { .irq = 33 + OMAP44XX_IRQ_GIC_START },
  1074. { .irq = -1 }
  1075. };
  1076. static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
  1077. { .role = "dbclk", .clk = "gpio5_dbclk" },
  1078. };
  1079. static struct omap_hwmod omap44xx_gpio5_hwmod = {
  1080. .name = "gpio5",
  1081. .class = &omap44xx_gpio_hwmod_class,
  1082. .clkdm_name = "l4_per_clkdm",
  1083. .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
  1084. .mpu_irqs = omap44xx_gpio5_irqs,
  1085. .main_clk = "gpio5_ick",
  1086. .prcm = {
  1087. .omap4 = {
  1088. .clkctrl_offs = OMAP4_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
  1089. .context_offs = OMAP4_RM_L4PER_GPIO5_CONTEXT_OFFSET,
  1090. .modulemode = MODULEMODE_HWCTRL,
  1091. },
  1092. },
  1093. .opt_clks = gpio5_opt_clks,
  1094. .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
  1095. .dev_attr = &gpio_dev_attr,
  1096. };
  1097. /* gpio6 */
  1098. static struct omap_hwmod_irq_info omap44xx_gpio6_irqs[] = {
  1099. { .irq = 34 + OMAP44XX_IRQ_GIC_START },
  1100. { .irq = -1 }
  1101. };
  1102. static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
  1103. { .role = "dbclk", .clk = "gpio6_dbclk" },
  1104. };
  1105. static struct omap_hwmod omap44xx_gpio6_hwmod = {
  1106. .name = "gpio6",
  1107. .class = &omap44xx_gpio_hwmod_class,
  1108. .clkdm_name = "l4_per_clkdm",
  1109. .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
  1110. .mpu_irqs = omap44xx_gpio6_irqs,
  1111. .main_clk = "gpio6_ick",
  1112. .prcm = {
  1113. .omap4 = {
  1114. .clkctrl_offs = OMAP4_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
  1115. .context_offs = OMAP4_RM_L4PER_GPIO6_CONTEXT_OFFSET,
  1116. .modulemode = MODULEMODE_HWCTRL,
  1117. },
  1118. },
  1119. .opt_clks = gpio6_opt_clks,
  1120. .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks),
  1121. .dev_attr = &gpio_dev_attr,
  1122. };
  1123. /*
  1124. * 'gpmc' class
  1125. * general purpose memory controller
  1126. */
  1127. static struct omap_hwmod_class_sysconfig omap44xx_gpmc_sysc = {
  1128. .rev_offs = 0x0000,
  1129. .sysc_offs = 0x0010,
  1130. .syss_offs = 0x0014,
  1131. .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
  1132. SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
  1133. .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
  1134. .sysc_fields = &omap_hwmod_sysc_type1,
  1135. };
  1136. static struct omap_hwmod_class omap44xx_gpmc_hwmod_class = {
  1137. .name = "gpmc",
  1138. .sysc = &omap44xx_gpmc_sysc,
  1139. };
  1140. /* gpmc */
  1141. static struct omap_hwmod_irq_info omap44xx_gpmc_irqs[] = {
  1142. { .irq = 20 + OMAP44XX_IRQ_GIC_START },
  1143. { .irq = -1 }
  1144. };
  1145. static struct omap_hwmod_dma_info omap44xx_gpmc_sdma_reqs[] = {
  1146. { .dma_req = 3 + OMAP44XX_DMA_REQ_START },
  1147. { .dma_req = -1 }
  1148. };
  1149. static struct omap_hwmod omap44xx_gpmc_hwmod = {
  1150. .name = "gpmc",
  1151. .class = &omap44xx_gpmc_hwmod_class,
  1152. .clkdm_name = "l3_2_clkdm",
  1153. .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
  1154. .mpu_irqs = omap44xx_gpmc_irqs,
  1155. .sdma_reqs = omap44xx_gpmc_sdma_reqs,
  1156. .prcm = {
  1157. .omap4 = {
  1158. .clkctrl_offs = OMAP4_CM_L3_2_GPMC_CLKCTRL_OFFSET,
  1159. .context_offs = OMAP4_RM_L3_2_GPMC_CONTEXT_OFFSET,
  1160. .modulemode = MODULEMODE_HWCTRL,
  1161. },
  1162. },
  1163. };
  1164. /*
  1165. * 'gpu' class
  1166. * 2d/3d graphics accelerator
  1167. */
  1168. static struct omap_hwmod_class_sysconfig omap44xx_gpu_sysc = {
  1169. .rev_offs = 0x1fc00,
  1170. .sysc_offs = 0x1fc10,
  1171. .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
  1172. .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
  1173. SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
  1174. MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
  1175. .sysc_fields = &omap_hwmod_sysc_type2,
  1176. };
  1177. static struct omap_hwmod_class omap44xx_gpu_hwmod_class = {
  1178. .name = "gpu",
  1179. .sysc = &omap44xx_gpu_sysc,
  1180. };
  1181. /* gpu */
  1182. static struct omap_hwmod_irq_info omap44xx_gpu_irqs[] = {
  1183. { .irq = 21 + OMAP44XX_IRQ_GIC_START },
  1184. { .irq = -1 }
  1185. };
  1186. static struct omap_hwmod omap44xx_gpu_hwmod = {
  1187. .name = "gpu",
  1188. .class = &omap44xx_gpu_hwmod_class,
  1189. .clkdm_name = "l3_gfx_clkdm",
  1190. .mpu_irqs = omap44xx_gpu_irqs,
  1191. .main_clk = "gpu_fck",
  1192. .prcm = {
  1193. .omap4 = {
  1194. .clkctrl_offs = OMAP4_CM_GFX_GFX_CLKCTRL_OFFSET,
  1195. .context_offs = OMAP4_RM_GFX_GFX_CONTEXT_OFFSET,
  1196. .modulemode = MODULEMODE_SWCTRL,
  1197. },
  1198. },
  1199. };
  1200. /*
  1201. * 'hdq1w' class
  1202. * hdq / 1-wire serial interface controller
  1203. */
  1204. static struct omap_hwmod_class_sysconfig omap44xx_hdq1w_sysc = {
  1205. .rev_offs = 0x0000,
  1206. .sysc_offs = 0x0014,
  1207. .syss_offs = 0x0018,
  1208. .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET |
  1209. SYSS_HAS_RESET_STATUS),
  1210. .sysc_fields = &omap_hwmod_sysc_type1,
  1211. };
  1212. static struct omap_hwmod_class omap44xx_hdq1w_hwmod_class = {
  1213. .name = "hdq1w",
  1214. .sysc = &omap44xx_hdq1w_sysc,
  1215. };
  1216. /* hdq1w */
  1217. static struct omap_hwmod_irq_info omap44xx_hdq1w_irqs[] = {
  1218. { .irq = 58 + OMAP44XX_IRQ_GIC_START },
  1219. { .irq = -1 }
  1220. };
  1221. static struct omap_hwmod omap44xx_hdq1w_hwmod = {
  1222. .name = "hdq1w",
  1223. .class = &omap44xx_hdq1w_hwmod_class,
  1224. .clkdm_name = "l4_per_clkdm",
  1225. .flags = HWMOD_INIT_NO_RESET, /* XXX temporary */
  1226. .mpu_irqs = omap44xx_hdq1w_irqs,
  1227. .main_clk = "hdq1w_fck",
  1228. .prcm = {
  1229. .omap4 = {
  1230. .clkctrl_offs = OMAP4_CM_L4PER_HDQ1W_CLKCTRL_OFFSET,
  1231. .context_offs = OMAP4_RM_L4PER_HDQ1W_CONTEXT_OFFSET,
  1232. .modulemode = MODULEMODE_SWCTRL,
  1233. },
  1234. },
  1235. };
  1236. /*
  1237. * 'hsi' class
  1238. * mipi high-speed synchronous serial interface (multichannel and full-duplex
  1239. * serial if)
  1240. */
  1241. static struct omap_hwmod_class_sysconfig omap44xx_hsi_sysc = {
  1242. .rev_offs = 0x0000,
  1243. .sysc_offs = 0x0010,
  1244. .syss_offs = 0x0014,
  1245. .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_EMUFREE |
  1246. SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
  1247. SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
  1248. .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
  1249. SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
  1250. MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
  1251. .sysc_fields = &omap_hwmod_sysc_type1,
  1252. };
  1253. static struct omap_hwmod_class omap44xx_hsi_hwmod_class = {
  1254. .name = "hsi",
  1255. .sysc = &omap44xx_hsi_sysc,
  1256. };
  1257. /* hsi */
  1258. static struct omap_hwmod_irq_info omap44xx_hsi_irqs[] = {
  1259. { .name = "mpu_p1", .irq = 67 + OMAP44XX_IRQ_GIC_START },
  1260. { .name = "mpu_p2", .irq = 68 + OMAP44XX_IRQ_GIC_START },
  1261. { .name = "mpu_dma", .irq = 71 + OMAP44XX_IRQ_GIC_START },
  1262. { .irq = -1 }
  1263. };
  1264. static struct omap_hwmod omap44xx_hsi_hwmod = {
  1265. .name = "hsi",
  1266. .class = &omap44xx_hsi_hwmod_class,
  1267. .clkdm_name = "l3_init_clkdm",
  1268. .mpu_irqs = omap44xx_hsi_irqs,
  1269. .main_clk = "hsi_fck",
  1270. .prcm = {
  1271. .omap4 = {
  1272. .clkctrl_offs = OMAP4_CM_L3INIT_HSI_CLKCTRL_OFFSET,
  1273. .context_offs = OMAP4_RM_L3INIT_HSI_CONTEXT_OFFSET,
  1274. .modulemode = MODULEMODE_HWCTRL,
  1275. },
  1276. },
  1277. };
  1278. /*
  1279. * 'i2c' class
  1280. * multimaster high-speed i2c controller
  1281. */
  1282. static struct omap_hwmod_class_sysconfig omap44xx_i2c_sysc = {
  1283. .sysc_offs = 0x0010,
  1284. .syss_offs = 0x0090,
  1285. .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
  1286. SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
  1287. SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
  1288. .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
  1289. SIDLE_SMART_WKUP),
  1290. .clockact = CLOCKACT_TEST_ICLK,
  1291. .sysc_fields = &omap_hwmod_sysc_type1,
  1292. };
  1293. static struct omap_hwmod_class omap44xx_i2c_hwmod_class = {
  1294. .name = "i2c",
  1295. .sysc = &omap44xx_i2c_sysc,
  1296. .rev = OMAP_I2C_IP_VERSION_2,
  1297. .reset = &omap_i2c_reset,
  1298. };
  1299. static struct omap_i2c_dev_attr i2c_dev_attr = {
  1300. .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
  1301. };
  1302. /* i2c1 */
  1303. static struct omap_hwmod_irq_info omap44xx_i2c1_irqs[] = {
  1304. { .irq = 56 + OMAP44XX_IRQ_GIC_START },
  1305. { .irq = -1 }
  1306. };
  1307. static struct omap_hwmod_dma_info omap44xx_i2c1_sdma_reqs[] = {
  1308. { .name = "tx", .dma_req = 26 + OMAP44XX_DMA_REQ_START },
  1309. { .name = "rx", .dma_req = 27 + OMAP44XX_DMA_REQ_START },
  1310. { .dma_req = -1 }
  1311. };
  1312. static struct omap_hwmod omap44xx_i2c1_hwmod = {
  1313. .name = "i2c1",
  1314. .class = &omap44xx_i2c_hwmod_class,
  1315. .clkdm_name = "l4_per_clkdm",
  1316. .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
  1317. .mpu_irqs = omap44xx_i2c1_irqs,
  1318. .sdma_reqs = omap44xx_i2c1_sdma_reqs,
  1319. .main_clk = "i2c1_fck",
  1320. .prcm = {
  1321. .omap4 = {
  1322. .clkctrl_offs = OMAP4_CM_L4PER_I2C1_CLKCTRL_OFFSET,
  1323. .context_offs = OMAP4_RM_L4PER_I2C1_CONTEXT_OFFSET,
  1324. .modulemode = MODULEMODE_SWCTRL,
  1325. },
  1326. },
  1327. .dev_attr = &i2c_dev_attr,
  1328. };
  1329. /* i2c2 */
  1330. static struct omap_hwmod_irq_info omap44xx_i2c2_irqs[] = {
  1331. { .irq = 57 + OMAP44XX_IRQ_GIC_START },
  1332. { .irq = -1 }
  1333. };
  1334. static struct omap_hwmod_dma_info omap44xx_i2c2_sdma_reqs[] = {
  1335. { .name = "tx", .dma_req = 28 + OMAP44XX_DMA_REQ_START },
  1336. { .name = "rx", .dma_req = 29 + OMAP44XX_DMA_REQ_START },
  1337. { .dma_req = -1 }
  1338. };
  1339. static struct omap_hwmod omap44xx_i2c2_hwmod = {
  1340. .name = "i2c2",
  1341. .class = &omap44xx_i2c_hwmod_class,
  1342. .clkdm_name = "l4_per_clkdm",
  1343. .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
  1344. .mpu_irqs = omap44xx_i2c2_irqs,
  1345. .sdma_reqs = omap44xx_i2c2_sdma_reqs,
  1346. .main_clk = "i2c2_fck",
  1347. .prcm = {
  1348. .omap4 = {
  1349. .clkctrl_offs = OMAP4_CM_L4PER_I2C2_CLKCTRL_OFFSET,
  1350. .context_offs = OMAP4_RM_L4PER_I2C2_CONTEXT_OFFSET,
  1351. .modulemode = MODULEMODE_SWCTRL,
  1352. },
  1353. },
  1354. .dev_attr = &i2c_dev_attr,
  1355. };
  1356. /* i2c3 */
  1357. static struct omap_hwmod_irq_info omap44xx_i2c3_irqs[] = {
  1358. { .irq = 61 + OMAP44XX_IRQ_GIC_START },
  1359. { .irq = -1 }
  1360. };
  1361. static struct omap_hwmod_dma_info omap44xx_i2c3_sdma_reqs[] = {
  1362. { .name = "tx", .dma_req = 24 + OMAP44XX_DMA_REQ_START },
  1363. { .name = "rx", .dma_req = 25 + OMAP44XX_DMA_REQ_START },
  1364. { .dma_req = -1 }
  1365. };
  1366. static struct omap_hwmod omap44xx_i2c3_hwmod = {
  1367. .name = "i2c3",
  1368. .class = &omap44xx_i2c_hwmod_class,
  1369. .clkdm_name = "l4_per_clkdm",
  1370. .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
  1371. .mpu_irqs = omap44xx_i2c3_irqs,
  1372. .sdma_reqs = omap44xx_i2c3_sdma_reqs,
  1373. .main_clk = "i2c3_fck",
  1374. .prcm = {
  1375. .omap4 = {
  1376. .clkctrl_offs = OMAP4_CM_L4PER_I2C3_CLKCTRL_OFFSET,
  1377. .context_offs = OMAP4_RM_L4PER_I2C3_CONTEXT_OFFSET,
  1378. .modulemode = MODULEMODE_SWCTRL,
  1379. },
  1380. },
  1381. .dev_attr = &i2c_dev_attr,
  1382. };
  1383. /* i2c4 */
  1384. static struct omap_hwmod_irq_info omap44xx_i2c4_irqs[] = {
  1385. { .irq = 62 + OMAP44XX_IRQ_GIC_START },
  1386. { .irq = -1 }
  1387. };
  1388. static struct omap_hwmod_dma_info omap44xx_i2c4_sdma_reqs[] = {
  1389. { .name = "tx", .dma_req = 123 + OMAP44XX_DMA_REQ_START },
  1390. { .name = "rx", .dma_req = 124 + OMAP44XX_DMA_REQ_START },
  1391. { .dma_req = -1 }
  1392. };
  1393. static struct omap_hwmod omap44xx_i2c4_hwmod = {
  1394. .name = "i2c4",
  1395. .class = &omap44xx_i2c_hwmod_class,
  1396. .clkdm_name = "l4_per_clkdm",
  1397. .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
  1398. .mpu_irqs = omap44xx_i2c4_irqs,
  1399. .sdma_reqs = omap44xx_i2c4_sdma_reqs,
  1400. .main_clk = "i2c4_fck",
  1401. .prcm = {
  1402. .omap4 = {
  1403. .clkctrl_offs = OMAP4_CM_L4PER_I2C4_CLKCTRL_OFFSET,
  1404. .context_offs = OMAP4_RM_L4PER_I2C4_CONTEXT_OFFSET,
  1405. .modulemode = MODULEMODE_SWCTRL,
  1406. },
  1407. },
  1408. .dev_attr = &i2c_dev_attr,
  1409. };
  1410. /*
  1411. * 'ipu' class
  1412. * imaging processor unit
  1413. */
  1414. static struct omap_hwmod_class omap44xx_ipu_hwmod_class = {
  1415. .name = "ipu",
  1416. };
  1417. /* ipu */
  1418. static struct omap_hwmod_irq_info omap44xx_ipu_irqs[] = {
  1419. { .irq = 100 + OMAP44XX_IRQ_GIC_START },
  1420. { .irq = -1 }
  1421. };
  1422. static struct omap_hwmod_rst_info omap44xx_ipu_resets[] = {
  1423. { .name = "cpu0", .rst_shift = 0 },
  1424. { .name = "cpu1", .rst_shift = 1 },
  1425. { .name = "mmu_cache", .rst_shift = 2 },
  1426. };
  1427. static struct omap_hwmod omap44xx_ipu_hwmod = {
  1428. .name = "ipu",
  1429. .class = &omap44xx_ipu_hwmod_class,
  1430. .clkdm_name = "ducati_clkdm",
  1431. .mpu_irqs = omap44xx_ipu_irqs,
  1432. .rst_lines = omap44xx_ipu_resets,
  1433. .rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_resets),
  1434. .main_clk = "ipu_fck",
  1435. .prcm = {
  1436. .omap4 = {
  1437. .clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET,
  1438. .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
  1439. .context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET,
  1440. .modulemode = MODULEMODE_HWCTRL,
  1441. },
  1442. },
  1443. };
  1444. /*
  1445. * 'iss' class
  1446. * external images sensor pixel data processor
  1447. */
  1448. static struct omap_hwmod_class_sysconfig omap44xx_iss_sysc = {
  1449. .rev_offs = 0x0000,
  1450. .sysc_offs = 0x0010,
  1451. /*
  1452. * ISS needs 100 OCP clk cycles delay after a softreset before
  1453. * accessing sysconfig again.
  1454. * The lowest frequency at the moment for L3 bus is 100 MHz, so
  1455. * 1usec delay is needed. Add an x2 margin to be safe (2 usecs).
  1456. *
  1457. * TODO: Indicate errata when available.
  1458. */
  1459. .srst_udelay = 2,
  1460. .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
  1461. SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
  1462. .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
  1463. SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
  1464. MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
  1465. .sysc_fields = &omap_hwmod_sysc_type2,
  1466. };
  1467. static struct omap_hwmod_class omap44xx_iss_hwmod_class = {
  1468. .name = "iss",
  1469. .sysc = &omap44xx_iss_sysc,
  1470. };
  1471. /* iss */
  1472. static struct omap_hwmod_irq_info omap44xx_iss_irqs[] = {
  1473. { .irq = 24 + OMAP44XX_IRQ_GIC_START },
  1474. { .irq = -1 }
  1475. };
  1476. static struct omap_hwmod_dma_info omap44xx_iss_sdma_reqs[] = {
  1477. { .name = "1", .dma_req = 8 + OMAP44XX_DMA_REQ_START },
  1478. { .name = "2", .dma_req = 9 + OMAP44XX_DMA_REQ_START },
  1479. { .name = "3", .dma_req = 11 + OMAP44XX_DMA_REQ_START },
  1480. { .name = "4", .dma_req = 12 + OMAP44XX_DMA_REQ_START },
  1481. { .dma_req = -1 }
  1482. };
  1483. static struct omap_hwmod_opt_clk iss_opt_clks[] = {
  1484. { .role = "ctrlclk", .clk = "iss_ctrlclk" },
  1485. };
  1486. static struct omap_hwmod omap44xx_iss_hwmod = {
  1487. .name = "iss",
  1488. .class = &omap44xx_iss_hwmod_class,
  1489. .clkdm_name = "iss_clkdm",
  1490. .mpu_irqs = omap44xx_iss_irqs,
  1491. .sdma_reqs = omap44xx_iss_sdma_reqs,
  1492. .main_clk = "iss_fck",
  1493. .prcm = {
  1494. .omap4 = {
  1495. .clkctrl_offs = OMAP4_CM_CAM_ISS_CLKCTRL_OFFSET,
  1496. .context_offs = OMAP4_RM_CAM_ISS_CONTEXT_OFFSET,
  1497. .modulemode = MODULEMODE_SWCTRL,
  1498. },
  1499. },
  1500. .opt_clks = iss_opt_clks,
  1501. .opt_clks_cnt = ARRAY_SIZE(iss_opt_clks),
  1502. };
  1503. /*
  1504. * 'iva' class
  1505. * multi-standard video encoder/decoder hardware accelerator
  1506. */
  1507. static struct omap_hwmod_class omap44xx_iva_hwmod_class = {
  1508. .name = "iva",
  1509. };
  1510. /* iva */
  1511. static struct omap_hwmod_irq_info omap44xx_iva_irqs[] = {
  1512. { .name = "sync_1", .irq = 103 + OMAP44XX_IRQ_GIC_START },
  1513. { .name = "sync_0", .irq = 104 + OMAP44XX_IRQ_GIC_START },
  1514. { .name = "mailbox_0", .irq = 107 + OMAP44XX_IRQ_GIC_START },
  1515. { .irq = -1 }
  1516. };
  1517. static struct omap_hwmod_rst_info omap44xx_iva_resets[] = {
  1518. { .name = "seq0", .rst_shift = 0 },
  1519. { .name = "seq1", .rst_shift = 1 },
  1520. { .name = "logic", .rst_shift = 2 },
  1521. };
  1522. static struct omap_hwmod omap44xx_iva_hwmod = {
  1523. .name = "iva",
  1524. .class = &omap44xx_iva_hwmod_class,
  1525. .clkdm_name = "ivahd_clkdm",
  1526. .mpu_irqs = omap44xx_iva_irqs,
  1527. .rst_lines = omap44xx_iva_resets,
  1528. .rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_resets),
  1529. .main_clk = "iva_fck",
  1530. .prcm = {
  1531. .omap4 = {
  1532. .clkctrl_offs = OMAP4_CM_IVAHD_IVAHD_CLKCTRL_OFFSET,
  1533. .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET,
  1534. .context_offs = OMAP4_RM_IVAHD_IVAHD_CONTEXT_OFFSET,
  1535. .modulemode = MODULEMODE_HWCTRL,
  1536. },
  1537. },
  1538. };
  1539. /*
  1540. * 'kbd' class
  1541. * keyboard controller
  1542. */
  1543. static struct omap_hwmod_class_sysconfig omap44xx_kbd_sysc = {
  1544. .rev_offs = 0x0000,
  1545. .sysc_offs = 0x0010,
  1546. .syss_offs = 0x0014,
  1547. .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
  1548. SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
  1549. SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
  1550. SYSS_HAS_RESET_STATUS),
  1551. .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
  1552. .sysc_fields = &omap_hwmod_sysc_type1,
  1553. };
  1554. static struct omap_hwmod_class omap44xx_kbd_hwmod_class = {
  1555. .name = "kbd",
  1556. .sysc = &omap44xx_kbd_sysc,
  1557. };
  1558. /* kbd */
  1559. static struct omap_hwmod_irq_info omap44xx_kbd_irqs[] = {
  1560. { .irq = 120 + OMAP44XX_IRQ_GIC_START },
  1561. { .irq = -1 }
  1562. };
  1563. static struct omap_hwmod omap44xx_kbd_hwmod = {
  1564. .name = "kbd",
  1565. .class = &omap44xx_kbd_hwmod_class,
  1566. .clkdm_name = "l4_wkup_clkdm",
  1567. .mpu_irqs = omap44xx_kbd_irqs,
  1568. .main_clk = "kbd_fck",
  1569. .prcm = {
  1570. .omap4 = {
  1571. .clkctrl_offs = OMAP4_CM_WKUP_KEYBOARD_CLKCTRL_OFFSET,
  1572. .context_offs = OMAP4_RM_WKUP_KEYBOARD_CONTEXT_OFFSET,
  1573. .modulemode = MODULEMODE_SWCTRL,
  1574. },
  1575. },
  1576. };
  1577. /*
  1578. * 'mailbox' class
  1579. * mailbox module allowing communication between the on-chip processors using a
  1580. * queued mailbox-interrupt mechanism.
  1581. */
  1582. static struct omap_hwmod_class_sysconfig omap44xx_mailbox_sysc = {
  1583. .rev_offs = 0x0000,
  1584. .sysc_offs = 0x0010,
  1585. .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
  1586. SYSC_HAS_SOFTRESET),
  1587. .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
  1588. .sysc_fields = &omap_hwmod_sysc_type2,
  1589. };
  1590. static struct omap_hwmod_class omap44xx_mailbox_hwmod_class = {
  1591. .name = "mailbox",
  1592. .sysc = &omap44xx_mailbox_sysc,
  1593. };
  1594. /* mailbox */
  1595. static struct omap_hwmod_irq_info omap44xx_mailbox_irqs[] = {
  1596. { .irq = 26 + OMAP44XX_IRQ_GIC_START },
  1597. { .irq = -1 }
  1598. };
  1599. static struct omap_hwmod omap44xx_mailbox_hwmod = {
  1600. .name = "mailbox",
  1601. .class = &omap44xx_mailbox_hwmod_class,
  1602. .clkdm_name = "l4_cfg_clkdm",
  1603. .mpu_irqs = omap44xx_mailbox_irqs,
  1604. .prcm = {
  1605. .omap4 = {
  1606. .clkctrl_offs = OMAP4_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET,
  1607. .context_offs = OMAP4_RM_L4CFG_MAILBOX_CONTEXT_OFFSET,
  1608. },
  1609. },
  1610. };
  1611. /*
  1612. * 'mcasp' class
  1613. * multi-channel audio serial port controller
  1614. */
  1615. /* The IP is not compliant to type1 / type2 scheme */
  1616. static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_mcasp = {
  1617. .sidle_shift = 0,
  1618. };
  1619. static struct omap_hwmod_class_sysconfig omap44xx_mcasp_sysc = {
  1620. .sysc_offs = 0x0004,
  1621. .sysc_flags = SYSC_HAS_SIDLEMODE,
  1622. .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
  1623. SIDLE_SMART_WKUP),
  1624. .sysc_fields = &omap_hwmod_sysc_type_mcasp,
  1625. };
  1626. static struct omap_hwmod_class omap44xx_mcasp_hwmod_class = {
  1627. .name = "mcasp",
  1628. .sysc = &omap44xx_mcasp_sysc,
  1629. };
  1630. /* mcasp */
  1631. static struct omap_hwmod_irq_info omap44xx_mcasp_irqs[] = {
  1632. { .name = "arevt", .irq = 108 + OMAP44XX_IRQ_GIC_START },
  1633. { .name = "axevt", .irq = 109 + OMAP44XX_IRQ_GIC_START },
  1634. { .irq = -1 }
  1635. };
  1636. static struct omap_hwmod_dma_info omap44xx_mcasp_sdma_reqs[] = {
  1637. { .name = "axevt", .dma_req = 7 + OMAP44XX_DMA_REQ_START },
  1638. { .name = "arevt", .dma_req = 10 + OMAP44XX_DMA_REQ_START },
  1639. { .dma_req = -1 }
  1640. };
  1641. static struct omap_hwmod omap44xx_mcasp_hwmod = {
  1642. .name = "mcasp",
  1643. .class = &omap44xx_mcasp_hwmod_class,
  1644. .clkdm_name = "abe_clkdm",
  1645. .mpu_irqs = omap44xx_mcasp_irqs,
  1646. .sdma_reqs = omap44xx_mcasp_sdma_reqs,
  1647. .main_clk = "mcasp_fck",
  1648. .prcm = {
  1649. .omap4 = {
  1650. .clkctrl_offs = OMAP4_CM1_ABE_MCASP_CLKCTRL_OFFSET,
  1651. .context_offs = OMAP4_RM_ABE_MCASP_CONTEXT_OFFSET,
  1652. .modulemode = MODULEMODE_SWCTRL,
  1653. },
  1654. },
  1655. };
  1656. /*
  1657. * 'mcbsp' class
  1658. * multi channel buffered serial port controller
  1659. */
  1660. static struct omap_hwmod_class_sysconfig omap44xx_mcbsp_sysc = {
  1661. .sysc_offs = 0x008c,
  1662. .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
  1663. SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
  1664. .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
  1665. .sysc_fields = &omap_hwmod_sysc_type1,
  1666. };
  1667. static struct omap_hwmod_class omap44xx_mcbsp_hwmod_class = {
  1668. .name = "mcbsp",
  1669. .sysc = &omap44xx_mcbsp_sysc,
  1670. .rev = MCBSP_CONFIG_TYPE4,
  1671. };
  1672. /* mcbsp1 */
  1673. static struct omap_hwmod_irq_info omap44xx_mcbsp1_irqs[] = {
  1674. { .irq = 17 + OMAP44XX_IRQ_GIC_START },
  1675. { .irq = -1 }
  1676. };
  1677. static struct omap_hwmod_dma_info omap44xx_mcbsp1_sdma_reqs[] = {
  1678. { .name = "tx", .dma_req = 32 + OMAP44XX_DMA_REQ_START },
  1679. { .name = "rx", .dma_req = 33 + OMAP44XX_DMA_REQ_START },
  1680. { .dma_req = -1 }
  1681. };
  1682. static struct omap_hwmod_opt_clk mcbsp1_opt_clks[] = {
  1683. { .role = "pad_fck", .clk = "pad_clks_ck" },
  1684. { .role = "prcm_clk", .clk = "mcbsp1_sync_mux_ck" },
  1685. };
  1686. static struct omap_hwmod omap44xx_mcbsp1_hwmod = {
  1687. .name = "mcbsp1",
  1688. .class = &omap44xx_mcbsp_hwmod_class,
  1689. .clkdm_name = "abe_clkdm",
  1690. .mpu_irqs = omap44xx_mcbsp1_irqs,
  1691. .sdma_reqs = omap44xx_mcbsp1_sdma_reqs,
  1692. .main_clk = "mcbsp1_fck",
  1693. .prcm = {
  1694. .omap4 = {
  1695. .clkctrl_offs = OMAP4_CM1_ABE_MCBSP1_CLKCTRL_OFFSET,
  1696. .context_offs = OMAP4_RM_ABE_MCBSP1_CONTEXT_OFFSET,
  1697. .modulemode = MODULEMODE_SWCTRL,
  1698. },
  1699. },
  1700. .opt_clks = mcbsp1_opt_clks,
  1701. .opt_clks_cnt = ARRAY_SIZE(mcbsp1_opt_clks),
  1702. };
  1703. /* mcbsp2 */
  1704. static struct omap_hwmod_irq_info omap44xx_mcbsp2_irqs[] = {
  1705. { .irq = 22 + OMAP44XX_IRQ_GIC_START },
  1706. { .irq = -1 }
  1707. };
  1708. static struct omap_hwmod_dma_info omap44xx_mcbsp2_sdma_reqs[] = {
  1709. { .name = "tx", .dma_req = 16 + OMAP44XX_DMA_REQ_START },
  1710. { .name = "rx", .dma_req = 17 + OMAP44XX_DMA_REQ_START },
  1711. { .dma_req = -1 }
  1712. };
  1713. static struct omap_hwmod_opt_clk mcbsp2_opt_clks[] = {
  1714. { .role = "pad_fck", .clk = "pad_clks_ck" },
  1715. { .role = "prcm_clk", .clk = "mcbsp2_sync_mux_ck" },
  1716. };
  1717. static struct omap_hwmod omap44xx_mcbsp2_hwmod = {
  1718. .name = "mcbsp2",
  1719. .class = &omap44xx_mcbsp_hwmod_class,
  1720. .clkdm_name = "abe_clkdm",
  1721. .mpu_irqs = omap44xx_mcbsp2_irqs,
  1722. .sdma_reqs = omap44xx_mcbsp2_sdma_reqs,
  1723. .main_clk = "mcbsp2_fck",
  1724. .prcm = {
  1725. .omap4 = {
  1726. .clkctrl_offs = OMAP4_CM1_ABE_MCBSP2_CLKCTRL_OFFSET,
  1727. .context_offs = OMAP4_RM_ABE_MCBSP2_CONTEXT_OFFSET,
  1728. .modulemode = MODULEMODE_SWCTRL,
  1729. },
  1730. },
  1731. .opt_clks = mcbsp2_opt_clks,
  1732. .opt_clks_cnt = ARRAY_SIZE(mcbsp2_opt_clks),
  1733. };
  1734. /* mcbsp3 */
  1735. static struct omap_hwmod_irq_info omap44xx_mcbsp3_irqs[] = {
  1736. { .irq = 23 + OMAP44XX_IRQ_GIC_START },
  1737. { .irq = -1 }
  1738. };
  1739. static struct omap_hwmod_dma_info omap44xx_mcbsp3_sdma_reqs[] = {
  1740. { .name = "tx", .dma_req = 18 + OMAP44XX_DMA_REQ_START },
  1741. { .name = "rx", .dma_req = 19 + OMAP44XX_DMA_REQ_START },
  1742. { .dma_req = -1 }
  1743. };
  1744. static struct omap_hwmod_opt_clk mcbsp3_opt_clks[] = {
  1745. { .role = "pad_fck", .clk = "pad_clks_ck" },
  1746. { .role = "prcm_clk", .clk = "mcbsp3_sync_mux_ck" },
  1747. };
  1748. static struct omap_hwmod omap44xx_mcbsp3_hwmod = {
  1749. .name = "mcbsp3",
  1750. .class = &omap44xx_mcbsp_hwmod_class,
  1751. .clkdm_name = "abe_clkdm",
  1752. .mpu_irqs = omap44xx_mcbsp3_irqs,
  1753. .sdma_reqs = omap44xx_mcbsp3_sdma_reqs,
  1754. .main_clk = "mcbsp3_fck",
  1755. .prcm = {
  1756. .omap4 = {
  1757. .clkctrl_offs = OMAP4_CM1_ABE_MCBSP3_CLKCTRL_OFFSET,
  1758. .context_offs = OMAP4_RM_ABE_MCBSP3_CONTEXT_OFFSET,
  1759. .modulemode = MODULEMODE_SWCTRL,
  1760. },
  1761. },
  1762. .opt_clks = mcbsp3_opt_clks,
  1763. .opt_clks_cnt = ARRAY_SIZE(mcbsp3_opt_clks),
  1764. };
  1765. /* mcbsp4 */
  1766. static struct omap_hwmod_irq_info omap44xx_mcbsp4_irqs[] = {
  1767. { .irq = 16 + OMAP44XX_IRQ_GIC_START },
  1768. { .irq = -1 }
  1769. };
  1770. static struct omap_hwmod_dma_info omap44xx_mcbsp4_sdma_reqs[] = {
  1771. { .name = "tx", .dma_req = 30 + OMAP44XX_DMA_REQ_START },
  1772. { .name = "rx", .dma_req = 31 + OMAP44XX_DMA_REQ_START },
  1773. { .dma_req = -1 }
  1774. };
  1775. static struct omap_hwmod_opt_clk mcbsp4_opt_clks[] = {
  1776. { .role = "pad_fck", .clk = "pad_clks_ck" },
  1777. { .role = "prcm_clk", .clk = "mcbsp4_sync_mux_ck" },
  1778. };
  1779. static struct omap_hwmod omap44xx_mcbsp4_hwmod = {
  1780. .name = "mcbsp4",
  1781. .class = &omap44xx_mcbsp_hwmod_class,
  1782. .clkdm_name = "l4_per_clkdm",
  1783. .mpu_irqs = omap44xx_mcbsp4_irqs,
  1784. .sdma_reqs = omap44xx_mcbsp4_sdma_reqs,
  1785. .main_clk = "mcbsp4_fck",
  1786. .prcm = {
  1787. .omap4 = {
  1788. .clkctrl_offs = OMAP4_CM_L4PER_MCBSP4_CLKCTRL_OFFSET,
  1789. .context_offs = OMAP4_RM_L4PER_MCBSP4_CONTEXT_OFFSET,
  1790. .modulemode = MODULEMODE_SWCTRL,
  1791. },
  1792. },
  1793. .opt_clks = mcbsp4_opt_clks,
  1794. .opt_clks_cnt = ARRAY_SIZE(mcbsp4_opt_clks),
  1795. };
  1796. /*
  1797. * 'mcpdm' class
  1798. * multi channel pdm controller (proprietary interface with phoenix power
  1799. * ic)
  1800. */
  1801. static struct omap_hwmod_class_sysconfig omap44xx_mcpdm_sysc = {
  1802. .rev_offs = 0x0000,
  1803. .sysc_offs = 0x0010,
  1804. .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
  1805. SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
  1806. .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
  1807. SIDLE_SMART_WKUP),
  1808. .sysc_fields = &omap_hwmod_sysc_type2,
  1809. };
  1810. static struct omap_hwmod_class omap44xx_mcpdm_hwmod_class = {
  1811. .name = "mcpdm",
  1812. .sysc = &omap44xx_mcpdm_sysc,
  1813. };
  1814. /* mcpdm */
  1815. static struct omap_hwmod_irq_info omap44xx_mcpdm_irqs[] = {
  1816. { .irq = 112 + OMAP44XX_IRQ_GIC_START },
  1817. { .irq = -1 }
  1818. };
  1819. static struct omap_hwmod_dma_info omap44xx_mcpdm_sdma_reqs[] = {
  1820. { .name = "up_link", .dma_req = 64 + OMAP44XX_DMA_REQ_START },
  1821. { .name = "dn_link", .dma_req = 65 + OMAP44XX_DMA_REQ_START },
  1822. { .dma_req = -1 }
  1823. };
  1824. static struct omap_hwmod omap44xx_mcpdm_hwmod = {
  1825. .name = "mcpdm",
  1826. .class = &omap44xx_mcpdm_hwmod_class,
  1827. .clkdm_name = "abe_clkdm",
  1828. .mpu_irqs = omap44xx_mcpdm_irqs,
  1829. .sdma_reqs = omap44xx_mcpdm_sdma_reqs,
  1830. .main_clk = "mcpdm_fck",
  1831. .prcm = {
  1832. .omap4 = {
  1833. .clkctrl_offs = OMAP4_CM1_ABE_PDM_CLKCTRL_OFFSET,
  1834. .context_offs = OMAP4_RM_ABE_PDM_CONTEXT_OFFSET,
  1835. .modulemode = MODULEMODE_SWCTRL,
  1836. },
  1837. },
  1838. };
  1839. /*
  1840. * 'mcspi' class
  1841. * multichannel serial port interface (mcspi) / master/slave synchronous serial
  1842. * bus
  1843. */
  1844. static struct omap_hwmod_class_sysconfig omap44xx_mcspi_sysc = {
  1845. .rev_offs = 0x0000,
  1846. .sysc_offs = 0x0010,
  1847. .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
  1848. SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
  1849. .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
  1850. SIDLE_SMART_WKUP),
  1851. .sysc_fields = &omap_hwmod_sysc_type2,
  1852. };
  1853. static struct omap_hwmod_class omap44xx_mcspi_hwmod_class = {
  1854. .name = "mcspi",
  1855. .sysc = &omap44xx_mcspi_sysc,
  1856. .rev = OMAP4_MCSPI_REV,
  1857. };
  1858. /* mcspi1 */
  1859. static struct omap_hwmod_irq_info omap44xx_mcspi1_irqs[] = {
  1860. { .irq = 65 + OMAP44XX_IRQ_GIC_START },
  1861. { .irq = -1 }
  1862. };
  1863. static struct omap_hwmod_dma_info omap44xx_mcspi1_sdma_reqs[] = {
  1864. { .name = "tx0", .dma_req = 34 + OMAP44XX_DMA_REQ_START },
  1865. { .name = "rx0", .dma_req = 35 + OMAP44XX_DMA_REQ_START },
  1866. { .name = "tx1", .dma_req = 36 + OMAP44XX_DMA_REQ_START },
  1867. { .name = "rx1", .dma_req = 37 + OMAP44XX_DMA_REQ_START },
  1868. { .name = "tx2", .dma_req = 38 + OMAP44XX_DMA_REQ_START },
  1869. { .name = "rx2", .dma_req = 39 + OMAP44XX_DMA_REQ_START },
  1870. { .name = "tx3", .dma_req = 40 + OMAP44XX_DMA_REQ_START },
  1871. { .name = "rx3", .dma_req = 41 + OMAP44XX_DMA_REQ_START },
  1872. { .dma_req = -1 }
  1873. };
  1874. /* mcspi1 dev_attr */
  1875. static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
  1876. .num_chipselect = 4,
  1877. };
  1878. static struct omap_hwmod omap44xx_mcspi1_hwmod = {
  1879. .name = "mcspi1",
  1880. .class = &omap44xx_mcspi_hwmod_class,
  1881. .clkdm_name = "l4_per_clkdm",
  1882. .mpu_irqs = omap44xx_mcspi1_irqs,
  1883. .sdma_reqs = omap44xx_mcspi1_sdma_reqs,
  1884. .main_clk = "mcspi1_fck",
  1885. .prcm = {
  1886. .omap4 = {
  1887. .clkctrl_offs = OMAP4_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
  1888. .context_offs = OMAP4_RM_L4PER_MCSPI1_CONTEXT_OFFSET,
  1889. .modulemode = MODULEMODE_SWCTRL,
  1890. },
  1891. },
  1892. .dev_attr = &mcspi1_dev_attr,
  1893. };
  1894. /* mcspi2 */
  1895. static struct omap_hwmod_irq_info omap44xx_mcspi2_irqs[] = {
  1896. { .irq = 66 + OMAP44XX_IRQ_GIC_START },
  1897. { .irq = -1 }
  1898. };
  1899. static struct omap_hwmod_dma_info omap44xx_mcspi2_sdma_reqs[] = {
  1900. { .name = "tx0", .dma_req = 42 + OMAP44XX_DMA_REQ_START },
  1901. { .name = "rx0", .dma_req = 43 + OMAP44XX_DMA_REQ_START },
  1902. { .name = "tx1", .dma_req = 44 + OMAP44XX_DMA_REQ_START },
  1903. { .name = "rx1", .dma_req = 45 + OMAP44XX_DMA_REQ_START },
  1904. { .dma_req = -1 }
  1905. };
  1906. /* mcspi2 dev_attr */
  1907. static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
  1908. .num_chipselect = 2,
  1909. };
  1910. static struct omap_hwmod omap44xx_mcspi2_hwmod = {
  1911. .name = "mcspi2",
  1912. .class = &omap44xx_mcspi_hwmod_class,
  1913. .clkdm_name = "l4_per_clkdm",
  1914. .mpu_irqs = omap44xx_mcspi2_irqs,
  1915. .sdma_reqs = omap44xx_mcspi2_sdma_reqs,
  1916. .main_clk = "mcspi2_fck",
  1917. .prcm = {
  1918. .omap4 = {
  1919. .clkctrl_offs = OMAP4_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
  1920. .context_offs = OMAP4_RM_L4PER_MCSPI2_CONTEXT_OFFSET,
  1921. .modulemode = MODULEMODE_SWCTRL,
  1922. },
  1923. },
  1924. .dev_attr = &mcspi2_dev_attr,
  1925. };
  1926. /* mcspi3 */
  1927. static struct omap_hwmod_irq_info omap44xx_mcspi3_irqs[] = {
  1928. { .irq = 91 + OMAP44XX_IRQ_GIC_START },
  1929. { .irq = -1 }
  1930. };
  1931. static struct omap_hwmod_dma_info omap44xx_mcspi3_sdma_reqs[] = {
  1932. { .name = "tx0", .dma_req = 14 + OMAP44XX_DMA_REQ_START },
  1933. { .name = "rx0", .dma_req = 15 + OMAP44XX_DMA_REQ_START },
  1934. { .name = "tx1", .dma_req = 22 + OMAP44XX_DMA_REQ_START },
  1935. { .name = "rx1", .dma_req = 23 + OMAP44XX_DMA_REQ_START },
  1936. { .dma_req = -1 }
  1937. };
  1938. /* mcspi3 dev_attr */
  1939. static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
  1940. .num_chipselect = 2,
  1941. };
  1942. static struct omap_hwmod omap44xx_mcspi3_hwmod = {
  1943. .name = "mcspi3",
  1944. .class = &omap44xx_mcspi_hwmod_class,
  1945. .clkdm_name = "l4_per_clkdm",
  1946. .mpu_irqs = omap44xx_mcspi3_irqs,
  1947. .sdma_reqs = omap44xx_mcspi3_sdma_reqs,
  1948. .main_clk = "mcspi3_fck",
  1949. .prcm = {
  1950. .omap4 = {
  1951. .clkctrl_offs = OMAP4_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
  1952. .context_offs = OMAP4_RM_L4PER_MCSPI3_CONTEXT_OFFSET,
  1953. .modulemode = MODULEMODE_SWCTRL,
  1954. },
  1955. },
  1956. .dev_attr = &mcspi3_dev_attr,
  1957. };
  1958. /* mcspi4 */
  1959. static struct omap_hwmod_irq_info omap44xx_mcspi4_irqs[] = {
  1960. { .irq = 48 + OMAP44XX_IRQ_GIC_START },
  1961. { .irq = -1 }
  1962. };
  1963. static struct omap_hwmod_dma_info omap44xx_mcspi4_sdma_reqs[] = {
  1964. { .name = "tx0", .dma_req = 69 + OMAP44XX_DMA_REQ_START },
  1965. { .name = "rx0", .dma_req = 70 + OMAP44XX_DMA_REQ_START },
  1966. { .dma_req = -1 }
  1967. };
  1968. /* mcspi4 dev_attr */
  1969. static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
  1970. .num_chipselect = 1,
  1971. };
  1972. static struct omap_hwmod omap44xx_mcspi4_hwmod = {
  1973. .name = "mcspi4",
  1974. .class = &omap44xx_mcspi_hwmod_class,
  1975. .clkdm_name = "l4_per_clkdm",
  1976. .mpu_irqs = omap44xx_mcspi4_irqs,
  1977. .sdma_reqs = omap44xx_mcspi4_sdma_reqs,
  1978. .main_clk = "mcspi4_fck",
  1979. .prcm = {
  1980. .omap4 = {
  1981. .clkctrl_offs = OMAP4_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
  1982. .context_offs = OMAP4_RM_L4PER_MCSPI4_CONTEXT_OFFSET,
  1983. .modulemode = MODULEMODE_SWCTRL,
  1984. },
  1985. },
  1986. .dev_attr = &mcspi4_dev_attr,
  1987. };
  1988. /*
  1989. * 'mmc' class
  1990. * multimedia card high-speed/sd/sdio (mmc/sd/sdio) host controller
  1991. */
  1992. static struct omap_hwmod_class_sysconfig omap44xx_mmc_sysc = {
  1993. .rev_offs = 0x0000,
  1994. .sysc_offs = 0x0010,
  1995. .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
  1996. SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
  1997. SYSC_HAS_SOFTRESET),
  1998. .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
  1999. SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
  2000. MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
  2001. .sysc_fields = &omap_hwmod_sysc_type2,
  2002. };
  2003. static struct omap_hwmod_class omap44xx_mmc_hwmod_class = {
  2004. .name = "mmc",
  2005. .sysc = &omap44xx_mmc_sysc,
  2006. };
  2007. /* mmc1 */
  2008. static struct omap_hwmod_irq_info omap44xx_mmc1_irqs[] = {
  2009. { .irq = 83 + OMAP44XX_IRQ_GIC_START },
  2010. { .irq = -1 }
  2011. };
  2012. static struct omap_hwmod_dma_info omap44xx_mmc1_sdma_reqs[] = {
  2013. { .name = "tx", .dma_req = 60 + OMAP44XX_DMA_REQ_START },
  2014. { .name = "rx", .dma_req = 61 + OMAP44XX_DMA_REQ_START },
  2015. { .dma_req = -1 }
  2016. };
  2017. /* mmc1 dev_attr */
  2018. static struct omap_mmc_dev_attr mmc1_dev_attr = {
  2019. .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
  2020. };
  2021. static struct omap_hwmod omap44xx_mmc1_hwmod = {
  2022. .name = "mmc1",
  2023. .class = &omap44xx_mmc_hwmod_class,
  2024. .clkdm_name = "l3_init_clkdm",
  2025. .mpu_irqs = omap44xx_mmc1_irqs,
  2026. .sdma_reqs = omap44xx_mmc1_sdma_reqs,
  2027. .main_clk = "mmc1_fck",
  2028. .prcm = {
  2029. .omap4 = {
  2030. .clkctrl_offs = OMAP4_CM_L3INIT_MMC1_CLKCTRL_OFFSET,
  2031. .context_offs = OMAP4_RM_L3INIT_MMC1_CONTEXT_OFFSET,
  2032. .modulemode = MODULEMODE_SWCTRL,
  2033. },
  2034. },
  2035. .dev_attr = &mmc1_dev_attr,
  2036. };
  2037. /* mmc2 */
  2038. static struct omap_hwmod_irq_info omap44xx_mmc2_irqs[] = {
  2039. { .irq = 86 + OMAP44XX_IRQ_GIC_START },
  2040. { .irq = -1 }
  2041. };
  2042. static struct omap_hwmod_dma_info omap44xx_mmc2_sdma_reqs[] = {
  2043. { .name = "tx", .dma_req = 46 + OMAP44XX_DMA_REQ_START },
  2044. { .name = "rx", .dma_req = 47 + OMAP44XX_DMA_REQ_START },
  2045. { .dma_req = -1 }
  2046. };
  2047. static struct omap_hwmod omap44xx_mmc2_hwmod = {
  2048. .name = "mmc2",
  2049. .class = &omap44xx_mmc_hwmod_class,
  2050. .clkdm_name = "l3_init_clkdm",
  2051. .mpu_irqs = omap44xx_mmc2_irqs,
  2052. .sdma_reqs = omap44xx_mmc2_sdma_reqs,
  2053. .main_clk = "mmc2_fck",
  2054. .prcm = {
  2055. .omap4 = {
  2056. .clkctrl_offs = OMAP4_CM_L3INIT_MMC2_CLKCTRL_OFFSET,
  2057. .context_offs = OMAP4_RM_L3INIT_MMC2_CONTEXT_OFFSET,
  2058. .modulemode = MODULEMODE_SWCTRL,
  2059. },
  2060. },
  2061. };
  2062. /* mmc3 */
  2063. static struct omap_hwmod_irq_info omap44xx_mmc3_irqs[] = {
  2064. { .irq = 94 + OMAP44XX_IRQ_GIC_START },
  2065. { .irq = -1 }
  2066. };
  2067. static struct omap_hwmod_dma_info omap44xx_mmc3_sdma_reqs[] = {
  2068. { .name = "tx", .dma_req = 76 + OMAP44XX_DMA_REQ_START },
  2069. { .name = "rx", .dma_req = 77 + OMAP44XX_DMA_REQ_START },
  2070. { .dma_req = -1 }
  2071. };
  2072. static struct omap_hwmod omap44xx_mmc3_hwmod = {
  2073. .name = "mmc3",
  2074. .class = &omap44xx_mmc_hwmod_class,
  2075. .clkdm_name = "l4_per_clkdm",
  2076. .mpu_irqs = omap44xx_mmc3_irqs,
  2077. .sdma_reqs = omap44xx_mmc3_sdma_reqs,
  2078. .main_clk = "mmc3_fck",
  2079. .prcm = {
  2080. .omap4 = {
  2081. .clkctrl_offs = OMAP4_CM_L4PER_MMCSD3_CLKCTRL_OFFSET,
  2082. .context_offs = OMAP4_RM_L4PER_MMCSD3_CONTEXT_OFFSET,
  2083. .modulemode = MODULEMODE_SWCTRL,
  2084. },
  2085. },
  2086. };
  2087. /* mmc4 */
  2088. static struct omap_hwmod_irq_info omap44xx_mmc4_irqs[] = {
  2089. { .irq = 96 + OMAP44XX_IRQ_GIC_START },
  2090. { .irq = -1 }
  2091. };
  2092. static struct omap_hwmod_dma_info omap44xx_mmc4_sdma_reqs[] = {
  2093. { .name = "tx", .dma_req = 56 + OMAP44XX_DMA_REQ_START },
  2094. { .name = "rx", .dma_req = 57 + OMAP44XX_DMA_REQ_START },
  2095. { .dma_req = -1 }
  2096. };
  2097. static struct omap_hwmod omap44xx_mmc4_hwmod = {
  2098. .name = "mmc4",
  2099. .class = &omap44xx_mmc_hwmod_class,
  2100. .clkdm_name = "l4_per_clkdm",
  2101. .mpu_irqs = omap44xx_mmc4_irqs,
  2102. .sdma_reqs = omap44xx_mmc4_sdma_reqs,
  2103. .main_clk = "mmc4_fck",
  2104. .prcm = {
  2105. .omap4 = {
  2106. .clkctrl_offs = OMAP4_CM_L4PER_MMCSD4_CLKCTRL_OFFSET,
  2107. .context_offs = OMAP4_RM_L4PER_MMCSD4_CONTEXT_OFFSET,
  2108. .modulemode = MODULEMODE_SWCTRL,
  2109. },
  2110. },
  2111. };
  2112. /* mmc5 */
  2113. static struct omap_hwmod_irq_info omap44xx_mmc5_irqs[] = {
  2114. { .irq = 59 + OMAP44XX_IRQ_GIC_START },
  2115. { .irq = -1 }
  2116. };
  2117. static struct omap_hwmod_dma_info omap44xx_mmc5_sdma_reqs[] = {
  2118. { .name = "tx", .dma_req = 58 + OMAP44XX_DMA_REQ_START },
  2119. { .name = "rx", .dma_req = 59 + OMAP44XX_DMA_REQ_START },
  2120. { .dma_req = -1 }
  2121. };
  2122. static struct omap_hwmod omap44xx_mmc5_hwmod = {
  2123. .name = "mmc5",
  2124. .class = &omap44xx_mmc_hwmod_class,
  2125. .clkdm_name = "l4_per_clkdm",
  2126. .mpu_irqs = omap44xx_mmc5_irqs,
  2127. .sdma_reqs = omap44xx_mmc5_sdma_reqs,
  2128. .main_clk = "mmc5_fck",
  2129. .prcm = {
  2130. .omap4 = {
  2131. .clkctrl_offs = OMAP4_CM_L4PER_MMCSD5_CLKCTRL_OFFSET,
  2132. .context_offs = OMAP4_RM_L4PER_MMCSD5_CONTEXT_OFFSET,
  2133. .modulemode = MODULEMODE_SWCTRL,
  2134. },
  2135. },
  2136. };
  2137. /*
  2138. * 'mpu' class
  2139. * mpu sub-system
  2140. */
  2141. static struct omap_hwmod_class omap44xx_mpu_hwmod_class = {
  2142. .name = "mpu",
  2143. };
  2144. /* mpu */
  2145. static struct omap_hwmod_irq_info omap44xx_mpu_irqs[] = {
  2146. { .name = "pl310", .irq = 0 + OMAP44XX_IRQ_GIC_START },
  2147. { .name = "cti0", .irq = 1 + OMAP44XX_IRQ_GIC_START },
  2148. { .name = "cti1", .irq = 2 + OMAP44XX_IRQ_GIC_START },
  2149. { .irq = -1 }
  2150. };
  2151. static struct omap_hwmod omap44xx_mpu_hwmod = {
  2152. .name = "mpu",
  2153. .class = &omap44xx_mpu_hwmod_class,
  2154. .clkdm_name = "mpuss_clkdm",
  2155. .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
  2156. .mpu_irqs = omap44xx_mpu_irqs,
  2157. .main_clk = "dpll_mpu_m2_ck",
  2158. .prcm = {
  2159. .omap4 = {
  2160. .clkctrl_offs = OMAP4_CM_MPU_MPU_CLKCTRL_OFFSET,
  2161. .context_offs = OMAP4_RM_MPU_MPU_CONTEXT_OFFSET,
  2162. },
  2163. },
  2164. };
  2165. /*
  2166. * 'ocmc_ram' class
  2167. * top-level core on-chip ram
  2168. */
  2169. static struct omap_hwmod_class omap44xx_ocmc_ram_hwmod_class = {
  2170. .name = "ocmc_ram",
  2171. };
  2172. /* ocmc_ram */
  2173. static struct omap_hwmod omap44xx_ocmc_ram_hwmod = {
  2174. .name = "ocmc_ram",
  2175. .class = &omap44xx_ocmc_ram_hwmod_class,
  2176. .clkdm_name = "l3_2_clkdm",
  2177. .prcm = {
  2178. .omap4 = {
  2179. .clkctrl_offs = OMAP4_CM_L3_2_OCMC_RAM_CLKCTRL_OFFSET,
  2180. .context_offs = OMAP4_RM_L3_2_OCMC_RAM_CONTEXT_OFFSET,
  2181. },
  2182. },
  2183. };
  2184. /*
  2185. * 'ocp2scp' class
  2186. * bridge to transform ocp interface protocol to scp (serial control port)
  2187. * protocol
  2188. */
  2189. static struct omap_hwmod_class omap44xx_ocp2scp_hwmod_class = {
  2190. .name = "ocp2scp",
  2191. };
  2192. /* ocp2scp_usb_phy */
  2193. static struct omap_hwmod_opt_clk ocp2scp_usb_phy_opt_clks[] = {
  2194. { .role = "phy_48m", .clk = "ocp2scp_usb_phy_phy_48m" },
  2195. };
  2196. static struct omap_hwmod omap44xx_ocp2scp_usb_phy_hwmod = {
  2197. .name = "ocp2scp_usb_phy",
  2198. .class = &omap44xx_ocp2scp_hwmod_class,
  2199. .clkdm_name = "l3_init_clkdm",
  2200. .prcm = {
  2201. .omap4 = {
  2202. .clkctrl_offs = OMAP4_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL_OFFSET,
  2203. .context_offs = OMAP4_RM_L3INIT_USBPHYOCP2SCP_CONTEXT_OFFSET,
  2204. .modulemode = MODULEMODE_HWCTRL,
  2205. },
  2206. },
  2207. .opt_clks = ocp2scp_usb_phy_opt_clks,
  2208. .opt_clks_cnt = ARRAY_SIZE(ocp2scp_usb_phy_opt_clks),
  2209. };
  2210. /*
  2211. * 'prcm' class
  2212. * power and reset manager (part of the prcm infrastructure) + clock manager 2
  2213. * + clock manager 1 (in always on power domain) + local prm in mpu
  2214. */
  2215. static struct omap_hwmod_class omap44xx_prcm_hwmod_class = {
  2216. .name = "prcm",
  2217. };
  2218. /* prcm_mpu */
  2219. static struct omap_hwmod omap44xx_prcm_mpu_hwmod = {
  2220. .name = "prcm_mpu",
  2221. .class = &omap44xx_prcm_hwmod_class,
  2222. .clkdm_name = "l4_wkup_clkdm",
  2223. };
  2224. /* cm_core_aon */
  2225. static struct omap_hwmod omap44xx_cm_core_aon_hwmod = {
  2226. .name = "cm_core_aon",
  2227. .class = &omap44xx_prcm_hwmod_class,
  2228. .clkdm_name = "cm_clkdm",
  2229. };
  2230. /* cm_core */
  2231. static struct omap_hwmod omap44xx_cm_core_hwmod = {
  2232. .name = "cm_core",
  2233. .class = &omap44xx_prcm_hwmod_class,
  2234. .clkdm_name = "cm_clkdm",
  2235. };
  2236. /* prm */
  2237. static struct omap_hwmod_irq_info omap44xx_prm_irqs[] = {
  2238. { .irq = 11 + OMAP44XX_IRQ_GIC_START },
  2239. { .irq = -1 }
  2240. };
  2241. static struct omap_hwmod_rst_info omap44xx_prm_resets[] = {
  2242. { .name = "rst_global_warm_sw", .rst_shift = 0 },
  2243. { .name = "rst_global_cold_sw", .rst_shift = 1 },
  2244. };
  2245. static struct omap_hwmod omap44xx_prm_hwmod = {
  2246. .name = "prm",
  2247. .class = &omap44xx_prcm_hwmod_class,
  2248. .clkdm_name = "prm_clkdm",
  2249. .mpu_irqs = omap44xx_prm_irqs,
  2250. .rst_lines = omap44xx_prm_resets,
  2251. .rst_lines_cnt = ARRAY_SIZE(omap44xx_prm_resets),
  2252. };
  2253. /*
  2254. * 'scrm' class
  2255. * system clock and reset manager
  2256. */
  2257. static struct omap_hwmod_class omap44xx_scrm_hwmod_class = {
  2258. .name = "scrm",
  2259. };
  2260. /* scrm */
  2261. static struct omap_hwmod omap44xx_scrm_hwmod = {
  2262. .name = "scrm",
  2263. .class = &omap44xx_scrm_hwmod_class,
  2264. .clkdm_name = "l4_wkup_clkdm",
  2265. };
  2266. /*
  2267. * 'sl2if' class
  2268. * shared level 2 memory interface
  2269. */
  2270. static struct omap_hwmod_class omap44xx_sl2if_hwmod_class = {
  2271. .name = "sl2if",
  2272. };
  2273. /* sl2if */
  2274. static struct omap_hwmod omap44xx_sl2if_hwmod = {
  2275. .name = "sl2if",
  2276. .class = &omap44xx_sl2if_hwmod_class,
  2277. .clkdm_name = "ivahd_clkdm",
  2278. .prcm = {
  2279. .omap4 = {
  2280. .clkctrl_offs = OMAP4_CM_IVAHD_SL2_CLKCTRL_OFFSET,
  2281. .context_offs = OMAP4_RM_IVAHD_SL2_CONTEXT_OFFSET,
  2282. .modulemode = MODULEMODE_HWCTRL,
  2283. },
  2284. },
  2285. };
  2286. /*
  2287. * 'slimbus' class
  2288. * bidirectional, multi-drop, multi-channel two-line serial interface between
  2289. * the device and external components
  2290. */
  2291. static struct omap_hwmod_class_sysconfig omap44xx_slimbus_sysc = {
  2292. .rev_offs = 0x0000,
  2293. .sysc_offs = 0x0010,
  2294. .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
  2295. SYSC_HAS_SOFTRESET),
  2296. .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
  2297. SIDLE_SMART_WKUP),
  2298. .sysc_fields = &omap_hwmod_sysc_type2,
  2299. };
  2300. static struct omap_hwmod_class omap44xx_slimbus_hwmod_class = {
  2301. .name = "slimbus",
  2302. .sysc = &omap44xx_slimbus_sysc,
  2303. };
  2304. /* slimbus1 */
  2305. static struct omap_hwmod_irq_info omap44xx_slimbus1_irqs[] = {
  2306. { .irq = 97 + OMAP44XX_IRQ_GIC_START },
  2307. { .irq = -1 }
  2308. };
  2309. static struct omap_hwmod_dma_info omap44xx_slimbus1_sdma_reqs[] = {
  2310. { .name = "tx0", .dma_req = 84 + OMAP44XX_DMA_REQ_START },
  2311. { .name = "tx1", .dma_req = 85 + OMAP44XX_DMA_REQ_START },
  2312. { .name = "tx2", .dma_req = 86 + OMAP44XX_DMA_REQ_START },
  2313. { .name = "tx3", .dma_req = 87 + OMAP44XX_DMA_REQ_START },
  2314. { .name = "rx0", .dma_req = 88 + OMAP44XX_DMA_REQ_START },
  2315. { .name = "rx1", .dma_req = 89 + OMAP44XX_DMA_REQ_START },
  2316. { .name = "rx2", .dma_req = 90 + OMAP44XX_DMA_REQ_START },
  2317. { .name = "rx3", .dma_req = 91 + OMAP44XX_DMA_REQ_START },
  2318. { .dma_req = -1 }
  2319. };
  2320. static struct omap_hwmod_opt_clk slimbus1_opt_clks[] = {
  2321. { .role = "fclk_1", .clk = "slimbus1_fclk_1" },
  2322. { .role = "fclk_0", .clk = "slimbus1_fclk_0" },
  2323. { .role = "fclk_2", .clk = "slimbus1_fclk_2" },
  2324. { .role = "slimbus_clk", .clk = "slimbus1_slimbus_clk" },
  2325. };
  2326. static struct omap_hwmod omap44xx_slimbus1_hwmod = {
  2327. .name = "slimbus1",
  2328. .class = &omap44xx_slimbus_hwmod_class,
  2329. .clkdm_name = "abe_clkdm",
  2330. .mpu_irqs = omap44xx_slimbus1_irqs,
  2331. .sdma_reqs = omap44xx_slimbus1_sdma_reqs,
  2332. .prcm = {
  2333. .omap4 = {
  2334. .clkctrl_offs = OMAP4_CM1_ABE_SLIMBUS_CLKCTRL_OFFSET,
  2335. .context_offs = OMAP4_RM_ABE_SLIMBUS_CONTEXT_OFFSET,
  2336. .modulemode = MODULEMODE_SWCTRL,
  2337. },
  2338. },
  2339. .opt_clks = slimbus1_opt_clks,
  2340. .opt_clks_cnt = ARRAY_SIZE(slimbus1_opt_clks),
  2341. };
  2342. /* slimbus2 */
  2343. static struct omap_hwmod_irq_info omap44xx_slimbus2_irqs[] = {
  2344. { .irq = 98 + OMAP44XX_IRQ_GIC_START },
  2345. { .irq = -1 }
  2346. };
  2347. static struct omap_hwmod_dma_info omap44xx_slimbus2_sdma_reqs[] = {
  2348. { .name = "tx0", .dma_req = 92 + OMAP44XX_DMA_REQ_START },
  2349. { .name = "tx1", .dma_req = 93 + OMAP44XX_DMA_REQ_START },
  2350. { .name = "tx2", .dma_req = 94 + OMAP44XX_DMA_REQ_START },
  2351. { .name = "tx3", .dma_req = 95 + OMAP44XX_DMA_REQ_START },
  2352. { .name = "rx0", .dma_req = 96 + OMAP44XX_DMA_REQ_START },
  2353. { .name = "rx1", .dma_req = 97 + OMAP44XX_DMA_REQ_START },
  2354. { .name = "rx2", .dma_req = 98 + OMAP44XX_DMA_REQ_START },
  2355. { .name = "rx3", .dma_req = 99 + OMAP44XX_DMA_REQ_START },
  2356. { .dma_req = -1 }
  2357. };
  2358. static struct omap_hwmod_opt_clk slimbus2_opt_clks[] = {
  2359. { .role = "fclk_1", .clk = "slimbus2_fclk_1" },
  2360. { .role = "fclk_0", .clk = "slimbus2_fclk_0" },
  2361. { .role = "slimbus_clk", .clk = "slimbus2_slimbus_clk" },
  2362. };
  2363. static struct omap_hwmod omap44xx_slimbus2_hwmod = {
  2364. .name = "slimbus2",
  2365. .class = &omap44xx_slimbus_hwmod_class,
  2366. .clkdm_name = "l4_per_clkdm",
  2367. .mpu_irqs = omap44xx_slimbus2_irqs,
  2368. .sdma_reqs = omap44xx_slimbus2_sdma_reqs,
  2369. .prcm = {
  2370. .omap4 = {
  2371. .clkctrl_offs = OMAP4_CM_L4PER_SLIMBUS2_CLKCTRL_OFFSET,
  2372. .context_offs = OMAP4_RM_L4PER_SLIMBUS2_CONTEXT_OFFSET,
  2373. .modulemode = MODULEMODE_SWCTRL,
  2374. },
  2375. },
  2376. .opt_clks = slimbus2_opt_clks,
  2377. .opt_clks_cnt = ARRAY_SIZE(slimbus2_opt_clks),
  2378. };
  2379. /*
  2380. * 'smartreflex' class
  2381. * smartreflex module (monitor silicon performance and outputs a measure of
  2382. * performance error)
  2383. */
  2384. /* The IP is not compliant to type1 / type2 scheme */
  2385. static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = {
  2386. .sidle_shift = 24,
  2387. .enwkup_shift = 26,
  2388. };
  2389. static struct omap_hwmod_class_sysconfig omap44xx_smartreflex_sysc = {
  2390. .sysc_offs = 0x0038,
  2391. .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
  2392. .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
  2393. SIDLE_SMART_WKUP),
  2394. .sysc_fields = &omap_hwmod_sysc_type_smartreflex,
  2395. };
  2396. static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class = {
  2397. .name = "smartreflex",
  2398. .sysc = &omap44xx_smartreflex_sysc,
  2399. .rev = 2,
  2400. };
  2401. /* smartreflex_core */
  2402. static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = {
  2403. .sensor_voltdm_name = "core",
  2404. };
  2405. static struct omap_hwmod_irq_info omap44xx_smartreflex_core_irqs[] = {
  2406. { .irq = 19 + OMAP44XX_IRQ_GIC_START },
  2407. { .irq = -1 }
  2408. };
  2409. static struct omap_hwmod omap44xx_smartreflex_core_hwmod = {
  2410. .name = "smartreflex_core",
  2411. .class = &omap44xx_smartreflex_hwmod_class,
  2412. .clkdm_name = "l4_ao_clkdm",
  2413. .mpu_irqs = omap44xx_smartreflex_core_irqs,
  2414. .main_clk = "smartreflex_core_fck",
  2415. .prcm = {
  2416. .omap4 = {
  2417. .clkctrl_offs = OMAP4_CM_ALWON_SR_CORE_CLKCTRL_OFFSET,
  2418. .context_offs = OMAP4_RM_ALWON_SR_CORE_CONTEXT_OFFSET,
  2419. .modulemode = MODULEMODE_SWCTRL,
  2420. },
  2421. },
  2422. .dev_attr = &smartreflex_core_dev_attr,
  2423. };
  2424. /* smartreflex_iva */
  2425. static struct omap_smartreflex_dev_attr smartreflex_iva_dev_attr = {
  2426. .sensor_voltdm_name = "iva",
  2427. };
  2428. static struct omap_hwmod_irq_info omap44xx_smartreflex_iva_irqs[] = {
  2429. { .irq = 102 + OMAP44XX_IRQ_GIC_START },
  2430. { .irq = -1 }
  2431. };
  2432. static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = {
  2433. .name = "smartreflex_iva",
  2434. .class = &omap44xx_smartreflex_hwmod_class,
  2435. .clkdm_name = "l4_ao_clkdm",
  2436. .mpu_irqs = omap44xx_smartreflex_iva_irqs,
  2437. .main_clk = "smartreflex_iva_fck",
  2438. .prcm = {
  2439. .omap4 = {
  2440. .clkctrl_offs = OMAP4_CM_ALWON_SR_IVA_CLKCTRL_OFFSET,
  2441. .context_offs = OMAP4_RM_ALWON_SR_IVA_CONTEXT_OFFSET,
  2442. .modulemode = MODULEMODE_SWCTRL,
  2443. },
  2444. },
  2445. .dev_attr = &smartreflex_iva_dev_attr,
  2446. };
  2447. /* smartreflex_mpu */
  2448. static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = {
  2449. .sensor_voltdm_name = "mpu",
  2450. };
  2451. static struct omap_hwmod_irq_info omap44xx_smartreflex_mpu_irqs[] = {
  2452. { .irq = 18 + OMAP44XX_IRQ_GIC_START },
  2453. { .irq = -1 }
  2454. };
  2455. static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = {
  2456. .name = "smartreflex_mpu",
  2457. .class = &omap44xx_smartreflex_hwmod_class,
  2458. .clkdm_name = "l4_ao_clkdm",
  2459. .mpu_irqs = omap44xx_smartreflex_mpu_irqs,
  2460. .main_clk = "smartreflex_mpu_fck",
  2461. .prcm = {
  2462. .omap4 = {
  2463. .clkctrl_offs = OMAP4_CM_ALWON_SR_MPU_CLKCTRL_OFFSET,
  2464. .context_offs = OMAP4_RM_ALWON_SR_MPU_CONTEXT_OFFSET,
  2465. .modulemode = MODULEMODE_SWCTRL,
  2466. },
  2467. },
  2468. .dev_attr = &smartreflex_mpu_dev_attr,
  2469. };
  2470. /*
  2471. * 'spinlock' class
  2472. * spinlock provides hardware assistance for synchronizing the processes
  2473. * running on multiple processors
  2474. */
  2475. static struct omap_hwmod_class_sysconfig omap44xx_spinlock_sysc = {
  2476. .rev_offs = 0x0000,
  2477. .sysc_offs = 0x0010,
  2478. .syss_offs = 0x0014,
  2479. .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
  2480. SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
  2481. SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
  2482. .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
  2483. SIDLE_SMART_WKUP),
  2484. .sysc_fields = &omap_hwmod_sysc_type1,
  2485. };
  2486. static struct omap_hwmod_class omap44xx_spinlock_hwmod_class = {
  2487. .name = "spinlock",
  2488. .sysc = &omap44xx_spinlock_sysc,
  2489. };
  2490. /* spinlock */
  2491. static struct omap_hwmod omap44xx_spinlock_hwmod = {
  2492. .name = "spinlock",
  2493. .class = &omap44xx_spinlock_hwmod_class,
  2494. .clkdm_name = "l4_cfg_clkdm",
  2495. .prcm = {
  2496. .omap4 = {
  2497. .clkctrl_offs = OMAP4_CM_L4CFG_HW_SEM_CLKCTRL_OFFSET,
  2498. .context_offs = OMAP4_RM_L4CFG_HW_SEM_CONTEXT_OFFSET,
  2499. },
  2500. },
  2501. };
  2502. /*
  2503. * 'timer' class
  2504. * general purpose timer module with accurate 1ms tick
  2505. * This class contains several variants: ['timer_1ms', 'timer']
  2506. */
  2507. static struct omap_hwmod_class_sysconfig omap44xx_timer_1ms_sysc = {
  2508. .rev_offs = 0x0000,
  2509. .sysc_offs = 0x0010,
  2510. .syss_offs = 0x0014,
  2511. .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
  2512. SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
  2513. SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
  2514. SYSS_HAS_RESET_STATUS),
  2515. .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
  2516. .sysc_fields = &omap_hwmod_sysc_type1,
  2517. };
  2518. static struct omap_hwmod_class omap44xx_timer_1ms_hwmod_class = {
  2519. .name = "timer",
  2520. .sysc = &omap44xx_timer_1ms_sysc,
  2521. };
  2522. static struct omap_hwmod_class_sysconfig omap44xx_timer_sysc = {
  2523. .rev_offs = 0x0000,
  2524. .sysc_offs = 0x0010,
  2525. .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
  2526. SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
  2527. .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
  2528. SIDLE_SMART_WKUP),
  2529. .sysc_fields = &omap_hwmod_sysc_type2,
  2530. };
  2531. static struct omap_hwmod_class omap44xx_timer_hwmod_class = {
  2532. .name = "timer",
  2533. .sysc = &omap44xx_timer_sysc,
  2534. };
  2535. /* always-on timers dev attribute */
  2536. static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
  2537. .timer_capability = OMAP_TIMER_ALWON,
  2538. };
  2539. /* pwm timers dev attribute */
  2540. static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
  2541. .timer_capability = OMAP_TIMER_HAS_PWM,
  2542. };
  2543. /* timer1 */
  2544. static struct omap_hwmod_irq_info omap44xx_timer1_irqs[] = {
  2545. { .irq = 37 + OMAP44XX_IRQ_GIC_START },
  2546. { .irq = -1 }
  2547. };
  2548. static struct omap_hwmod omap44xx_timer1_hwmod = {
  2549. .name = "timer1",
  2550. .class = &omap44xx_timer_1ms_hwmod_class,
  2551. .clkdm_name = "l4_wkup_clkdm",
  2552. .mpu_irqs = omap44xx_timer1_irqs,
  2553. .main_clk = "timer1_fck",
  2554. .prcm = {
  2555. .omap4 = {
  2556. .clkctrl_offs = OMAP4_CM_WKUP_TIMER1_CLKCTRL_OFFSET,
  2557. .context_offs = OMAP4_RM_WKUP_TIMER1_CONTEXT_OFFSET,
  2558. .modulemode = MODULEMODE_SWCTRL,
  2559. },
  2560. },
  2561. .dev_attr = &capability_alwon_dev_attr,
  2562. };
  2563. /* timer2 */
  2564. static struct omap_hwmod_irq_info omap44xx_timer2_irqs[] = {
  2565. { .irq = 38 + OMAP44XX_IRQ_GIC_START },
  2566. { .irq = -1 }
  2567. };
  2568. static struct omap_hwmod omap44xx_timer2_hwmod = {
  2569. .name = "timer2",
  2570. .class = &omap44xx_timer_1ms_hwmod_class,
  2571. .clkdm_name = "l4_per_clkdm",
  2572. .mpu_irqs = omap44xx_timer2_irqs,
  2573. .main_clk = "timer2_fck",
  2574. .prcm = {
  2575. .omap4 = {
  2576. .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER2_CLKCTRL_OFFSET,
  2577. .context_offs = OMAP4_RM_L4PER_DMTIMER2_CONTEXT_OFFSET,
  2578. .modulemode = MODULEMODE_SWCTRL,
  2579. },
  2580. },
  2581. .dev_attr = &capability_alwon_dev_attr,
  2582. };
  2583. /* timer3 */
  2584. static struct omap_hwmod_irq_info omap44xx_timer3_irqs[] = {
  2585. { .irq = 39 + OMAP44XX_IRQ_GIC_START },
  2586. { .irq = -1 }
  2587. };
  2588. static struct omap_hwmod omap44xx_timer3_hwmod = {
  2589. .name = "timer3",
  2590. .class = &omap44xx_timer_hwmod_class,
  2591. .clkdm_name = "l4_per_clkdm",
  2592. .mpu_irqs = omap44xx_timer3_irqs,
  2593. .main_clk = "timer3_fck",
  2594. .prcm = {
  2595. .omap4 = {
  2596. .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER3_CLKCTRL_OFFSET,
  2597. .context_offs = OMAP4_RM_L4PER_DMTIMER3_CONTEXT_OFFSET,
  2598. .modulemode = MODULEMODE_SWCTRL,
  2599. },
  2600. },
  2601. .dev_attr = &capability_alwon_dev_attr,
  2602. };
  2603. /* timer4 */
  2604. static struct omap_hwmod_irq_info omap44xx_timer4_irqs[] = {
  2605. { .irq = 40 + OMAP44XX_IRQ_GIC_START },
  2606. { .irq = -1 }
  2607. };
  2608. static struct omap_hwmod omap44xx_timer4_hwmod = {
  2609. .name = "timer4",
  2610. .class = &omap44xx_timer_hwmod_class,
  2611. .clkdm_name = "l4_per_clkdm",
  2612. .mpu_irqs = omap44xx_timer4_irqs,
  2613. .main_clk = "timer4_fck",
  2614. .prcm = {
  2615. .omap4 = {
  2616. .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER4_CLKCTRL_OFFSET,
  2617. .context_offs = OMAP4_RM_L4PER_DMTIMER4_CONTEXT_OFFSET,
  2618. .modulemode = MODULEMODE_SWCTRL,
  2619. },
  2620. },
  2621. .dev_attr = &capability_alwon_dev_attr,
  2622. };
  2623. /* timer5 */
  2624. static struct omap_hwmod_irq_info omap44xx_timer5_irqs[] = {
  2625. { .irq = 41 + OMAP44XX_IRQ_GIC_START },
  2626. { .irq = -1 }
  2627. };
  2628. static struct omap_hwmod omap44xx_timer5_hwmod = {
  2629. .name = "timer5",
  2630. .class = &omap44xx_timer_hwmod_class,
  2631. .clkdm_name = "abe_clkdm",
  2632. .mpu_irqs = omap44xx_timer5_irqs,
  2633. .main_clk = "timer5_fck",
  2634. .prcm = {
  2635. .omap4 = {
  2636. .clkctrl_offs = OMAP4_CM1_ABE_TIMER5_CLKCTRL_OFFSET,
  2637. .context_offs = OMAP4_RM_ABE_TIMER5_CONTEXT_OFFSET,
  2638. .modulemode = MODULEMODE_SWCTRL,
  2639. },
  2640. },
  2641. .dev_attr = &capability_alwon_dev_attr,
  2642. };
  2643. /* timer6 */
  2644. static struct omap_hwmod_irq_info omap44xx_timer6_irqs[] = {
  2645. { .irq = 42 + OMAP44XX_IRQ_GIC_START },
  2646. { .irq = -1 }
  2647. };
  2648. static struct omap_hwmod omap44xx_timer6_hwmod = {
  2649. .name = "timer6",
  2650. .class = &omap44xx_timer_hwmod_class,
  2651. .clkdm_name = "abe_clkdm",
  2652. .mpu_irqs = omap44xx_timer6_irqs,
  2653. .main_clk = "timer6_fck",
  2654. .prcm = {
  2655. .omap4 = {
  2656. .clkctrl_offs = OMAP4_CM1_ABE_TIMER6_CLKCTRL_OFFSET,
  2657. .context_offs = OMAP4_RM_ABE_TIMER6_CONTEXT_OFFSET,
  2658. .modulemode = MODULEMODE_SWCTRL,
  2659. },
  2660. },
  2661. .dev_attr = &capability_alwon_dev_attr,
  2662. };
  2663. /* timer7 */
  2664. static struct omap_hwmod_irq_info omap44xx_timer7_irqs[] = {
  2665. { .irq = 43 + OMAP44XX_IRQ_GIC_START },
  2666. { .irq = -1 }
  2667. };
  2668. static struct omap_hwmod omap44xx_timer7_hwmod = {
  2669. .name = "timer7",
  2670. .class = &omap44xx_timer_hwmod_class,
  2671. .clkdm_name = "abe_clkdm",
  2672. .mpu_irqs = omap44xx_timer7_irqs,
  2673. .main_clk = "timer7_fck",
  2674. .prcm = {
  2675. .omap4 = {
  2676. .clkctrl_offs = OMAP4_CM1_ABE_TIMER7_CLKCTRL_OFFSET,
  2677. .context_offs = OMAP4_RM_ABE_TIMER7_CONTEXT_OFFSET,
  2678. .modulemode = MODULEMODE_SWCTRL,
  2679. },
  2680. },
  2681. .dev_attr = &capability_alwon_dev_attr,
  2682. };
  2683. /* timer8 */
  2684. static struct omap_hwmod_irq_info omap44xx_timer8_irqs[] = {
  2685. { .irq = 44 + OMAP44XX_IRQ_GIC_START },
  2686. { .irq = -1 }
  2687. };
  2688. static struct omap_hwmod omap44xx_timer8_hwmod = {
  2689. .name = "timer8",
  2690. .class = &omap44xx_timer_hwmod_class,
  2691. .clkdm_name = "abe_clkdm",
  2692. .mpu_irqs = omap44xx_timer8_irqs,
  2693. .main_clk = "timer8_fck",
  2694. .prcm = {
  2695. .omap4 = {
  2696. .clkctrl_offs = OMAP4_CM1_ABE_TIMER8_CLKCTRL_OFFSET,
  2697. .context_offs = OMAP4_RM_ABE_TIMER8_CONTEXT_OFFSET,
  2698. .modulemode = MODULEMODE_SWCTRL,
  2699. },
  2700. },
  2701. .dev_attr = &capability_pwm_dev_attr,
  2702. };
  2703. /* timer9 */
  2704. static struct omap_hwmod_irq_info omap44xx_timer9_irqs[] = {
  2705. { .irq = 45 + OMAP44XX_IRQ_GIC_START },
  2706. { .irq = -1 }
  2707. };
  2708. static struct omap_hwmod omap44xx_timer9_hwmod = {
  2709. .name = "timer9",
  2710. .class = &omap44xx_timer_hwmod_class,
  2711. .clkdm_name = "l4_per_clkdm",
  2712. .mpu_irqs = omap44xx_timer9_irqs,
  2713. .main_clk = "timer9_fck",
  2714. .prcm = {
  2715. .omap4 = {
  2716. .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER9_CLKCTRL_OFFSET,
  2717. .context_offs = OMAP4_RM_L4PER_DMTIMER9_CONTEXT_OFFSET,
  2718. .modulemode = MODULEMODE_SWCTRL,
  2719. },
  2720. },
  2721. .dev_attr = &capability_pwm_dev_attr,
  2722. };
  2723. /* timer10 */
  2724. static struct omap_hwmod_irq_info omap44xx_timer10_irqs[] = {
  2725. { .irq = 46 + OMAP44XX_IRQ_GIC_START },
  2726. { .irq = -1 }
  2727. };
  2728. static struct omap_hwmod omap44xx_timer10_hwmod = {
  2729. .name = "timer10",
  2730. .class = &omap44xx_timer_1ms_hwmod_class,
  2731. .clkdm_name = "l4_per_clkdm",
  2732. .mpu_irqs = omap44xx_timer10_irqs,
  2733. .main_clk = "timer10_fck",
  2734. .prcm = {
  2735. .omap4 = {
  2736. .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER10_CLKCTRL_OFFSET,
  2737. .context_offs = OMAP4_RM_L4PER_DMTIMER10_CONTEXT_OFFSET,
  2738. .modulemode = MODULEMODE_SWCTRL,
  2739. },
  2740. },
  2741. .dev_attr = &capability_pwm_dev_attr,
  2742. };
  2743. /* timer11 */
  2744. static struct omap_hwmod_irq_info omap44xx_timer11_irqs[] = {
  2745. { .irq = 47 + OMAP44XX_IRQ_GIC_START },
  2746. { .irq = -1 }
  2747. };
  2748. static struct omap_hwmod omap44xx_timer11_hwmod = {
  2749. .name = "timer11",
  2750. .class = &omap44xx_timer_hwmod_class,
  2751. .clkdm_name = "l4_per_clkdm",
  2752. .mpu_irqs = omap44xx_timer11_irqs,
  2753. .main_clk = "timer11_fck",
  2754. .prcm = {
  2755. .omap4 = {
  2756. .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER11_CLKCTRL_OFFSET,
  2757. .context_offs = OMAP4_RM_L4PER_DMTIMER11_CONTEXT_OFFSET,
  2758. .modulemode = MODULEMODE_SWCTRL,
  2759. },
  2760. },
  2761. .dev_attr = &capability_pwm_dev_attr,
  2762. };
  2763. /*
  2764. * 'uart' class
  2765. * universal asynchronous receiver/transmitter (uart)
  2766. */
  2767. static struct omap_hwmod_class_sysconfig omap44xx_uart_sysc = {
  2768. .rev_offs = 0x0050,
  2769. .sysc_offs = 0x0054,
  2770. .syss_offs = 0x0058,
  2771. .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
  2772. SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
  2773. SYSS_HAS_RESET_STATUS),
  2774. .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
  2775. SIDLE_SMART_WKUP),
  2776. .sysc_fields = &omap_hwmod_sysc_type1,
  2777. };
  2778. static struct omap_hwmod_class omap44xx_uart_hwmod_class = {
  2779. .name = "uart",
  2780. .sysc = &omap44xx_uart_sysc,
  2781. };
  2782. /* uart1 */
  2783. static struct omap_hwmod_irq_info omap44xx_uart1_irqs[] = {
  2784. { .irq = 72 + OMAP44XX_IRQ_GIC_START },
  2785. { .irq = -1 }
  2786. };
  2787. static struct omap_hwmod_dma_info omap44xx_uart1_sdma_reqs[] = {
  2788. { .name = "tx", .dma_req = 48 + OMAP44XX_DMA_REQ_START },
  2789. { .name = "rx", .dma_req = 49 + OMAP44XX_DMA_REQ_START },
  2790. { .dma_req = -1 }
  2791. };
  2792. static struct omap_hwmod omap44xx_uart1_hwmod = {
  2793. .name = "uart1",
  2794. .class = &omap44xx_uart_hwmod_class,
  2795. .clkdm_name = "l4_per_clkdm",
  2796. .mpu_irqs = omap44xx_uart1_irqs,
  2797. .sdma_reqs = omap44xx_uart1_sdma_reqs,
  2798. .main_clk = "uart1_fck",
  2799. .prcm = {
  2800. .omap4 = {
  2801. .clkctrl_offs = OMAP4_CM_L4PER_UART1_CLKCTRL_OFFSET,
  2802. .context_offs = OMAP4_RM_L4PER_UART1_CONTEXT_OFFSET,
  2803. .modulemode = MODULEMODE_SWCTRL,
  2804. },
  2805. },
  2806. };
  2807. /* uart2 */
  2808. static struct omap_hwmod_irq_info omap44xx_uart2_irqs[] = {
  2809. { .irq = 73 + OMAP44XX_IRQ_GIC_START },
  2810. { .irq = -1 }
  2811. };
  2812. static struct omap_hwmod_dma_info omap44xx_uart2_sdma_reqs[] = {
  2813. { .name = "tx", .dma_req = 50 + OMAP44XX_DMA_REQ_START },
  2814. { .name = "rx", .dma_req = 51 + OMAP44XX_DMA_REQ_START },
  2815. { .dma_req = -1 }
  2816. };
  2817. static struct omap_hwmod omap44xx_uart2_hwmod = {
  2818. .name = "uart2",
  2819. .class = &omap44xx_uart_hwmod_class,
  2820. .clkdm_name = "l4_per_clkdm",
  2821. .mpu_irqs = omap44xx_uart2_irqs,
  2822. .sdma_reqs = omap44xx_uart2_sdma_reqs,
  2823. .main_clk = "uart2_fck",
  2824. .prcm = {
  2825. .omap4 = {
  2826. .clkctrl_offs = OMAP4_CM_L4PER_UART2_CLKCTRL_OFFSET,
  2827. .context_offs = OMAP4_RM_L4PER_UART2_CONTEXT_OFFSET,
  2828. .modulemode = MODULEMODE_SWCTRL,
  2829. },
  2830. },
  2831. };
  2832. /* uart3 */
  2833. static struct omap_hwmod_irq_info omap44xx_uart3_irqs[] = {
  2834. { .irq = 74 + OMAP44XX_IRQ_GIC_START },
  2835. { .irq = -1 }
  2836. };
  2837. static struct omap_hwmod_dma_info omap44xx_uart3_sdma_reqs[] = {
  2838. { .name = "tx", .dma_req = 52 + OMAP44XX_DMA_REQ_START },
  2839. { .name = "rx", .dma_req = 53 + OMAP44XX_DMA_REQ_START },
  2840. { .dma_req = -1 }
  2841. };
  2842. static struct omap_hwmod omap44xx_uart3_hwmod = {
  2843. .name = "uart3",
  2844. .class = &omap44xx_uart_hwmod_class,
  2845. .clkdm_name = "l4_per_clkdm",
  2846. .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
  2847. .mpu_irqs = omap44xx_uart3_irqs,
  2848. .sdma_reqs = omap44xx_uart3_sdma_reqs,
  2849. .main_clk = "uart3_fck",
  2850. .prcm = {
  2851. .omap4 = {
  2852. .clkctrl_offs = OMAP4_CM_L4PER_UART3_CLKCTRL_OFFSET,
  2853. .context_offs = OMAP4_RM_L4PER_UART3_CONTEXT_OFFSET,
  2854. .modulemode = MODULEMODE_SWCTRL,
  2855. },
  2856. },
  2857. };
  2858. /* uart4 */
  2859. static struct omap_hwmod_irq_info omap44xx_uart4_irqs[] = {
  2860. { .irq = 70 + OMAP44XX_IRQ_GIC_START },
  2861. { .irq = -1 }
  2862. };
  2863. static struct omap_hwmod_dma_info omap44xx_uart4_sdma_reqs[] = {
  2864. { .name = "tx", .dma_req = 54 + OMAP44XX_DMA_REQ_START },
  2865. { .name = "rx", .dma_req = 55 + OMAP44XX_DMA_REQ_START },
  2866. { .dma_req = -1 }
  2867. };
  2868. static struct omap_hwmod omap44xx_uart4_hwmod = {
  2869. .name = "uart4",
  2870. .class = &omap44xx_uart_hwmod_class,
  2871. .clkdm_name = "l4_per_clkdm",
  2872. .mpu_irqs = omap44xx_uart4_irqs,
  2873. .sdma_reqs = omap44xx_uart4_sdma_reqs,
  2874. .main_clk = "uart4_fck",
  2875. .prcm = {
  2876. .omap4 = {
  2877. .clkctrl_offs = OMAP4_CM_L4PER_UART4_CLKCTRL_OFFSET,
  2878. .context_offs = OMAP4_RM_L4PER_UART4_CONTEXT_OFFSET,
  2879. .modulemode = MODULEMODE_SWCTRL,
  2880. },
  2881. },
  2882. };
  2883. /*
  2884. * 'usb_host_fs' class
  2885. * full-speed usb host controller
  2886. */
  2887. /* The IP is not compliant to type1 / type2 scheme */
  2888. static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_usb_host_fs = {
  2889. .midle_shift = 4,
  2890. .sidle_shift = 2,
  2891. .srst_shift = 1,
  2892. };
  2893. static struct omap_hwmod_class_sysconfig omap44xx_usb_host_fs_sysc = {
  2894. .rev_offs = 0x0000,
  2895. .sysc_offs = 0x0210,
  2896. .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
  2897. SYSC_HAS_SOFTRESET),
  2898. .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
  2899. SIDLE_SMART_WKUP),
  2900. .sysc_fields = &omap_hwmod_sysc_type_usb_host_fs,
  2901. };
  2902. static struct omap_hwmod_class omap44xx_usb_host_fs_hwmod_class = {
  2903. .name = "usb_host_fs",
  2904. .sysc = &omap44xx_usb_host_fs_sysc,
  2905. };
  2906. /* usb_host_fs */
  2907. static struct omap_hwmod_irq_info omap44xx_usb_host_fs_irqs[] = {
  2908. { .name = "std", .irq = 89 + OMAP44XX_IRQ_GIC_START },
  2909. { .name = "smi", .irq = 90 + OMAP44XX_IRQ_GIC_START },
  2910. { .irq = -1 }
  2911. };
  2912. static struct omap_hwmod omap44xx_usb_host_fs_hwmod = {
  2913. .name = "usb_host_fs",
  2914. .class = &omap44xx_usb_host_fs_hwmod_class,
  2915. .clkdm_name = "l3_init_clkdm",
  2916. .mpu_irqs = omap44xx_usb_host_fs_irqs,
  2917. .main_clk = "usb_host_fs_fck",
  2918. .prcm = {
  2919. .omap4 = {
  2920. .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_FS_CLKCTRL_OFFSET,
  2921. .context_offs = OMAP4_RM_L3INIT_USB_HOST_FS_CONTEXT_OFFSET,
  2922. .modulemode = MODULEMODE_SWCTRL,
  2923. },
  2924. },
  2925. };
  2926. /*
  2927. * 'usb_host_hs' class
  2928. * high-speed multi-port usb host controller
  2929. */
  2930. static struct omap_hwmod_class_sysconfig omap44xx_usb_host_hs_sysc = {
  2931. .rev_offs = 0x0000,
  2932. .sysc_offs = 0x0010,
  2933. .syss_offs = 0x0014,
  2934. .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
  2935. SYSC_HAS_SOFTRESET),
  2936. .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
  2937. SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
  2938. MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
  2939. .sysc_fields = &omap_hwmod_sysc_type2,
  2940. };
  2941. static struct omap_hwmod_class omap44xx_usb_host_hs_hwmod_class = {
  2942. .name = "usb_host_hs",
  2943. .sysc = &omap44xx_usb_host_hs_sysc,
  2944. };
  2945. /* usb_host_hs */
  2946. static struct omap_hwmod_irq_info omap44xx_usb_host_hs_irqs[] = {
  2947. { .name = "ohci-irq", .irq = 76 + OMAP44XX_IRQ_GIC_START },
  2948. { .name = "ehci-irq", .irq = 77 + OMAP44XX_IRQ_GIC_START },
  2949. { .irq = -1 }
  2950. };
  2951. static struct omap_hwmod omap44xx_usb_host_hs_hwmod = {
  2952. .name = "usb_host_hs",
  2953. .class = &omap44xx_usb_host_hs_hwmod_class,
  2954. .clkdm_name = "l3_init_clkdm",
  2955. .main_clk = "usb_host_hs_fck",
  2956. .prcm = {
  2957. .omap4 = {
  2958. .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_OFFSET,
  2959. .context_offs = OMAP4_RM_L3INIT_USB_HOST_CONTEXT_OFFSET,
  2960. .modulemode = MODULEMODE_SWCTRL,
  2961. },
  2962. },
  2963. .mpu_irqs = omap44xx_usb_host_hs_irqs,
  2964. /*
  2965. * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
  2966. * id: i660
  2967. *
  2968. * Description:
  2969. * In the following configuration :
  2970. * - USBHOST module is set to smart-idle mode
  2971. * - PRCM asserts idle_req to the USBHOST module ( This typically
  2972. * happens when the system is going to a low power mode : all ports
  2973. * have been suspended, the master part of the USBHOST module has
  2974. * entered the standby state, and SW has cut the functional clocks)
  2975. * - an USBHOST interrupt occurs before the module is able to answer
  2976. * idle_ack, typically a remote wakeup IRQ.
  2977. * Then the USB HOST module will enter a deadlock situation where it
  2978. * is no more accessible nor functional.
  2979. *
  2980. * Workaround:
  2981. * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE
  2982. */
  2983. /*
  2984. * Errata: USB host EHCI may stall when entering smart-standby mode
  2985. * Id: i571
  2986. *
  2987. * Description:
  2988. * When the USBHOST module is set to smart-standby mode, and when it is
  2989. * ready to enter the standby state (i.e. all ports are suspended and
  2990. * all attached devices are in suspend mode), then it can wrongly assert
  2991. * the Mstandby signal too early while there are still some residual OCP
  2992. * transactions ongoing. If this condition occurs, the internal state
  2993. * machine may go to an undefined state and the USB link may be stuck
  2994. * upon the next resume.
  2995. *
  2996. * Workaround:
  2997. * Don't use smart standby; use only force standby,
  2998. * hence HWMOD_SWSUP_MSTANDBY
  2999. */
  3000. /*
  3001. * During system boot; If the hwmod framework resets the module
  3002. * the module will have smart idle settings; which can lead to deadlock
  3003. * (above Errata Id:i660); so, dont reset the module during boot;
  3004. * Use HWMOD_INIT_NO_RESET.
  3005. */
  3006. .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY |
  3007. HWMOD_INIT_NO_RESET,
  3008. };
  3009. /*
  3010. * 'usb_otg_hs' class
  3011. * high-speed on-the-go universal serial bus (usb_otg_hs) controller
  3012. */
  3013. static struct omap_hwmod_class_sysconfig omap44xx_usb_otg_hs_sysc = {
  3014. .rev_offs = 0x0400,
  3015. .sysc_offs = 0x0404,
  3016. .syss_offs = 0x0408,
  3017. .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
  3018. SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
  3019. SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
  3020. .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
  3021. SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
  3022. MSTANDBY_SMART),
  3023. .sysc_fields = &omap_hwmod_sysc_type1,
  3024. };
  3025. static struct omap_hwmod_class omap44xx_usb_otg_hs_hwmod_class = {
  3026. .name = "usb_otg_hs",
  3027. .sysc = &omap44xx_usb_otg_hs_sysc,
  3028. };
  3029. /* usb_otg_hs */
  3030. static struct omap_hwmod_irq_info omap44xx_usb_otg_hs_irqs[] = {
  3031. { .name = "mc", .irq = 92 + OMAP44XX_IRQ_GIC_START },
  3032. { .name = "dma", .irq = 93 + OMAP44XX_IRQ_GIC_START },
  3033. { .irq = -1 }
  3034. };
  3035. static struct omap_hwmod_opt_clk usb_otg_hs_opt_clks[] = {
  3036. { .role = "xclk", .clk = "usb_otg_hs_xclk" },
  3037. };
  3038. static struct omap_hwmod omap44xx_usb_otg_hs_hwmod = {
  3039. .name = "usb_otg_hs",
  3040. .class = &omap44xx_usb_otg_hs_hwmod_class,
  3041. .clkdm_name = "l3_init_clkdm",
  3042. .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
  3043. .mpu_irqs = omap44xx_usb_otg_hs_irqs,
  3044. .main_clk = "usb_otg_hs_ick",
  3045. .prcm = {
  3046. .omap4 = {
  3047. .clkctrl_offs = OMAP4_CM_L3INIT_USB_OTG_CLKCTRL_OFFSET,
  3048. .context_offs = OMAP4_RM_L3INIT_USB_OTG_CONTEXT_OFFSET,
  3049. .modulemode = MODULEMODE_HWCTRL,
  3050. },
  3051. },
  3052. .opt_clks = usb_otg_hs_opt_clks,
  3053. .opt_clks_cnt = ARRAY_SIZE(usb_otg_hs_opt_clks),
  3054. };
  3055. /*
  3056. * 'usb_tll_hs' class
  3057. * usb_tll_hs module is the adapter on the usb_host_hs ports
  3058. */
  3059. static struct omap_hwmod_class_sysconfig omap44xx_usb_tll_hs_sysc = {
  3060. .rev_offs = 0x0000,
  3061. .sysc_offs = 0x0010,
  3062. .syss_offs = 0x0014,
  3063. .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
  3064. SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
  3065. SYSC_HAS_AUTOIDLE),
  3066. .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
  3067. .sysc_fields = &omap_hwmod_sysc_type1,
  3068. };
  3069. static struct omap_hwmod_class omap44xx_usb_tll_hs_hwmod_class = {
  3070. .name = "usb_tll_hs",
  3071. .sysc = &omap44xx_usb_tll_hs_sysc,
  3072. };
  3073. static struct omap_hwmod_irq_info omap44xx_usb_tll_hs_irqs[] = {
  3074. { .name = "tll-irq", .irq = 78 + OMAP44XX_IRQ_GIC_START },
  3075. { .irq = -1 }
  3076. };
  3077. static struct omap_hwmod omap44xx_usb_tll_hs_hwmod = {
  3078. .name = "usb_tll_hs",
  3079. .class = &omap44xx_usb_tll_hs_hwmod_class,
  3080. .clkdm_name = "l3_init_clkdm",
  3081. .mpu_irqs = omap44xx_usb_tll_hs_irqs,
  3082. .main_clk = "usb_tll_hs_ick",
  3083. .prcm = {
  3084. .omap4 = {
  3085. .clkctrl_offs = OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_OFFSET,
  3086. .context_offs = OMAP4_RM_L3INIT_USB_TLL_CONTEXT_OFFSET,
  3087. .modulemode = MODULEMODE_HWCTRL,
  3088. },
  3089. },
  3090. };
  3091. /*
  3092. * 'wd_timer' class
  3093. * 32-bit watchdog upward counter that generates a pulse on the reset pin on
  3094. * overflow condition
  3095. */
  3096. static struct omap_hwmod_class_sysconfig omap44xx_wd_timer_sysc = {
  3097. .rev_offs = 0x0000,
  3098. .sysc_offs = 0x0010,
  3099. .syss_offs = 0x0014,
  3100. .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
  3101. SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
  3102. .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
  3103. SIDLE_SMART_WKUP),
  3104. .sysc_fields = &omap_hwmod_sysc_type1,
  3105. };
  3106. static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = {
  3107. .name = "wd_timer",
  3108. .sysc = &omap44xx_wd_timer_sysc,
  3109. .pre_shutdown = &omap2_wd_timer_disable,
  3110. };
  3111. /* wd_timer2 */
  3112. static struct omap_hwmod_irq_info omap44xx_wd_timer2_irqs[] = {
  3113. { .irq = 80 + OMAP44XX_IRQ_GIC_START },
  3114. { .irq = -1 }
  3115. };
  3116. static struct omap_hwmod omap44xx_wd_timer2_hwmod = {
  3117. .name = "wd_timer2",
  3118. .class = &omap44xx_wd_timer_hwmod_class,
  3119. .clkdm_name = "l4_wkup_clkdm",
  3120. .mpu_irqs = omap44xx_wd_timer2_irqs,
  3121. .main_clk = "wd_timer2_fck",
  3122. .prcm = {
  3123. .omap4 = {
  3124. .clkctrl_offs = OMAP4_CM_WKUP_WDT2_CLKCTRL_OFFSET,
  3125. .context_offs = OMAP4_RM_WKUP_WDT2_CONTEXT_OFFSET,
  3126. .modulemode = MODULEMODE_SWCTRL,
  3127. },
  3128. },
  3129. };
  3130. /* wd_timer3 */
  3131. static struct omap_hwmod_irq_info omap44xx_wd_timer3_irqs[] = {
  3132. { .irq = 36 + OMAP44XX_IRQ_GIC_START },
  3133. { .irq = -1 }
  3134. };
  3135. static struct omap_hwmod omap44xx_wd_timer3_hwmod = {
  3136. .name = "wd_timer3",
  3137. .class = &omap44xx_wd_timer_hwmod_class,
  3138. .clkdm_name = "abe_clkdm",
  3139. .mpu_irqs = omap44xx_wd_timer3_irqs,
  3140. .main_clk = "wd_timer3_fck",
  3141. .prcm = {
  3142. .omap4 = {
  3143. .clkctrl_offs = OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET,
  3144. .context_offs = OMAP4_RM_ABE_WDT3_CONTEXT_OFFSET,
  3145. .modulemode = MODULEMODE_SWCTRL,
  3146. },
  3147. },
  3148. };
  3149. /*
  3150. * interfaces
  3151. */
  3152. static struct omap_hwmod_addr_space omap44xx_c2c_target_fw_addrs[] = {
  3153. {
  3154. .pa_start = 0x4a204000,
  3155. .pa_end = 0x4a2040ff,
  3156. .flags = ADDR_TYPE_RT
  3157. },
  3158. { }
  3159. };
  3160. /* c2c -> c2c_target_fw */
  3161. static struct omap_hwmod_ocp_if omap44xx_c2c__c2c_target_fw = {
  3162. .master = &omap44xx_c2c_hwmod,
  3163. .slave = &omap44xx_c2c_target_fw_hwmod,
  3164. .clk = "div_core_ck",
  3165. .addr = omap44xx_c2c_target_fw_addrs,
  3166. .user = OCP_USER_MPU,
  3167. };
  3168. /* l4_cfg -> c2c_target_fw */
  3169. static struct omap_hwmod_ocp_if omap44xx_l4_cfg__c2c_target_fw = {
  3170. .master = &omap44xx_l4_cfg_hwmod,
  3171. .slave = &omap44xx_c2c_target_fw_hwmod,
  3172. .clk = "l4_div_ck",
  3173. .user = OCP_USER_MPU | OCP_USER_SDMA,
  3174. };
  3175. /* l3_main_1 -> dmm */
  3176. static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = {
  3177. .master = &omap44xx_l3_main_1_hwmod,
  3178. .slave = &omap44xx_dmm_hwmod,
  3179. .clk = "l3_div_ck",
  3180. .user = OCP_USER_SDMA,
  3181. };
  3182. static struct omap_hwmod_addr_space omap44xx_dmm_addrs[] = {
  3183. {
  3184. .pa_start = 0x4e000000,
  3185. .pa_end = 0x4e0007ff,
  3186. .flags = ADDR_TYPE_RT
  3187. },
  3188. { }
  3189. };
  3190. /* mpu -> dmm */
  3191. static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = {
  3192. .master = &omap44xx_mpu_hwmod,
  3193. .slave = &omap44xx_dmm_hwmod,
  3194. .clk = "l3_div_ck",
  3195. .addr = omap44xx_dmm_addrs,
  3196. .user = OCP_USER_MPU,
  3197. };
  3198. /* c2c -> emif_fw */
  3199. static struct omap_hwmod_ocp_if omap44xx_c2c__emif_fw = {
  3200. .master = &omap44xx_c2c_hwmod,
  3201. .slave = &omap44xx_emif_fw_hwmod,
  3202. .clk = "div_core_ck",
  3203. .user = OCP_USER_MPU | OCP_USER_SDMA,
  3204. };
  3205. /* dmm -> emif_fw */
  3206. static struct omap_hwmod_ocp_if omap44xx_dmm__emif_fw = {
  3207. .master = &omap44xx_dmm_hwmod,
  3208. .slave = &omap44xx_emif_fw_hwmod,
  3209. .clk = "l3_div_ck",
  3210. .user = OCP_USER_MPU | OCP_USER_SDMA,
  3211. };
  3212. static struct omap_hwmod_addr_space omap44xx_emif_fw_addrs[] = {
  3213. {
  3214. .pa_start = 0x4a20c000,
  3215. .pa_end = 0x4a20c0ff,
  3216. .flags = ADDR_TYPE_RT
  3217. },
  3218. { }
  3219. };
  3220. /* l4_cfg -> emif_fw */
  3221. static struct omap_hwmod_ocp_if omap44xx_l4_cfg__emif_fw = {
  3222. .master = &omap44xx_l4_cfg_hwmod,
  3223. .slave = &omap44xx_emif_fw_hwmod,
  3224. .clk = "l4_div_ck",
  3225. .addr = omap44xx_emif_fw_addrs,
  3226. .user = OCP_USER_MPU,
  3227. };
  3228. /* iva -> l3_instr */
  3229. static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr = {
  3230. .master = &omap44xx_iva_hwmod,
  3231. .slave = &omap44xx_l3_instr_hwmod,
  3232. .clk = "l3_div_ck",
  3233. .user = OCP_USER_MPU | OCP_USER_SDMA,
  3234. };
  3235. /* l3_main_3 -> l3_instr */
  3236. static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = {
  3237. .master = &omap44xx_l3_main_3_hwmod,
  3238. .slave = &omap44xx_l3_instr_hwmod,
  3239. .clk = "l3_div_ck",
  3240. .user = OCP_USER_MPU | OCP_USER_SDMA,
  3241. };
  3242. /* ocp_wp_noc -> l3_instr */
  3243. static struct omap_hwmod_ocp_if omap44xx_ocp_wp_noc__l3_instr = {
  3244. .master = &omap44xx_ocp_wp_noc_hwmod,
  3245. .slave = &omap44xx_l3_instr_hwmod,
  3246. .clk = "l3_div_ck",
  3247. .user = OCP_USER_MPU | OCP_USER_SDMA,
  3248. };
  3249. /* dsp -> l3_main_1 */
  3250. static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1 = {
  3251. .master = &omap44xx_dsp_hwmod,
  3252. .slave = &omap44xx_l3_main_1_hwmod,
  3253. .clk = "l3_div_ck",
  3254. .user = OCP_USER_MPU | OCP_USER_SDMA,
  3255. };
  3256. /* dss -> l3_main_1 */
  3257. static struct omap_hwmod_ocp_if omap44xx_dss__l3_main_1 = {
  3258. .master = &omap44xx_dss_hwmod,
  3259. .slave = &omap44xx_l3_main_1_hwmod,
  3260. .clk = "l3_div_ck",
  3261. .user = OCP_USER_MPU | OCP_USER_SDMA,
  3262. };
  3263. /* l3_main_2 -> l3_main_1 */
  3264. static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = {
  3265. .master = &omap44xx_l3_main_2_hwmod,
  3266. .slave = &omap44xx_l3_main_1_hwmod,
  3267. .clk = "l3_div_ck",
  3268. .user = OCP_USER_MPU | OCP_USER_SDMA,
  3269. };
  3270. /* l4_cfg -> l3_main_1 */
  3271. static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = {
  3272. .master = &omap44xx_l4_cfg_hwmod,
  3273. .slave = &omap44xx_l3_main_1_hwmod,
  3274. .clk = "l4_div_ck",
  3275. .user = OCP_USER_MPU | OCP_USER_SDMA,
  3276. };
  3277. /* mmc1 -> l3_main_1 */
  3278. static struct omap_hwmod_ocp_if omap44xx_mmc1__l3_main_1 = {
  3279. .master = &omap44xx_mmc1_hwmod,
  3280. .slave = &omap44xx_l3_main_1_hwmod,
  3281. .clk = "l3_div_ck",
  3282. .user = OCP_USER_MPU | OCP_USER_SDMA,
  3283. };
  3284. /* mmc2 -> l3_main_1 */
  3285. static struct omap_hwmod_ocp_if omap44xx_mmc2__l3_main_1 = {
  3286. .master = &omap44xx_mmc2_hwmod,
  3287. .slave = &omap44xx_l3_main_1_hwmod,
  3288. .clk = "l3_div_ck",
  3289. .user = OCP_USER_MPU | OCP_USER_SDMA,
  3290. };
  3291. static struct omap_hwmod_addr_space omap44xx_l3_main_1_addrs[] = {
  3292. {
  3293. .pa_start = 0x44000000,
  3294. .pa_end = 0x44000fff,
  3295. .flags = ADDR_TYPE_RT
  3296. },
  3297. { }
  3298. };
  3299. /* mpu -> l3_main_1 */
  3300. static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = {
  3301. .master = &omap44xx_mpu_hwmod,
  3302. .slave = &omap44xx_l3_main_1_hwmod,
  3303. .clk = "l3_div_ck",
  3304. .addr = omap44xx_l3_main_1_addrs,
  3305. .user = OCP_USER_MPU,
  3306. };
  3307. /* c2c_target_fw -> l3_main_2 */
  3308. static struct omap_hwmod_ocp_if omap44xx_c2c_target_fw__l3_main_2 = {
  3309. .master = &omap44xx_c2c_target_fw_hwmod,
  3310. .slave = &omap44xx_l3_main_2_hwmod,
  3311. .clk = "l3_div_ck",
  3312. .user = OCP_USER_MPU | OCP_USER_SDMA,
  3313. };
  3314. /* dma_system -> l3_main_2 */
  3315. static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = {
  3316. .master = &omap44xx_dma_system_hwmod,
  3317. .slave = &omap44xx_l3_main_2_hwmod,
  3318. .clk = "l3_div_ck",
  3319. .user = OCP_USER_MPU | OCP_USER_SDMA,
  3320. };
  3321. /* fdif -> l3_main_2 */
  3322. static struct omap_hwmod_ocp_if omap44xx_fdif__l3_main_2 = {
  3323. .master = &omap44xx_fdif_hwmod,
  3324. .slave = &omap44xx_l3_main_2_hwmod,
  3325. .clk = "l3_div_ck",
  3326. .user = OCP_USER_MPU | OCP_USER_SDMA,
  3327. };
  3328. /* gpu -> l3_main_2 */
  3329. static struct omap_hwmod_ocp_if omap44xx_gpu__l3_main_2 = {
  3330. .master = &omap44xx_gpu_hwmod,
  3331. .slave = &omap44xx_l3_main_2_hwmod,
  3332. .clk = "l3_div_ck",
  3333. .user = OCP_USER_MPU | OCP_USER_SDMA,
  3334. };
  3335. /* hsi -> l3_main_2 */
  3336. static struct omap_hwmod_ocp_if omap44xx_hsi__l3_main_2 = {
  3337. .master = &omap44xx_hsi_hwmod,
  3338. .slave = &omap44xx_l3_main_2_hwmod,
  3339. .clk = "l3_div_ck",
  3340. .user = OCP_USER_MPU | OCP_USER_SDMA,
  3341. };
  3342. /* ipu -> l3_main_2 */
  3343. static struct omap_hwmod_ocp_if omap44xx_ipu__l3_main_2 = {
  3344. .master = &omap44xx_ipu_hwmod,
  3345. .slave = &omap44xx_l3_main_2_hwmod,
  3346. .clk = "l3_div_ck",
  3347. .user = OCP_USER_MPU | OCP_USER_SDMA,
  3348. };
  3349. /* iss -> l3_main_2 */
  3350. static struct omap_hwmod_ocp_if omap44xx_iss__l3_main_2 = {
  3351. .master = &omap44xx_iss_hwmod,
  3352. .slave = &omap44xx_l3_main_2_hwmod,
  3353. .clk = "l3_div_ck",
  3354. .user = OCP_USER_MPU | OCP_USER_SDMA,
  3355. };
  3356. /* iva -> l3_main_2 */
  3357. static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = {
  3358. .master = &omap44xx_iva_hwmod,
  3359. .slave = &omap44xx_l3_main_2_hwmod,
  3360. .clk = "l3_div_ck",
  3361. .user = OCP_USER_MPU | OCP_USER_SDMA,
  3362. };
  3363. static struct omap_hwmod_addr_space omap44xx_l3_main_2_addrs[] = {
  3364. {
  3365. .pa_start = 0x44800000,
  3366. .pa_end = 0x44801fff,
  3367. .flags = ADDR_TYPE_RT
  3368. },
  3369. { }
  3370. };
  3371. /* l3_main_1 -> l3_main_2 */
  3372. static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = {
  3373. .master = &omap44xx_l3_main_1_hwmod,
  3374. .slave = &omap44xx_l3_main_2_hwmod,
  3375. .clk = "l3_div_ck",
  3376. .addr = omap44xx_l3_main_2_addrs,
  3377. .user = OCP_USER_MPU,
  3378. };
  3379. /* l4_cfg -> l3_main_2 */
  3380. static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = {
  3381. .master = &omap44xx_l4_cfg_hwmod,
  3382. .slave = &omap44xx_l3_main_2_hwmod,
  3383. .clk = "l4_div_ck",
  3384. .user = OCP_USER_MPU | OCP_USER_SDMA,
  3385. };
  3386. /* usb_host_fs -> l3_main_2 */
  3387. static struct omap_hwmod_ocp_if omap44xx_usb_host_fs__l3_main_2 = {
  3388. .master = &omap44xx_usb_host_fs_hwmod,
  3389. .slave = &omap44xx_l3_main_2_hwmod,
  3390. .clk = "l3_div_ck",
  3391. .user = OCP_USER_MPU | OCP_USER_SDMA,
  3392. };
  3393. /* usb_host_hs -> l3_main_2 */
  3394. static struct omap_hwmod_ocp_if omap44xx_usb_host_hs__l3_main_2 = {
  3395. .master = &omap44xx_usb_host_hs_hwmod,
  3396. .slave = &omap44xx_l3_main_2_hwmod,
  3397. .clk = "l3_div_ck",
  3398. .user = OCP_USER_MPU | OCP_USER_SDMA,
  3399. };
  3400. /* usb_otg_hs -> l3_main_2 */
  3401. static struct omap_hwmod_ocp_if omap44xx_usb_otg_hs__l3_main_2 = {
  3402. .master = &omap44xx_usb_otg_hs_hwmod,
  3403. .slave = &omap44xx_l3_main_2_hwmod,
  3404. .clk = "l3_div_ck",
  3405. .user = OCP_USER_MPU | OCP_USER_SDMA,
  3406. };
  3407. static struct omap_hwmod_addr_space omap44xx_l3_main_3_addrs[] = {
  3408. {
  3409. .pa_start = 0x45000000,
  3410. .pa_end = 0x45000fff,
  3411. .flags = ADDR_TYPE_RT
  3412. },
  3413. { }
  3414. };
  3415. /* l3_main_1 -> l3_main_3 */
  3416. static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = {
  3417. .master = &omap44xx_l3_main_1_hwmod,
  3418. .slave = &omap44xx_l3_main_3_hwmod,
  3419. .clk = "l3_div_ck",
  3420. .addr = omap44xx_l3_main_3_addrs,
  3421. .user = OCP_USER_MPU,
  3422. };
  3423. /* l3_main_2 -> l3_main_3 */
  3424. static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = {
  3425. .master = &omap44xx_l3_main_2_hwmod,
  3426. .slave = &omap44xx_l3_main_3_hwmod,
  3427. .clk = "l3_div_ck",
  3428. .user = OCP_USER_MPU | OCP_USER_SDMA,
  3429. };
  3430. /* l4_cfg -> l3_main_3 */
  3431. static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = {
  3432. .master = &omap44xx_l4_cfg_hwmod,
  3433. .slave = &omap44xx_l3_main_3_hwmod,
  3434. .clk = "l4_div_ck",
  3435. .user = OCP_USER_MPU | OCP_USER_SDMA,
  3436. };
  3437. /* aess -> l4_abe */
  3438. static struct omap_hwmod_ocp_if omap44xx_aess__l4_abe = {
  3439. .master = &omap44xx_aess_hwmod,
  3440. .slave = &omap44xx_l4_abe_hwmod,
  3441. .clk = "ocp_abe_iclk",
  3442. .user = OCP_USER_MPU | OCP_USER_SDMA,
  3443. };
  3444. /* dsp -> l4_abe */
  3445. static struct omap_hwmod_ocp_if omap44xx_dsp__l4_abe = {
  3446. .master = &omap44xx_dsp_hwmod,
  3447. .slave = &omap44xx_l4_abe_hwmod,
  3448. .clk = "ocp_abe_iclk",
  3449. .user = OCP_USER_MPU | OCP_USER_SDMA,
  3450. };
  3451. /* l3_main_1 -> l4_abe */
  3452. static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = {
  3453. .master = &omap44xx_l3_main_1_hwmod,
  3454. .slave = &omap44xx_l4_abe_hwmod,
  3455. .clk = "l3_div_ck",
  3456. .user = OCP_USER_MPU | OCP_USER_SDMA,
  3457. };
  3458. /* mpu -> l4_abe */
  3459. static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = {
  3460. .master = &omap44xx_mpu_hwmod,
  3461. .slave = &omap44xx_l4_abe_hwmod,
  3462. .clk = "ocp_abe_iclk",
  3463. .user = OCP_USER_MPU | OCP_USER_SDMA,
  3464. };
  3465. /* l3_main_1 -> l4_cfg */
  3466. static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = {
  3467. .master = &omap44xx_l3_main_1_hwmod,
  3468. .slave = &omap44xx_l4_cfg_hwmod,
  3469. .clk = "l3_div_ck",
  3470. .user = OCP_USER_MPU | OCP_USER_SDMA,
  3471. };
  3472. /* l3_main_2 -> l4_per */
  3473. static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = {
  3474. .master = &omap44xx_l3_main_2_hwmod,
  3475. .slave = &omap44xx_l4_per_hwmod,
  3476. .clk = "l3_div_ck",
  3477. .user = OCP_USER_MPU | OCP_USER_SDMA,
  3478. };
  3479. /* l4_cfg -> l4_wkup */
  3480. static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = {
  3481. .master = &omap44xx_l4_cfg_hwmod,
  3482. .slave = &omap44xx_l4_wkup_hwmod,
  3483. .clk = "l4_div_ck",
  3484. .user = OCP_USER_MPU | OCP_USER_SDMA,
  3485. };
  3486. /* mpu -> mpu_private */
  3487. static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = {
  3488. .master = &omap44xx_mpu_hwmod,
  3489. .slave = &omap44xx_mpu_private_hwmod,
  3490. .clk = "l3_div_ck",
  3491. .user = OCP_USER_MPU | OCP_USER_SDMA,
  3492. };
  3493. static struct omap_hwmod_addr_space omap44xx_ocp_wp_noc_addrs[] = {
  3494. {
  3495. .pa_start = 0x4a102000,
  3496. .pa_end = 0x4a10207f,
  3497. .flags = ADDR_TYPE_RT
  3498. },
  3499. { }
  3500. };
  3501. /* l4_cfg -> ocp_wp_noc */
  3502. static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp_wp_noc = {
  3503. .master = &omap44xx_l4_cfg_hwmod,
  3504. .slave = &omap44xx_ocp_wp_noc_hwmod,
  3505. .clk = "l4_div_ck",
  3506. .addr = omap44xx_ocp_wp_noc_addrs,
  3507. .user = OCP_USER_MPU | OCP_USER_SDMA,
  3508. };
  3509. static struct omap_hwmod_addr_space omap44xx_aess_addrs[] = {
  3510. {
  3511. .pa_start = 0x401f1000,
  3512. .pa_end = 0x401f13ff,
  3513. .flags = ADDR_TYPE_RT
  3514. },
  3515. { }
  3516. };
  3517. /* l4_abe -> aess */
  3518. static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess = {
  3519. .master = &omap44xx_l4_abe_hwmod,
  3520. .slave = &omap44xx_aess_hwmod,
  3521. .clk = "ocp_abe_iclk",
  3522. .addr = omap44xx_aess_addrs,
  3523. .user = OCP_USER_MPU,
  3524. };
  3525. static struct omap_hwmod_addr_space omap44xx_aess_dma_addrs[] = {
  3526. {
  3527. .pa_start = 0x490f1000,
  3528. .pa_end = 0x490f13ff,
  3529. .flags = ADDR_TYPE_RT
  3530. },
  3531. { }
  3532. };
  3533. /* l4_abe -> aess (dma) */
  3534. static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess_dma = {
  3535. .master = &omap44xx_l4_abe_hwmod,
  3536. .slave = &omap44xx_aess_hwmod,
  3537. .clk = "ocp_abe_iclk",
  3538. .addr = omap44xx_aess_dma_addrs,
  3539. .user = OCP_USER_SDMA,
  3540. };
  3541. /* l3_main_2 -> c2c */
  3542. static struct omap_hwmod_ocp_if omap44xx_l3_main_2__c2c = {
  3543. .master = &omap44xx_l3_main_2_hwmod,
  3544. .slave = &omap44xx_c2c_hwmod,
  3545. .clk = "l3_div_ck",
  3546. .user = OCP_USER_MPU | OCP_USER_SDMA,
  3547. };
  3548. static struct omap_hwmod_addr_space omap44xx_counter_32k_addrs[] = {
  3549. {
  3550. .pa_start = 0x4a304000,
  3551. .pa_end = 0x4a30401f,
  3552. .flags = ADDR_TYPE_RT
  3553. },
  3554. { }
  3555. };
  3556. /* l4_wkup -> counter_32k */
  3557. static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = {
  3558. .master = &omap44xx_l4_wkup_hwmod,
  3559. .slave = &omap44xx_counter_32k_hwmod,
  3560. .clk = "l4_wkup_clk_mux_ck",
  3561. .addr = omap44xx_counter_32k_addrs,
  3562. .user = OCP_USER_MPU | OCP_USER_SDMA,
  3563. };
  3564. static struct omap_hwmod_addr_space omap44xx_ctrl_module_core_addrs[] = {
  3565. {
  3566. .pa_start = 0x4a002000,
  3567. .pa_end = 0x4a0027ff,
  3568. .flags = ADDR_TYPE_RT
  3569. },
  3570. { }
  3571. };
  3572. /* l4_cfg -> ctrl_module_core */
  3573. static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_core = {
  3574. .master = &omap44xx_l4_cfg_hwmod,
  3575. .slave = &omap44xx_ctrl_module_core_hwmod,
  3576. .clk = "l4_div_ck",
  3577. .addr = omap44xx_ctrl_module_core_addrs,
  3578. .user = OCP_USER_MPU | OCP_USER_SDMA,
  3579. };
  3580. static struct omap_hwmod_addr_space omap44xx_ctrl_module_pad_core_addrs[] = {
  3581. {
  3582. .pa_start = 0x4a100000,
  3583. .pa_end = 0x4a1007ff,
  3584. .flags = ADDR_TYPE_RT
  3585. },
  3586. { }
  3587. };
  3588. /* l4_cfg -> ctrl_module_pad_core */
  3589. static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_pad_core = {
  3590. .master = &omap44xx_l4_cfg_hwmod,
  3591. .slave = &omap44xx_ctrl_module_pad_core_hwmod,
  3592. .clk = "l4_div_ck",
  3593. .addr = omap44xx_ctrl_module_pad_core_addrs,
  3594. .user = OCP_USER_MPU | OCP_USER_SDMA,
  3595. };
  3596. static struct omap_hwmod_addr_space omap44xx_ctrl_module_wkup_addrs[] = {
  3597. {
  3598. .pa_start = 0x4a30c000,
  3599. .pa_end = 0x4a30c7ff,
  3600. .flags = ADDR_TYPE_RT
  3601. },
  3602. { }
  3603. };
  3604. /* l4_wkup -> ctrl_module_wkup */
  3605. static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_wkup = {
  3606. .master = &omap44xx_l4_wkup_hwmod,
  3607. .slave = &omap44xx_ctrl_module_wkup_hwmod,
  3608. .clk = "l4_wkup_clk_mux_ck",
  3609. .addr = omap44xx_ctrl_module_wkup_addrs,
  3610. .user = OCP_USER_MPU | OCP_USER_SDMA,
  3611. };
  3612. static struct omap_hwmod_addr_space omap44xx_ctrl_module_pad_wkup_addrs[] = {
  3613. {
  3614. .pa_start = 0x4a31e000,
  3615. .pa_end = 0x4a31e7ff,
  3616. .flags = ADDR_TYPE_RT
  3617. },
  3618. { }
  3619. };
  3620. /* l4_wkup -> ctrl_module_pad_wkup */
  3621. static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_pad_wkup = {
  3622. .master = &omap44xx_l4_wkup_hwmod,
  3623. .slave = &omap44xx_ctrl_module_pad_wkup_hwmod,
  3624. .clk = "l4_wkup_clk_mux_ck",
  3625. .addr = omap44xx_ctrl_module_pad_wkup_addrs,
  3626. .user = OCP_USER_MPU | OCP_USER_SDMA,
  3627. };
  3628. static struct omap_hwmod_addr_space omap44xx_dma_system_addrs[] = {
  3629. {
  3630. .pa_start = 0x4a056000,
  3631. .pa_end = 0x4a056fff,
  3632. .flags = ADDR_TYPE_RT
  3633. },
  3634. { }
  3635. };
  3636. /* l4_cfg -> dma_system */
  3637. static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = {
  3638. .master = &omap44xx_l4_cfg_hwmod,
  3639. .slave = &omap44xx_dma_system_hwmod,
  3640. .clk = "l4_div_ck",
  3641. .addr = omap44xx_dma_system_addrs,
  3642. .user = OCP_USER_MPU | OCP_USER_SDMA,
  3643. };
  3644. static struct omap_hwmod_addr_space omap44xx_dmic_addrs[] = {
  3645. {
  3646. .name = "mpu",
  3647. .pa_start = 0x4012e000,
  3648. .pa_end = 0x4012e07f,
  3649. .flags = ADDR_TYPE_RT
  3650. },
  3651. { }
  3652. };
  3653. /* l4_abe -> dmic */
  3654. static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic = {
  3655. .master = &omap44xx_l4_abe_hwmod,
  3656. .slave = &omap44xx_dmic_hwmod,
  3657. .clk = "ocp_abe_iclk",
  3658. .addr = omap44xx_dmic_addrs,
  3659. .user = OCP_USER_MPU,
  3660. };
  3661. static struct omap_hwmod_addr_space omap44xx_dmic_dma_addrs[] = {
  3662. {
  3663. .name = "dma",
  3664. .pa_start = 0x4902e000,
  3665. .pa_end = 0x4902e07f,
  3666. .flags = ADDR_TYPE_RT
  3667. },
  3668. { }
  3669. };
  3670. /* l4_abe -> dmic (dma) */
  3671. static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic_dma = {
  3672. .master = &omap44xx_l4_abe_hwmod,
  3673. .slave = &omap44xx_dmic_hwmod,
  3674. .clk = "ocp_abe_iclk",
  3675. .addr = omap44xx_dmic_dma_addrs,
  3676. .user = OCP_USER_SDMA,
  3677. };
  3678. /* dsp -> iva */
  3679. static struct omap_hwmod_ocp_if omap44xx_dsp__iva = {
  3680. .master = &omap44xx_dsp_hwmod,
  3681. .slave = &omap44xx_iva_hwmod,
  3682. .clk = "dpll_iva_m5x2_ck",
  3683. .user = OCP_USER_DSP,
  3684. };
  3685. /* dsp -> sl2if */
  3686. static struct omap_hwmod_ocp_if omap44xx_dsp__sl2if = {
  3687. .master = &omap44xx_dsp_hwmod,
  3688. .slave = &omap44xx_sl2if_hwmod,
  3689. .clk = "dpll_iva_m5x2_ck",
  3690. .user = OCP_USER_DSP,
  3691. };
  3692. /* l4_cfg -> dsp */
  3693. static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dsp = {
  3694. .master = &omap44xx_l4_cfg_hwmod,
  3695. .slave = &omap44xx_dsp_hwmod,
  3696. .clk = "l4_div_ck",
  3697. .user = OCP_USER_MPU | OCP_USER_SDMA,
  3698. };
  3699. static struct omap_hwmod_addr_space omap44xx_dss_dma_addrs[] = {
  3700. {
  3701. .pa_start = 0x58000000,
  3702. .pa_end = 0x5800007f,
  3703. .flags = ADDR_TYPE_RT
  3704. },
  3705. { }
  3706. };
  3707. /* l3_main_2 -> dss */
  3708. static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss = {
  3709. .master = &omap44xx_l3_main_2_hwmod,
  3710. .slave = &omap44xx_dss_hwmod,
  3711. .clk = "dss_fck",
  3712. .addr = omap44xx_dss_dma_addrs,
  3713. .user = OCP_USER_SDMA,
  3714. };
  3715. static struct omap_hwmod_addr_space omap44xx_dss_addrs[] = {
  3716. {
  3717. .pa_start = 0x48040000,
  3718. .pa_end = 0x4804007f,
  3719. .flags = ADDR_TYPE_RT
  3720. },
  3721. { }
  3722. };
  3723. /* l4_per -> dss */
  3724. static struct omap_hwmod_ocp_if omap44xx_l4_per__dss = {
  3725. .master = &omap44xx_l4_per_hwmod,
  3726. .slave = &omap44xx_dss_hwmod,
  3727. .clk = "l4_div_ck",
  3728. .addr = omap44xx_dss_addrs,
  3729. .user = OCP_USER_MPU,
  3730. };
  3731. static struct omap_hwmod_addr_space omap44xx_dss_dispc_dma_addrs[] = {
  3732. {
  3733. .pa_start = 0x58001000,
  3734. .pa_end = 0x58001fff,
  3735. .flags = ADDR_TYPE_RT
  3736. },
  3737. { }
  3738. };
  3739. /* l3_main_2 -> dss_dispc */
  3740. static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc = {
  3741. .master = &omap44xx_l3_main_2_hwmod,
  3742. .slave = &omap44xx_dss_dispc_hwmod,
  3743. .clk = "dss_fck",
  3744. .addr = omap44xx_dss_dispc_dma_addrs,
  3745. .user = OCP_USER_SDMA,
  3746. };
  3747. static struct omap_hwmod_addr_space omap44xx_dss_dispc_addrs[] = {
  3748. {
  3749. .pa_start = 0x48041000,
  3750. .pa_end = 0x48041fff,
  3751. .flags = ADDR_TYPE_RT
  3752. },
  3753. { }
  3754. };
  3755. /* l4_per -> dss_dispc */
  3756. static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc = {
  3757. .master = &omap44xx_l4_per_hwmod,
  3758. .slave = &omap44xx_dss_dispc_hwmod,
  3759. .clk = "l4_div_ck",
  3760. .addr = omap44xx_dss_dispc_addrs,
  3761. .user = OCP_USER_MPU,
  3762. };
  3763. static struct omap_hwmod_addr_space omap44xx_dss_dsi1_dma_addrs[] = {
  3764. {
  3765. .pa_start = 0x58004000,
  3766. .pa_end = 0x580041ff,
  3767. .flags = ADDR_TYPE_RT
  3768. },
  3769. { }
  3770. };
  3771. /* l3_main_2 -> dss_dsi1 */
  3772. static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1 = {
  3773. .master = &omap44xx_l3_main_2_hwmod,
  3774. .slave = &omap44xx_dss_dsi1_hwmod,
  3775. .clk = "dss_fck",
  3776. .addr = omap44xx_dss_dsi1_dma_addrs,
  3777. .user = OCP_USER_SDMA,
  3778. };
  3779. static struct omap_hwmod_addr_space omap44xx_dss_dsi1_addrs[] = {
  3780. {
  3781. .pa_start = 0x48044000,
  3782. .pa_end = 0x480441ff,
  3783. .flags = ADDR_TYPE_RT
  3784. },
  3785. { }
  3786. };
  3787. /* l4_per -> dss_dsi1 */
  3788. static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi1 = {
  3789. .master = &omap44xx_l4_per_hwmod,
  3790. .slave = &omap44xx_dss_dsi1_hwmod,
  3791. .clk = "l4_div_ck",
  3792. .addr = omap44xx_dss_dsi1_addrs,
  3793. .user = OCP_USER_MPU,
  3794. };
  3795. static struct omap_hwmod_addr_space omap44xx_dss_dsi2_dma_addrs[] = {
  3796. {
  3797. .pa_start = 0x58005000,
  3798. .pa_end = 0x580051ff,
  3799. .flags = ADDR_TYPE_RT
  3800. },
  3801. { }
  3802. };
  3803. /* l3_main_2 -> dss_dsi2 */
  3804. static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2 = {
  3805. .master = &omap44xx_l3_main_2_hwmod,
  3806. .slave = &omap44xx_dss_dsi2_hwmod,
  3807. .clk = "dss_fck",
  3808. .addr = omap44xx_dss_dsi2_dma_addrs,
  3809. .user = OCP_USER_SDMA,
  3810. };
  3811. static struct omap_hwmod_addr_space omap44xx_dss_dsi2_addrs[] = {
  3812. {
  3813. .pa_start = 0x48045000,
  3814. .pa_end = 0x480451ff,
  3815. .flags = ADDR_TYPE_RT
  3816. },
  3817. { }
  3818. };
  3819. /* l4_per -> dss_dsi2 */
  3820. static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi2 = {
  3821. .master = &omap44xx_l4_per_hwmod,
  3822. .slave = &omap44xx_dss_dsi2_hwmod,
  3823. .clk = "l4_div_ck",
  3824. .addr = omap44xx_dss_dsi2_addrs,
  3825. .user = OCP_USER_MPU,
  3826. };
  3827. static struct omap_hwmod_addr_space omap44xx_dss_hdmi_dma_addrs[] = {
  3828. {
  3829. .pa_start = 0x58006000,
  3830. .pa_end = 0x58006fff,
  3831. .flags = ADDR_TYPE_RT
  3832. },
  3833. { }
  3834. };
  3835. /* l3_main_2 -> dss_hdmi */
  3836. static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi = {
  3837. .master = &omap44xx_l3_main_2_hwmod,
  3838. .slave = &omap44xx_dss_hdmi_hwmod,
  3839. .clk = "dss_fck",
  3840. .addr = omap44xx_dss_hdmi_dma_addrs,
  3841. .user = OCP_USER_SDMA,
  3842. };
  3843. static struct omap_hwmod_addr_space omap44xx_dss_hdmi_addrs[] = {
  3844. {
  3845. .pa_start = 0x48046000,
  3846. .pa_end = 0x48046fff,
  3847. .flags = ADDR_TYPE_RT
  3848. },
  3849. { }
  3850. };
  3851. /* l4_per -> dss_hdmi */
  3852. static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_hdmi = {
  3853. .master = &omap44xx_l4_per_hwmod,
  3854. .slave = &omap44xx_dss_hdmi_hwmod,
  3855. .clk = "l4_div_ck",
  3856. .addr = omap44xx_dss_hdmi_addrs,
  3857. .user = OCP_USER_MPU,
  3858. };
  3859. static struct omap_hwmod_addr_space omap44xx_dss_rfbi_dma_addrs[] = {
  3860. {
  3861. .pa_start = 0x58002000,
  3862. .pa_end = 0x580020ff,
  3863. .flags = ADDR_TYPE_RT
  3864. },
  3865. { }
  3866. };
  3867. /* l3_main_2 -> dss_rfbi */
  3868. static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi = {
  3869. .master = &omap44xx_l3_main_2_hwmod,
  3870. .slave = &omap44xx_dss_rfbi_hwmod,
  3871. .clk = "dss_fck",
  3872. .addr = omap44xx_dss_rfbi_dma_addrs,
  3873. .user = OCP_USER_SDMA,
  3874. };
  3875. static struct omap_hwmod_addr_space omap44xx_dss_rfbi_addrs[] = {
  3876. {
  3877. .pa_start = 0x48042000,
  3878. .pa_end = 0x480420ff,
  3879. .flags = ADDR_TYPE_RT
  3880. },
  3881. { }
  3882. };
  3883. /* l4_per -> dss_rfbi */
  3884. static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_rfbi = {
  3885. .master = &omap44xx_l4_per_hwmod,
  3886. .slave = &omap44xx_dss_rfbi_hwmod,
  3887. .clk = "l4_div_ck",
  3888. .addr = omap44xx_dss_rfbi_addrs,
  3889. .user = OCP_USER_MPU,
  3890. };
  3891. static struct omap_hwmod_addr_space omap44xx_dss_venc_dma_addrs[] = {
  3892. {
  3893. .pa_start = 0x58003000,
  3894. .pa_end = 0x580030ff,
  3895. .flags = ADDR_TYPE_RT
  3896. },
  3897. { }
  3898. };
  3899. /* l3_main_2 -> dss_venc */
  3900. static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc = {
  3901. .master = &omap44xx_l3_main_2_hwmod,
  3902. .slave = &omap44xx_dss_venc_hwmod,
  3903. .clk = "dss_fck",
  3904. .addr = omap44xx_dss_venc_dma_addrs,
  3905. .user = OCP_USER_SDMA,
  3906. };
  3907. static struct omap_hwmod_addr_space omap44xx_dss_venc_addrs[] = {
  3908. {
  3909. .pa_start = 0x48043000,
  3910. .pa_end = 0x480430ff,
  3911. .flags = ADDR_TYPE_RT
  3912. },
  3913. { }
  3914. };
  3915. /* l4_per -> dss_venc */
  3916. static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = {
  3917. .master = &omap44xx_l4_per_hwmod,
  3918. .slave = &omap44xx_dss_venc_hwmod,
  3919. .clk = "l4_div_ck",
  3920. .addr = omap44xx_dss_venc_addrs,
  3921. .user = OCP_USER_MPU,
  3922. };
  3923. static struct omap_hwmod_addr_space omap44xx_elm_addrs[] = {
  3924. {
  3925. .pa_start = 0x48078000,
  3926. .pa_end = 0x48078fff,
  3927. .flags = ADDR_TYPE_RT
  3928. },
  3929. { }
  3930. };
  3931. /* l4_per -> elm */
  3932. static struct omap_hwmod_ocp_if omap44xx_l4_per__elm = {
  3933. .master = &omap44xx_l4_per_hwmod,
  3934. .slave = &omap44xx_elm_hwmod,
  3935. .clk = "l4_div_ck",
  3936. .addr = omap44xx_elm_addrs,
  3937. .user = OCP_USER_MPU | OCP_USER_SDMA,
  3938. };
  3939. static struct omap_hwmod_addr_space omap44xx_emif1_addrs[] = {
  3940. {
  3941. .pa_start = 0x4c000000,
  3942. .pa_end = 0x4c0000ff,
  3943. .flags = ADDR_TYPE_RT
  3944. },
  3945. { }
  3946. };
  3947. /* emif_fw -> emif1 */
  3948. static struct omap_hwmod_ocp_if omap44xx_emif_fw__emif1 = {
  3949. .master = &omap44xx_emif_fw_hwmod,
  3950. .slave = &omap44xx_emif1_hwmod,
  3951. .clk = "l3_div_ck",
  3952. .addr = omap44xx_emif1_addrs,
  3953. .user = OCP_USER_MPU | OCP_USER_SDMA,
  3954. };
  3955. static struct omap_hwmod_addr_space omap44xx_emif2_addrs[] = {
  3956. {
  3957. .pa_start = 0x4d000000,
  3958. .pa_end = 0x4d0000ff,
  3959. .flags = ADDR_TYPE_RT
  3960. },
  3961. { }
  3962. };
  3963. /* emif_fw -> emif2 */
  3964. static struct omap_hwmod_ocp_if omap44xx_emif_fw__emif2 = {
  3965. .master = &omap44xx_emif_fw_hwmod,
  3966. .slave = &omap44xx_emif2_hwmod,
  3967. .clk = "l3_div_ck",
  3968. .addr = omap44xx_emif2_addrs,
  3969. .user = OCP_USER_MPU | OCP_USER_SDMA,
  3970. };
  3971. static struct omap_hwmod_addr_space omap44xx_fdif_addrs[] = {
  3972. {
  3973. .pa_start = 0x4a10a000,
  3974. .pa_end = 0x4a10a1ff,
  3975. .flags = ADDR_TYPE_RT
  3976. },
  3977. { }
  3978. };
  3979. /* l4_cfg -> fdif */
  3980. static struct omap_hwmod_ocp_if omap44xx_l4_cfg__fdif = {
  3981. .master = &omap44xx_l4_cfg_hwmod,
  3982. .slave = &omap44xx_fdif_hwmod,
  3983. .clk = "l4_div_ck",
  3984. .addr = omap44xx_fdif_addrs,
  3985. .user = OCP_USER_MPU | OCP_USER_SDMA,
  3986. };
  3987. static struct omap_hwmod_addr_space omap44xx_gpio1_addrs[] = {
  3988. {
  3989. .pa_start = 0x4a310000,
  3990. .pa_end = 0x4a3101ff,
  3991. .flags = ADDR_TYPE_RT
  3992. },
  3993. { }
  3994. };
  3995. /* l4_wkup -> gpio1 */
  3996. static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = {
  3997. .master = &omap44xx_l4_wkup_hwmod,
  3998. .slave = &omap44xx_gpio1_hwmod,
  3999. .clk = "l4_wkup_clk_mux_ck",
  4000. .addr = omap44xx_gpio1_addrs,
  4001. .user = OCP_USER_MPU | OCP_USER_SDMA,
  4002. };
  4003. static struct omap_hwmod_addr_space omap44xx_gpio2_addrs[] = {
  4004. {
  4005. .pa_start = 0x48055000,
  4006. .pa_end = 0x480551ff,
  4007. .flags = ADDR_TYPE_RT
  4008. },
  4009. { }
  4010. };
  4011. /* l4_per -> gpio2 */
  4012. static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = {
  4013. .master = &omap44xx_l4_per_hwmod,
  4014. .slave = &omap44xx_gpio2_hwmod,
  4015. .clk = "l4_div_ck",
  4016. .addr = omap44xx_gpio2_addrs,
  4017. .user = OCP_USER_MPU | OCP_USER_SDMA,
  4018. };
  4019. static struct omap_hwmod_addr_space omap44xx_gpio3_addrs[] = {
  4020. {
  4021. .pa_start = 0x48057000,
  4022. .pa_end = 0x480571ff,
  4023. .flags = ADDR_TYPE_RT
  4024. },
  4025. { }
  4026. };
  4027. /* l4_per -> gpio3 */
  4028. static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = {
  4029. .master = &omap44xx_l4_per_hwmod,
  4030. .slave = &omap44xx_gpio3_hwmod,
  4031. .clk = "l4_div_ck",
  4032. .addr = omap44xx_gpio3_addrs,
  4033. .user = OCP_USER_MPU | OCP_USER_SDMA,
  4034. };
  4035. static struct omap_hwmod_addr_space omap44xx_gpio4_addrs[] = {
  4036. {
  4037. .pa_start = 0x48059000,
  4038. .pa_end = 0x480591ff,
  4039. .flags = ADDR_TYPE_RT
  4040. },
  4041. { }
  4042. };
  4043. /* l4_per -> gpio4 */
  4044. static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = {
  4045. .master = &omap44xx_l4_per_hwmod,
  4046. .slave = &omap44xx_gpio4_hwmod,
  4047. .clk = "l4_div_ck",
  4048. .addr = omap44xx_gpio4_addrs,
  4049. .user = OCP_USER_MPU | OCP_USER_SDMA,
  4050. };
  4051. static struct omap_hwmod_addr_space omap44xx_gpio5_addrs[] = {
  4052. {
  4053. .pa_start = 0x4805b000,
  4054. .pa_end = 0x4805b1ff,
  4055. .flags = ADDR_TYPE_RT
  4056. },
  4057. { }
  4058. };
  4059. /* l4_per -> gpio5 */
  4060. static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = {
  4061. .master = &omap44xx_l4_per_hwmod,
  4062. .slave = &omap44xx_gpio5_hwmod,
  4063. .clk = "l4_div_ck",
  4064. .addr = omap44xx_gpio5_addrs,
  4065. .user = OCP_USER_MPU | OCP_USER_SDMA,
  4066. };
  4067. static struct omap_hwmod_addr_space omap44xx_gpio6_addrs[] = {
  4068. {
  4069. .pa_start = 0x4805d000,
  4070. .pa_end = 0x4805d1ff,
  4071. .flags = ADDR_TYPE_RT
  4072. },
  4073. { }
  4074. };
  4075. /* l4_per -> gpio6 */
  4076. static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = {
  4077. .master = &omap44xx_l4_per_hwmod,
  4078. .slave = &omap44xx_gpio6_hwmod,
  4079. .clk = "l4_div_ck",
  4080. .addr = omap44xx_gpio6_addrs,
  4081. .user = OCP_USER_MPU | OCP_USER_SDMA,
  4082. };
  4083. static struct omap_hwmod_addr_space omap44xx_gpmc_addrs[] = {
  4084. {
  4085. .pa_start = 0x50000000,
  4086. .pa_end = 0x500003ff,
  4087. .flags = ADDR_TYPE_RT
  4088. },
  4089. { }
  4090. };
  4091. /* l3_main_2 -> gpmc */
  4092. static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpmc = {
  4093. .master = &omap44xx_l3_main_2_hwmod,
  4094. .slave = &omap44xx_gpmc_hwmod,
  4095. .clk = "l3_div_ck",
  4096. .addr = omap44xx_gpmc_addrs,
  4097. .user = OCP_USER_MPU | OCP_USER_SDMA,
  4098. };
  4099. static struct omap_hwmod_addr_space omap44xx_gpu_addrs[] = {
  4100. {
  4101. .pa_start = 0x56000000,
  4102. .pa_end = 0x5600ffff,
  4103. .flags = ADDR_TYPE_RT
  4104. },
  4105. { }
  4106. };
  4107. /* l3_main_2 -> gpu */
  4108. static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpu = {
  4109. .master = &omap44xx_l3_main_2_hwmod,
  4110. .slave = &omap44xx_gpu_hwmod,
  4111. .clk = "l3_div_ck",
  4112. .addr = omap44xx_gpu_addrs,
  4113. .user = OCP_USER_MPU | OCP_USER_SDMA,
  4114. };
  4115. static struct omap_hwmod_addr_space omap44xx_hdq1w_addrs[] = {
  4116. {
  4117. .pa_start = 0x480b2000,
  4118. .pa_end = 0x480b201f,
  4119. .flags = ADDR_TYPE_RT
  4120. },
  4121. { }
  4122. };
  4123. /* l4_per -> hdq1w */
  4124. static struct omap_hwmod_ocp_if omap44xx_l4_per__hdq1w = {
  4125. .master = &omap44xx_l4_per_hwmod,
  4126. .slave = &omap44xx_hdq1w_hwmod,
  4127. .clk = "l4_div_ck",
  4128. .addr = omap44xx_hdq1w_addrs,
  4129. .user = OCP_USER_MPU | OCP_USER_SDMA,
  4130. };
  4131. static struct omap_hwmod_addr_space omap44xx_hsi_addrs[] = {
  4132. {
  4133. .pa_start = 0x4a058000,
  4134. .pa_end = 0x4a05bfff,
  4135. .flags = ADDR_TYPE_RT
  4136. },
  4137. { }
  4138. };
  4139. /* l4_cfg -> hsi */
  4140. static struct omap_hwmod_ocp_if omap44xx_l4_cfg__hsi = {
  4141. .master = &omap44xx_l4_cfg_hwmod,
  4142. .slave = &omap44xx_hsi_hwmod,
  4143. .clk = "l4_div_ck",
  4144. .addr = omap44xx_hsi_addrs,
  4145. .user = OCP_USER_MPU | OCP_USER_SDMA,
  4146. };
  4147. static struct omap_hwmod_addr_space omap44xx_i2c1_addrs[] = {
  4148. {
  4149. .pa_start = 0x48070000,
  4150. .pa_end = 0x480700ff,
  4151. .flags = ADDR_TYPE_RT
  4152. },
  4153. { }
  4154. };
  4155. /* l4_per -> i2c1 */
  4156. static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = {
  4157. .master = &omap44xx_l4_per_hwmod,
  4158. .slave = &omap44xx_i2c1_hwmod,
  4159. .clk = "l4_div_ck",
  4160. .addr = omap44xx_i2c1_addrs,
  4161. .user = OCP_USER_MPU | OCP_USER_SDMA,
  4162. };
  4163. static struct omap_hwmod_addr_space omap44xx_i2c2_addrs[] = {
  4164. {
  4165. .pa_start = 0x48072000,
  4166. .pa_end = 0x480720ff,
  4167. .flags = ADDR_TYPE_RT
  4168. },
  4169. { }
  4170. };
  4171. /* l4_per -> i2c2 */
  4172. static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = {
  4173. .master = &omap44xx_l4_per_hwmod,
  4174. .slave = &omap44xx_i2c2_hwmod,
  4175. .clk = "l4_div_ck",
  4176. .addr = omap44xx_i2c2_addrs,
  4177. .user = OCP_USER_MPU | OCP_USER_SDMA,
  4178. };
  4179. static struct omap_hwmod_addr_space omap44xx_i2c3_addrs[] = {
  4180. {
  4181. .pa_start = 0x48060000,
  4182. .pa_end = 0x480600ff,
  4183. .flags = ADDR_TYPE_RT
  4184. },
  4185. { }
  4186. };
  4187. /* l4_per -> i2c3 */
  4188. static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = {
  4189. .master = &omap44xx_l4_per_hwmod,
  4190. .slave = &omap44xx_i2c3_hwmod,
  4191. .clk = "l4_div_ck",
  4192. .addr = omap44xx_i2c3_addrs,
  4193. .user = OCP_USER_MPU | OCP_USER_SDMA,
  4194. };
  4195. static struct omap_hwmod_addr_space omap44xx_i2c4_addrs[] = {
  4196. {
  4197. .pa_start = 0x48350000,
  4198. .pa_end = 0x483500ff,
  4199. .flags = ADDR_TYPE_RT
  4200. },
  4201. { }
  4202. };
  4203. /* l4_per -> i2c4 */
  4204. static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = {
  4205. .master = &omap44xx_l4_per_hwmod,
  4206. .slave = &omap44xx_i2c4_hwmod,
  4207. .clk = "l4_div_ck",
  4208. .addr = omap44xx_i2c4_addrs,
  4209. .user = OCP_USER_MPU | OCP_USER_SDMA,
  4210. };
  4211. /* l3_main_2 -> ipu */
  4212. static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ipu = {
  4213. .master = &omap44xx_l3_main_2_hwmod,
  4214. .slave = &omap44xx_ipu_hwmod,
  4215. .clk = "l3_div_ck",
  4216. .user = OCP_USER_MPU | OCP_USER_SDMA,
  4217. };
  4218. static struct omap_hwmod_addr_space omap44xx_iss_addrs[] = {
  4219. {
  4220. .pa_start = 0x52000000,
  4221. .pa_end = 0x520000ff,
  4222. .flags = ADDR_TYPE_RT
  4223. },
  4224. { }
  4225. };
  4226. /* l3_main_2 -> iss */
  4227. static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = {
  4228. .master = &omap44xx_l3_main_2_hwmod,
  4229. .slave = &omap44xx_iss_hwmod,
  4230. .clk = "l3_div_ck",
  4231. .addr = omap44xx_iss_addrs,
  4232. .user = OCP_USER_MPU | OCP_USER_SDMA,
  4233. };
  4234. /* iva -> sl2if */
  4235. static struct omap_hwmod_ocp_if omap44xx_iva__sl2if = {
  4236. .master = &omap44xx_iva_hwmod,
  4237. .slave = &omap44xx_sl2if_hwmod,
  4238. .clk = "dpll_iva_m5x2_ck",
  4239. .user = OCP_USER_IVA,
  4240. };
  4241. static struct omap_hwmod_addr_space omap44xx_iva_addrs[] = {
  4242. {
  4243. .pa_start = 0x5a000000,
  4244. .pa_end = 0x5a07ffff,
  4245. .flags = ADDR_TYPE_RT
  4246. },
  4247. { }
  4248. };
  4249. /* l3_main_2 -> iva */
  4250. static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = {
  4251. .master = &omap44xx_l3_main_2_hwmod,
  4252. .slave = &omap44xx_iva_hwmod,
  4253. .clk = "l3_div_ck",
  4254. .addr = omap44xx_iva_addrs,
  4255. .user = OCP_USER_MPU,
  4256. };
  4257. static struct omap_hwmod_addr_space omap44xx_kbd_addrs[] = {
  4258. {
  4259. .pa_start = 0x4a31c000,
  4260. .pa_end = 0x4a31c07f,
  4261. .flags = ADDR_TYPE_RT
  4262. },
  4263. { }
  4264. };
  4265. /* l4_wkup -> kbd */
  4266. static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd = {
  4267. .master = &omap44xx_l4_wkup_hwmod,
  4268. .slave = &omap44xx_kbd_hwmod,
  4269. .clk = "l4_wkup_clk_mux_ck",
  4270. .addr = omap44xx_kbd_addrs,
  4271. .user = OCP_USER_MPU | OCP_USER_SDMA,
  4272. };
  4273. static struct omap_hwmod_addr_space omap44xx_mailbox_addrs[] = {
  4274. {
  4275. .pa_start = 0x4a0f4000,
  4276. .pa_end = 0x4a0f41ff,
  4277. .flags = ADDR_TYPE_RT
  4278. },
  4279. { }
  4280. };
  4281. /* l4_cfg -> mailbox */
  4282. static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mailbox = {
  4283. .master = &omap44xx_l4_cfg_hwmod,
  4284. .slave = &omap44xx_mailbox_hwmod,
  4285. .clk = "l4_div_ck",
  4286. .addr = omap44xx_mailbox_addrs,
  4287. .user = OCP_USER_MPU | OCP_USER_SDMA,
  4288. };
  4289. static struct omap_hwmod_addr_space omap44xx_mcasp_addrs[] = {
  4290. {
  4291. .pa_start = 0x40128000,
  4292. .pa_end = 0x401283ff,
  4293. .flags = ADDR_TYPE_RT
  4294. },
  4295. { }
  4296. };
  4297. /* l4_abe -> mcasp */
  4298. static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp = {
  4299. .master = &omap44xx_l4_abe_hwmod,
  4300. .slave = &omap44xx_mcasp_hwmod,
  4301. .clk = "ocp_abe_iclk",
  4302. .addr = omap44xx_mcasp_addrs,
  4303. .user = OCP_USER_MPU,
  4304. };
  4305. static struct omap_hwmod_addr_space omap44xx_mcasp_dma_addrs[] = {
  4306. {
  4307. .pa_start = 0x49028000,
  4308. .pa_end = 0x490283ff,
  4309. .flags = ADDR_TYPE_RT
  4310. },
  4311. { }
  4312. };
  4313. /* l4_abe -> mcasp (dma) */
  4314. static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp_dma = {
  4315. .master = &omap44xx_l4_abe_hwmod,
  4316. .slave = &omap44xx_mcasp_hwmod,
  4317. .clk = "ocp_abe_iclk",
  4318. .addr = omap44xx_mcasp_dma_addrs,
  4319. .user = OCP_USER_SDMA,
  4320. };
  4321. static struct omap_hwmod_addr_space omap44xx_mcbsp1_addrs[] = {
  4322. {
  4323. .name = "mpu",
  4324. .pa_start = 0x40122000,
  4325. .pa_end = 0x401220ff,
  4326. .flags = ADDR_TYPE_RT
  4327. },
  4328. { }
  4329. };
  4330. /* l4_abe -> mcbsp1 */
  4331. static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1 = {
  4332. .master = &omap44xx_l4_abe_hwmod,
  4333. .slave = &omap44xx_mcbsp1_hwmod,
  4334. .clk = "ocp_abe_iclk",
  4335. .addr = omap44xx_mcbsp1_addrs,
  4336. .user = OCP_USER_MPU,
  4337. };
  4338. static struct omap_hwmod_addr_space omap44xx_mcbsp1_dma_addrs[] = {
  4339. {
  4340. .name = "dma",
  4341. .pa_start = 0x49022000,
  4342. .pa_end = 0x490220ff,
  4343. .flags = ADDR_TYPE_RT
  4344. },
  4345. { }
  4346. };
  4347. /* l4_abe -> mcbsp1 (dma) */
  4348. static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1_dma = {
  4349. .master = &omap44xx_l4_abe_hwmod,
  4350. .slave = &omap44xx_mcbsp1_hwmod,
  4351. .clk = "ocp_abe_iclk",
  4352. .addr = omap44xx_mcbsp1_dma_addrs,
  4353. .user = OCP_USER_SDMA,
  4354. };
  4355. static struct omap_hwmod_addr_space omap44xx_mcbsp2_addrs[] = {
  4356. {
  4357. .name = "mpu",
  4358. .pa_start = 0x40124000,
  4359. .pa_end = 0x401240ff,
  4360. .flags = ADDR_TYPE_RT
  4361. },
  4362. { }
  4363. };
  4364. /* l4_abe -> mcbsp2 */
  4365. static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2 = {
  4366. .master = &omap44xx_l4_abe_hwmod,
  4367. .slave = &omap44xx_mcbsp2_hwmod,
  4368. .clk = "ocp_abe_iclk",
  4369. .addr = omap44xx_mcbsp2_addrs,
  4370. .user = OCP_USER_MPU,
  4371. };
  4372. static struct omap_hwmod_addr_space omap44xx_mcbsp2_dma_addrs[] = {
  4373. {
  4374. .name = "dma",
  4375. .pa_start = 0x49024000,
  4376. .pa_end = 0x490240ff,
  4377. .flags = ADDR_TYPE_RT
  4378. },
  4379. { }
  4380. };
  4381. /* l4_abe -> mcbsp2 (dma) */
  4382. static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2_dma = {
  4383. .master = &omap44xx_l4_abe_hwmod,
  4384. .slave = &omap44xx_mcbsp2_hwmod,
  4385. .clk = "ocp_abe_iclk",
  4386. .addr = omap44xx_mcbsp2_dma_addrs,
  4387. .user = OCP_USER_SDMA,
  4388. };
  4389. static struct omap_hwmod_addr_space omap44xx_mcbsp3_addrs[] = {
  4390. {
  4391. .name = "mpu",
  4392. .pa_start = 0x40126000,
  4393. .pa_end = 0x401260ff,
  4394. .flags = ADDR_TYPE_RT
  4395. },
  4396. { }
  4397. };
  4398. /* l4_abe -> mcbsp3 */
  4399. static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3 = {
  4400. .master = &omap44xx_l4_abe_hwmod,
  4401. .slave = &omap44xx_mcbsp3_hwmod,
  4402. .clk = "ocp_abe_iclk",
  4403. .addr = omap44xx_mcbsp3_addrs,
  4404. .user = OCP_USER_MPU,
  4405. };
  4406. static struct omap_hwmod_addr_space omap44xx_mcbsp3_dma_addrs[] = {
  4407. {
  4408. .name = "dma",
  4409. .pa_start = 0x49026000,
  4410. .pa_end = 0x490260ff,
  4411. .flags = ADDR_TYPE_RT
  4412. },
  4413. { }
  4414. };
  4415. /* l4_abe -> mcbsp3 (dma) */
  4416. static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3_dma = {
  4417. .master = &omap44xx_l4_abe_hwmod,
  4418. .slave = &omap44xx_mcbsp3_hwmod,
  4419. .clk = "ocp_abe_iclk",
  4420. .addr = omap44xx_mcbsp3_dma_addrs,
  4421. .user = OCP_USER_SDMA,
  4422. };
  4423. static struct omap_hwmod_addr_space omap44xx_mcbsp4_addrs[] = {
  4424. {
  4425. .pa_start = 0x48096000,
  4426. .pa_end = 0x480960ff,
  4427. .flags = ADDR_TYPE_RT
  4428. },
  4429. { }
  4430. };
  4431. /* l4_per -> mcbsp4 */
  4432. static struct omap_hwmod_ocp_if omap44xx_l4_per__mcbsp4 = {
  4433. .master = &omap44xx_l4_per_hwmod,
  4434. .slave = &omap44xx_mcbsp4_hwmod,
  4435. .clk = "l4_div_ck",
  4436. .addr = omap44xx_mcbsp4_addrs,
  4437. .user = OCP_USER_MPU | OCP_USER_SDMA,
  4438. };
  4439. static struct omap_hwmod_addr_space omap44xx_mcpdm_addrs[] = {
  4440. {
  4441. .pa_start = 0x40132000,
  4442. .pa_end = 0x4013207f,
  4443. .flags = ADDR_TYPE_RT
  4444. },
  4445. { }
  4446. };
  4447. /* l4_abe -> mcpdm */
  4448. static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm = {
  4449. .master = &omap44xx_l4_abe_hwmod,
  4450. .slave = &omap44xx_mcpdm_hwmod,
  4451. .clk = "ocp_abe_iclk",
  4452. .addr = omap44xx_mcpdm_addrs,
  4453. .user = OCP_USER_MPU,
  4454. };
  4455. static struct omap_hwmod_addr_space omap44xx_mcpdm_dma_addrs[] = {
  4456. {
  4457. .pa_start = 0x49032000,
  4458. .pa_end = 0x4903207f,
  4459. .flags = ADDR_TYPE_RT
  4460. },
  4461. { }
  4462. };
  4463. /* l4_abe -> mcpdm (dma) */
  4464. static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm_dma = {
  4465. .master = &omap44xx_l4_abe_hwmod,
  4466. .slave = &omap44xx_mcpdm_hwmod,
  4467. .clk = "ocp_abe_iclk",
  4468. .addr = omap44xx_mcpdm_dma_addrs,
  4469. .user = OCP_USER_SDMA,
  4470. };
  4471. static struct omap_hwmod_addr_space omap44xx_mcspi1_addrs[] = {
  4472. {
  4473. .pa_start = 0x48098000,
  4474. .pa_end = 0x480981ff,
  4475. .flags = ADDR_TYPE_RT
  4476. },
  4477. { }
  4478. };
  4479. /* l4_per -> mcspi1 */
  4480. static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi1 = {
  4481. .master = &omap44xx_l4_per_hwmod,
  4482. .slave = &omap44xx_mcspi1_hwmod,
  4483. .clk = "l4_div_ck",
  4484. .addr = omap44xx_mcspi1_addrs,
  4485. .user = OCP_USER_MPU | OCP_USER_SDMA,
  4486. };
  4487. static struct omap_hwmod_addr_space omap44xx_mcspi2_addrs[] = {
  4488. {
  4489. .pa_start = 0x4809a000,
  4490. .pa_end = 0x4809a1ff,
  4491. .flags = ADDR_TYPE_RT
  4492. },
  4493. { }
  4494. };
  4495. /* l4_per -> mcspi2 */
  4496. static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi2 = {
  4497. .master = &omap44xx_l4_per_hwmod,
  4498. .slave = &omap44xx_mcspi2_hwmod,
  4499. .clk = "l4_div_ck",
  4500. .addr = omap44xx_mcspi2_addrs,
  4501. .user = OCP_USER_MPU | OCP_USER_SDMA,
  4502. };
  4503. static struct omap_hwmod_addr_space omap44xx_mcspi3_addrs[] = {
  4504. {
  4505. .pa_start = 0x480b8000,
  4506. .pa_end = 0x480b81ff,
  4507. .flags = ADDR_TYPE_RT
  4508. },
  4509. { }
  4510. };
  4511. /* l4_per -> mcspi3 */
  4512. static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi3 = {
  4513. .master = &omap44xx_l4_per_hwmod,
  4514. .slave = &omap44xx_mcspi3_hwmod,
  4515. .clk = "l4_div_ck",
  4516. .addr = omap44xx_mcspi3_addrs,
  4517. .user = OCP_USER_MPU | OCP_USER_SDMA,
  4518. };
  4519. static struct omap_hwmod_addr_space omap44xx_mcspi4_addrs[] = {
  4520. {
  4521. .pa_start = 0x480ba000,
  4522. .pa_end = 0x480ba1ff,
  4523. .flags = ADDR_TYPE_RT
  4524. },
  4525. { }
  4526. };
  4527. /* l4_per -> mcspi4 */
  4528. static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi4 = {
  4529. .master = &omap44xx_l4_per_hwmod,
  4530. .slave = &omap44xx_mcspi4_hwmod,
  4531. .clk = "l4_div_ck",
  4532. .addr = omap44xx_mcspi4_addrs,
  4533. .user = OCP_USER_MPU | OCP_USER_SDMA,
  4534. };
  4535. static struct omap_hwmod_addr_space omap44xx_mmc1_addrs[] = {
  4536. {
  4537. .pa_start = 0x4809c000,
  4538. .pa_end = 0x4809c3ff,
  4539. .flags = ADDR_TYPE_RT
  4540. },
  4541. { }
  4542. };
  4543. /* l4_per -> mmc1 */
  4544. static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc1 = {
  4545. .master = &omap44xx_l4_per_hwmod,
  4546. .slave = &omap44xx_mmc1_hwmod,
  4547. .clk = "l4_div_ck",
  4548. .addr = omap44xx_mmc1_addrs,
  4549. .user = OCP_USER_MPU | OCP_USER_SDMA,
  4550. };
  4551. static struct omap_hwmod_addr_space omap44xx_mmc2_addrs[] = {
  4552. {
  4553. .pa_start = 0x480b4000,
  4554. .pa_end = 0x480b43ff,
  4555. .flags = ADDR_TYPE_RT
  4556. },
  4557. { }
  4558. };
  4559. /* l4_per -> mmc2 */
  4560. static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc2 = {
  4561. .master = &omap44xx_l4_per_hwmod,
  4562. .slave = &omap44xx_mmc2_hwmod,
  4563. .clk = "l4_div_ck",
  4564. .addr = omap44xx_mmc2_addrs,
  4565. .user = OCP_USER_MPU | OCP_USER_SDMA,
  4566. };
  4567. static struct omap_hwmod_addr_space omap44xx_mmc3_addrs[] = {
  4568. {
  4569. .pa_start = 0x480ad000,
  4570. .pa_end = 0x480ad3ff,
  4571. .flags = ADDR_TYPE_RT
  4572. },
  4573. { }
  4574. };
  4575. /* l4_per -> mmc3 */
  4576. static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc3 = {
  4577. .master = &omap44xx_l4_per_hwmod,
  4578. .slave = &omap44xx_mmc3_hwmod,
  4579. .clk = "l4_div_ck",
  4580. .addr = omap44xx_mmc3_addrs,
  4581. .user = OCP_USER_MPU | OCP_USER_SDMA,
  4582. };
  4583. static struct omap_hwmod_addr_space omap44xx_mmc4_addrs[] = {
  4584. {
  4585. .pa_start = 0x480d1000,
  4586. .pa_end = 0x480d13ff,
  4587. .flags = ADDR_TYPE_RT
  4588. },
  4589. { }
  4590. };
  4591. /* l4_per -> mmc4 */
  4592. static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc4 = {
  4593. .master = &omap44xx_l4_per_hwmod,
  4594. .slave = &omap44xx_mmc4_hwmod,
  4595. .clk = "l4_div_ck",
  4596. .addr = omap44xx_mmc4_addrs,
  4597. .user = OCP_USER_MPU | OCP_USER_SDMA,
  4598. };
  4599. static struct omap_hwmod_addr_space omap44xx_mmc5_addrs[] = {
  4600. {
  4601. .pa_start = 0x480d5000,
  4602. .pa_end = 0x480d53ff,
  4603. .flags = ADDR_TYPE_RT
  4604. },
  4605. { }
  4606. };
  4607. /* l4_per -> mmc5 */
  4608. static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc5 = {
  4609. .master = &omap44xx_l4_per_hwmod,
  4610. .slave = &omap44xx_mmc5_hwmod,
  4611. .clk = "l4_div_ck",
  4612. .addr = omap44xx_mmc5_addrs,
  4613. .user = OCP_USER_MPU | OCP_USER_SDMA,
  4614. };
  4615. /* l3_main_2 -> ocmc_ram */
  4616. static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ocmc_ram = {
  4617. .master = &omap44xx_l3_main_2_hwmod,
  4618. .slave = &omap44xx_ocmc_ram_hwmod,
  4619. .clk = "l3_div_ck",
  4620. .user = OCP_USER_MPU | OCP_USER_SDMA,
  4621. };
  4622. /* l4_cfg -> ocp2scp_usb_phy */
  4623. static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp2scp_usb_phy = {
  4624. .master = &omap44xx_l4_cfg_hwmod,
  4625. .slave = &omap44xx_ocp2scp_usb_phy_hwmod,
  4626. .clk = "l4_div_ck",
  4627. .user = OCP_USER_MPU | OCP_USER_SDMA,
  4628. };
  4629. static struct omap_hwmod_addr_space omap44xx_prcm_mpu_addrs[] = {
  4630. {
  4631. .pa_start = 0x48243000,
  4632. .pa_end = 0x48243fff,
  4633. .flags = ADDR_TYPE_RT
  4634. },
  4635. { }
  4636. };
  4637. /* mpu_private -> prcm_mpu */
  4638. static struct omap_hwmod_ocp_if omap44xx_mpu_private__prcm_mpu = {
  4639. .master = &omap44xx_mpu_private_hwmod,
  4640. .slave = &omap44xx_prcm_mpu_hwmod,
  4641. .clk = "l3_div_ck",
  4642. .addr = omap44xx_prcm_mpu_addrs,
  4643. .user = OCP_USER_MPU | OCP_USER_SDMA,
  4644. };
  4645. static struct omap_hwmod_addr_space omap44xx_cm_core_aon_addrs[] = {
  4646. {
  4647. .pa_start = 0x4a004000,
  4648. .pa_end = 0x4a004fff,
  4649. .flags = ADDR_TYPE_RT
  4650. },
  4651. { }
  4652. };
  4653. /* l4_wkup -> cm_core_aon */
  4654. static struct omap_hwmod_ocp_if omap44xx_l4_wkup__cm_core_aon = {
  4655. .master = &omap44xx_l4_wkup_hwmod,
  4656. .slave = &omap44xx_cm_core_aon_hwmod,
  4657. .clk = "l4_wkup_clk_mux_ck",
  4658. .addr = omap44xx_cm_core_aon_addrs,
  4659. .user = OCP_USER_MPU | OCP_USER_SDMA,
  4660. };
  4661. static struct omap_hwmod_addr_space omap44xx_cm_core_addrs[] = {
  4662. {
  4663. .pa_start = 0x4a008000,
  4664. .pa_end = 0x4a009fff,
  4665. .flags = ADDR_TYPE_RT
  4666. },
  4667. { }
  4668. };
  4669. /* l4_cfg -> cm_core */
  4670. static struct omap_hwmod_ocp_if omap44xx_l4_cfg__cm_core = {
  4671. .master = &omap44xx_l4_cfg_hwmod,
  4672. .slave = &omap44xx_cm_core_hwmod,
  4673. .clk = "l4_div_ck",
  4674. .addr = omap44xx_cm_core_addrs,
  4675. .user = OCP_USER_MPU | OCP_USER_SDMA,
  4676. };
  4677. static struct omap_hwmod_addr_space omap44xx_prm_addrs[] = {
  4678. {
  4679. .pa_start = 0x4a306000,
  4680. .pa_end = 0x4a307fff,
  4681. .flags = ADDR_TYPE_RT
  4682. },
  4683. { }
  4684. };
  4685. /* l4_wkup -> prm */
  4686. static struct omap_hwmod_ocp_if omap44xx_l4_wkup__prm = {
  4687. .master = &omap44xx_l4_wkup_hwmod,
  4688. .slave = &omap44xx_prm_hwmod,
  4689. .clk = "l4_wkup_clk_mux_ck",
  4690. .addr = omap44xx_prm_addrs,
  4691. .user = OCP_USER_MPU | OCP_USER_SDMA,
  4692. };
  4693. static struct omap_hwmod_addr_space omap44xx_scrm_addrs[] = {
  4694. {
  4695. .pa_start = 0x4a30a000,
  4696. .pa_end = 0x4a30a7ff,
  4697. .flags = ADDR_TYPE_RT
  4698. },
  4699. { }
  4700. };
  4701. /* l4_wkup -> scrm */
  4702. static struct omap_hwmod_ocp_if omap44xx_l4_wkup__scrm = {
  4703. .master = &omap44xx_l4_wkup_hwmod,
  4704. .slave = &omap44xx_scrm_hwmod,
  4705. .clk = "l4_wkup_clk_mux_ck",
  4706. .addr = omap44xx_scrm_addrs,
  4707. .user = OCP_USER_MPU | OCP_USER_SDMA,
  4708. };
  4709. /* l3_main_2 -> sl2if */
  4710. static struct omap_hwmod_ocp_if omap44xx_l3_main_2__sl2if = {
  4711. .master = &omap44xx_l3_main_2_hwmod,
  4712. .slave = &omap44xx_sl2if_hwmod,
  4713. .clk = "l3_div_ck",
  4714. .user = OCP_USER_MPU | OCP_USER_SDMA,
  4715. };
  4716. static struct omap_hwmod_addr_space omap44xx_slimbus1_addrs[] = {
  4717. {
  4718. .pa_start = 0x4012c000,
  4719. .pa_end = 0x4012c3ff,
  4720. .flags = ADDR_TYPE_RT
  4721. },
  4722. { }
  4723. };
  4724. /* l4_abe -> slimbus1 */
  4725. static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1 = {
  4726. .master = &omap44xx_l4_abe_hwmod,
  4727. .slave = &omap44xx_slimbus1_hwmod,
  4728. .clk = "ocp_abe_iclk",
  4729. .addr = omap44xx_slimbus1_addrs,
  4730. .user = OCP_USER_MPU,
  4731. };
  4732. static struct omap_hwmod_addr_space omap44xx_slimbus1_dma_addrs[] = {
  4733. {
  4734. .pa_start = 0x4902c000,
  4735. .pa_end = 0x4902c3ff,
  4736. .flags = ADDR_TYPE_RT
  4737. },
  4738. { }
  4739. };
  4740. /* l4_abe -> slimbus1 (dma) */
  4741. static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1_dma = {
  4742. .master = &omap44xx_l4_abe_hwmod,
  4743. .slave = &omap44xx_slimbus1_hwmod,
  4744. .clk = "ocp_abe_iclk",
  4745. .addr = omap44xx_slimbus1_dma_addrs,
  4746. .user = OCP_USER_SDMA,
  4747. };
  4748. static struct omap_hwmod_addr_space omap44xx_slimbus2_addrs[] = {
  4749. {
  4750. .pa_start = 0x48076000,
  4751. .pa_end = 0x480763ff,
  4752. .flags = ADDR_TYPE_RT
  4753. },
  4754. { }
  4755. };
  4756. /* l4_per -> slimbus2 */
  4757. static struct omap_hwmod_ocp_if omap44xx_l4_per__slimbus2 = {
  4758. .master = &omap44xx_l4_per_hwmod,
  4759. .slave = &omap44xx_slimbus2_hwmod,
  4760. .clk = "l4_div_ck",
  4761. .addr = omap44xx_slimbus2_addrs,
  4762. .user = OCP_USER_MPU | OCP_USER_SDMA,
  4763. };
  4764. static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs[] = {
  4765. {
  4766. .pa_start = 0x4a0dd000,
  4767. .pa_end = 0x4a0dd03f,
  4768. .flags = ADDR_TYPE_RT
  4769. },
  4770. { }
  4771. };
  4772. /* l4_cfg -> smartreflex_core */
  4773. static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core = {
  4774. .master = &omap44xx_l4_cfg_hwmod,
  4775. .slave = &omap44xx_smartreflex_core_hwmod,
  4776. .clk = "l4_div_ck",
  4777. .addr = omap44xx_smartreflex_core_addrs,
  4778. .user = OCP_USER_MPU | OCP_USER_SDMA,
  4779. };
  4780. static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs[] = {
  4781. {
  4782. .pa_start = 0x4a0db000,
  4783. .pa_end = 0x4a0db03f,
  4784. .flags = ADDR_TYPE_RT
  4785. },
  4786. { }
  4787. };
  4788. /* l4_cfg -> smartreflex_iva */
  4789. static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva = {
  4790. .master = &omap44xx_l4_cfg_hwmod,
  4791. .slave = &omap44xx_smartreflex_iva_hwmod,
  4792. .clk = "l4_div_ck",
  4793. .addr = omap44xx_smartreflex_iva_addrs,
  4794. .user = OCP_USER_MPU | OCP_USER_SDMA,
  4795. };
  4796. static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs[] = {
  4797. {
  4798. .pa_start = 0x4a0d9000,
  4799. .pa_end = 0x4a0d903f,
  4800. .flags = ADDR_TYPE_RT
  4801. },
  4802. { }
  4803. };
  4804. /* l4_cfg -> smartreflex_mpu */
  4805. static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu = {
  4806. .master = &omap44xx_l4_cfg_hwmod,
  4807. .slave = &omap44xx_smartreflex_mpu_hwmod,
  4808. .clk = "l4_div_ck",
  4809. .addr = omap44xx_smartreflex_mpu_addrs,
  4810. .user = OCP_USER_MPU | OCP_USER_SDMA,
  4811. };
  4812. static struct omap_hwmod_addr_space omap44xx_spinlock_addrs[] = {
  4813. {
  4814. .pa_start = 0x4a0f6000,
  4815. .pa_end = 0x4a0f6fff,
  4816. .flags = ADDR_TYPE_RT
  4817. },
  4818. { }
  4819. };
  4820. /* l4_cfg -> spinlock */
  4821. static struct omap_hwmod_ocp_if omap44xx_l4_cfg__spinlock = {
  4822. .master = &omap44xx_l4_cfg_hwmod,
  4823. .slave = &omap44xx_spinlock_hwmod,
  4824. .clk = "l4_div_ck",
  4825. .addr = omap44xx_spinlock_addrs,
  4826. .user = OCP_USER_MPU | OCP_USER_SDMA,
  4827. };
  4828. static struct omap_hwmod_addr_space omap44xx_timer1_addrs[] = {
  4829. {
  4830. .pa_start = 0x4a318000,
  4831. .pa_end = 0x4a31807f,
  4832. .flags = ADDR_TYPE_RT
  4833. },
  4834. { }
  4835. };
  4836. /* l4_wkup -> timer1 */
  4837. static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1 = {
  4838. .master = &omap44xx_l4_wkup_hwmod,
  4839. .slave = &omap44xx_timer1_hwmod,
  4840. .clk = "l4_wkup_clk_mux_ck",
  4841. .addr = omap44xx_timer1_addrs,
  4842. .user = OCP_USER_MPU | OCP_USER_SDMA,
  4843. };
  4844. static struct omap_hwmod_addr_space omap44xx_timer2_addrs[] = {
  4845. {
  4846. .pa_start = 0x48032000,
  4847. .pa_end = 0x4803207f,
  4848. .flags = ADDR_TYPE_RT
  4849. },
  4850. { }
  4851. };
  4852. /* l4_per -> timer2 */
  4853. static struct omap_hwmod_ocp_if omap44xx_l4_per__timer2 = {
  4854. .master = &omap44xx_l4_per_hwmod,
  4855. .slave = &omap44xx_timer2_hwmod,
  4856. .clk = "l4_div_ck",
  4857. .addr = omap44xx_timer2_addrs,
  4858. .user = OCP_USER_MPU | OCP_USER_SDMA,
  4859. };
  4860. static struct omap_hwmod_addr_space omap44xx_timer3_addrs[] = {
  4861. {
  4862. .pa_start = 0x48034000,
  4863. .pa_end = 0x4803407f,
  4864. .flags = ADDR_TYPE_RT
  4865. },
  4866. { }
  4867. };
  4868. /* l4_per -> timer3 */
  4869. static struct omap_hwmod_ocp_if omap44xx_l4_per__timer3 = {
  4870. .master = &omap44xx_l4_per_hwmod,
  4871. .slave = &omap44xx_timer3_hwmod,
  4872. .clk = "l4_div_ck",
  4873. .addr = omap44xx_timer3_addrs,
  4874. .user = OCP_USER_MPU | OCP_USER_SDMA,
  4875. };
  4876. static struct omap_hwmod_addr_space omap44xx_timer4_addrs[] = {
  4877. {
  4878. .pa_start = 0x48036000,
  4879. .pa_end = 0x4803607f,
  4880. .flags = ADDR_TYPE_RT
  4881. },
  4882. { }
  4883. };
  4884. /* l4_per -> timer4 */
  4885. static struct omap_hwmod_ocp_if omap44xx_l4_per__timer4 = {
  4886. .master = &omap44xx_l4_per_hwmod,
  4887. .slave = &omap44xx_timer4_hwmod,
  4888. .clk = "l4_div_ck",
  4889. .addr = omap44xx_timer4_addrs,
  4890. .user = OCP_USER_MPU | OCP_USER_SDMA,
  4891. };
  4892. static struct omap_hwmod_addr_space omap44xx_timer5_addrs[] = {
  4893. {
  4894. .pa_start = 0x40138000,
  4895. .pa_end = 0x4013807f,
  4896. .flags = ADDR_TYPE_RT
  4897. },
  4898. { }
  4899. };
  4900. /* l4_abe -> timer5 */
  4901. static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5 = {
  4902. .master = &omap44xx_l4_abe_hwmod,
  4903. .slave = &omap44xx_timer5_hwmod,
  4904. .clk = "ocp_abe_iclk",
  4905. .addr = omap44xx_timer5_addrs,
  4906. .user = OCP_USER_MPU,
  4907. };
  4908. static struct omap_hwmod_addr_space omap44xx_timer5_dma_addrs[] = {
  4909. {
  4910. .pa_start = 0x49038000,
  4911. .pa_end = 0x4903807f,
  4912. .flags = ADDR_TYPE_RT
  4913. },
  4914. { }
  4915. };
  4916. /* l4_abe -> timer5 (dma) */
  4917. static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5_dma = {
  4918. .master = &omap44xx_l4_abe_hwmod,
  4919. .slave = &omap44xx_timer5_hwmod,
  4920. .clk = "ocp_abe_iclk",
  4921. .addr = omap44xx_timer5_dma_addrs,
  4922. .user = OCP_USER_SDMA,
  4923. };
  4924. static struct omap_hwmod_addr_space omap44xx_timer6_addrs[] = {
  4925. {
  4926. .pa_start = 0x4013a000,
  4927. .pa_end = 0x4013a07f,
  4928. .flags = ADDR_TYPE_RT
  4929. },
  4930. { }
  4931. };
  4932. /* l4_abe -> timer6 */
  4933. static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6 = {
  4934. .master = &omap44xx_l4_abe_hwmod,
  4935. .slave = &omap44xx_timer6_hwmod,
  4936. .clk = "ocp_abe_iclk",
  4937. .addr = omap44xx_timer6_addrs,
  4938. .user = OCP_USER_MPU,
  4939. };
  4940. static struct omap_hwmod_addr_space omap44xx_timer6_dma_addrs[] = {
  4941. {
  4942. .pa_start = 0x4903a000,
  4943. .pa_end = 0x4903a07f,
  4944. .flags = ADDR_TYPE_RT
  4945. },
  4946. { }
  4947. };
  4948. /* l4_abe -> timer6 (dma) */
  4949. static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6_dma = {
  4950. .master = &omap44xx_l4_abe_hwmod,
  4951. .slave = &omap44xx_timer6_hwmod,
  4952. .clk = "ocp_abe_iclk",
  4953. .addr = omap44xx_timer6_dma_addrs,
  4954. .user = OCP_USER_SDMA,
  4955. };
  4956. static struct omap_hwmod_addr_space omap44xx_timer7_addrs[] = {
  4957. {
  4958. .pa_start = 0x4013c000,
  4959. .pa_end = 0x4013c07f,
  4960. .flags = ADDR_TYPE_RT
  4961. },
  4962. { }
  4963. };
  4964. /* l4_abe -> timer7 */
  4965. static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7 = {
  4966. .master = &omap44xx_l4_abe_hwmod,
  4967. .slave = &omap44xx_timer7_hwmod,
  4968. .clk = "ocp_abe_iclk",
  4969. .addr = omap44xx_timer7_addrs,
  4970. .user = OCP_USER_MPU,
  4971. };
  4972. static struct omap_hwmod_addr_space omap44xx_timer7_dma_addrs[] = {
  4973. {
  4974. .pa_start = 0x4903c000,
  4975. .pa_end = 0x4903c07f,
  4976. .flags = ADDR_TYPE_RT
  4977. },
  4978. { }
  4979. };
  4980. /* l4_abe -> timer7 (dma) */
  4981. static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7_dma = {
  4982. .master = &omap44xx_l4_abe_hwmod,
  4983. .slave = &omap44xx_timer7_hwmod,
  4984. .clk = "ocp_abe_iclk",
  4985. .addr = omap44xx_timer7_dma_addrs,
  4986. .user = OCP_USER_SDMA,
  4987. };
  4988. static struct omap_hwmod_addr_space omap44xx_timer8_addrs[] = {
  4989. {
  4990. .pa_start = 0x4013e000,
  4991. .pa_end = 0x4013e07f,
  4992. .flags = ADDR_TYPE_RT
  4993. },
  4994. { }
  4995. };
  4996. /* l4_abe -> timer8 */
  4997. static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8 = {
  4998. .master = &omap44xx_l4_abe_hwmod,
  4999. .slave = &omap44xx_timer8_hwmod,
  5000. .clk = "ocp_abe_iclk",
  5001. .addr = omap44xx_timer8_addrs,
  5002. .user = OCP_USER_MPU,
  5003. };
  5004. static struct omap_hwmod_addr_space omap44xx_timer8_dma_addrs[] = {
  5005. {
  5006. .pa_start = 0x4903e000,
  5007. .pa_end = 0x4903e07f,
  5008. .flags = ADDR_TYPE_RT
  5009. },
  5010. { }
  5011. };
  5012. /* l4_abe -> timer8 (dma) */
  5013. static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8_dma = {
  5014. .master = &omap44xx_l4_abe_hwmod,
  5015. .slave = &omap44xx_timer8_hwmod,
  5016. .clk = "ocp_abe_iclk",
  5017. .addr = omap44xx_timer8_dma_addrs,
  5018. .user = OCP_USER_SDMA,
  5019. };
  5020. static struct omap_hwmod_addr_space omap44xx_timer9_addrs[] = {
  5021. {
  5022. .pa_start = 0x4803e000,
  5023. .pa_end = 0x4803e07f,
  5024. .flags = ADDR_TYPE_RT
  5025. },
  5026. { }
  5027. };
  5028. /* l4_per -> timer9 */
  5029. static struct omap_hwmod_ocp_if omap44xx_l4_per__timer9 = {
  5030. .master = &omap44xx_l4_per_hwmod,
  5031. .slave = &omap44xx_timer9_hwmod,
  5032. .clk = "l4_div_ck",
  5033. .addr = omap44xx_timer9_addrs,
  5034. .user = OCP_USER_MPU | OCP_USER_SDMA,
  5035. };
  5036. static struct omap_hwmod_addr_space omap44xx_timer10_addrs[] = {
  5037. {
  5038. .pa_start = 0x48086000,
  5039. .pa_end = 0x4808607f,
  5040. .flags = ADDR_TYPE_RT
  5041. },
  5042. { }
  5043. };
  5044. /* l4_per -> timer10 */
  5045. static struct omap_hwmod_ocp_if omap44xx_l4_per__timer10 = {
  5046. .master = &omap44xx_l4_per_hwmod,
  5047. .slave = &omap44xx_timer10_hwmod,
  5048. .clk = "l4_div_ck",
  5049. .addr = omap44xx_timer10_addrs,
  5050. .user = OCP_USER_MPU | OCP_USER_SDMA,
  5051. };
  5052. static struct omap_hwmod_addr_space omap44xx_timer11_addrs[] = {
  5053. {
  5054. .pa_start = 0x48088000,
  5055. .pa_end = 0x4808807f,
  5056. .flags = ADDR_TYPE_RT
  5057. },
  5058. { }
  5059. };
  5060. /* l4_per -> timer11 */
  5061. static struct omap_hwmod_ocp_if omap44xx_l4_per__timer11 = {
  5062. .master = &omap44xx_l4_per_hwmod,
  5063. .slave = &omap44xx_timer11_hwmod,
  5064. .clk = "l4_div_ck",
  5065. .addr = omap44xx_timer11_addrs,
  5066. .user = OCP_USER_MPU | OCP_USER_SDMA,
  5067. };
  5068. static struct omap_hwmod_addr_space omap44xx_uart1_addrs[] = {
  5069. {
  5070. .pa_start = 0x4806a000,
  5071. .pa_end = 0x4806a0ff,
  5072. .flags = ADDR_TYPE_RT
  5073. },
  5074. { }
  5075. };
  5076. /* l4_per -> uart1 */
  5077. static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1 = {
  5078. .master = &omap44xx_l4_per_hwmod,
  5079. .slave = &omap44xx_uart1_hwmod,
  5080. .clk = "l4_div_ck",
  5081. .addr = omap44xx_uart1_addrs,
  5082. .user = OCP_USER_MPU | OCP_USER_SDMA,
  5083. };
  5084. static struct omap_hwmod_addr_space omap44xx_uart2_addrs[] = {
  5085. {
  5086. .pa_start = 0x4806c000,
  5087. .pa_end = 0x4806c0ff,
  5088. .flags = ADDR_TYPE_RT
  5089. },
  5090. { }
  5091. };
  5092. /* l4_per -> uart2 */
  5093. static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = {
  5094. .master = &omap44xx_l4_per_hwmod,
  5095. .slave = &omap44xx_uart2_hwmod,
  5096. .clk = "l4_div_ck",
  5097. .addr = omap44xx_uart2_addrs,
  5098. .user = OCP_USER_MPU | OCP_USER_SDMA,
  5099. };
  5100. static struct omap_hwmod_addr_space omap44xx_uart3_addrs[] = {
  5101. {
  5102. .pa_start = 0x48020000,
  5103. .pa_end = 0x480200ff,
  5104. .flags = ADDR_TYPE_RT
  5105. },
  5106. { }
  5107. };
  5108. /* l4_per -> uart3 */
  5109. static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = {
  5110. .master = &omap44xx_l4_per_hwmod,
  5111. .slave = &omap44xx_uart3_hwmod,
  5112. .clk = "l4_div_ck",
  5113. .addr = omap44xx_uart3_addrs,
  5114. .user = OCP_USER_MPU | OCP_USER_SDMA,
  5115. };
  5116. static struct omap_hwmod_addr_space omap44xx_uart4_addrs[] = {
  5117. {
  5118. .pa_start = 0x4806e000,
  5119. .pa_end = 0x4806e0ff,
  5120. .flags = ADDR_TYPE_RT
  5121. },
  5122. { }
  5123. };
  5124. /* l4_per -> uart4 */
  5125. static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = {
  5126. .master = &omap44xx_l4_per_hwmod,
  5127. .slave = &omap44xx_uart4_hwmod,
  5128. .clk = "l4_div_ck",
  5129. .addr = omap44xx_uart4_addrs,
  5130. .user = OCP_USER_MPU | OCP_USER_SDMA,
  5131. };
  5132. static struct omap_hwmod_addr_space omap44xx_usb_host_fs_addrs[] = {
  5133. {
  5134. .pa_start = 0x4a0a9000,
  5135. .pa_end = 0x4a0a93ff,
  5136. .flags = ADDR_TYPE_RT
  5137. },
  5138. { }
  5139. };
  5140. /* l4_cfg -> usb_host_fs */
  5141. static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_host_fs = {
  5142. .master = &omap44xx_l4_cfg_hwmod,
  5143. .slave = &omap44xx_usb_host_fs_hwmod,
  5144. .clk = "l4_div_ck",
  5145. .addr = omap44xx_usb_host_fs_addrs,
  5146. .user = OCP_USER_MPU | OCP_USER_SDMA,
  5147. };
  5148. static struct omap_hwmod_addr_space omap44xx_usb_host_hs_addrs[] = {
  5149. {
  5150. .name = "uhh",
  5151. .pa_start = 0x4a064000,
  5152. .pa_end = 0x4a0647ff,
  5153. .flags = ADDR_TYPE_RT
  5154. },
  5155. {
  5156. .name = "ohci",
  5157. .pa_start = 0x4a064800,
  5158. .pa_end = 0x4a064bff,
  5159. },
  5160. {
  5161. .name = "ehci",
  5162. .pa_start = 0x4a064c00,
  5163. .pa_end = 0x4a064fff,
  5164. },
  5165. {}
  5166. };
  5167. /* l4_cfg -> usb_host_hs */
  5168. static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_host_hs = {
  5169. .master = &omap44xx_l4_cfg_hwmod,
  5170. .slave = &omap44xx_usb_host_hs_hwmod,
  5171. .clk = "l4_div_ck",
  5172. .addr = omap44xx_usb_host_hs_addrs,
  5173. .user = OCP_USER_MPU | OCP_USER_SDMA,
  5174. };
  5175. static struct omap_hwmod_addr_space omap44xx_usb_otg_hs_addrs[] = {
  5176. {
  5177. .pa_start = 0x4a0ab000,
  5178. .pa_end = 0x4a0ab003,
  5179. .flags = ADDR_TYPE_RT
  5180. },
  5181. { }
  5182. };
  5183. /* l4_cfg -> usb_otg_hs */
  5184. static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_otg_hs = {
  5185. .master = &omap44xx_l4_cfg_hwmod,
  5186. .slave = &omap44xx_usb_otg_hs_hwmod,
  5187. .clk = "l4_div_ck",
  5188. .addr = omap44xx_usb_otg_hs_addrs,
  5189. .user = OCP_USER_MPU | OCP_USER_SDMA,
  5190. };
  5191. static struct omap_hwmod_addr_space omap44xx_usb_tll_hs_addrs[] = {
  5192. {
  5193. .name = "tll",
  5194. .pa_start = 0x4a062000,
  5195. .pa_end = 0x4a063fff,
  5196. .flags = ADDR_TYPE_RT
  5197. },
  5198. {}
  5199. };
  5200. /* l4_cfg -> usb_tll_hs */
  5201. static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_tll_hs = {
  5202. .master = &omap44xx_l4_cfg_hwmod,
  5203. .slave = &omap44xx_usb_tll_hs_hwmod,
  5204. .clk = "l4_div_ck",
  5205. .addr = omap44xx_usb_tll_hs_addrs,
  5206. .user = OCP_USER_MPU | OCP_USER_SDMA,
  5207. };
  5208. static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs[] = {
  5209. {
  5210. .pa_start = 0x4a314000,
  5211. .pa_end = 0x4a31407f,
  5212. .flags = ADDR_TYPE_RT
  5213. },
  5214. { }
  5215. };
  5216. /* l4_wkup -> wd_timer2 */
  5217. static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = {
  5218. .master = &omap44xx_l4_wkup_hwmod,
  5219. .slave = &omap44xx_wd_timer2_hwmod,
  5220. .clk = "l4_wkup_clk_mux_ck",
  5221. .addr = omap44xx_wd_timer2_addrs,
  5222. .user = OCP_USER_MPU | OCP_USER_SDMA,
  5223. };
  5224. static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = {
  5225. {
  5226. .pa_start = 0x40130000,
  5227. .pa_end = 0x4013007f,
  5228. .flags = ADDR_TYPE_RT
  5229. },
  5230. { }
  5231. };
  5232. /* l4_abe -> wd_timer3 */
  5233. static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = {
  5234. .master = &omap44xx_l4_abe_hwmod,
  5235. .slave = &omap44xx_wd_timer3_hwmod,
  5236. .clk = "ocp_abe_iclk",
  5237. .addr = omap44xx_wd_timer3_addrs,
  5238. .user = OCP_USER_MPU,
  5239. };
  5240. static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs[] = {
  5241. {
  5242. .pa_start = 0x49030000,
  5243. .pa_end = 0x4903007f,
  5244. .flags = ADDR_TYPE_RT
  5245. },
  5246. { }
  5247. };
  5248. /* l4_abe -> wd_timer3 (dma) */
  5249. static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = {
  5250. .master = &omap44xx_l4_abe_hwmod,
  5251. .slave = &omap44xx_wd_timer3_hwmod,
  5252. .clk = "ocp_abe_iclk",
  5253. .addr = omap44xx_wd_timer3_dma_addrs,
  5254. .user = OCP_USER_SDMA,
  5255. };
  5256. static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
  5257. &omap44xx_c2c__c2c_target_fw,
  5258. &omap44xx_l4_cfg__c2c_target_fw,
  5259. &omap44xx_l3_main_1__dmm,
  5260. &omap44xx_mpu__dmm,
  5261. &omap44xx_c2c__emif_fw,
  5262. &omap44xx_dmm__emif_fw,
  5263. &omap44xx_l4_cfg__emif_fw,
  5264. &omap44xx_iva__l3_instr,
  5265. &omap44xx_l3_main_3__l3_instr,
  5266. &omap44xx_ocp_wp_noc__l3_instr,
  5267. &omap44xx_dsp__l3_main_1,
  5268. &omap44xx_dss__l3_main_1,
  5269. &omap44xx_l3_main_2__l3_main_1,
  5270. &omap44xx_l4_cfg__l3_main_1,
  5271. &omap44xx_mmc1__l3_main_1,
  5272. &omap44xx_mmc2__l3_main_1,
  5273. &omap44xx_mpu__l3_main_1,
  5274. &omap44xx_c2c_target_fw__l3_main_2,
  5275. &omap44xx_dma_system__l3_main_2,
  5276. &omap44xx_fdif__l3_main_2,
  5277. &omap44xx_gpu__l3_main_2,
  5278. &omap44xx_hsi__l3_main_2,
  5279. &omap44xx_ipu__l3_main_2,
  5280. &omap44xx_iss__l3_main_2,
  5281. &omap44xx_iva__l3_main_2,
  5282. &omap44xx_l3_main_1__l3_main_2,
  5283. &omap44xx_l4_cfg__l3_main_2,
  5284. &omap44xx_usb_host_fs__l3_main_2,
  5285. &omap44xx_usb_host_hs__l3_main_2,
  5286. &omap44xx_usb_otg_hs__l3_main_2,
  5287. &omap44xx_l3_main_1__l3_main_3,
  5288. &omap44xx_l3_main_2__l3_main_3,
  5289. &omap44xx_l4_cfg__l3_main_3,
  5290. &omap44xx_aess__l4_abe,
  5291. &omap44xx_dsp__l4_abe,
  5292. &omap44xx_l3_main_1__l4_abe,
  5293. &omap44xx_mpu__l4_abe,
  5294. &omap44xx_l3_main_1__l4_cfg,
  5295. &omap44xx_l3_main_2__l4_per,
  5296. &omap44xx_l4_cfg__l4_wkup,
  5297. &omap44xx_mpu__mpu_private,
  5298. &omap44xx_l4_cfg__ocp_wp_noc,
  5299. &omap44xx_l4_abe__aess,
  5300. &omap44xx_l4_abe__aess_dma,
  5301. &omap44xx_l3_main_2__c2c,
  5302. &omap44xx_l4_wkup__counter_32k,
  5303. &omap44xx_l4_cfg__ctrl_module_core,
  5304. &omap44xx_l4_cfg__ctrl_module_pad_core,
  5305. &omap44xx_l4_wkup__ctrl_module_wkup,
  5306. &omap44xx_l4_wkup__ctrl_module_pad_wkup,
  5307. &omap44xx_l4_cfg__dma_system,
  5308. &omap44xx_l4_abe__dmic,
  5309. &omap44xx_l4_abe__dmic_dma,
  5310. &omap44xx_dsp__iva,
  5311. &omap44xx_dsp__sl2if,
  5312. &omap44xx_l4_cfg__dsp,
  5313. &omap44xx_l3_main_2__dss,
  5314. &omap44xx_l4_per__dss,
  5315. &omap44xx_l3_main_2__dss_dispc,
  5316. &omap44xx_l4_per__dss_dispc,
  5317. &omap44xx_l3_main_2__dss_dsi1,
  5318. &omap44xx_l4_per__dss_dsi1,
  5319. &omap44xx_l3_main_2__dss_dsi2,
  5320. &omap44xx_l4_per__dss_dsi2,
  5321. &omap44xx_l3_main_2__dss_hdmi,
  5322. &omap44xx_l4_per__dss_hdmi,
  5323. &omap44xx_l3_main_2__dss_rfbi,
  5324. &omap44xx_l4_per__dss_rfbi,
  5325. &omap44xx_l3_main_2__dss_venc,
  5326. &omap44xx_l4_per__dss_venc,
  5327. &omap44xx_l4_per__elm,
  5328. &omap44xx_emif_fw__emif1,
  5329. &omap44xx_emif_fw__emif2,
  5330. &omap44xx_l4_cfg__fdif,
  5331. &omap44xx_l4_wkup__gpio1,
  5332. &omap44xx_l4_per__gpio2,
  5333. &omap44xx_l4_per__gpio3,
  5334. &omap44xx_l4_per__gpio4,
  5335. &omap44xx_l4_per__gpio5,
  5336. &omap44xx_l4_per__gpio6,
  5337. &omap44xx_l3_main_2__gpmc,
  5338. &omap44xx_l3_main_2__gpu,
  5339. &omap44xx_l4_per__hdq1w,
  5340. &omap44xx_l4_cfg__hsi,
  5341. &omap44xx_l4_per__i2c1,
  5342. &omap44xx_l4_per__i2c2,
  5343. &omap44xx_l4_per__i2c3,
  5344. &omap44xx_l4_per__i2c4,
  5345. &omap44xx_l3_main_2__ipu,
  5346. &omap44xx_l3_main_2__iss,
  5347. &omap44xx_iva__sl2if,
  5348. &omap44xx_l3_main_2__iva,
  5349. &omap44xx_l4_wkup__kbd,
  5350. &omap44xx_l4_cfg__mailbox,
  5351. &omap44xx_l4_abe__mcasp,
  5352. &omap44xx_l4_abe__mcasp_dma,
  5353. &omap44xx_l4_abe__mcbsp1,
  5354. &omap44xx_l4_abe__mcbsp1_dma,
  5355. &omap44xx_l4_abe__mcbsp2,
  5356. &omap44xx_l4_abe__mcbsp2_dma,
  5357. &omap44xx_l4_abe__mcbsp3,
  5358. &omap44xx_l4_abe__mcbsp3_dma,
  5359. &omap44xx_l4_per__mcbsp4,
  5360. &omap44xx_l4_abe__mcpdm,
  5361. &omap44xx_l4_abe__mcpdm_dma,
  5362. &omap44xx_l4_per__mcspi1,
  5363. &omap44xx_l4_per__mcspi2,
  5364. &omap44xx_l4_per__mcspi3,
  5365. &omap44xx_l4_per__mcspi4,
  5366. &omap44xx_l4_per__mmc1,
  5367. &omap44xx_l4_per__mmc2,
  5368. &omap44xx_l4_per__mmc3,
  5369. &omap44xx_l4_per__mmc4,
  5370. &omap44xx_l4_per__mmc5,
  5371. &omap44xx_l3_main_2__ocmc_ram,
  5372. &omap44xx_l4_cfg__ocp2scp_usb_phy,
  5373. &omap44xx_mpu_private__prcm_mpu,
  5374. &omap44xx_l4_wkup__cm_core_aon,
  5375. &omap44xx_l4_cfg__cm_core,
  5376. &omap44xx_l4_wkup__prm,
  5377. &omap44xx_l4_wkup__scrm,
  5378. &omap44xx_l3_main_2__sl2if,
  5379. &omap44xx_l4_abe__slimbus1,
  5380. &omap44xx_l4_abe__slimbus1_dma,
  5381. &omap44xx_l4_per__slimbus2,
  5382. &omap44xx_l4_cfg__smartreflex_core,
  5383. &omap44xx_l4_cfg__smartreflex_iva,
  5384. &omap44xx_l4_cfg__smartreflex_mpu,
  5385. &omap44xx_l4_cfg__spinlock,
  5386. &omap44xx_l4_wkup__timer1,
  5387. &omap44xx_l4_per__timer2,
  5388. &omap44xx_l4_per__timer3,
  5389. &omap44xx_l4_per__timer4,
  5390. &omap44xx_l4_abe__timer5,
  5391. &omap44xx_l4_abe__timer5_dma,
  5392. &omap44xx_l4_abe__timer6,
  5393. &omap44xx_l4_abe__timer6_dma,
  5394. &omap44xx_l4_abe__timer7,
  5395. &omap44xx_l4_abe__timer7_dma,
  5396. &omap44xx_l4_abe__timer8,
  5397. &omap44xx_l4_abe__timer8_dma,
  5398. &omap44xx_l4_per__timer9,
  5399. &omap44xx_l4_per__timer10,
  5400. &omap44xx_l4_per__timer11,
  5401. &omap44xx_l4_per__uart1,
  5402. &omap44xx_l4_per__uart2,
  5403. &omap44xx_l4_per__uart3,
  5404. &omap44xx_l4_per__uart4,
  5405. &omap44xx_l4_cfg__usb_host_fs,
  5406. &omap44xx_l4_cfg__usb_host_hs,
  5407. &omap44xx_l4_cfg__usb_otg_hs,
  5408. &omap44xx_l4_cfg__usb_tll_hs,
  5409. &omap44xx_l4_wkup__wd_timer2,
  5410. &omap44xx_l4_abe__wd_timer3,
  5411. &omap44xx_l4_abe__wd_timer3_dma,
  5412. NULL,
  5413. };
  5414. int __init omap44xx_hwmod_init(void)
  5415. {
  5416. return omap_hwmod_register_links(omap44xx_hwmod_ocp_ifs);
  5417. }