imx28.dtsi 25 KB

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  1. /*
  2. * Copyright 2012 Freescale Semiconductor, Inc.
  3. *
  4. * The code contained herein is licensed under the GNU General Public
  5. * License. You may obtain a copy of the GNU General Public License
  6. * Version 2 or later at the following locations:
  7. *
  8. * http://www.opensource.org/licenses/gpl-license.html
  9. * http://www.gnu.org/copyleft/gpl.html
  10. */
  11. /include/ "skeleton.dtsi"
  12. / {
  13. interrupt-parent = <&icoll>;
  14. aliases {
  15. gpio0 = &gpio0;
  16. gpio1 = &gpio1;
  17. gpio2 = &gpio2;
  18. gpio3 = &gpio3;
  19. gpio4 = &gpio4;
  20. saif0 = &saif0;
  21. saif1 = &saif1;
  22. serial0 = &auart0;
  23. serial1 = &auart1;
  24. serial2 = &auart2;
  25. serial3 = &auart3;
  26. serial4 = &auart4;
  27. ethernet0 = &mac0;
  28. ethernet1 = &mac1;
  29. };
  30. cpus {
  31. #address-cells = <0>;
  32. #size-cells = <0>;
  33. cpu {
  34. compatible = "arm,arm926ej-s";
  35. device_type = "cpu";
  36. };
  37. };
  38. apb@80000000 {
  39. compatible = "simple-bus";
  40. #address-cells = <1>;
  41. #size-cells = <1>;
  42. reg = <0x80000000 0x80000>;
  43. ranges;
  44. apbh@80000000 {
  45. compatible = "simple-bus";
  46. #address-cells = <1>;
  47. #size-cells = <1>;
  48. reg = <0x80000000 0x3c900>;
  49. ranges;
  50. icoll: interrupt-controller@80000000 {
  51. compatible = "fsl,imx28-icoll", "fsl,icoll";
  52. interrupt-controller;
  53. #interrupt-cells = <1>;
  54. reg = <0x80000000 0x2000>;
  55. };
  56. hsadc@80002000 {
  57. reg = <0x80002000 0x2000>;
  58. interrupts = <13 87>;
  59. dmas = <&dma_apbh 12>;
  60. dma-names = "rx";
  61. status = "disabled";
  62. };
  63. dma_apbh: dma-apbh@80004000 {
  64. compatible = "fsl,imx28-dma-apbh";
  65. reg = <0x80004000 0x2000>;
  66. interrupts = <82 83 84 85
  67. 88 88 88 88
  68. 88 88 88 88
  69. 87 86 0 0>;
  70. interrupt-names = "ssp0", "ssp1", "ssp2", "ssp3",
  71. "gpmi0", "gmpi1", "gpmi2", "gmpi3",
  72. "gpmi4", "gmpi5", "gpmi6", "gmpi7",
  73. "hsadc", "lcdif", "empty", "empty";
  74. #dma-cells = <1>;
  75. dma-channels = <16>;
  76. clocks = <&clks 25>;
  77. };
  78. perfmon@80006000 {
  79. reg = <0x80006000 0x800>;
  80. interrupts = <27>;
  81. status = "disabled";
  82. };
  83. gpmi-nand@8000c000 {
  84. compatible = "fsl,imx28-gpmi-nand";
  85. #address-cells = <1>;
  86. #size-cells = <1>;
  87. reg = <0x8000c000 0x2000>, <0x8000a000 0x2000>;
  88. reg-names = "gpmi-nand", "bch";
  89. interrupts = <88>, <41>;
  90. interrupt-names = "gpmi-dma", "bch";
  91. clocks = <&clks 50>;
  92. clock-names = "gpmi_io";
  93. dmas = <&dma_apbh 4>;
  94. dma-names = "rx-tx";
  95. fsl,gpmi-dma-channel = <4>;
  96. status = "disabled";
  97. };
  98. ssp0: ssp@80010000 {
  99. #address-cells = <1>;
  100. #size-cells = <0>;
  101. reg = <0x80010000 0x2000>;
  102. interrupts = <96 82>;
  103. clocks = <&clks 46>;
  104. dmas = <&dma_apbh 0>;
  105. dma-names = "rx-tx";
  106. fsl,ssp-dma-channel = <0>;
  107. status = "disabled";
  108. };
  109. ssp1: ssp@80012000 {
  110. #address-cells = <1>;
  111. #size-cells = <0>;
  112. reg = <0x80012000 0x2000>;
  113. interrupts = <97 83>;
  114. clocks = <&clks 47>;
  115. dmas = <&dma_apbh 1>;
  116. dma-names = "rx-tx";
  117. fsl,ssp-dma-channel = <1>;
  118. status = "disabled";
  119. };
  120. ssp2: ssp@80014000 {
  121. #address-cells = <1>;
  122. #size-cells = <0>;
  123. reg = <0x80014000 0x2000>;
  124. interrupts = <98 84>;
  125. clocks = <&clks 48>;
  126. dmas = <&dma_apbh 2>;
  127. dma-names = "rx-tx";
  128. fsl,ssp-dma-channel = <2>;
  129. status = "disabled";
  130. };
  131. ssp3: ssp@80016000 {
  132. #address-cells = <1>;
  133. #size-cells = <0>;
  134. reg = <0x80016000 0x2000>;
  135. interrupts = <99 85>;
  136. clocks = <&clks 49>;
  137. dmas = <&dma_apbh 3>;
  138. dma-names = "rx-tx";
  139. fsl,ssp-dma-channel = <3>;
  140. status = "disabled";
  141. };
  142. pinctrl@80018000 {
  143. #address-cells = <1>;
  144. #size-cells = <0>;
  145. compatible = "fsl,imx28-pinctrl", "simple-bus";
  146. reg = <0x80018000 0x2000>;
  147. gpio0: gpio@0 {
  148. compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
  149. interrupts = <127>;
  150. gpio-controller;
  151. #gpio-cells = <2>;
  152. interrupt-controller;
  153. #interrupt-cells = <2>;
  154. };
  155. gpio1: gpio@1 {
  156. compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
  157. interrupts = <126>;
  158. gpio-controller;
  159. #gpio-cells = <2>;
  160. interrupt-controller;
  161. #interrupt-cells = <2>;
  162. };
  163. gpio2: gpio@2 {
  164. compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
  165. interrupts = <125>;
  166. gpio-controller;
  167. #gpio-cells = <2>;
  168. interrupt-controller;
  169. #interrupt-cells = <2>;
  170. };
  171. gpio3: gpio@3 {
  172. compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
  173. interrupts = <124>;
  174. gpio-controller;
  175. #gpio-cells = <2>;
  176. interrupt-controller;
  177. #interrupt-cells = <2>;
  178. };
  179. gpio4: gpio@4 {
  180. compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
  181. interrupts = <123>;
  182. gpio-controller;
  183. #gpio-cells = <2>;
  184. interrupt-controller;
  185. #interrupt-cells = <2>;
  186. };
  187. duart_pins_a: duart@0 {
  188. reg = <0>;
  189. fsl,pinmux-ids = <
  190. 0x3102 /* MX28_PAD_PWM0__DUART_RX */
  191. 0x3112 /* MX28_PAD_PWM1__DUART_TX */
  192. >;
  193. fsl,drive-strength = <0>;
  194. fsl,voltage = <1>;
  195. fsl,pull-up = <0>;
  196. };
  197. duart_pins_b: duart@1 {
  198. reg = <1>;
  199. fsl,pinmux-ids = <
  200. 0x3022 /* MX28_PAD_AUART0_CTS__DUART_RX */
  201. 0x3032 /* MX28_PAD_AUART0_RTS__DUART_TX */
  202. >;
  203. fsl,drive-strength = <0>;
  204. fsl,voltage = <1>;
  205. fsl,pull-up = <0>;
  206. };
  207. duart_4pins_a: duart-4pins@0 {
  208. reg = <0>;
  209. fsl,pinmux-ids = <
  210. 0x3022 /* MX28_PAD_AUART0_CTS__DUART_RX */
  211. 0x3032 /* MX28_PAD_AUART0_RTS__DUART_TX */
  212. 0x3002 /* MX28_PAD_AUART0_RX__DUART_CTS */
  213. 0x3012 /* MX28_PAD_AUART0_TX__DUART_RTS */
  214. >;
  215. fsl,drive-strength = <0>;
  216. fsl,voltage = <1>;
  217. fsl,pull-up = <0>;
  218. };
  219. gpmi_pins_a: gpmi-nand@0 {
  220. reg = <0>;
  221. fsl,pinmux-ids = <
  222. 0x0000 /* MX28_PAD_GPMI_D00__GPMI_D0 */
  223. 0x0010 /* MX28_PAD_GPMI_D01__GPMI_D1 */
  224. 0x0020 /* MX28_PAD_GPMI_D02__GPMI_D2 */
  225. 0x0030 /* MX28_PAD_GPMI_D03__GPMI_D3 */
  226. 0x0040 /* MX28_PAD_GPMI_D04__GPMI_D4 */
  227. 0x0050 /* MX28_PAD_GPMI_D05__GPMI_D5 */
  228. 0x0060 /* MX28_PAD_GPMI_D06__GPMI_D6 */
  229. 0x0070 /* MX28_PAD_GPMI_D07__GPMI_D7 */
  230. 0x0100 /* MX28_PAD_GPMI_CE0N__GPMI_CE0N */
  231. 0x0140 /* MX28_PAD_GPMI_RDY0__GPMI_READY0 */
  232. 0x0180 /* MX28_PAD_GPMI_RDN__GPMI_RDN */
  233. 0x0190 /* MX28_PAD_GPMI_WRN__GPMI_WRN */
  234. 0x01a0 /* MX28_PAD_GPMI_ALE__GPMI_ALE */
  235. 0x01b0 /* MX28_PAD_GPMI_CLE__GPMI_CLE */
  236. 0x01c0 /* MX28_PAD_GPMI_RESETN__GPMI_RESETN */
  237. >;
  238. fsl,drive-strength = <0>;
  239. fsl,voltage = <1>;
  240. fsl,pull-up = <0>;
  241. };
  242. gpmi_status_cfg: gpmi-status-cfg {
  243. fsl,pinmux-ids = <
  244. 0x0180 /* MX28_PAD_GPMI_RDN__GPMI_RDN */
  245. 0x0190 /* MX28_PAD_GPMI_WRN__GPMI_WRN */
  246. 0x01c0 /* MX28_PAD_GPMI_RESETN__GPMI_RESETN */
  247. >;
  248. fsl,drive-strength = <2>;
  249. };
  250. auart0_pins_a: auart0@0 {
  251. reg = <0>;
  252. fsl,pinmux-ids = <
  253. 0x3000 /* MX28_PAD_AUART0_RX__AUART0_RX */
  254. 0x3010 /* MX28_PAD_AUART0_TX__AUART0_TX */
  255. 0x3020 /* MX28_PAD_AUART0_CTS__AUART0_CTS */
  256. 0x3030 /* MX28_PAD_AUART0_RTS__AUART0_RTS */
  257. >;
  258. fsl,drive-strength = <0>;
  259. fsl,voltage = <1>;
  260. fsl,pull-up = <0>;
  261. };
  262. auart0_2pins_a: auart0-2pins@0 {
  263. reg = <0>;
  264. fsl,pinmux-ids = <
  265. 0x3000 /* MX28_PAD_AUART0_RX__AUART0_RX */
  266. 0x3010 /* MX28_PAD_AUART0_TX__AUART0_TX */
  267. >;
  268. fsl,drive-strength = <0>;
  269. fsl,voltage = <1>;
  270. fsl,pull-up = <0>;
  271. };
  272. auart1_pins_a: auart1@0 {
  273. reg = <0>;
  274. fsl,pinmux-ids = <
  275. 0x3040 /* MX28_PAD_AUART1_RX__AUART1_RX */
  276. 0x3050 /* MX28_PAD_AUART1_TX__AUART1_TX */
  277. 0x3060 /* MX28_PAD_AUART1_CTS__AUART1_CTS */
  278. 0x3070 /* MX28_PAD_AUART1_RTS__AUART1_RTS */
  279. >;
  280. fsl,drive-strength = <0>;
  281. fsl,voltage = <1>;
  282. fsl,pull-up = <0>;
  283. };
  284. auart1_2pins_a: auart1-2pins@0 {
  285. reg = <0>;
  286. fsl,pinmux-ids = <
  287. 0x3040 /* MX28_PAD_AUART1_RX__AUART1_RX */
  288. 0x3050 /* MX28_PAD_AUART1_TX__AUART1_TX */
  289. >;
  290. fsl,drive-strength = <0>;
  291. fsl,voltage = <1>;
  292. fsl,pull-up = <0>;
  293. };
  294. auart2_2pins_a: auart2-2pins@0 {
  295. reg = <0>;
  296. fsl,pinmux-ids = <
  297. 0x2101 /* MX28_PAD_SSP2_SCK__AUART2_RX */
  298. 0x2111 /* MX28_PAD_SSP2_MOSI__AUART2_TX */
  299. >;
  300. fsl,drive-strength = <0>;
  301. fsl,voltage = <1>;
  302. fsl,pull-up = <0>;
  303. };
  304. auart3_pins_a: auart3@0 {
  305. reg = <0>;
  306. fsl,pinmux-ids = <
  307. 0x30c0 /* MX28_PAD_AUART3_RX__AUART3_RX */
  308. 0x30d0 /* MX28_PAD_AUART3_TX__AUART3_TX */
  309. 0x30e0 /* MX28_PAD_AUART3_CTS__AUART3_CTS */
  310. 0x30f0 /* MX28_PAD_AUART3_RTS__AUART3_RTS */
  311. >;
  312. fsl,drive-strength = <0>;
  313. fsl,voltage = <1>;
  314. fsl,pull-up = <0>;
  315. };
  316. auart3_2pins_a: auart3-2pins@0 {
  317. reg = <0>;
  318. fsl,pinmux-ids = <
  319. 0x2121 /* MX28_PAD_SSP2_MISO__AUART3_RX */
  320. 0x2131 /* MX28_PAD_SSP2_SS0__AUART3_TX */
  321. >;
  322. fsl,drive-strength = <0>;
  323. fsl,voltage = <1>;
  324. fsl,pull-up = <0>;
  325. };
  326. mac0_pins_a: mac0@0 {
  327. reg = <0>;
  328. fsl,pinmux-ids = <
  329. 0x4000 /* MX28_PAD_ENET0_MDC__ENET0_MDC */
  330. 0x4010 /* MX28_PAD_ENET0_MDIO__ENET0_MDIO */
  331. 0x4020 /* MX28_PAD_ENET0_RX_EN__ENET0_RX_EN */
  332. 0x4030 /* MX28_PAD_ENET0_RXD0__ENET0_RXD0 */
  333. 0x4040 /* MX28_PAD_ENET0_RXD1__ENET0_RXD1 */
  334. 0x4060 /* MX28_PAD_ENET0_TX_EN__ENET0_TX_EN */
  335. 0x4070 /* MX28_PAD_ENET0_TXD0__ENET0_TXD0 */
  336. 0x4080 /* MX28_PAD_ENET0_TXD1__ENET0_TXD1 */
  337. 0x4100 /* MX28_PAD_ENET_CLK__CLKCTRL_ENET */
  338. >;
  339. fsl,drive-strength = <1>;
  340. fsl,voltage = <1>;
  341. fsl,pull-up = <1>;
  342. };
  343. mac1_pins_a: mac1@0 {
  344. reg = <0>;
  345. fsl,pinmux-ids = <
  346. 0x40f1 /* MX28_PAD_ENET0_CRS__ENET1_RX_EN */
  347. 0x4091 /* MX28_PAD_ENET0_RXD2__ENET1_RXD0 */
  348. 0x40a1 /* MX28_PAD_ENET0_RXD3__ENET1_RXD1 */
  349. 0x40e1 /* MX28_PAD_ENET0_COL__ENET1_TX_EN */
  350. 0x40b1 /* MX28_PAD_ENET0_TXD2__ENET1_TXD0 */
  351. 0x40c1 /* MX28_PAD_ENET0_TXD3__ENET1_TXD1 */
  352. >;
  353. fsl,drive-strength = <1>;
  354. fsl,voltage = <1>;
  355. fsl,pull-up = <1>;
  356. };
  357. mmc0_8bit_pins_a: mmc0-8bit@0 {
  358. reg = <0>;
  359. fsl,pinmux-ids = <
  360. 0x2000 /* MX28_PAD_SSP0_DATA0__SSP0_D0 */
  361. 0x2010 /* MX28_PAD_SSP0_DATA1__SSP0_D1 */
  362. 0x2020 /* MX28_PAD_SSP0_DATA2__SSP0_D2 */
  363. 0x2030 /* MX28_PAD_SSP0_DATA3__SSP0_D3 */
  364. 0x2040 /* MX28_PAD_SSP0_DATA4__SSP0_D4 */
  365. 0x2050 /* MX28_PAD_SSP0_DATA5__SSP0_D5 */
  366. 0x2060 /* MX28_PAD_SSP0_DATA6__SSP0_D6 */
  367. 0x2070 /* MX28_PAD_SSP0_DATA7__SSP0_D7 */
  368. 0x2080 /* MX28_PAD_SSP0_CMD__SSP0_CMD */
  369. 0x2090 /* MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT */
  370. 0x20a0 /* MX28_PAD_SSP0_SCK__SSP0_SCK */
  371. >;
  372. fsl,drive-strength = <1>;
  373. fsl,voltage = <1>;
  374. fsl,pull-up = <1>;
  375. };
  376. mmc0_4bit_pins_a: mmc0-4bit@0 {
  377. reg = <0>;
  378. fsl,pinmux-ids = <
  379. 0x2000 /* MX28_PAD_SSP0_DATA0__SSP0_D0 */
  380. 0x2010 /* MX28_PAD_SSP0_DATA1__SSP0_D1 */
  381. 0x2020 /* MX28_PAD_SSP0_DATA2__SSP0_D2 */
  382. 0x2030 /* MX28_PAD_SSP0_DATA3__SSP0_D3 */
  383. 0x2080 /* MX28_PAD_SSP0_CMD__SSP0_CMD */
  384. 0x2090 /* MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT */
  385. 0x20a0 /* MX28_PAD_SSP0_SCK__SSP0_SCK */
  386. >;
  387. fsl,drive-strength = <1>;
  388. fsl,voltage = <1>;
  389. fsl,pull-up = <1>;
  390. };
  391. mmc0_cd_cfg: mmc0-cd-cfg {
  392. fsl,pinmux-ids = <
  393. 0x2090 /* MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT */
  394. >;
  395. fsl,pull-up = <0>;
  396. };
  397. mmc0_sck_cfg: mmc0-sck-cfg {
  398. fsl,pinmux-ids = <
  399. 0x20a0 /* MX28_PAD_SSP0_SCK__SSP0_SCK */
  400. >;
  401. fsl,drive-strength = <2>;
  402. fsl,pull-up = <0>;
  403. };
  404. i2c0_pins_a: i2c0@0 {
  405. reg = <0>;
  406. fsl,pinmux-ids = <
  407. 0x3180 /* MX28_PAD_I2C0_SCL__I2C0_SCL */
  408. 0x3190 /* MX28_PAD_I2C0_SDA__I2C0_SDA */
  409. >;
  410. fsl,drive-strength = <1>;
  411. fsl,voltage = <1>;
  412. fsl,pull-up = <1>;
  413. };
  414. i2c0_pins_b: i2c0@1 {
  415. reg = <1>;
  416. fsl,pinmux-ids = <
  417. 0x3001 /* MX28_PAD_AUART0_RX__I2C0_SCL */
  418. 0x3011 /* MX28_PAD_AUART0_TX__I2C0_SDA */
  419. >;
  420. fsl,drive-strength = <1>;
  421. fsl,voltage = <1>;
  422. fsl,pull-up = <1>;
  423. };
  424. i2c1_pins_a: i2c1@0 {
  425. reg = <0>;
  426. fsl,pinmux-ids = <
  427. 0x3101 /* MX28_PAD_PWM0__I2C1_SCL */
  428. 0x3111 /* MX28_PAD_PWM1__I2C1_SDA */
  429. >;
  430. fsl,drive-strength = <1>;
  431. fsl,voltage = <1>;
  432. fsl,pull-up = <1>;
  433. };
  434. saif0_pins_a: saif0@0 {
  435. reg = <0>;
  436. fsl,pinmux-ids = <
  437. 0x3140 /* MX28_PAD_SAIF0_MCLK__SAIF0_MCLK */
  438. 0x3150 /* MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK */
  439. 0x3160 /* MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK */
  440. 0x3170 /* MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0 */
  441. >;
  442. fsl,drive-strength = <2>;
  443. fsl,voltage = <1>;
  444. fsl,pull-up = <1>;
  445. };
  446. saif1_pins_a: saif1@0 {
  447. reg = <0>;
  448. fsl,pinmux-ids = <
  449. 0x31a0 /* MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0 */
  450. >;
  451. fsl,drive-strength = <2>;
  452. fsl,voltage = <1>;
  453. fsl,pull-up = <1>;
  454. };
  455. pwm0_pins_a: pwm0@0 {
  456. reg = <0>;
  457. fsl,pinmux-ids = <
  458. 0x3100 /* MX28_PAD_PWM0__PWM_0 */
  459. >;
  460. fsl,drive-strength = <0>;
  461. fsl,voltage = <1>;
  462. fsl,pull-up = <0>;
  463. };
  464. pwm2_pins_a: pwm2@0 {
  465. reg = <0>;
  466. fsl,pinmux-ids = <
  467. 0x3120 /* MX28_PAD_PWM2__PWM_2 */
  468. >;
  469. fsl,drive-strength = <0>;
  470. fsl,voltage = <1>;
  471. fsl,pull-up = <0>;
  472. };
  473. pwm3_pins_a: pwm3@0 {
  474. reg = <0>;
  475. fsl,pinmux-ids = <
  476. 0x31c0 /* MX28_PAD_PWM3__PWM_3 */
  477. >;
  478. fsl,drive-strength = <0>;
  479. fsl,voltage = <1>;
  480. fsl,pull-up = <0>;
  481. };
  482. pwm3_pins_b: pwm3@1 {
  483. reg = <1>;
  484. fsl,pinmux-ids = <
  485. 0x3141 /* MX28_PAD_SAIF0_MCLK__PWM3 */
  486. >;
  487. fsl,drive-strength = <0>;
  488. fsl,voltage = <1>;
  489. fsl,pull-up = <0>;
  490. };
  491. pwm4_pins_a: pwm4@0 {
  492. reg = <0>;
  493. fsl,pinmux-ids = <
  494. 0x31d0 /* MX28_PAD_PWM4__PWM_4 */
  495. >;
  496. fsl,drive-strength = <0>;
  497. fsl,voltage = <1>;
  498. fsl,pull-up = <0>;
  499. };
  500. lcdif_24bit_pins_a: lcdif-24bit@0 {
  501. reg = <0>;
  502. fsl,pinmux-ids = <
  503. 0x1000 /* MX28_PAD_LCD_D00__LCD_D0 */
  504. 0x1010 /* MX28_PAD_LCD_D01__LCD_D1 */
  505. 0x1020 /* MX28_PAD_LCD_D02__LCD_D2 */
  506. 0x1030 /* MX28_PAD_LCD_D03__LCD_D3 */
  507. 0x1040 /* MX28_PAD_LCD_D04__LCD_D4 */
  508. 0x1050 /* MX28_PAD_LCD_D05__LCD_D5 */
  509. 0x1060 /* MX28_PAD_LCD_D06__LCD_D6 */
  510. 0x1070 /* MX28_PAD_LCD_D07__LCD_D7 */
  511. 0x1080 /* MX28_PAD_LCD_D08__LCD_D8 */
  512. 0x1090 /* MX28_PAD_LCD_D09__LCD_D9 */
  513. 0x10a0 /* MX28_PAD_LCD_D10__LCD_D10 */
  514. 0x10b0 /* MX28_PAD_LCD_D11__LCD_D11 */
  515. 0x10c0 /* MX28_PAD_LCD_D12__LCD_D12 */
  516. 0x10d0 /* MX28_PAD_LCD_D13__LCD_D13 */
  517. 0x10e0 /* MX28_PAD_LCD_D14__LCD_D14 */
  518. 0x10f0 /* MX28_PAD_LCD_D15__LCD_D15 */
  519. 0x1100 /* MX28_PAD_LCD_D16__LCD_D16 */
  520. 0x1110 /* MX28_PAD_LCD_D17__LCD_D17 */
  521. 0x1120 /* MX28_PAD_LCD_D18__LCD_D18 */
  522. 0x1130 /* MX28_PAD_LCD_D19__LCD_D19 */
  523. 0x1140 /* MX28_PAD_LCD_D20__LCD_D20 */
  524. 0x1150 /* MX28_PAD_LCD_D21__LCD_D21 */
  525. 0x1160 /* MX28_PAD_LCD_D22__LCD_D22 */
  526. 0x1170 /* MX28_PAD_LCD_D23__LCD_D23 */
  527. >;
  528. fsl,drive-strength = <0>;
  529. fsl,voltage = <1>;
  530. fsl,pull-up = <0>;
  531. };
  532. lcdif_16bit_pins_a: lcdif-16bit@0 {
  533. reg = <0>;
  534. fsl,pinmux-ids = <
  535. 0x1000 /* MX28_PAD_LCD_D00__LCD_D0 */
  536. 0x1010 /* MX28_PAD_LCD_D01__LCD_D1 */
  537. 0x1020 /* MX28_PAD_LCD_D02__LCD_D2 */
  538. 0x1030 /* MX28_PAD_LCD_D03__LCD_D3 */
  539. 0x1040 /* MX28_PAD_LCD_D04__LCD_D4 */
  540. 0x1050 /* MX28_PAD_LCD_D05__LCD_D5 */
  541. 0x1060 /* MX28_PAD_LCD_D06__LCD_D6 */
  542. 0x1070 /* MX28_PAD_LCD_D07__LCD_D7 */
  543. 0x1080 /* MX28_PAD_LCD_D08__LCD_D8 */
  544. 0x1090 /* MX28_PAD_LCD_D09__LCD_D9 */
  545. 0x10a0 /* MX28_PAD_LCD_D10__LCD_D10 */
  546. 0x10b0 /* MX28_PAD_LCD_D11__LCD_D11 */
  547. 0x10c0 /* MX28_PAD_LCD_D12__LCD_D12 */
  548. 0x10d0 /* MX28_PAD_LCD_D13__LCD_D13 */
  549. 0x10e0 /* MX28_PAD_LCD_D14__LCD_D14 */
  550. 0x10f0 /* MX28_PAD_LCD_D15__LCD_D15 */
  551. >;
  552. fsl,drive-strength = <0>;
  553. fsl,voltage = <1>;
  554. fsl,pull-up = <0>;
  555. };
  556. can0_pins_a: can0@0 {
  557. reg = <0>;
  558. fsl,pinmux-ids = <
  559. 0x0161 /* MX28_PAD_GPMI_RDY2__CAN0_TX */
  560. 0x0171 /* MX28_PAD_GPMI_RDY3__CAN0_RX */
  561. >;
  562. fsl,drive-strength = <0>;
  563. fsl,voltage = <1>;
  564. fsl,pull-up = <0>;
  565. };
  566. can1_pins_a: can1@0 {
  567. reg = <0>;
  568. fsl,pinmux-ids = <
  569. 0x0121 /* MX28_PAD_GPMI_CE2N__CAN1_TX */
  570. 0x0131 /* MX28_PAD_GPMI_CE3N__CAN1_RX */
  571. >;
  572. fsl,drive-strength = <0>;
  573. fsl,voltage = <1>;
  574. fsl,pull-up = <0>;
  575. };
  576. spi2_pins_a: spi2@0 {
  577. reg = <0>;
  578. fsl,pinmux-ids = <
  579. 0x2100 /* MX28_PAD_SSP2_SCK__SSP2_SCK */
  580. 0x2110 /* MX28_PAD_SSP2_MOSI__SSP2_CMD */
  581. 0x2120 /* MX28_PAD_SSP2_MISO__SSP2_D0 */
  582. 0x2130 /* MX28_PAD_SSP2_SS0__SSP2_D3 */
  583. >;
  584. fsl,drive-strength = <1>;
  585. fsl,voltage = <1>;
  586. fsl,pull-up = <1>;
  587. };
  588. usbphy0_pins_a: usbphy0@0 {
  589. reg = <0>;
  590. fsl,pinmux-ids = <
  591. 0x2152 /* MX28_PAD_SSP2_SS2__USB0_OVERCURRENT */
  592. >;
  593. fsl,drive-strength = <2>;
  594. fsl,voltage = <1>;
  595. fsl,pull-up = <0>;
  596. };
  597. usbphy0_pins_b: usbphy0@1 {
  598. reg = <1>;
  599. fsl,pinmux-ids = <
  600. 0x3061 /* MX28_PAD_AUART1_CTS__USB0_OVERCURRENT */
  601. >;
  602. fsl,drive-strength = <2>;
  603. fsl,voltage = <1>;
  604. fsl,pull-up = <0>;
  605. };
  606. usbphy1_pins_a: usbphy1@0 {
  607. reg = <0>;
  608. fsl,pinmux-ids = <
  609. 0x2142 /* MX28_PAD_SSP2_SS1__USB1_OVERCURRENT */
  610. >;
  611. fsl,drive-strength = <2>;
  612. fsl,voltage = <1>;
  613. fsl,pull-up = <0>;
  614. };
  615. };
  616. digctl@8001c000 {
  617. compatible = "fsl,imx28-digctl";
  618. reg = <0x8001c000 0x2000>;
  619. interrupts = <89>;
  620. status = "disabled";
  621. };
  622. etm@80022000 {
  623. reg = <0x80022000 0x2000>;
  624. status = "disabled";
  625. };
  626. dma_apbx: dma-apbx@80024000 {
  627. compatible = "fsl,imx28-dma-apbx";
  628. reg = <0x80024000 0x2000>;
  629. interrupts = <78 79 66 0
  630. 80 81 68 69
  631. 70 71 72 73
  632. 74 75 76 77>;
  633. interrupt-names = "auart4-rx", "aurat4-tx", "spdif-tx", "empty",
  634. "saif0", "saif1", "i2c0", "i2c1",
  635. "auart0-rx", "auart0-tx", "auart1-rx", "auart1-tx",
  636. "auart2-rx", "auart2-tx", "auart3-rx", "auart3-tx";
  637. #dma-cells = <1>;
  638. dma-channels = <16>;
  639. clocks = <&clks 26>;
  640. };
  641. dcp@80028000 {
  642. reg = <0x80028000 0x2000>;
  643. interrupts = <52 53 54>;
  644. status = "disabled";
  645. };
  646. pxp@8002a000 {
  647. reg = <0x8002a000 0x2000>;
  648. interrupts = <39>;
  649. status = "disabled";
  650. };
  651. ocotp@8002c000 {
  652. compatible = "fsl,ocotp";
  653. reg = <0x8002c000 0x2000>;
  654. status = "disabled";
  655. };
  656. axi-ahb@8002e000 {
  657. reg = <0x8002e000 0x2000>;
  658. status = "disabled";
  659. };
  660. lcdif@80030000 {
  661. compatible = "fsl,imx28-lcdif";
  662. reg = <0x80030000 0x2000>;
  663. interrupts = <38 86>;
  664. clocks = <&clks 55>;
  665. dmas = <&dma_apbh 13>;
  666. dma-names = "rx";
  667. status = "disabled";
  668. };
  669. can0: can@80032000 {
  670. compatible = "fsl,imx28-flexcan", "fsl,p1010-flexcan";
  671. reg = <0x80032000 0x2000>;
  672. interrupts = <8>;
  673. clocks = <&clks 58>, <&clks 58>;
  674. clock-names = "ipg", "per";
  675. status = "disabled";
  676. };
  677. can1: can@80034000 {
  678. compatible = "fsl,imx28-flexcan", "fsl,p1010-flexcan";
  679. reg = <0x80034000 0x2000>;
  680. interrupts = <9>;
  681. clocks = <&clks 59>, <&clks 59>;
  682. clock-names = "ipg", "per";
  683. status = "disabled";
  684. };
  685. simdbg@8003c000 {
  686. reg = <0x8003c000 0x200>;
  687. status = "disabled";
  688. };
  689. simgpmisel@8003c200 {
  690. reg = <0x8003c200 0x100>;
  691. status = "disabled";
  692. };
  693. simsspsel@8003c300 {
  694. reg = <0x8003c300 0x100>;
  695. status = "disabled";
  696. };
  697. simmemsel@8003c400 {
  698. reg = <0x8003c400 0x100>;
  699. status = "disabled";
  700. };
  701. gpiomon@8003c500 {
  702. reg = <0x8003c500 0x100>;
  703. status = "disabled";
  704. };
  705. simenet@8003c700 {
  706. reg = <0x8003c700 0x100>;
  707. status = "disabled";
  708. };
  709. armjtag@8003c800 {
  710. reg = <0x8003c800 0x100>;
  711. status = "disabled";
  712. };
  713. };
  714. apbx@80040000 {
  715. compatible = "simple-bus";
  716. #address-cells = <1>;
  717. #size-cells = <1>;
  718. reg = <0x80040000 0x40000>;
  719. ranges;
  720. clks: clkctrl@80040000 {
  721. compatible = "fsl,imx28-clkctrl", "fsl,clkctrl";
  722. reg = <0x80040000 0x2000>;
  723. #clock-cells = <1>;
  724. };
  725. saif0: saif@80042000 {
  726. compatible = "fsl,imx28-saif";
  727. reg = <0x80042000 0x2000>;
  728. interrupts = <59 80>;
  729. clocks = <&clks 53>;
  730. dmas = <&dma_apbx 4>;
  731. dma-names = "rx-tx";
  732. fsl,saif-dma-channel = <4>;
  733. status = "disabled";
  734. };
  735. power@80044000 {
  736. reg = <0x80044000 0x2000>;
  737. status = "disabled";
  738. };
  739. saif1: saif@80046000 {
  740. compatible = "fsl,imx28-saif";
  741. reg = <0x80046000 0x2000>;
  742. interrupts = <58 81>;
  743. clocks = <&clks 54>;
  744. dmas = <&dma_apbx 5>;
  745. dma-names = "rx-tx";
  746. fsl,saif-dma-channel = <5>;
  747. status = "disabled";
  748. };
  749. lradc@80050000 {
  750. compatible = "fsl,imx28-lradc";
  751. reg = <0x80050000 0x2000>;
  752. interrupts = <10 14 15 16 17 18 19
  753. 20 21 22 23 24 25>;
  754. status = "disabled";
  755. };
  756. spdif@80054000 {
  757. reg = <0x80054000 0x2000>;
  758. interrupts = <45 66>;
  759. dmas = <&dma_apbx 2>;
  760. dma-names = "tx";
  761. status = "disabled";
  762. };
  763. rtc@80056000 {
  764. compatible = "fsl,imx28-rtc", "fsl,stmp3xxx-rtc";
  765. reg = <0x80056000 0x2000>;
  766. interrupts = <29>;
  767. };
  768. i2c0: i2c@80058000 {
  769. #address-cells = <1>;
  770. #size-cells = <0>;
  771. compatible = "fsl,imx28-i2c";
  772. reg = <0x80058000 0x2000>;
  773. interrupts = <111 68>;
  774. clock-frequency = <100000>;
  775. dmas = <&dma_apbx 6>;
  776. dma-names = "rx-tx";
  777. fsl,i2c-dma-channel = <6>;
  778. status = "disabled";
  779. };
  780. i2c1: i2c@8005a000 {
  781. #address-cells = <1>;
  782. #size-cells = <0>;
  783. compatible = "fsl,imx28-i2c";
  784. reg = <0x8005a000 0x2000>;
  785. interrupts = <110 69>;
  786. clock-frequency = <100000>;
  787. dmas = <&dma_apbx 7>;
  788. dma-names = "rx-tx";
  789. fsl,i2c-dma-channel = <7>;
  790. status = "disabled";
  791. };
  792. pwm: pwm@80064000 {
  793. compatible = "fsl,imx28-pwm", "fsl,imx23-pwm";
  794. reg = <0x80064000 0x2000>;
  795. clocks = <&clks 44>;
  796. #pwm-cells = <2>;
  797. fsl,pwm-number = <8>;
  798. status = "disabled";
  799. };
  800. timrot@80068000 {
  801. compatible = "fsl,imx28-timrot", "fsl,timrot";
  802. reg = <0x80068000 0x2000>;
  803. interrupts = <48 49 50 51>;
  804. clocks = <&clks 26>;
  805. };
  806. auart0: serial@8006a000 {
  807. compatible = "fsl,imx28-auart", "fsl,imx23-auart";
  808. reg = <0x8006a000 0x2000>;
  809. interrupts = <112 70 71>;
  810. dmas = <&dma_apbx 8>, <&dma_apbx 9>;
  811. dma-names = "rx", "tx";
  812. fsl,auart-dma-channel = <8 9>;
  813. clocks = <&clks 45>;
  814. status = "disabled";
  815. };
  816. auart1: serial@8006c000 {
  817. compatible = "fsl,imx28-auart", "fsl,imx23-auart";
  818. reg = <0x8006c000 0x2000>;
  819. interrupts = <113 72 73>;
  820. dmas = <&dma_apbx 10>, <&dma_apbx 11>;
  821. dma-names = "rx", "tx";
  822. clocks = <&clks 45>;
  823. status = "disabled";
  824. };
  825. auart2: serial@8006e000 {
  826. compatible = "fsl,imx28-auart", "fsl,imx23-auart";
  827. reg = <0x8006e000 0x2000>;
  828. interrupts = <114 74 75>;
  829. dmas = <&dma_apbx 12>, <&dma_apbx 13>;
  830. dma-names = "rx", "tx";
  831. clocks = <&clks 45>;
  832. status = "disabled";
  833. };
  834. auart3: serial@80070000 {
  835. compatible = "fsl,imx28-auart", "fsl,imx23-auart";
  836. reg = <0x80070000 0x2000>;
  837. interrupts = <115 76 77>;
  838. dmas = <&dma_apbx 14>, <&dma_apbx 15>;
  839. dma-names = "rx", "tx";
  840. clocks = <&clks 45>;
  841. status = "disabled";
  842. };
  843. auart4: serial@80072000 {
  844. compatible = "fsl,imx28-auart", "fsl,imx23-auart";
  845. reg = <0x80072000 0x2000>;
  846. interrupts = <116 78 79>;
  847. dmas = <&dma_apbx 0>, <&dma_apbx 1>;
  848. dma-names = "rx", "tx";
  849. clocks = <&clks 45>;
  850. status = "disabled";
  851. };
  852. duart: serial@80074000 {
  853. compatible = "arm,pl011", "arm,primecell";
  854. reg = <0x80074000 0x1000>;
  855. interrupts = <47>;
  856. clocks = <&clks 45>, <&clks 26>;
  857. clock-names = "uart", "apb_pclk";
  858. status = "disabled";
  859. };
  860. usbphy0: usbphy@8007c000 {
  861. compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy";
  862. reg = <0x8007c000 0x2000>;
  863. clocks = <&clks 62>;
  864. status = "disabled";
  865. };
  866. usbphy1: usbphy@8007e000 {
  867. compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy";
  868. reg = <0x8007e000 0x2000>;
  869. clocks = <&clks 63>;
  870. status = "disabled";
  871. };
  872. };
  873. };
  874. ahb@80080000 {
  875. compatible = "simple-bus";
  876. #address-cells = <1>;
  877. #size-cells = <1>;
  878. reg = <0x80080000 0x80000>;
  879. ranges;
  880. usb0: usb@80080000 {
  881. compatible = "fsl,imx28-usb", "fsl,imx27-usb";
  882. reg = <0x80080000 0x10000>;
  883. interrupts = <93>;
  884. clocks = <&clks 60>;
  885. fsl,usbphy = <&usbphy0>;
  886. status = "disabled";
  887. };
  888. usb1: usb@80090000 {
  889. compatible = "fsl,imx28-usb", "fsl,imx27-usb";
  890. reg = <0x80090000 0x10000>;
  891. interrupts = <92>;
  892. clocks = <&clks 61>;
  893. fsl,usbphy = <&usbphy1>;
  894. status = "disabled";
  895. };
  896. dflpt@800c0000 {
  897. reg = <0x800c0000 0x10000>;
  898. status = "disabled";
  899. };
  900. mac0: ethernet@800f0000 {
  901. compatible = "fsl,imx28-fec";
  902. reg = <0x800f0000 0x4000>;
  903. interrupts = <101>;
  904. clocks = <&clks 57>, <&clks 57>, <&clks 64>;
  905. clock-names = "ipg", "ahb", "enet_out";
  906. status = "disabled";
  907. };
  908. mac1: ethernet@800f4000 {
  909. compatible = "fsl,imx28-fec";
  910. reg = <0x800f4000 0x4000>;
  911. interrupts = <102>;
  912. clocks = <&clks 57>, <&clks 57>;
  913. clock-names = "ipg", "ahb";
  914. status = "disabled";
  915. };
  916. switch@800f8000 {
  917. reg = <0x800f8000 0x8000>;
  918. status = "disabled";
  919. };
  920. };
  921. };