cnic.c 145 KB

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  1. /* cnic.c: Broadcom CNIC core network driver.
  2. *
  3. * Copyright (c) 2006-2012 Broadcom Corporation
  4. *
  5. * This program is free software; you can redistribute it and/or modify
  6. * it under the terms of the GNU General Public License as published by
  7. * the Free Software Foundation.
  8. *
  9. * Original skeleton written by: John(Zongxi) Chen (zongxi@broadcom.com)
  10. * Modified and maintained by: Michael Chan <mchan@broadcom.com>
  11. */
  12. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  13. #include <linux/module.h>
  14. #include <linux/kernel.h>
  15. #include <linux/errno.h>
  16. #include <linux/list.h>
  17. #include <linux/slab.h>
  18. #include <linux/pci.h>
  19. #include <linux/init.h>
  20. #include <linux/netdevice.h>
  21. #include <linux/uio_driver.h>
  22. #include <linux/in.h>
  23. #include <linux/dma-mapping.h>
  24. #include <linux/delay.h>
  25. #include <linux/ethtool.h>
  26. #include <linux/if_vlan.h>
  27. #include <linux/prefetch.h>
  28. #include <linux/random.h>
  29. #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
  30. #define BCM_VLAN 1
  31. #endif
  32. #include <net/ip.h>
  33. #include <net/tcp.h>
  34. #include <net/route.h>
  35. #include <net/ipv6.h>
  36. #include <net/ip6_route.h>
  37. #include <net/ip6_checksum.h>
  38. #include <scsi/iscsi_if.h>
  39. #include "cnic_if.h"
  40. #include "bnx2.h"
  41. #include "bnx2x/bnx2x_reg.h"
  42. #include "bnx2x/bnx2x_fw_defs.h"
  43. #include "bnx2x/bnx2x_hsi.h"
  44. #include "../../../scsi/bnx2i/57xx_iscsi_constants.h"
  45. #include "../../../scsi/bnx2i/57xx_iscsi_hsi.h"
  46. #include "../../../scsi/bnx2fc/bnx2fc_constants.h"
  47. #include "cnic.h"
  48. #include "cnic_defs.h"
  49. #define DRV_MODULE_NAME "cnic"
  50. static char version[] __devinitdata =
  51. "Broadcom NetXtreme II CNIC Driver " DRV_MODULE_NAME " v" CNIC_MODULE_VERSION " (" CNIC_MODULE_RELDATE ")\n";
  52. MODULE_AUTHOR("Michael Chan <mchan@broadcom.com> and John(Zongxi) "
  53. "Chen (zongxi@broadcom.com");
  54. MODULE_DESCRIPTION("Broadcom NetXtreme II CNIC Driver");
  55. MODULE_LICENSE("GPL");
  56. MODULE_VERSION(CNIC_MODULE_VERSION);
  57. /* cnic_dev_list modifications are protected by both rtnl and cnic_dev_lock */
  58. static LIST_HEAD(cnic_dev_list);
  59. static LIST_HEAD(cnic_udev_list);
  60. static DEFINE_RWLOCK(cnic_dev_lock);
  61. static DEFINE_MUTEX(cnic_lock);
  62. static struct cnic_ulp_ops __rcu *cnic_ulp_tbl[MAX_CNIC_ULP_TYPE];
  63. /* helper function, assuming cnic_lock is held */
  64. static inline struct cnic_ulp_ops *cnic_ulp_tbl_prot(int type)
  65. {
  66. return rcu_dereference_protected(cnic_ulp_tbl[type],
  67. lockdep_is_held(&cnic_lock));
  68. }
  69. static int cnic_service_bnx2(void *, void *);
  70. static int cnic_service_bnx2x(void *, void *);
  71. static int cnic_ctl(void *, struct cnic_ctl_info *);
  72. static struct cnic_ops cnic_bnx2_ops = {
  73. .cnic_owner = THIS_MODULE,
  74. .cnic_handler = cnic_service_bnx2,
  75. .cnic_ctl = cnic_ctl,
  76. };
  77. static struct cnic_ops cnic_bnx2x_ops = {
  78. .cnic_owner = THIS_MODULE,
  79. .cnic_handler = cnic_service_bnx2x,
  80. .cnic_ctl = cnic_ctl,
  81. };
  82. static struct workqueue_struct *cnic_wq;
  83. static void cnic_shutdown_rings(struct cnic_dev *);
  84. static void cnic_init_rings(struct cnic_dev *);
  85. static int cnic_cm_set_pg(struct cnic_sock *);
  86. static int cnic_uio_open(struct uio_info *uinfo, struct inode *inode)
  87. {
  88. struct cnic_uio_dev *udev = uinfo->priv;
  89. struct cnic_dev *dev;
  90. if (!capable(CAP_NET_ADMIN))
  91. return -EPERM;
  92. if (udev->uio_dev != -1)
  93. return -EBUSY;
  94. rtnl_lock();
  95. dev = udev->dev;
  96. if (!dev || !test_bit(CNIC_F_CNIC_UP, &dev->flags)) {
  97. rtnl_unlock();
  98. return -ENODEV;
  99. }
  100. udev->uio_dev = iminor(inode);
  101. cnic_shutdown_rings(dev);
  102. cnic_init_rings(dev);
  103. rtnl_unlock();
  104. return 0;
  105. }
  106. static int cnic_uio_close(struct uio_info *uinfo, struct inode *inode)
  107. {
  108. struct cnic_uio_dev *udev = uinfo->priv;
  109. udev->uio_dev = -1;
  110. return 0;
  111. }
  112. static inline void cnic_hold(struct cnic_dev *dev)
  113. {
  114. atomic_inc(&dev->ref_count);
  115. }
  116. static inline void cnic_put(struct cnic_dev *dev)
  117. {
  118. atomic_dec(&dev->ref_count);
  119. }
  120. static inline void csk_hold(struct cnic_sock *csk)
  121. {
  122. atomic_inc(&csk->ref_count);
  123. }
  124. static inline void csk_put(struct cnic_sock *csk)
  125. {
  126. atomic_dec(&csk->ref_count);
  127. }
  128. static struct cnic_dev *cnic_from_netdev(struct net_device *netdev)
  129. {
  130. struct cnic_dev *cdev;
  131. read_lock(&cnic_dev_lock);
  132. list_for_each_entry(cdev, &cnic_dev_list, list) {
  133. if (netdev == cdev->netdev) {
  134. cnic_hold(cdev);
  135. read_unlock(&cnic_dev_lock);
  136. return cdev;
  137. }
  138. }
  139. read_unlock(&cnic_dev_lock);
  140. return NULL;
  141. }
  142. static inline void ulp_get(struct cnic_ulp_ops *ulp_ops)
  143. {
  144. atomic_inc(&ulp_ops->ref_count);
  145. }
  146. static inline void ulp_put(struct cnic_ulp_ops *ulp_ops)
  147. {
  148. atomic_dec(&ulp_ops->ref_count);
  149. }
  150. static void cnic_ctx_wr(struct cnic_dev *dev, u32 cid_addr, u32 off, u32 val)
  151. {
  152. struct cnic_local *cp = dev->cnic_priv;
  153. struct cnic_eth_dev *ethdev = cp->ethdev;
  154. struct drv_ctl_info info;
  155. struct drv_ctl_io *io = &info.data.io;
  156. info.cmd = DRV_CTL_CTX_WR_CMD;
  157. io->cid_addr = cid_addr;
  158. io->offset = off;
  159. io->data = val;
  160. ethdev->drv_ctl(dev->netdev, &info);
  161. }
  162. static void cnic_ctx_tbl_wr(struct cnic_dev *dev, u32 off, dma_addr_t addr)
  163. {
  164. struct cnic_local *cp = dev->cnic_priv;
  165. struct cnic_eth_dev *ethdev = cp->ethdev;
  166. struct drv_ctl_info info;
  167. struct drv_ctl_io *io = &info.data.io;
  168. info.cmd = DRV_CTL_CTXTBL_WR_CMD;
  169. io->offset = off;
  170. io->dma_addr = addr;
  171. ethdev->drv_ctl(dev->netdev, &info);
  172. }
  173. static void cnic_ring_ctl(struct cnic_dev *dev, u32 cid, u32 cl_id, int start)
  174. {
  175. struct cnic_local *cp = dev->cnic_priv;
  176. struct cnic_eth_dev *ethdev = cp->ethdev;
  177. struct drv_ctl_info info;
  178. struct drv_ctl_l2_ring *ring = &info.data.ring;
  179. if (start)
  180. info.cmd = DRV_CTL_START_L2_CMD;
  181. else
  182. info.cmd = DRV_CTL_STOP_L2_CMD;
  183. ring->cid = cid;
  184. ring->client_id = cl_id;
  185. ethdev->drv_ctl(dev->netdev, &info);
  186. }
  187. static void cnic_reg_wr_ind(struct cnic_dev *dev, u32 off, u32 val)
  188. {
  189. struct cnic_local *cp = dev->cnic_priv;
  190. struct cnic_eth_dev *ethdev = cp->ethdev;
  191. struct drv_ctl_info info;
  192. struct drv_ctl_io *io = &info.data.io;
  193. info.cmd = DRV_CTL_IO_WR_CMD;
  194. io->offset = off;
  195. io->data = val;
  196. ethdev->drv_ctl(dev->netdev, &info);
  197. }
  198. static u32 cnic_reg_rd_ind(struct cnic_dev *dev, u32 off)
  199. {
  200. struct cnic_local *cp = dev->cnic_priv;
  201. struct cnic_eth_dev *ethdev = cp->ethdev;
  202. struct drv_ctl_info info;
  203. struct drv_ctl_io *io = &info.data.io;
  204. info.cmd = DRV_CTL_IO_RD_CMD;
  205. io->offset = off;
  206. ethdev->drv_ctl(dev->netdev, &info);
  207. return io->data;
  208. }
  209. static void cnic_ulp_ctl(struct cnic_dev *dev, int ulp_type, bool reg)
  210. {
  211. struct cnic_local *cp = dev->cnic_priv;
  212. struct cnic_eth_dev *ethdev = cp->ethdev;
  213. struct drv_ctl_info info;
  214. struct fcoe_capabilities *fcoe_cap =
  215. &info.data.register_data.fcoe_features;
  216. if (reg) {
  217. info.cmd = DRV_CTL_ULP_REGISTER_CMD;
  218. if (ulp_type == CNIC_ULP_FCOE && dev->fcoe_cap)
  219. memcpy(fcoe_cap, dev->fcoe_cap, sizeof(*fcoe_cap));
  220. } else {
  221. info.cmd = DRV_CTL_ULP_UNREGISTER_CMD;
  222. }
  223. info.data.ulp_type = ulp_type;
  224. ethdev->drv_ctl(dev->netdev, &info);
  225. }
  226. static int cnic_in_use(struct cnic_sock *csk)
  227. {
  228. return test_bit(SK_F_INUSE, &csk->flags);
  229. }
  230. static void cnic_spq_completion(struct cnic_dev *dev, int cmd, u32 count)
  231. {
  232. struct cnic_local *cp = dev->cnic_priv;
  233. struct cnic_eth_dev *ethdev = cp->ethdev;
  234. struct drv_ctl_info info;
  235. info.cmd = cmd;
  236. info.data.credit.credit_count = count;
  237. ethdev->drv_ctl(dev->netdev, &info);
  238. }
  239. static int cnic_get_l5_cid(struct cnic_local *cp, u32 cid, u32 *l5_cid)
  240. {
  241. u32 i;
  242. if (!cp->ctx_tbl)
  243. return -EINVAL;
  244. for (i = 0; i < cp->max_cid_space; i++) {
  245. if (cp->ctx_tbl[i].cid == cid) {
  246. *l5_cid = i;
  247. return 0;
  248. }
  249. }
  250. return -EINVAL;
  251. }
  252. static int cnic_send_nlmsg(struct cnic_local *cp, u32 type,
  253. struct cnic_sock *csk)
  254. {
  255. struct iscsi_path path_req;
  256. char *buf = NULL;
  257. u16 len = 0;
  258. u32 msg_type = ISCSI_KEVENT_IF_DOWN;
  259. struct cnic_ulp_ops *ulp_ops;
  260. struct cnic_uio_dev *udev = cp->udev;
  261. int rc = 0, retry = 0;
  262. if (!udev || udev->uio_dev == -1)
  263. return -ENODEV;
  264. if (csk) {
  265. len = sizeof(path_req);
  266. buf = (char *) &path_req;
  267. memset(&path_req, 0, len);
  268. msg_type = ISCSI_KEVENT_PATH_REQ;
  269. path_req.handle = (u64) csk->l5_cid;
  270. if (test_bit(SK_F_IPV6, &csk->flags)) {
  271. memcpy(&path_req.dst.v6_addr, &csk->dst_ip[0],
  272. sizeof(struct in6_addr));
  273. path_req.ip_addr_len = 16;
  274. } else {
  275. memcpy(&path_req.dst.v4_addr, &csk->dst_ip[0],
  276. sizeof(struct in_addr));
  277. path_req.ip_addr_len = 4;
  278. }
  279. path_req.vlan_id = csk->vlan_id;
  280. path_req.pmtu = csk->mtu;
  281. }
  282. while (retry < 3) {
  283. rc = 0;
  284. rcu_read_lock();
  285. ulp_ops = rcu_dereference(cnic_ulp_tbl[CNIC_ULP_ISCSI]);
  286. if (ulp_ops)
  287. rc = ulp_ops->iscsi_nl_send_msg(
  288. cp->ulp_handle[CNIC_ULP_ISCSI],
  289. msg_type, buf, len);
  290. rcu_read_unlock();
  291. if (rc == 0 || msg_type != ISCSI_KEVENT_PATH_REQ)
  292. break;
  293. msleep(100);
  294. retry++;
  295. }
  296. return rc;
  297. }
  298. static void cnic_cm_upcall(struct cnic_local *, struct cnic_sock *, u8);
  299. static int cnic_iscsi_nl_msg_recv(struct cnic_dev *dev, u32 msg_type,
  300. char *buf, u16 len)
  301. {
  302. int rc = -EINVAL;
  303. switch (msg_type) {
  304. case ISCSI_UEVENT_PATH_UPDATE: {
  305. struct cnic_local *cp;
  306. u32 l5_cid;
  307. struct cnic_sock *csk;
  308. struct iscsi_path *path_resp;
  309. if (len < sizeof(*path_resp))
  310. break;
  311. path_resp = (struct iscsi_path *) buf;
  312. cp = dev->cnic_priv;
  313. l5_cid = (u32) path_resp->handle;
  314. if (l5_cid >= MAX_CM_SK_TBL_SZ)
  315. break;
  316. rcu_read_lock();
  317. if (!rcu_dereference(cp->ulp_ops[CNIC_ULP_L4])) {
  318. rc = -ENODEV;
  319. rcu_read_unlock();
  320. break;
  321. }
  322. csk = &cp->csk_tbl[l5_cid];
  323. csk_hold(csk);
  324. if (cnic_in_use(csk) &&
  325. test_bit(SK_F_CONNECT_START, &csk->flags)) {
  326. csk->vlan_id = path_resp->vlan_id;
  327. memcpy(csk->ha, path_resp->mac_addr, 6);
  328. if (test_bit(SK_F_IPV6, &csk->flags))
  329. memcpy(&csk->src_ip[0], &path_resp->src.v6_addr,
  330. sizeof(struct in6_addr));
  331. else
  332. memcpy(&csk->src_ip[0], &path_resp->src.v4_addr,
  333. sizeof(struct in_addr));
  334. if (is_valid_ether_addr(csk->ha)) {
  335. cnic_cm_set_pg(csk);
  336. } else if (!test_bit(SK_F_OFFLD_SCHED, &csk->flags) &&
  337. !test_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) {
  338. cnic_cm_upcall(cp, csk,
  339. L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE);
  340. clear_bit(SK_F_CONNECT_START, &csk->flags);
  341. }
  342. }
  343. csk_put(csk);
  344. rcu_read_unlock();
  345. rc = 0;
  346. }
  347. }
  348. return rc;
  349. }
  350. static int cnic_offld_prep(struct cnic_sock *csk)
  351. {
  352. if (test_and_set_bit(SK_F_OFFLD_SCHED, &csk->flags))
  353. return 0;
  354. if (!test_bit(SK_F_CONNECT_START, &csk->flags)) {
  355. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  356. return 0;
  357. }
  358. return 1;
  359. }
  360. static int cnic_close_prep(struct cnic_sock *csk)
  361. {
  362. clear_bit(SK_F_CONNECT_START, &csk->flags);
  363. smp_mb__after_clear_bit();
  364. if (test_and_clear_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) {
  365. while (test_and_set_bit(SK_F_OFFLD_SCHED, &csk->flags))
  366. msleep(1);
  367. return 1;
  368. }
  369. return 0;
  370. }
  371. static int cnic_abort_prep(struct cnic_sock *csk)
  372. {
  373. clear_bit(SK_F_CONNECT_START, &csk->flags);
  374. smp_mb__after_clear_bit();
  375. while (test_and_set_bit(SK_F_OFFLD_SCHED, &csk->flags))
  376. msleep(1);
  377. if (test_and_clear_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) {
  378. csk->state = L4_KCQE_OPCODE_VALUE_RESET_COMP;
  379. return 1;
  380. }
  381. return 0;
  382. }
  383. int cnic_register_driver(int ulp_type, struct cnic_ulp_ops *ulp_ops)
  384. {
  385. struct cnic_dev *dev;
  386. if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
  387. pr_err("%s: Bad type %d\n", __func__, ulp_type);
  388. return -EINVAL;
  389. }
  390. mutex_lock(&cnic_lock);
  391. if (cnic_ulp_tbl_prot(ulp_type)) {
  392. pr_err("%s: Type %d has already been registered\n",
  393. __func__, ulp_type);
  394. mutex_unlock(&cnic_lock);
  395. return -EBUSY;
  396. }
  397. read_lock(&cnic_dev_lock);
  398. list_for_each_entry(dev, &cnic_dev_list, list) {
  399. struct cnic_local *cp = dev->cnic_priv;
  400. clear_bit(ULP_F_INIT, &cp->ulp_flags[ulp_type]);
  401. }
  402. read_unlock(&cnic_dev_lock);
  403. atomic_set(&ulp_ops->ref_count, 0);
  404. rcu_assign_pointer(cnic_ulp_tbl[ulp_type], ulp_ops);
  405. mutex_unlock(&cnic_lock);
  406. /* Prevent race conditions with netdev_event */
  407. rtnl_lock();
  408. list_for_each_entry(dev, &cnic_dev_list, list) {
  409. struct cnic_local *cp = dev->cnic_priv;
  410. if (!test_and_set_bit(ULP_F_INIT, &cp->ulp_flags[ulp_type]))
  411. ulp_ops->cnic_init(dev);
  412. }
  413. rtnl_unlock();
  414. return 0;
  415. }
  416. int cnic_unregister_driver(int ulp_type)
  417. {
  418. struct cnic_dev *dev;
  419. struct cnic_ulp_ops *ulp_ops;
  420. int i = 0;
  421. if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
  422. pr_err("%s: Bad type %d\n", __func__, ulp_type);
  423. return -EINVAL;
  424. }
  425. mutex_lock(&cnic_lock);
  426. ulp_ops = cnic_ulp_tbl_prot(ulp_type);
  427. if (!ulp_ops) {
  428. pr_err("%s: Type %d has not been registered\n",
  429. __func__, ulp_type);
  430. goto out_unlock;
  431. }
  432. read_lock(&cnic_dev_lock);
  433. list_for_each_entry(dev, &cnic_dev_list, list) {
  434. struct cnic_local *cp = dev->cnic_priv;
  435. if (rcu_dereference(cp->ulp_ops[ulp_type])) {
  436. pr_err("%s: Type %d still has devices registered\n",
  437. __func__, ulp_type);
  438. read_unlock(&cnic_dev_lock);
  439. goto out_unlock;
  440. }
  441. }
  442. read_unlock(&cnic_dev_lock);
  443. RCU_INIT_POINTER(cnic_ulp_tbl[ulp_type], NULL);
  444. mutex_unlock(&cnic_lock);
  445. synchronize_rcu();
  446. while ((atomic_read(&ulp_ops->ref_count) != 0) && (i < 20)) {
  447. msleep(100);
  448. i++;
  449. }
  450. if (atomic_read(&ulp_ops->ref_count) != 0)
  451. netdev_warn(dev->netdev, "Failed waiting for ref count to go to zero\n");
  452. return 0;
  453. out_unlock:
  454. mutex_unlock(&cnic_lock);
  455. return -EINVAL;
  456. }
  457. static int cnic_start_hw(struct cnic_dev *);
  458. static void cnic_stop_hw(struct cnic_dev *);
  459. static int cnic_register_device(struct cnic_dev *dev, int ulp_type,
  460. void *ulp_ctx)
  461. {
  462. struct cnic_local *cp = dev->cnic_priv;
  463. struct cnic_ulp_ops *ulp_ops;
  464. if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
  465. pr_err("%s: Bad type %d\n", __func__, ulp_type);
  466. return -EINVAL;
  467. }
  468. mutex_lock(&cnic_lock);
  469. if (cnic_ulp_tbl_prot(ulp_type) == NULL) {
  470. pr_err("%s: Driver with type %d has not been registered\n",
  471. __func__, ulp_type);
  472. mutex_unlock(&cnic_lock);
  473. return -EAGAIN;
  474. }
  475. if (rcu_dereference(cp->ulp_ops[ulp_type])) {
  476. pr_err("%s: Type %d has already been registered to this device\n",
  477. __func__, ulp_type);
  478. mutex_unlock(&cnic_lock);
  479. return -EBUSY;
  480. }
  481. clear_bit(ULP_F_START, &cp->ulp_flags[ulp_type]);
  482. cp->ulp_handle[ulp_type] = ulp_ctx;
  483. ulp_ops = cnic_ulp_tbl_prot(ulp_type);
  484. rcu_assign_pointer(cp->ulp_ops[ulp_type], ulp_ops);
  485. cnic_hold(dev);
  486. if (test_bit(CNIC_F_CNIC_UP, &dev->flags))
  487. if (!test_and_set_bit(ULP_F_START, &cp->ulp_flags[ulp_type]))
  488. ulp_ops->cnic_start(cp->ulp_handle[ulp_type]);
  489. mutex_unlock(&cnic_lock);
  490. cnic_ulp_ctl(dev, ulp_type, true);
  491. return 0;
  492. }
  493. EXPORT_SYMBOL(cnic_register_driver);
  494. static int cnic_unregister_device(struct cnic_dev *dev, int ulp_type)
  495. {
  496. struct cnic_local *cp = dev->cnic_priv;
  497. int i = 0;
  498. if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
  499. pr_err("%s: Bad type %d\n", __func__, ulp_type);
  500. return -EINVAL;
  501. }
  502. mutex_lock(&cnic_lock);
  503. if (rcu_dereference(cp->ulp_ops[ulp_type])) {
  504. RCU_INIT_POINTER(cp->ulp_ops[ulp_type], NULL);
  505. cnic_put(dev);
  506. } else {
  507. pr_err("%s: device not registered to this ulp type %d\n",
  508. __func__, ulp_type);
  509. mutex_unlock(&cnic_lock);
  510. return -EINVAL;
  511. }
  512. mutex_unlock(&cnic_lock);
  513. if (ulp_type == CNIC_ULP_ISCSI)
  514. cnic_send_nlmsg(cp, ISCSI_KEVENT_IF_DOWN, NULL);
  515. else if (ulp_type == CNIC_ULP_FCOE)
  516. dev->fcoe_cap = NULL;
  517. synchronize_rcu();
  518. while (test_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[ulp_type]) &&
  519. i < 20) {
  520. msleep(100);
  521. i++;
  522. }
  523. if (test_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[ulp_type]))
  524. netdev_warn(dev->netdev, "Failed waiting for ULP up call to complete\n");
  525. cnic_ulp_ctl(dev, ulp_type, false);
  526. return 0;
  527. }
  528. EXPORT_SYMBOL(cnic_unregister_driver);
  529. static int cnic_init_id_tbl(struct cnic_id_tbl *id_tbl, u32 size, u32 start_id,
  530. u32 next)
  531. {
  532. id_tbl->start = start_id;
  533. id_tbl->max = size;
  534. id_tbl->next = next;
  535. spin_lock_init(&id_tbl->lock);
  536. id_tbl->table = kzalloc(DIV_ROUND_UP(size, 32) * 4, GFP_KERNEL);
  537. if (!id_tbl->table)
  538. return -ENOMEM;
  539. return 0;
  540. }
  541. static void cnic_free_id_tbl(struct cnic_id_tbl *id_tbl)
  542. {
  543. kfree(id_tbl->table);
  544. id_tbl->table = NULL;
  545. }
  546. static int cnic_alloc_id(struct cnic_id_tbl *id_tbl, u32 id)
  547. {
  548. int ret = -1;
  549. id -= id_tbl->start;
  550. if (id >= id_tbl->max)
  551. return ret;
  552. spin_lock(&id_tbl->lock);
  553. if (!test_bit(id, id_tbl->table)) {
  554. set_bit(id, id_tbl->table);
  555. ret = 0;
  556. }
  557. spin_unlock(&id_tbl->lock);
  558. return ret;
  559. }
  560. /* Returns -1 if not successful */
  561. static u32 cnic_alloc_new_id(struct cnic_id_tbl *id_tbl)
  562. {
  563. u32 id;
  564. spin_lock(&id_tbl->lock);
  565. id = find_next_zero_bit(id_tbl->table, id_tbl->max, id_tbl->next);
  566. if (id >= id_tbl->max) {
  567. id = -1;
  568. if (id_tbl->next != 0) {
  569. id = find_first_zero_bit(id_tbl->table, id_tbl->next);
  570. if (id >= id_tbl->next)
  571. id = -1;
  572. }
  573. }
  574. if (id < id_tbl->max) {
  575. set_bit(id, id_tbl->table);
  576. id_tbl->next = (id + 1) & (id_tbl->max - 1);
  577. id += id_tbl->start;
  578. }
  579. spin_unlock(&id_tbl->lock);
  580. return id;
  581. }
  582. static void cnic_free_id(struct cnic_id_tbl *id_tbl, u32 id)
  583. {
  584. if (id == -1)
  585. return;
  586. id -= id_tbl->start;
  587. if (id >= id_tbl->max)
  588. return;
  589. clear_bit(id, id_tbl->table);
  590. }
  591. static void cnic_free_dma(struct cnic_dev *dev, struct cnic_dma *dma)
  592. {
  593. int i;
  594. if (!dma->pg_arr)
  595. return;
  596. for (i = 0; i < dma->num_pages; i++) {
  597. if (dma->pg_arr[i]) {
  598. dma_free_coherent(&dev->pcidev->dev, BCM_PAGE_SIZE,
  599. dma->pg_arr[i], dma->pg_map_arr[i]);
  600. dma->pg_arr[i] = NULL;
  601. }
  602. }
  603. if (dma->pgtbl) {
  604. dma_free_coherent(&dev->pcidev->dev, dma->pgtbl_size,
  605. dma->pgtbl, dma->pgtbl_map);
  606. dma->pgtbl = NULL;
  607. }
  608. kfree(dma->pg_arr);
  609. dma->pg_arr = NULL;
  610. dma->num_pages = 0;
  611. }
  612. static void cnic_setup_page_tbl(struct cnic_dev *dev, struct cnic_dma *dma)
  613. {
  614. int i;
  615. __le32 *page_table = (__le32 *) dma->pgtbl;
  616. for (i = 0; i < dma->num_pages; i++) {
  617. /* Each entry needs to be in big endian format. */
  618. *page_table = cpu_to_le32((u64) dma->pg_map_arr[i] >> 32);
  619. page_table++;
  620. *page_table = cpu_to_le32(dma->pg_map_arr[i] & 0xffffffff);
  621. page_table++;
  622. }
  623. }
  624. static void cnic_setup_page_tbl_le(struct cnic_dev *dev, struct cnic_dma *dma)
  625. {
  626. int i;
  627. __le32 *page_table = (__le32 *) dma->pgtbl;
  628. for (i = 0; i < dma->num_pages; i++) {
  629. /* Each entry needs to be in little endian format. */
  630. *page_table = cpu_to_le32(dma->pg_map_arr[i] & 0xffffffff);
  631. page_table++;
  632. *page_table = cpu_to_le32((u64) dma->pg_map_arr[i] >> 32);
  633. page_table++;
  634. }
  635. }
  636. static int cnic_alloc_dma(struct cnic_dev *dev, struct cnic_dma *dma,
  637. int pages, int use_pg_tbl)
  638. {
  639. int i, size;
  640. struct cnic_local *cp = dev->cnic_priv;
  641. size = pages * (sizeof(void *) + sizeof(dma_addr_t));
  642. dma->pg_arr = kzalloc(size, GFP_ATOMIC);
  643. if (dma->pg_arr == NULL)
  644. return -ENOMEM;
  645. dma->pg_map_arr = (dma_addr_t *) (dma->pg_arr + pages);
  646. dma->num_pages = pages;
  647. for (i = 0; i < pages; i++) {
  648. dma->pg_arr[i] = dma_alloc_coherent(&dev->pcidev->dev,
  649. BCM_PAGE_SIZE,
  650. &dma->pg_map_arr[i],
  651. GFP_ATOMIC);
  652. if (dma->pg_arr[i] == NULL)
  653. goto error;
  654. }
  655. if (!use_pg_tbl)
  656. return 0;
  657. dma->pgtbl_size = ((pages * 8) + BCM_PAGE_SIZE - 1) &
  658. ~(BCM_PAGE_SIZE - 1);
  659. dma->pgtbl = dma_alloc_coherent(&dev->pcidev->dev, dma->pgtbl_size,
  660. &dma->pgtbl_map, GFP_ATOMIC);
  661. if (dma->pgtbl == NULL)
  662. goto error;
  663. cp->setup_pgtbl(dev, dma);
  664. return 0;
  665. error:
  666. cnic_free_dma(dev, dma);
  667. return -ENOMEM;
  668. }
  669. static void cnic_free_context(struct cnic_dev *dev)
  670. {
  671. struct cnic_local *cp = dev->cnic_priv;
  672. int i;
  673. for (i = 0; i < cp->ctx_blks; i++) {
  674. if (cp->ctx_arr[i].ctx) {
  675. dma_free_coherent(&dev->pcidev->dev, cp->ctx_blk_size,
  676. cp->ctx_arr[i].ctx,
  677. cp->ctx_arr[i].mapping);
  678. cp->ctx_arr[i].ctx = NULL;
  679. }
  680. }
  681. }
  682. static void __cnic_free_uio(struct cnic_uio_dev *udev)
  683. {
  684. uio_unregister_device(&udev->cnic_uinfo);
  685. if (udev->l2_buf) {
  686. dma_free_coherent(&udev->pdev->dev, udev->l2_buf_size,
  687. udev->l2_buf, udev->l2_buf_map);
  688. udev->l2_buf = NULL;
  689. }
  690. if (udev->l2_ring) {
  691. dma_free_coherent(&udev->pdev->dev, udev->l2_ring_size,
  692. udev->l2_ring, udev->l2_ring_map);
  693. udev->l2_ring = NULL;
  694. }
  695. pci_dev_put(udev->pdev);
  696. kfree(udev);
  697. }
  698. static void cnic_free_uio(struct cnic_uio_dev *udev)
  699. {
  700. if (!udev)
  701. return;
  702. write_lock(&cnic_dev_lock);
  703. list_del_init(&udev->list);
  704. write_unlock(&cnic_dev_lock);
  705. __cnic_free_uio(udev);
  706. }
  707. static void cnic_free_resc(struct cnic_dev *dev)
  708. {
  709. struct cnic_local *cp = dev->cnic_priv;
  710. struct cnic_uio_dev *udev = cp->udev;
  711. if (udev) {
  712. udev->dev = NULL;
  713. cp->udev = NULL;
  714. }
  715. cnic_free_context(dev);
  716. kfree(cp->ctx_arr);
  717. cp->ctx_arr = NULL;
  718. cp->ctx_blks = 0;
  719. cnic_free_dma(dev, &cp->gbl_buf_info);
  720. cnic_free_dma(dev, &cp->kwq_info);
  721. cnic_free_dma(dev, &cp->kwq_16_data_info);
  722. cnic_free_dma(dev, &cp->kcq2.dma);
  723. cnic_free_dma(dev, &cp->kcq1.dma);
  724. kfree(cp->iscsi_tbl);
  725. cp->iscsi_tbl = NULL;
  726. kfree(cp->ctx_tbl);
  727. cp->ctx_tbl = NULL;
  728. cnic_free_id_tbl(&cp->fcoe_cid_tbl);
  729. cnic_free_id_tbl(&cp->cid_tbl);
  730. }
  731. static int cnic_alloc_context(struct cnic_dev *dev)
  732. {
  733. struct cnic_local *cp = dev->cnic_priv;
  734. if (CHIP_NUM(cp) == CHIP_NUM_5709) {
  735. int i, k, arr_size;
  736. cp->ctx_blk_size = BCM_PAGE_SIZE;
  737. cp->cids_per_blk = BCM_PAGE_SIZE / 128;
  738. arr_size = BNX2_MAX_CID / cp->cids_per_blk *
  739. sizeof(struct cnic_ctx);
  740. cp->ctx_arr = kzalloc(arr_size, GFP_KERNEL);
  741. if (cp->ctx_arr == NULL)
  742. return -ENOMEM;
  743. k = 0;
  744. for (i = 0; i < 2; i++) {
  745. u32 j, reg, off, lo, hi;
  746. if (i == 0)
  747. off = BNX2_PG_CTX_MAP;
  748. else
  749. off = BNX2_ISCSI_CTX_MAP;
  750. reg = cnic_reg_rd_ind(dev, off);
  751. lo = reg >> 16;
  752. hi = reg & 0xffff;
  753. for (j = lo; j < hi; j += cp->cids_per_blk, k++)
  754. cp->ctx_arr[k].cid = j;
  755. }
  756. cp->ctx_blks = k;
  757. if (cp->ctx_blks >= (BNX2_MAX_CID / cp->cids_per_blk)) {
  758. cp->ctx_blks = 0;
  759. return -ENOMEM;
  760. }
  761. for (i = 0; i < cp->ctx_blks; i++) {
  762. cp->ctx_arr[i].ctx =
  763. dma_alloc_coherent(&dev->pcidev->dev,
  764. BCM_PAGE_SIZE,
  765. &cp->ctx_arr[i].mapping,
  766. GFP_KERNEL);
  767. if (cp->ctx_arr[i].ctx == NULL)
  768. return -ENOMEM;
  769. }
  770. }
  771. return 0;
  772. }
  773. static u16 cnic_bnx2_next_idx(u16 idx)
  774. {
  775. return idx + 1;
  776. }
  777. static u16 cnic_bnx2_hw_idx(u16 idx)
  778. {
  779. return idx;
  780. }
  781. static u16 cnic_bnx2x_next_idx(u16 idx)
  782. {
  783. idx++;
  784. if ((idx & MAX_KCQE_CNT) == MAX_KCQE_CNT)
  785. idx++;
  786. return idx;
  787. }
  788. static u16 cnic_bnx2x_hw_idx(u16 idx)
  789. {
  790. if ((idx & MAX_KCQE_CNT) == MAX_KCQE_CNT)
  791. idx++;
  792. return idx;
  793. }
  794. static int cnic_alloc_kcq(struct cnic_dev *dev, struct kcq_info *info,
  795. bool use_pg_tbl)
  796. {
  797. int err, i, use_page_tbl = 0;
  798. struct kcqe **kcq;
  799. if (use_pg_tbl)
  800. use_page_tbl = 1;
  801. err = cnic_alloc_dma(dev, &info->dma, KCQ_PAGE_CNT, use_page_tbl);
  802. if (err)
  803. return err;
  804. kcq = (struct kcqe **) info->dma.pg_arr;
  805. info->kcq = kcq;
  806. info->next_idx = cnic_bnx2_next_idx;
  807. info->hw_idx = cnic_bnx2_hw_idx;
  808. if (use_pg_tbl)
  809. return 0;
  810. info->next_idx = cnic_bnx2x_next_idx;
  811. info->hw_idx = cnic_bnx2x_hw_idx;
  812. for (i = 0; i < KCQ_PAGE_CNT; i++) {
  813. struct bnx2x_bd_chain_next *next =
  814. (struct bnx2x_bd_chain_next *) &kcq[i][MAX_KCQE_CNT];
  815. int j = i + 1;
  816. if (j >= KCQ_PAGE_CNT)
  817. j = 0;
  818. next->addr_hi = (u64) info->dma.pg_map_arr[j] >> 32;
  819. next->addr_lo = info->dma.pg_map_arr[j] & 0xffffffff;
  820. }
  821. return 0;
  822. }
  823. static int cnic_alloc_uio_rings(struct cnic_dev *dev, int pages)
  824. {
  825. struct cnic_local *cp = dev->cnic_priv;
  826. struct cnic_uio_dev *udev;
  827. read_lock(&cnic_dev_lock);
  828. list_for_each_entry(udev, &cnic_udev_list, list) {
  829. if (udev->pdev == dev->pcidev) {
  830. udev->dev = dev;
  831. cp->udev = udev;
  832. read_unlock(&cnic_dev_lock);
  833. return 0;
  834. }
  835. }
  836. read_unlock(&cnic_dev_lock);
  837. udev = kzalloc(sizeof(struct cnic_uio_dev), GFP_ATOMIC);
  838. if (!udev)
  839. return -ENOMEM;
  840. udev->uio_dev = -1;
  841. udev->dev = dev;
  842. udev->pdev = dev->pcidev;
  843. udev->l2_ring_size = pages * BCM_PAGE_SIZE;
  844. udev->l2_ring = dma_alloc_coherent(&udev->pdev->dev, udev->l2_ring_size,
  845. &udev->l2_ring_map,
  846. GFP_KERNEL | __GFP_COMP);
  847. if (!udev->l2_ring)
  848. goto err_udev;
  849. udev->l2_buf_size = (cp->l2_rx_ring_size + 1) * cp->l2_single_buf_size;
  850. udev->l2_buf_size = PAGE_ALIGN(udev->l2_buf_size);
  851. udev->l2_buf = dma_alloc_coherent(&udev->pdev->dev, udev->l2_buf_size,
  852. &udev->l2_buf_map,
  853. GFP_KERNEL | __GFP_COMP);
  854. if (!udev->l2_buf)
  855. goto err_dma;
  856. write_lock(&cnic_dev_lock);
  857. list_add(&udev->list, &cnic_udev_list);
  858. write_unlock(&cnic_dev_lock);
  859. pci_dev_get(udev->pdev);
  860. cp->udev = udev;
  861. return 0;
  862. err_dma:
  863. dma_free_coherent(&udev->pdev->dev, udev->l2_ring_size,
  864. udev->l2_ring, udev->l2_ring_map);
  865. err_udev:
  866. kfree(udev);
  867. return -ENOMEM;
  868. }
  869. static int cnic_init_uio(struct cnic_dev *dev)
  870. {
  871. struct cnic_local *cp = dev->cnic_priv;
  872. struct cnic_uio_dev *udev = cp->udev;
  873. struct uio_info *uinfo;
  874. int ret = 0;
  875. if (!udev)
  876. return -ENOMEM;
  877. uinfo = &udev->cnic_uinfo;
  878. uinfo->mem[0].addr = dev->netdev->base_addr;
  879. uinfo->mem[0].internal_addr = dev->regview;
  880. uinfo->mem[0].size = dev->netdev->mem_end - dev->netdev->mem_start;
  881. uinfo->mem[0].memtype = UIO_MEM_PHYS;
  882. if (test_bit(CNIC_F_BNX2_CLASS, &dev->flags)) {
  883. uinfo->mem[1].addr = (unsigned long) cp->status_blk.gen &
  884. PAGE_MASK;
  885. if (cp->ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX)
  886. uinfo->mem[1].size = BNX2_SBLK_MSIX_ALIGN_SIZE * 9;
  887. else
  888. uinfo->mem[1].size = BNX2_SBLK_MSIX_ALIGN_SIZE;
  889. uinfo->name = "bnx2_cnic";
  890. } else if (test_bit(CNIC_F_BNX2X_CLASS, &dev->flags)) {
  891. uinfo->mem[1].addr = (unsigned long) cp->bnx2x_def_status_blk &
  892. PAGE_MASK;
  893. uinfo->mem[1].size = sizeof(*cp->bnx2x_def_status_blk);
  894. uinfo->name = "bnx2x_cnic";
  895. }
  896. uinfo->mem[1].memtype = UIO_MEM_LOGICAL;
  897. uinfo->mem[2].addr = (unsigned long) udev->l2_ring;
  898. uinfo->mem[2].size = udev->l2_ring_size;
  899. uinfo->mem[2].memtype = UIO_MEM_LOGICAL;
  900. uinfo->mem[3].addr = (unsigned long) udev->l2_buf;
  901. uinfo->mem[3].size = udev->l2_buf_size;
  902. uinfo->mem[3].memtype = UIO_MEM_LOGICAL;
  903. uinfo->version = CNIC_MODULE_VERSION;
  904. uinfo->irq = UIO_IRQ_CUSTOM;
  905. uinfo->open = cnic_uio_open;
  906. uinfo->release = cnic_uio_close;
  907. if (udev->uio_dev == -1) {
  908. if (!uinfo->priv) {
  909. uinfo->priv = udev;
  910. ret = uio_register_device(&udev->pdev->dev, uinfo);
  911. }
  912. } else {
  913. cnic_init_rings(dev);
  914. }
  915. return ret;
  916. }
  917. static int cnic_alloc_bnx2_resc(struct cnic_dev *dev)
  918. {
  919. struct cnic_local *cp = dev->cnic_priv;
  920. int ret;
  921. ret = cnic_alloc_dma(dev, &cp->kwq_info, KWQ_PAGE_CNT, 1);
  922. if (ret)
  923. goto error;
  924. cp->kwq = (struct kwqe **) cp->kwq_info.pg_arr;
  925. ret = cnic_alloc_kcq(dev, &cp->kcq1, true);
  926. if (ret)
  927. goto error;
  928. ret = cnic_alloc_context(dev);
  929. if (ret)
  930. goto error;
  931. ret = cnic_alloc_uio_rings(dev, 2);
  932. if (ret)
  933. goto error;
  934. ret = cnic_init_uio(dev);
  935. if (ret)
  936. goto error;
  937. return 0;
  938. error:
  939. cnic_free_resc(dev);
  940. return ret;
  941. }
  942. static int cnic_alloc_bnx2x_context(struct cnic_dev *dev)
  943. {
  944. struct cnic_local *cp = dev->cnic_priv;
  945. int ctx_blk_size = cp->ethdev->ctx_blk_size;
  946. int total_mem, blks, i;
  947. total_mem = BNX2X_CONTEXT_MEM_SIZE * cp->max_cid_space;
  948. blks = total_mem / ctx_blk_size;
  949. if (total_mem % ctx_blk_size)
  950. blks++;
  951. if (blks > cp->ethdev->ctx_tbl_len)
  952. return -ENOMEM;
  953. cp->ctx_arr = kcalloc(blks, sizeof(struct cnic_ctx), GFP_KERNEL);
  954. if (cp->ctx_arr == NULL)
  955. return -ENOMEM;
  956. cp->ctx_blks = blks;
  957. cp->ctx_blk_size = ctx_blk_size;
  958. if (!BNX2X_CHIP_IS_57710(cp->chip_id))
  959. cp->ctx_align = 0;
  960. else
  961. cp->ctx_align = ctx_blk_size;
  962. cp->cids_per_blk = ctx_blk_size / BNX2X_CONTEXT_MEM_SIZE;
  963. for (i = 0; i < blks; i++) {
  964. cp->ctx_arr[i].ctx =
  965. dma_alloc_coherent(&dev->pcidev->dev, cp->ctx_blk_size,
  966. &cp->ctx_arr[i].mapping,
  967. GFP_KERNEL);
  968. if (cp->ctx_arr[i].ctx == NULL)
  969. return -ENOMEM;
  970. if (cp->ctx_align && cp->ctx_blk_size == ctx_blk_size) {
  971. if (cp->ctx_arr[i].mapping & (cp->ctx_align - 1)) {
  972. cnic_free_context(dev);
  973. cp->ctx_blk_size += cp->ctx_align;
  974. i = -1;
  975. continue;
  976. }
  977. }
  978. }
  979. return 0;
  980. }
  981. static int cnic_alloc_bnx2x_resc(struct cnic_dev *dev)
  982. {
  983. struct cnic_local *cp = dev->cnic_priv;
  984. struct cnic_eth_dev *ethdev = cp->ethdev;
  985. u32 start_cid = ethdev->starting_cid;
  986. int i, j, n, ret, pages;
  987. struct cnic_dma *kwq_16_dma = &cp->kwq_16_data_info;
  988. cp->iro_arr = ethdev->iro_arr;
  989. cp->max_cid_space = MAX_ISCSI_TBL_SZ;
  990. cp->iscsi_start_cid = start_cid;
  991. cp->fcoe_start_cid = start_cid + MAX_ISCSI_TBL_SZ;
  992. if (BNX2X_CHIP_IS_E2_PLUS(cp->chip_id)) {
  993. cp->max_cid_space += dev->max_fcoe_conn;
  994. cp->fcoe_init_cid = ethdev->fcoe_init_cid;
  995. if (!cp->fcoe_init_cid)
  996. cp->fcoe_init_cid = 0x10;
  997. }
  998. cp->iscsi_tbl = kzalloc(sizeof(struct cnic_iscsi) * MAX_ISCSI_TBL_SZ,
  999. GFP_KERNEL);
  1000. if (!cp->iscsi_tbl)
  1001. goto error;
  1002. cp->ctx_tbl = kzalloc(sizeof(struct cnic_context) *
  1003. cp->max_cid_space, GFP_KERNEL);
  1004. if (!cp->ctx_tbl)
  1005. goto error;
  1006. for (i = 0; i < MAX_ISCSI_TBL_SZ; i++) {
  1007. cp->ctx_tbl[i].proto.iscsi = &cp->iscsi_tbl[i];
  1008. cp->ctx_tbl[i].ulp_proto_id = CNIC_ULP_ISCSI;
  1009. }
  1010. for (i = MAX_ISCSI_TBL_SZ; i < cp->max_cid_space; i++)
  1011. cp->ctx_tbl[i].ulp_proto_id = CNIC_ULP_FCOE;
  1012. pages = PAGE_ALIGN(cp->max_cid_space * CNIC_KWQ16_DATA_SIZE) /
  1013. PAGE_SIZE;
  1014. ret = cnic_alloc_dma(dev, kwq_16_dma, pages, 0);
  1015. if (ret)
  1016. return -ENOMEM;
  1017. n = PAGE_SIZE / CNIC_KWQ16_DATA_SIZE;
  1018. for (i = 0, j = 0; i < cp->max_cid_space; i++) {
  1019. long off = CNIC_KWQ16_DATA_SIZE * (i % n);
  1020. cp->ctx_tbl[i].kwqe_data = kwq_16_dma->pg_arr[j] + off;
  1021. cp->ctx_tbl[i].kwqe_data_mapping = kwq_16_dma->pg_map_arr[j] +
  1022. off;
  1023. if ((i % n) == (n - 1))
  1024. j++;
  1025. }
  1026. ret = cnic_alloc_kcq(dev, &cp->kcq1, false);
  1027. if (ret)
  1028. goto error;
  1029. if (BNX2X_CHIP_IS_E2_PLUS(cp->chip_id)) {
  1030. ret = cnic_alloc_kcq(dev, &cp->kcq2, true);
  1031. if (ret)
  1032. goto error;
  1033. }
  1034. pages = PAGE_ALIGN(BNX2X_ISCSI_GLB_BUF_SIZE) / PAGE_SIZE;
  1035. ret = cnic_alloc_dma(dev, &cp->gbl_buf_info, pages, 0);
  1036. if (ret)
  1037. goto error;
  1038. ret = cnic_alloc_bnx2x_context(dev);
  1039. if (ret)
  1040. goto error;
  1041. cp->bnx2x_def_status_blk = cp->ethdev->irq_arr[1].status_blk;
  1042. cp->l2_rx_ring_size = 15;
  1043. ret = cnic_alloc_uio_rings(dev, 4);
  1044. if (ret)
  1045. goto error;
  1046. ret = cnic_init_uio(dev);
  1047. if (ret)
  1048. goto error;
  1049. return 0;
  1050. error:
  1051. cnic_free_resc(dev);
  1052. return -ENOMEM;
  1053. }
  1054. static inline u32 cnic_kwq_avail(struct cnic_local *cp)
  1055. {
  1056. return cp->max_kwq_idx -
  1057. ((cp->kwq_prod_idx - cp->kwq_con_idx) & cp->max_kwq_idx);
  1058. }
  1059. static int cnic_submit_bnx2_kwqes(struct cnic_dev *dev, struct kwqe *wqes[],
  1060. u32 num_wqes)
  1061. {
  1062. struct cnic_local *cp = dev->cnic_priv;
  1063. struct kwqe *prod_qe;
  1064. u16 prod, sw_prod, i;
  1065. if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
  1066. return -EAGAIN; /* bnx2 is down */
  1067. spin_lock_bh(&cp->cnic_ulp_lock);
  1068. if (num_wqes > cnic_kwq_avail(cp) &&
  1069. !test_bit(CNIC_LCL_FL_KWQ_INIT, &cp->cnic_local_flags)) {
  1070. spin_unlock_bh(&cp->cnic_ulp_lock);
  1071. return -EAGAIN;
  1072. }
  1073. clear_bit(CNIC_LCL_FL_KWQ_INIT, &cp->cnic_local_flags);
  1074. prod = cp->kwq_prod_idx;
  1075. sw_prod = prod & MAX_KWQ_IDX;
  1076. for (i = 0; i < num_wqes; i++) {
  1077. prod_qe = &cp->kwq[KWQ_PG(sw_prod)][KWQ_IDX(sw_prod)];
  1078. memcpy(prod_qe, wqes[i], sizeof(struct kwqe));
  1079. prod++;
  1080. sw_prod = prod & MAX_KWQ_IDX;
  1081. }
  1082. cp->kwq_prod_idx = prod;
  1083. CNIC_WR16(dev, cp->kwq_io_addr, cp->kwq_prod_idx);
  1084. spin_unlock_bh(&cp->cnic_ulp_lock);
  1085. return 0;
  1086. }
  1087. static void *cnic_get_kwqe_16_data(struct cnic_local *cp, u32 l5_cid,
  1088. union l5cm_specific_data *l5_data)
  1089. {
  1090. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1091. dma_addr_t map;
  1092. map = ctx->kwqe_data_mapping;
  1093. l5_data->phy_address.lo = (u64) map & 0xffffffff;
  1094. l5_data->phy_address.hi = (u64) map >> 32;
  1095. return ctx->kwqe_data;
  1096. }
  1097. static int cnic_submit_kwqe_16(struct cnic_dev *dev, u32 cmd, u32 cid,
  1098. u32 type, union l5cm_specific_data *l5_data)
  1099. {
  1100. struct cnic_local *cp = dev->cnic_priv;
  1101. struct l5cm_spe kwqe;
  1102. struct kwqe_16 *kwq[1];
  1103. u16 type_16;
  1104. int ret;
  1105. kwqe.hdr.conn_and_cmd_data =
  1106. cpu_to_le32(((cmd << SPE_HDR_CMD_ID_SHIFT) |
  1107. BNX2X_HW_CID(cp, cid)));
  1108. type_16 = (type << SPE_HDR_CONN_TYPE_SHIFT) & SPE_HDR_CONN_TYPE;
  1109. type_16 |= (cp->pfid << SPE_HDR_FUNCTION_ID_SHIFT) &
  1110. SPE_HDR_FUNCTION_ID;
  1111. kwqe.hdr.type = cpu_to_le16(type_16);
  1112. kwqe.hdr.reserved1 = 0;
  1113. kwqe.data.phy_address.lo = cpu_to_le32(l5_data->phy_address.lo);
  1114. kwqe.data.phy_address.hi = cpu_to_le32(l5_data->phy_address.hi);
  1115. kwq[0] = (struct kwqe_16 *) &kwqe;
  1116. spin_lock_bh(&cp->cnic_ulp_lock);
  1117. ret = cp->ethdev->drv_submit_kwqes_16(dev->netdev, kwq, 1);
  1118. spin_unlock_bh(&cp->cnic_ulp_lock);
  1119. if (ret == 1)
  1120. return 0;
  1121. return ret;
  1122. }
  1123. static void cnic_reply_bnx2x_kcqes(struct cnic_dev *dev, int ulp_type,
  1124. struct kcqe *cqes[], u32 num_cqes)
  1125. {
  1126. struct cnic_local *cp = dev->cnic_priv;
  1127. struct cnic_ulp_ops *ulp_ops;
  1128. rcu_read_lock();
  1129. ulp_ops = rcu_dereference(cp->ulp_ops[ulp_type]);
  1130. if (likely(ulp_ops)) {
  1131. ulp_ops->indicate_kcqes(cp->ulp_handle[ulp_type],
  1132. cqes, num_cqes);
  1133. }
  1134. rcu_read_unlock();
  1135. }
  1136. static int cnic_bnx2x_iscsi_init1(struct cnic_dev *dev, struct kwqe *kwqe)
  1137. {
  1138. struct cnic_local *cp = dev->cnic_priv;
  1139. struct iscsi_kwqe_init1 *req1 = (struct iscsi_kwqe_init1 *) kwqe;
  1140. int hq_bds, pages;
  1141. u32 pfid = cp->pfid;
  1142. cp->num_iscsi_tasks = req1->num_tasks_per_conn;
  1143. cp->num_ccells = req1->num_ccells_per_conn;
  1144. cp->task_array_size = BNX2X_ISCSI_TASK_CONTEXT_SIZE *
  1145. cp->num_iscsi_tasks;
  1146. cp->r2tq_size = cp->num_iscsi_tasks * BNX2X_ISCSI_MAX_PENDING_R2TS *
  1147. BNX2X_ISCSI_R2TQE_SIZE;
  1148. cp->hq_size = cp->num_ccells * BNX2X_ISCSI_HQ_BD_SIZE;
  1149. pages = PAGE_ALIGN(cp->hq_size) / PAGE_SIZE;
  1150. hq_bds = pages * (PAGE_SIZE / BNX2X_ISCSI_HQ_BD_SIZE);
  1151. cp->num_cqs = req1->num_cqs;
  1152. if (!dev->max_iscsi_conn)
  1153. return 0;
  1154. /* init Tstorm RAM */
  1155. CNIC_WR16(dev, BAR_TSTRORM_INTMEM + TSTORM_ISCSI_RQ_SIZE_OFFSET(pfid),
  1156. req1->rq_num_wqes);
  1157. CNIC_WR16(dev, BAR_TSTRORM_INTMEM + TSTORM_ISCSI_PAGE_SIZE_OFFSET(pfid),
  1158. PAGE_SIZE);
  1159. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1160. TSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfid), PAGE_SHIFT);
  1161. CNIC_WR16(dev, BAR_TSTRORM_INTMEM +
  1162. TSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfid),
  1163. req1->num_tasks_per_conn);
  1164. /* init Ustorm RAM */
  1165. CNIC_WR16(dev, BAR_USTRORM_INTMEM +
  1166. USTORM_ISCSI_RQ_BUFFER_SIZE_OFFSET(pfid),
  1167. req1->rq_buffer_size);
  1168. CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_PAGE_SIZE_OFFSET(pfid),
  1169. PAGE_SIZE);
  1170. CNIC_WR8(dev, BAR_USTRORM_INTMEM +
  1171. USTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfid), PAGE_SHIFT);
  1172. CNIC_WR16(dev, BAR_USTRORM_INTMEM +
  1173. USTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfid),
  1174. req1->num_tasks_per_conn);
  1175. CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_RQ_SIZE_OFFSET(pfid),
  1176. req1->rq_num_wqes);
  1177. CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_CQ_SIZE_OFFSET(pfid),
  1178. req1->cq_num_wqes);
  1179. CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_R2TQ_SIZE_OFFSET(pfid),
  1180. cp->num_iscsi_tasks * BNX2X_ISCSI_MAX_PENDING_R2TS);
  1181. /* init Xstorm RAM */
  1182. CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_PAGE_SIZE_OFFSET(pfid),
  1183. PAGE_SIZE);
  1184. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1185. XSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfid), PAGE_SHIFT);
  1186. CNIC_WR16(dev, BAR_XSTRORM_INTMEM +
  1187. XSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfid),
  1188. req1->num_tasks_per_conn);
  1189. CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_HQ_SIZE_OFFSET(pfid),
  1190. hq_bds);
  1191. CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_SQ_SIZE_OFFSET(pfid),
  1192. req1->num_tasks_per_conn);
  1193. CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_R2TQ_SIZE_OFFSET(pfid),
  1194. cp->num_iscsi_tasks * BNX2X_ISCSI_MAX_PENDING_R2TS);
  1195. /* init Cstorm RAM */
  1196. CNIC_WR16(dev, BAR_CSTRORM_INTMEM + CSTORM_ISCSI_PAGE_SIZE_OFFSET(pfid),
  1197. PAGE_SIZE);
  1198. CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
  1199. CSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfid), PAGE_SHIFT);
  1200. CNIC_WR16(dev, BAR_CSTRORM_INTMEM +
  1201. CSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfid),
  1202. req1->num_tasks_per_conn);
  1203. CNIC_WR16(dev, BAR_CSTRORM_INTMEM + CSTORM_ISCSI_CQ_SIZE_OFFSET(pfid),
  1204. req1->cq_num_wqes);
  1205. CNIC_WR16(dev, BAR_CSTRORM_INTMEM + CSTORM_ISCSI_HQ_SIZE_OFFSET(pfid),
  1206. hq_bds);
  1207. return 0;
  1208. }
  1209. static int cnic_bnx2x_iscsi_init2(struct cnic_dev *dev, struct kwqe *kwqe)
  1210. {
  1211. struct iscsi_kwqe_init2 *req2 = (struct iscsi_kwqe_init2 *) kwqe;
  1212. struct cnic_local *cp = dev->cnic_priv;
  1213. u32 pfid = cp->pfid;
  1214. struct iscsi_kcqe kcqe;
  1215. struct kcqe *cqes[1];
  1216. memset(&kcqe, 0, sizeof(kcqe));
  1217. if (!dev->max_iscsi_conn) {
  1218. kcqe.completion_status =
  1219. ISCSI_KCQE_COMPLETION_STATUS_ISCSI_NOT_SUPPORTED;
  1220. goto done;
  1221. }
  1222. CNIC_WR(dev, BAR_TSTRORM_INTMEM +
  1223. TSTORM_ISCSI_ERROR_BITMAP_OFFSET(pfid), req2->error_bit_map[0]);
  1224. CNIC_WR(dev, BAR_TSTRORM_INTMEM +
  1225. TSTORM_ISCSI_ERROR_BITMAP_OFFSET(pfid) + 4,
  1226. req2->error_bit_map[1]);
  1227. CNIC_WR16(dev, BAR_USTRORM_INTMEM +
  1228. USTORM_ISCSI_CQ_SQN_SIZE_OFFSET(pfid), req2->max_cq_sqn);
  1229. CNIC_WR(dev, BAR_USTRORM_INTMEM +
  1230. USTORM_ISCSI_ERROR_BITMAP_OFFSET(pfid), req2->error_bit_map[0]);
  1231. CNIC_WR(dev, BAR_USTRORM_INTMEM +
  1232. USTORM_ISCSI_ERROR_BITMAP_OFFSET(pfid) + 4,
  1233. req2->error_bit_map[1]);
  1234. CNIC_WR16(dev, BAR_CSTRORM_INTMEM +
  1235. CSTORM_ISCSI_CQ_SQN_SIZE_OFFSET(pfid), req2->max_cq_sqn);
  1236. kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_SUCCESS;
  1237. done:
  1238. kcqe.op_code = ISCSI_KCQE_OPCODE_INIT;
  1239. cqes[0] = (struct kcqe *) &kcqe;
  1240. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_ISCSI, cqes, 1);
  1241. return 0;
  1242. }
  1243. static void cnic_free_bnx2x_conn_resc(struct cnic_dev *dev, u32 l5_cid)
  1244. {
  1245. struct cnic_local *cp = dev->cnic_priv;
  1246. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1247. if (ctx->ulp_proto_id == CNIC_ULP_ISCSI) {
  1248. struct cnic_iscsi *iscsi = ctx->proto.iscsi;
  1249. cnic_free_dma(dev, &iscsi->hq_info);
  1250. cnic_free_dma(dev, &iscsi->r2tq_info);
  1251. cnic_free_dma(dev, &iscsi->task_array_info);
  1252. cnic_free_id(&cp->cid_tbl, ctx->cid);
  1253. } else {
  1254. cnic_free_id(&cp->fcoe_cid_tbl, ctx->cid);
  1255. }
  1256. ctx->cid = 0;
  1257. }
  1258. static int cnic_alloc_bnx2x_conn_resc(struct cnic_dev *dev, u32 l5_cid)
  1259. {
  1260. u32 cid;
  1261. int ret, pages;
  1262. struct cnic_local *cp = dev->cnic_priv;
  1263. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1264. struct cnic_iscsi *iscsi = ctx->proto.iscsi;
  1265. if (ctx->ulp_proto_id == CNIC_ULP_FCOE) {
  1266. cid = cnic_alloc_new_id(&cp->fcoe_cid_tbl);
  1267. if (cid == -1) {
  1268. ret = -ENOMEM;
  1269. goto error;
  1270. }
  1271. ctx->cid = cid;
  1272. return 0;
  1273. }
  1274. cid = cnic_alloc_new_id(&cp->cid_tbl);
  1275. if (cid == -1) {
  1276. ret = -ENOMEM;
  1277. goto error;
  1278. }
  1279. ctx->cid = cid;
  1280. pages = PAGE_ALIGN(cp->task_array_size) / PAGE_SIZE;
  1281. ret = cnic_alloc_dma(dev, &iscsi->task_array_info, pages, 1);
  1282. if (ret)
  1283. goto error;
  1284. pages = PAGE_ALIGN(cp->r2tq_size) / PAGE_SIZE;
  1285. ret = cnic_alloc_dma(dev, &iscsi->r2tq_info, pages, 1);
  1286. if (ret)
  1287. goto error;
  1288. pages = PAGE_ALIGN(cp->hq_size) / PAGE_SIZE;
  1289. ret = cnic_alloc_dma(dev, &iscsi->hq_info, pages, 1);
  1290. if (ret)
  1291. goto error;
  1292. return 0;
  1293. error:
  1294. cnic_free_bnx2x_conn_resc(dev, l5_cid);
  1295. return ret;
  1296. }
  1297. static void *cnic_get_bnx2x_ctx(struct cnic_dev *dev, u32 cid, int init,
  1298. struct regpair *ctx_addr)
  1299. {
  1300. struct cnic_local *cp = dev->cnic_priv;
  1301. struct cnic_eth_dev *ethdev = cp->ethdev;
  1302. int blk = (cid - ethdev->starting_cid) / cp->cids_per_blk;
  1303. int off = (cid - ethdev->starting_cid) % cp->cids_per_blk;
  1304. unsigned long align_off = 0;
  1305. dma_addr_t ctx_map;
  1306. void *ctx;
  1307. if (cp->ctx_align) {
  1308. unsigned long mask = cp->ctx_align - 1;
  1309. if (cp->ctx_arr[blk].mapping & mask)
  1310. align_off = cp->ctx_align -
  1311. (cp->ctx_arr[blk].mapping & mask);
  1312. }
  1313. ctx_map = cp->ctx_arr[blk].mapping + align_off +
  1314. (off * BNX2X_CONTEXT_MEM_SIZE);
  1315. ctx = cp->ctx_arr[blk].ctx + align_off +
  1316. (off * BNX2X_CONTEXT_MEM_SIZE);
  1317. if (init)
  1318. memset(ctx, 0, BNX2X_CONTEXT_MEM_SIZE);
  1319. ctx_addr->lo = ctx_map & 0xffffffff;
  1320. ctx_addr->hi = (u64) ctx_map >> 32;
  1321. return ctx;
  1322. }
  1323. static int cnic_setup_bnx2x_ctx(struct cnic_dev *dev, struct kwqe *wqes[],
  1324. u32 num)
  1325. {
  1326. struct cnic_local *cp = dev->cnic_priv;
  1327. struct iscsi_kwqe_conn_offload1 *req1 =
  1328. (struct iscsi_kwqe_conn_offload1 *) wqes[0];
  1329. struct iscsi_kwqe_conn_offload2 *req2 =
  1330. (struct iscsi_kwqe_conn_offload2 *) wqes[1];
  1331. struct iscsi_kwqe_conn_offload3 *req3;
  1332. struct cnic_context *ctx = &cp->ctx_tbl[req1->iscsi_conn_id];
  1333. struct cnic_iscsi *iscsi = ctx->proto.iscsi;
  1334. u32 cid = ctx->cid;
  1335. u32 hw_cid = BNX2X_HW_CID(cp, cid);
  1336. struct iscsi_context *ictx;
  1337. struct regpair context_addr;
  1338. int i, j, n = 2, n_max;
  1339. u8 port = CNIC_PORT(cp);
  1340. ctx->ctx_flags = 0;
  1341. if (!req2->num_additional_wqes)
  1342. return -EINVAL;
  1343. n_max = req2->num_additional_wqes + 2;
  1344. ictx = cnic_get_bnx2x_ctx(dev, cid, 1, &context_addr);
  1345. if (ictx == NULL)
  1346. return -ENOMEM;
  1347. req3 = (struct iscsi_kwqe_conn_offload3 *) wqes[n++];
  1348. ictx->xstorm_ag_context.hq_prod = 1;
  1349. ictx->xstorm_st_context.iscsi.first_burst_length =
  1350. ISCSI_DEF_FIRST_BURST_LEN;
  1351. ictx->xstorm_st_context.iscsi.max_send_pdu_length =
  1352. ISCSI_DEF_MAX_RECV_SEG_LEN;
  1353. ictx->xstorm_st_context.iscsi.sq_pbl_base.lo =
  1354. req1->sq_page_table_addr_lo;
  1355. ictx->xstorm_st_context.iscsi.sq_pbl_base.hi =
  1356. req1->sq_page_table_addr_hi;
  1357. ictx->xstorm_st_context.iscsi.sq_curr_pbe.lo = req2->sq_first_pte.hi;
  1358. ictx->xstorm_st_context.iscsi.sq_curr_pbe.hi = req2->sq_first_pte.lo;
  1359. ictx->xstorm_st_context.iscsi.hq_pbl_base.lo =
  1360. iscsi->hq_info.pgtbl_map & 0xffffffff;
  1361. ictx->xstorm_st_context.iscsi.hq_pbl_base.hi =
  1362. (u64) iscsi->hq_info.pgtbl_map >> 32;
  1363. ictx->xstorm_st_context.iscsi.hq_curr_pbe_base.lo =
  1364. iscsi->hq_info.pgtbl[0];
  1365. ictx->xstorm_st_context.iscsi.hq_curr_pbe_base.hi =
  1366. iscsi->hq_info.pgtbl[1];
  1367. ictx->xstorm_st_context.iscsi.r2tq_pbl_base.lo =
  1368. iscsi->r2tq_info.pgtbl_map & 0xffffffff;
  1369. ictx->xstorm_st_context.iscsi.r2tq_pbl_base.hi =
  1370. (u64) iscsi->r2tq_info.pgtbl_map >> 32;
  1371. ictx->xstorm_st_context.iscsi.r2tq_curr_pbe_base.lo =
  1372. iscsi->r2tq_info.pgtbl[0];
  1373. ictx->xstorm_st_context.iscsi.r2tq_curr_pbe_base.hi =
  1374. iscsi->r2tq_info.pgtbl[1];
  1375. ictx->xstorm_st_context.iscsi.task_pbl_base.lo =
  1376. iscsi->task_array_info.pgtbl_map & 0xffffffff;
  1377. ictx->xstorm_st_context.iscsi.task_pbl_base.hi =
  1378. (u64) iscsi->task_array_info.pgtbl_map >> 32;
  1379. ictx->xstorm_st_context.iscsi.task_pbl_cache_idx =
  1380. BNX2X_ISCSI_PBL_NOT_CACHED;
  1381. ictx->xstorm_st_context.iscsi.flags.flags |=
  1382. XSTORM_ISCSI_CONTEXT_FLAGS_B_IMMEDIATE_DATA;
  1383. ictx->xstorm_st_context.iscsi.flags.flags |=
  1384. XSTORM_ISCSI_CONTEXT_FLAGS_B_INITIAL_R2T;
  1385. ictx->xstorm_st_context.common.ethernet.reserved_vlan_type =
  1386. ETH_P_8021Q;
  1387. if (BNX2X_CHIP_IS_E2_PLUS(cp->chip_id) &&
  1388. cp->port_mode == CHIP_2_PORT_MODE) {
  1389. port = 0;
  1390. }
  1391. ictx->xstorm_st_context.common.flags =
  1392. 1 << XSTORM_COMMON_CONTEXT_SECTION_PHYSQ_INITIALIZED_SHIFT;
  1393. ictx->xstorm_st_context.common.flags =
  1394. port << XSTORM_COMMON_CONTEXT_SECTION_PBF_PORT_SHIFT;
  1395. ictx->tstorm_st_context.iscsi.hdr_bytes_2_fetch = ISCSI_HEADER_SIZE;
  1396. /* TSTORM requires the base address of RQ DB & not PTE */
  1397. ictx->tstorm_st_context.iscsi.rq_db_phy_addr.lo =
  1398. req2->rq_page_table_addr_lo & PAGE_MASK;
  1399. ictx->tstorm_st_context.iscsi.rq_db_phy_addr.hi =
  1400. req2->rq_page_table_addr_hi;
  1401. ictx->tstorm_st_context.iscsi.iscsi_conn_id = req1->iscsi_conn_id;
  1402. ictx->tstorm_st_context.tcp.cwnd = 0x5A8;
  1403. ictx->tstorm_st_context.tcp.flags2 |=
  1404. TSTORM_TCP_ST_CONTEXT_SECTION_DA_EN;
  1405. ictx->tstorm_st_context.tcp.ooo_support_mode =
  1406. TCP_TSTORM_OOO_DROP_AND_PROC_ACK;
  1407. ictx->timers_context.flags |= TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG;
  1408. ictx->ustorm_st_context.ring.rq.pbl_base.lo =
  1409. req2->rq_page_table_addr_lo;
  1410. ictx->ustorm_st_context.ring.rq.pbl_base.hi =
  1411. req2->rq_page_table_addr_hi;
  1412. ictx->ustorm_st_context.ring.rq.curr_pbe.lo = req3->qp_first_pte[0].hi;
  1413. ictx->ustorm_st_context.ring.rq.curr_pbe.hi = req3->qp_first_pte[0].lo;
  1414. ictx->ustorm_st_context.ring.r2tq.pbl_base.lo =
  1415. iscsi->r2tq_info.pgtbl_map & 0xffffffff;
  1416. ictx->ustorm_st_context.ring.r2tq.pbl_base.hi =
  1417. (u64) iscsi->r2tq_info.pgtbl_map >> 32;
  1418. ictx->ustorm_st_context.ring.r2tq.curr_pbe.lo =
  1419. iscsi->r2tq_info.pgtbl[0];
  1420. ictx->ustorm_st_context.ring.r2tq.curr_pbe.hi =
  1421. iscsi->r2tq_info.pgtbl[1];
  1422. ictx->ustorm_st_context.ring.cq_pbl_base.lo =
  1423. req1->cq_page_table_addr_lo;
  1424. ictx->ustorm_st_context.ring.cq_pbl_base.hi =
  1425. req1->cq_page_table_addr_hi;
  1426. ictx->ustorm_st_context.ring.cq[0].cq_sn = ISCSI_INITIAL_SN;
  1427. ictx->ustorm_st_context.ring.cq[0].curr_pbe.lo = req2->cq_first_pte.hi;
  1428. ictx->ustorm_st_context.ring.cq[0].curr_pbe.hi = req2->cq_first_pte.lo;
  1429. ictx->ustorm_st_context.task_pbe_cache_index =
  1430. BNX2X_ISCSI_PBL_NOT_CACHED;
  1431. ictx->ustorm_st_context.task_pdu_cache_index =
  1432. BNX2X_ISCSI_PDU_HEADER_NOT_CACHED;
  1433. for (i = 1, j = 1; i < cp->num_cqs; i++, j++) {
  1434. if (j == 3) {
  1435. if (n >= n_max)
  1436. break;
  1437. req3 = (struct iscsi_kwqe_conn_offload3 *) wqes[n++];
  1438. j = 0;
  1439. }
  1440. ictx->ustorm_st_context.ring.cq[i].cq_sn = ISCSI_INITIAL_SN;
  1441. ictx->ustorm_st_context.ring.cq[i].curr_pbe.lo =
  1442. req3->qp_first_pte[j].hi;
  1443. ictx->ustorm_st_context.ring.cq[i].curr_pbe.hi =
  1444. req3->qp_first_pte[j].lo;
  1445. }
  1446. ictx->ustorm_st_context.task_pbl_base.lo =
  1447. iscsi->task_array_info.pgtbl_map & 0xffffffff;
  1448. ictx->ustorm_st_context.task_pbl_base.hi =
  1449. (u64) iscsi->task_array_info.pgtbl_map >> 32;
  1450. ictx->ustorm_st_context.tce_phy_addr.lo =
  1451. iscsi->task_array_info.pgtbl[0];
  1452. ictx->ustorm_st_context.tce_phy_addr.hi =
  1453. iscsi->task_array_info.pgtbl[1];
  1454. ictx->ustorm_st_context.iscsi_conn_id = req1->iscsi_conn_id;
  1455. ictx->ustorm_st_context.num_cqs = cp->num_cqs;
  1456. ictx->ustorm_st_context.negotiated_rx |= ISCSI_DEF_MAX_RECV_SEG_LEN;
  1457. ictx->ustorm_st_context.negotiated_rx_and_flags |=
  1458. ISCSI_DEF_MAX_BURST_LEN;
  1459. ictx->ustorm_st_context.negotiated_rx |=
  1460. ISCSI_DEFAULT_MAX_OUTSTANDING_R2T <<
  1461. USTORM_ISCSI_ST_CONTEXT_MAX_OUTSTANDING_R2TS_SHIFT;
  1462. ictx->cstorm_st_context.hq_pbl_base.lo =
  1463. iscsi->hq_info.pgtbl_map & 0xffffffff;
  1464. ictx->cstorm_st_context.hq_pbl_base.hi =
  1465. (u64) iscsi->hq_info.pgtbl_map >> 32;
  1466. ictx->cstorm_st_context.hq_curr_pbe.lo = iscsi->hq_info.pgtbl[0];
  1467. ictx->cstorm_st_context.hq_curr_pbe.hi = iscsi->hq_info.pgtbl[1];
  1468. ictx->cstorm_st_context.task_pbl_base.lo =
  1469. iscsi->task_array_info.pgtbl_map & 0xffffffff;
  1470. ictx->cstorm_st_context.task_pbl_base.hi =
  1471. (u64) iscsi->task_array_info.pgtbl_map >> 32;
  1472. /* CSTORM and USTORM initialization is different, CSTORM requires
  1473. * CQ DB base & not PTE addr */
  1474. ictx->cstorm_st_context.cq_db_base.lo =
  1475. req1->cq_page_table_addr_lo & PAGE_MASK;
  1476. ictx->cstorm_st_context.cq_db_base.hi = req1->cq_page_table_addr_hi;
  1477. ictx->cstorm_st_context.iscsi_conn_id = req1->iscsi_conn_id;
  1478. ictx->cstorm_st_context.cq_proc_en_bit_map = (1 << cp->num_cqs) - 1;
  1479. for (i = 0; i < cp->num_cqs; i++) {
  1480. ictx->cstorm_st_context.cq_c_prod_sqn_arr.sqn[i] =
  1481. ISCSI_INITIAL_SN;
  1482. ictx->cstorm_st_context.cq_c_sqn_2_notify_arr.sqn[i] =
  1483. ISCSI_INITIAL_SN;
  1484. }
  1485. ictx->xstorm_ag_context.cdu_reserved =
  1486. CDU_RSRVD_VALUE_TYPE_A(hw_cid, CDU_REGION_NUMBER_XCM_AG,
  1487. ISCSI_CONNECTION_TYPE);
  1488. ictx->ustorm_ag_context.cdu_usage =
  1489. CDU_RSRVD_VALUE_TYPE_A(hw_cid, CDU_REGION_NUMBER_UCM_AG,
  1490. ISCSI_CONNECTION_TYPE);
  1491. return 0;
  1492. }
  1493. static int cnic_bnx2x_iscsi_ofld1(struct cnic_dev *dev, struct kwqe *wqes[],
  1494. u32 num, int *work)
  1495. {
  1496. struct iscsi_kwqe_conn_offload1 *req1;
  1497. struct iscsi_kwqe_conn_offload2 *req2;
  1498. struct cnic_local *cp = dev->cnic_priv;
  1499. struct cnic_context *ctx;
  1500. struct iscsi_kcqe kcqe;
  1501. struct kcqe *cqes[1];
  1502. u32 l5_cid;
  1503. int ret = 0;
  1504. if (num < 2) {
  1505. *work = num;
  1506. return -EINVAL;
  1507. }
  1508. req1 = (struct iscsi_kwqe_conn_offload1 *) wqes[0];
  1509. req2 = (struct iscsi_kwqe_conn_offload2 *) wqes[1];
  1510. if ((num - 2) < req2->num_additional_wqes) {
  1511. *work = num;
  1512. return -EINVAL;
  1513. }
  1514. *work = 2 + req2->num_additional_wqes;
  1515. l5_cid = req1->iscsi_conn_id;
  1516. if (l5_cid >= MAX_ISCSI_TBL_SZ)
  1517. return -EINVAL;
  1518. memset(&kcqe, 0, sizeof(kcqe));
  1519. kcqe.op_code = ISCSI_KCQE_OPCODE_OFFLOAD_CONN;
  1520. kcqe.iscsi_conn_id = l5_cid;
  1521. kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAILURE;
  1522. ctx = &cp->ctx_tbl[l5_cid];
  1523. if (test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags)) {
  1524. kcqe.completion_status =
  1525. ISCSI_KCQE_COMPLETION_STATUS_CID_BUSY;
  1526. goto done;
  1527. }
  1528. if (atomic_inc_return(&cp->iscsi_conn) > dev->max_iscsi_conn) {
  1529. atomic_dec(&cp->iscsi_conn);
  1530. goto done;
  1531. }
  1532. ret = cnic_alloc_bnx2x_conn_resc(dev, l5_cid);
  1533. if (ret) {
  1534. atomic_dec(&cp->iscsi_conn);
  1535. ret = 0;
  1536. goto done;
  1537. }
  1538. ret = cnic_setup_bnx2x_ctx(dev, wqes, num);
  1539. if (ret < 0) {
  1540. cnic_free_bnx2x_conn_resc(dev, l5_cid);
  1541. atomic_dec(&cp->iscsi_conn);
  1542. goto done;
  1543. }
  1544. kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_SUCCESS;
  1545. kcqe.iscsi_conn_context_id = BNX2X_HW_CID(cp, cp->ctx_tbl[l5_cid].cid);
  1546. done:
  1547. cqes[0] = (struct kcqe *) &kcqe;
  1548. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_ISCSI, cqes, 1);
  1549. return 0;
  1550. }
  1551. static int cnic_bnx2x_iscsi_update(struct cnic_dev *dev, struct kwqe *kwqe)
  1552. {
  1553. struct cnic_local *cp = dev->cnic_priv;
  1554. struct iscsi_kwqe_conn_update *req =
  1555. (struct iscsi_kwqe_conn_update *) kwqe;
  1556. void *data;
  1557. union l5cm_specific_data l5_data;
  1558. u32 l5_cid, cid = BNX2X_SW_CID(req->context_id);
  1559. int ret;
  1560. if (cnic_get_l5_cid(cp, cid, &l5_cid) != 0)
  1561. return -EINVAL;
  1562. data = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
  1563. if (!data)
  1564. return -ENOMEM;
  1565. memcpy(data, kwqe, sizeof(struct kwqe));
  1566. ret = cnic_submit_kwqe_16(dev, ISCSI_RAMROD_CMD_ID_UPDATE_CONN,
  1567. req->context_id, ISCSI_CONNECTION_TYPE, &l5_data);
  1568. return ret;
  1569. }
  1570. static int cnic_bnx2x_destroy_ramrod(struct cnic_dev *dev, u32 l5_cid)
  1571. {
  1572. struct cnic_local *cp = dev->cnic_priv;
  1573. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1574. union l5cm_specific_data l5_data;
  1575. int ret;
  1576. u32 hw_cid;
  1577. init_waitqueue_head(&ctx->waitq);
  1578. ctx->wait_cond = 0;
  1579. memset(&l5_data, 0, sizeof(l5_data));
  1580. hw_cid = BNX2X_HW_CID(cp, ctx->cid);
  1581. ret = cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_COMMON_CFC_DEL,
  1582. hw_cid, NONE_CONNECTION_TYPE, &l5_data);
  1583. if (ret == 0) {
  1584. wait_event_timeout(ctx->waitq, ctx->wait_cond, CNIC_RAMROD_TMO);
  1585. if (unlikely(test_bit(CTX_FL_CID_ERROR, &ctx->ctx_flags)))
  1586. return -EBUSY;
  1587. }
  1588. return 0;
  1589. }
  1590. static int cnic_bnx2x_iscsi_destroy(struct cnic_dev *dev, struct kwqe *kwqe)
  1591. {
  1592. struct cnic_local *cp = dev->cnic_priv;
  1593. struct iscsi_kwqe_conn_destroy *req =
  1594. (struct iscsi_kwqe_conn_destroy *) kwqe;
  1595. u32 l5_cid = req->reserved0;
  1596. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1597. int ret = 0;
  1598. struct iscsi_kcqe kcqe;
  1599. struct kcqe *cqes[1];
  1600. if (!test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags))
  1601. goto skip_cfc_delete;
  1602. if (!time_after(jiffies, ctx->timestamp + (2 * HZ))) {
  1603. unsigned long delta = ctx->timestamp + (2 * HZ) - jiffies;
  1604. if (delta > (2 * HZ))
  1605. delta = 0;
  1606. set_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags);
  1607. queue_delayed_work(cnic_wq, &cp->delete_task, delta);
  1608. goto destroy_reply;
  1609. }
  1610. ret = cnic_bnx2x_destroy_ramrod(dev, l5_cid);
  1611. skip_cfc_delete:
  1612. cnic_free_bnx2x_conn_resc(dev, l5_cid);
  1613. if (!ret) {
  1614. atomic_dec(&cp->iscsi_conn);
  1615. clear_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags);
  1616. }
  1617. destroy_reply:
  1618. memset(&kcqe, 0, sizeof(kcqe));
  1619. kcqe.op_code = ISCSI_KCQE_OPCODE_DESTROY_CONN;
  1620. kcqe.iscsi_conn_id = l5_cid;
  1621. kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_SUCCESS;
  1622. kcqe.iscsi_conn_context_id = req->context_id;
  1623. cqes[0] = (struct kcqe *) &kcqe;
  1624. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_ISCSI, cqes, 1);
  1625. return 0;
  1626. }
  1627. static void cnic_init_storm_conn_bufs(struct cnic_dev *dev,
  1628. struct l4_kwq_connect_req1 *kwqe1,
  1629. struct l4_kwq_connect_req3 *kwqe3,
  1630. struct l5cm_active_conn_buffer *conn_buf)
  1631. {
  1632. struct l5cm_conn_addr_params *conn_addr = &conn_buf->conn_addr_buf;
  1633. struct l5cm_xstorm_conn_buffer *xstorm_buf =
  1634. &conn_buf->xstorm_conn_buffer;
  1635. struct l5cm_tstorm_conn_buffer *tstorm_buf =
  1636. &conn_buf->tstorm_conn_buffer;
  1637. struct regpair context_addr;
  1638. u32 cid = BNX2X_SW_CID(kwqe1->cid);
  1639. struct in6_addr src_ip, dst_ip;
  1640. int i;
  1641. u32 *addrp;
  1642. addrp = (u32 *) &conn_addr->local_ip_addr;
  1643. for (i = 0; i < 4; i++, addrp++)
  1644. src_ip.in6_u.u6_addr32[i] = cpu_to_be32(*addrp);
  1645. addrp = (u32 *) &conn_addr->remote_ip_addr;
  1646. for (i = 0; i < 4; i++, addrp++)
  1647. dst_ip.in6_u.u6_addr32[i] = cpu_to_be32(*addrp);
  1648. cnic_get_bnx2x_ctx(dev, cid, 0, &context_addr);
  1649. xstorm_buf->context_addr.hi = context_addr.hi;
  1650. xstorm_buf->context_addr.lo = context_addr.lo;
  1651. xstorm_buf->mss = 0xffff;
  1652. xstorm_buf->rcv_buf = kwqe3->rcv_buf;
  1653. if (kwqe1->tcp_flags & L4_KWQ_CONNECT_REQ1_NAGLE_ENABLE)
  1654. xstorm_buf->params |= L5CM_XSTORM_CONN_BUFFER_NAGLE_ENABLE;
  1655. xstorm_buf->pseudo_header_checksum =
  1656. swab16(~csum_ipv6_magic(&src_ip, &dst_ip, 0, IPPROTO_TCP, 0));
  1657. if (!(kwqe1->tcp_flags & L4_KWQ_CONNECT_REQ1_NO_DELAY_ACK))
  1658. tstorm_buf->params |=
  1659. L5CM_TSTORM_CONN_BUFFER_DELAYED_ACK_ENABLE;
  1660. if (kwqe3->ka_timeout) {
  1661. tstorm_buf->ka_enable = 1;
  1662. tstorm_buf->ka_timeout = kwqe3->ka_timeout;
  1663. tstorm_buf->ka_interval = kwqe3->ka_interval;
  1664. tstorm_buf->ka_max_probe_count = kwqe3->ka_max_probe_count;
  1665. }
  1666. tstorm_buf->max_rt_time = 0xffffffff;
  1667. }
  1668. static void cnic_init_bnx2x_mac(struct cnic_dev *dev)
  1669. {
  1670. struct cnic_local *cp = dev->cnic_priv;
  1671. u32 pfid = cp->pfid;
  1672. u8 *mac = dev->mac_addr;
  1673. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1674. XSTORM_ISCSI_LOCAL_MAC_ADDR0_OFFSET(pfid), mac[0]);
  1675. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1676. XSTORM_ISCSI_LOCAL_MAC_ADDR1_OFFSET(pfid), mac[1]);
  1677. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1678. XSTORM_ISCSI_LOCAL_MAC_ADDR2_OFFSET(pfid), mac[2]);
  1679. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1680. XSTORM_ISCSI_LOCAL_MAC_ADDR3_OFFSET(pfid), mac[3]);
  1681. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1682. XSTORM_ISCSI_LOCAL_MAC_ADDR4_OFFSET(pfid), mac[4]);
  1683. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1684. XSTORM_ISCSI_LOCAL_MAC_ADDR5_OFFSET(pfid), mac[5]);
  1685. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1686. TSTORM_ISCSI_TCP_VARS_LSB_LOCAL_MAC_ADDR_OFFSET(pfid), mac[5]);
  1687. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1688. TSTORM_ISCSI_TCP_VARS_LSB_LOCAL_MAC_ADDR_OFFSET(pfid) + 1,
  1689. mac[4]);
  1690. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1691. TSTORM_ISCSI_TCP_VARS_MID_LOCAL_MAC_ADDR_OFFSET(pfid), mac[3]);
  1692. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1693. TSTORM_ISCSI_TCP_VARS_MID_LOCAL_MAC_ADDR_OFFSET(pfid) + 1,
  1694. mac[2]);
  1695. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1696. TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(pfid), mac[1]);
  1697. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1698. TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(pfid) + 1,
  1699. mac[0]);
  1700. }
  1701. static void cnic_bnx2x_set_tcp_timestamp(struct cnic_dev *dev, int tcp_ts)
  1702. {
  1703. struct cnic_local *cp = dev->cnic_priv;
  1704. u8 xstorm_flags = XSTORM_L5CM_TCP_FLAGS_WND_SCL_EN;
  1705. u16 tstorm_flags = 0;
  1706. if (tcp_ts) {
  1707. xstorm_flags |= XSTORM_L5CM_TCP_FLAGS_TS_ENABLED;
  1708. tstorm_flags |= TSTORM_L5CM_TCP_FLAGS_TS_ENABLED;
  1709. }
  1710. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1711. XSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(cp->pfid), xstorm_flags);
  1712. CNIC_WR16(dev, BAR_TSTRORM_INTMEM +
  1713. TSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(cp->pfid), tstorm_flags);
  1714. }
  1715. static int cnic_bnx2x_connect(struct cnic_dev *dev, struct kwqe *wqes[],
  1716. u32 num, int *work)
  1717. {
  1718. struct cnic_local *cp = dev->cnic_priv;
  1719. struct l4_kwq_connect_req1 *kwqe1 =
  1720. (struct l4_kwq_connect_req1 *) wqes[0];
  1721. struct l4_kwq_connect_req3 *kwqe3;
  1722. struct l5cm_active_conn_buffer *conn_buf;
  1723. struct l5cm_conn_addr_params *conn_addr;
  1724. union l5cm_specific_data l5_data;
  1725. u32 l5_cid = kwqe1->pg_cid;
  1726. struct cnic_sock *csk = &cp->csk_tbl[l5_cid];
  1727. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1728. int ret;
  1729. if (num < 2) {
  1730. *work = num;
  1731. return -EINVAL;
  1732. }
  1733. if (kwqe1->conn_flags & L4_KWQ_CONNECT_REQ1_IP_V6)
  1734. *work = 3;
  1735. else
  1736. *work = 2;
  1737. if (num < *work) {
  1738. *work = num;
  1739. return -EINVAL;
  1740. }
  1741. if (sizeof(*conn_buf) > CNIC_KWQ16_DATA_SIZE) {
  1742. netdev_err(dev->netdev, "conn_buf size too big\n");
  1743. return -ENOMEM;
  1744. }
  1745. conn_buf = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
  1746. if (!conn_buf)
  1747. return -ENOMEM;
  1748. memset(conn_buf, 0, sizeof(*conn_buf));
  1749. conn_addr = &conn_buf->conn_addr_buf;
  1750. conn_addr->remote_addr_0 = csk->ha[0];
  1751. conn_addr->remote_addr_1 = csk->ha[1];
  1752. conn_addr->remote_addr_2 = csk->ha[2];
  1753. conn_addr->remote_addr_3 = csk->ha[3];
  1754. conn_addr->remote_addr_4 = csk->ha[4];
  1755. conn_addr->remote_addr_5 = csk->ha[5];
  1756. if (kwqe1->conn_flags & L4_KWQ_CONNECT_REQ1_IP_V6) {
  1757. struct l4_kwq_connect_req2 *kwqe2 =
  1758. (struct l4_kwq_connect_req2 *) wqes[1];
  1759. conn_addr->local_ip_addr.ip_addr_hi_hi = kwqe2->src_ip_v6_4;
  1760. conn_addr->local_ip_addr.ip_addr_hi_lo = kwqe2->src_ip_v6_3;
  1761. conn_addr->local_ip_addr.ip_addr_lo_hi = kwqe2->src_ip_v6_2;
  1762. conn_addr->remote_ip_addr.ip_addr_hi_hi = kwqe2->dst_ip_v6_4;
  1763. conn_addr->remote_ip_addr.ip_addr_hi_lo = kwqe2->dst_ip_v6_3;
  1764. conn_addr->remote_ip_addr.ip_addr_lo_hi = kwqe2->dst_ip_v6_2;
  1765. conn_addr->params |= L5CM_CONN_ADDR_PARAMS_IP_VERSION;
  1766. }
  1767. kwqe3 = (struct l4_kwq_connect_req3 *) wqes[*work - 1];
  1768. conn_addr->local_ip_addr.ip_addr_lo_lo = kwqe1->src_ip;
  1769. conn_addr->remote_ip_addr.ip_addr_lo_lo = kwqe1->dst_ip;
  1770. conn_addr->local_tcp_port = kwqe1->src_port;
  1771. conn_addr->remote_tcp_port = kwqe1->dst_port;
  1772. conn_addr->pmtu = kwqe3->pmtu;
  1773. cnic_init_storm_conn_bufs(dev, kwqe1, kwqe3, conn_buf);
  1774. CNIC_WR16(dev, BAR_XSTRORM_INTMEM +
  1775. XSTORM_ISCSI_LOCAL_VLAN_OFFSET(cp->pfid), csk->vlan_id);
  1776. cnic_bnx2x_set_tcp_timestamp(dev,
  1777. kwqe1->tcp_flags & L4_KWQ_CONNECT_REQ1_TIME_STAMP);
  1778. ret = cnic_submit_kwqe_16(dev, L5CM_RAMROD_CMD_ID_TCP_CONNECT,
  1779. kwqe1->cid, ISCSI_CONNECTION_TYPE, &l5_data);
  1780. if (!ret)
  1781. set_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags);
  1782. return ret;
  1783. }
  1784. static int cnic_bnx2x_close(struct cnic_dev *dev, struct kwqe *kwqe)
  1785. {
  1786. struct l4_kwq_close_req *req = (struct l4_kwq_close_req *) kwqe;
  1787. union l5cm_specific_data l5_data;
  1788. int ret;
  1789. memset(&l5_data, 0, sizeof(l5_data));
  1790. ret = cnic_submit_kwqe_16(dev, L5CM_RAMROD_CMD_ID_CLOSE,
  1791. req->cid, ISCSI_CONNECTION_TYPE, &l5_data);
  1792. return ret;
  1793. }
  1794. static int cnic_bnx2x_reset(struct cnic_dev *dev, struct kwqe *kwqe)
  1795. {
  1796. struct l4_kwq_reset_req *req = (struct l4_kwq_reset_req *) kwqe;
  1797. union l5cm_specific_data l5_data;
  1798. int ret;
  1799. memset(&l5_data, 0, sizeof(l5_data));
  1800. ret = cnic_submit_kwqe_16(dev, L5CM_RAMROD_CMD_ID_ABORT,
  1801. req->cid, ISCSI_CONNECTION_TYPE, &l5_data);
  1802. return ret;
  1803. }
  1804. static int cnic_bnx2x_offload_pg(struct cnic_dev *dev, struct kwqe *kwqe)
  1805. {
  1806. struct l4_kwq_offload_pg *req = (struct l4_kwq_offload_pg *) kwqe;
  1807. struct l4_kcq kcqe;
  1808. struct kcqe *cqes[1];
  1809. memset(&kcqe, 0, sizeof(kcqe));
  1810. kcqe.pg_host_opaque = req->host_opaque;
  1811. kcqe.pg_cid = req->host_opaque;
  1812. kcqe.op_code = L4_KCQE_OPCODE_VALUE_OFFLOAD_PG;
  1813. cqes[0] = (struct kcqe *) &kcqe;
  1814. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_L4, cqes, 1);
  1815. return 0;
  1816. }
  1817. static int cnic_bnx2x_update_pg(struct cnic_dev *dev, struct kwqe *kwqe)
  1818. {
  1819. struct l4_kwq_update_pg *req = (struct l4_kwq_update_pg *) kwqe;
  1820. struct l4_kcq kcqe;
  1821. struct kcqe *cqes[1];
  1822. memset(&kcqe, 0, sizeof(kcqe));
  1823. kcqe.pg_host_opaque = req->pg_host_opaque;
  1824. kcqe.pg_cid = req->pg_cid;
  1825. kcqe.op_code = L4_KCQE_OPCODE_VALUE_UPDATE_PG;
  1826. cqes[0] = (struct kcqe *) &kcqe;
  1827. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_L4, cqes, 1);
  1828. return 0;
  1829. }
  1830. static int cnic_bnx2x_fcoe_stat(struct cnic_dev *dev, struct kwqe *kwqe)
  1831. {
  1832. struct fcoe_kwqe_stat *req;
  1833. struct fcoe_stat_ramrod_params *fcoe_stat;
  1834. union l5cm_specific_data l5_data;
  1835. struct cnic_local *cp = dev->cnic_priv;
  1836. int ret;
  1837. u32 cid;
  1838. req = (struct fcoe_kwqe_stat *) kwqe;
  1839. cid = BNX2X_HW_CID(cp, cp->fcoe_init_cid);
  1840. fcoe_stat = cnic_get_kwqe_16_data(cp, BNX2X_FCOE_L5_CID_BASE, &l5_data);
  1841. if (!fcoe_stat)
  1842. return -ENOMEM;
  1843. memset(fcoe_stat, 0, sizeof(*fcoe_stat));
  1844. memcpy(&fcoe_stat->stat_kwqe, req, sizeof(*req));
  1845. ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_STAT_FUNC, cid,
  1846. FCOE_CONNECTION_TYPE, &l5_data);
  1847. return ret;
  1848. }
  1849. static int cnic_bnx2x_fcoe_init1(struct cnic_dev *dev, struct kwqe *wqes[],
  1850. u32 num, int *work)
  1851. {
  1852. int ret;
  1853. struct cnic_local *cp = dev->cnic_priv;
  1854. u32 cid;
  1855. struct fcoe_init_ramrod_params *fcoe_init;
  1856. struct fcoe_kwqe_init1 *req1;
  1857. struct fcoe_kwqe_init2 *req2;
  1858. struct fcoe_kwqe_init3 *req3;
  1859. union l5cm_specific_data l5_data;
  1860. if (num < 3) {
  1861. *work = num;
  1862. return -EINVAL;
  1863. }
  1864. req1 = (struct fcoe_kwqe_init1 *) wqes[0];
  1865. req2 = (struct fcoe_kwqe_init2 *) wqes[1];
  1866. req3 = (struct fcoe_kwqe_init3 *) wqes[2];
  1867. if (req2->hdr.op_code != FCOE_KWQE_OPCODE_INIT2) {
  1868. *work = 1;
  1869. return -EINVAL;
  1870. }
  1871. if (req3->hdr.op_code != FCOE_KWQE_OPCODE_INIT3) {
  1872. *work = 2;
  1873. return -EINVAL;
  1874. }
  1875. if (sizeof(*fcoe_init) > CNIC_KWQ16_DATA_SIZE) {
  1876. netdev_err(dev->netdev, "fcoe_init size too big\n");
  1877. return -ENOMEM;
  1878. }
  1879. fcoe_init = cnic_get_kwqe_16_data(cp, BNX2X_FCOE_L5_CID_BASE, &l5_data);
  1880. if (!fcoe_init)
  1881. return -ENOMEM;
  1882. memset(fcoe_init, 0, sizeof(*fcoe_init));
  1883. memcpy(&fcoe_init->init_kwqe1, req1, sizeof(*req1));
  1884. memcpy(&fcoe_init->init_kwqe2, req2, sizeof(*req2));
  1885. memcpy(&fcoe_init->init_kwqe3, req3, sizeof(*req3));
  1886. fcoe_init->eq_pbl_base.lo = cp->kcq2.dma.pgtbl_map & 0xffffffff;
  1887. fcoe_init->eq_pbl_base.hi = (u64) cp->kcq2.dma.pgtbl_map >> 32;
  1888. fcoe_init->eq_pbl_size = cp->kcq2.dma.num_pages;
  1889. fcoe_init->sb_num = cp->status_blk_num;
  1890. fcoe_init->eq_prod = MAX_KCQ_IDX;
  1891. fcoe_init->sb_id = HC_INDEX_FCOE_EQ_CONS;
  1892. cp->kcq2.sw_prod_idx = 0;
  1893. cid = BNX2X_HW_CID(cp, cp->fcoe_init_cid);
  1894. ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_INIT_FUNC, cid,
  1895. FCOE_CONNECTION_TYPE, &l5_data);
  1896. *work = 3;
  1897. return ret;
  1898. }
  1899. static int cnic_bnx2x_fcoe_ofld1(struct cnic_dev *dev, struct kwqe *wqes[],
  1900. u32 num, int *work)
  1901. {
  1902. int ret = 0;
  1903. u32 cid = -1, l5_cid;
  1904. struct cnic_local *cp = dev->cnic_priv;
  1905. struct fcoe_kwqe_conn_offload1 *req1;
  1906. struct fcoe_kwqe_conn_offload2 *req2;
  1907. struct fcoe_kwqe_conn_offload3 *req3;
  1908. struct fcoe_kwqe_conn_offload4 *req4;
  1909. struct fcoe_conn_offload_ramrod_params *fcoe_offload;
  1910. struct cnic_context *ctx;
  1911. struct fcoe_context *fctx;
  1912. struct regpair ctx_addr;
  1913. union l5cm_specific_data l5_data;
  1914. struct fcoe_kcqe kcqe;
  1915. struct kcqe *cqes[1];
  1916. if (num < 4) {
  1917. *work = num;
  1918. return -EINVAL;
  1919. }
  1920. req1 = (struct fcoe_kwqe_conn_offload1 *) wqes[0];
  1921. req2 = (struct fcoe_kwqe_conn_offload2 *) wqes[1];
  1922. req3 = (struct fcoe_kwqe_conn_offload3 *) wqes[2];
  1923. req4 = (struct fcoe_kwqe_conn_offload4 *) wqes[3];
  1924. *work = 4;
  1925. l5_cid = req1->fcoe_conn_id;
  1926. if (l5_cid >= dev->max_fcoe_conn)
  1927. goto err_reply;
  1928. l5_cid += BNX2X_FCOE_L5_CID_BASE;
  1929. ctx = &cp->ctx_tbl[l5_cid];
  1930. if (test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags))
  1931. goto err_reply;
  1932. ret = cnic_alloc_bnx2x_conn_resc(dev, l5_cid);
  1933. if (ret) {
  1934. ret = 0;
  1935. goto err_reply;
  1936. }
  1937. cid = ctx->cid;
  1938. fctx = cnic_get_bnx2x_ctx(dev, cid, 1, &ctx_addr);
  1939. if (fctx) {
  1940. u32 hw_cid = BNX2X_HW_CID(cp, cid);
  1941. u32 val;
  1942. val = CDU_RSRVD_VALUE_TYPE_A(hw_cid, CDU_REGION_NUMBER_XCM_AG,
  1943. FCOE_CONNECTION_TYPE);
  1944. fctx->xstorm_ag_context.cdu_reserved = val;
  1945. val = CDU_RSRVD_VALUE_TYPE_A(hw_cid, CDU_REGION_NUMBER_UCM_AG,
  1946. FCOE_CONNECTION_TYPE);
  1947. fctx->ustorm_ag_context.cdu_usage = val;
  1948. }
  1949. if (sizeof(*fcoe_offload) > CNIC_KWQ16_DATA_SIZE) {
  1950. netdev_err(dev->netdev, "fcoe_offload size too big\n");
  1951. goto err_reply;
  1952. }
  1953. fcoe_offload = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
  1954. if (!fcoe_offload)
  1955. goto err_reply;
  1956. memset(fcoe_offload, 0, sizeof(*fcoe_offload));
  1957. memcpy(&fcoe_offload->offload_kwqe1, req1, sizeof(*req1));
  1958. memcpy(&fcoe_offload->offload_kwqe2, req2, sizeof(*req2));
  1959. memcpy(&fcoe_offload->offload_kwqe3, req3, sizeof(*req3));
  1960. memcpy(&fcoe_offload->offload_kwqe4, req4, sizeof(*req4));
  1961. cid = BNX2X_HW_CID(cp, cid);
  1962. ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_OFFLOAD_CONN, cid,
  1963. FCOE_CONNECTION_TYPE, &l5_data);
  1964. if (!ret)
  1965. set_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags);
  1966. return ret;
  1967. err_reply:
  1968. if (cid != -1)
  1969. cnic_free_bnx2x_conn_resc(dev, l5_cid);
  1970. memset(&kcqe, 0, sizeof(kcqe));
  1971. kcqe.op_code = FCOE_KCQE_OPCODE_OFFLOAD_CONN;
  1972. kcqe.fcoe_conn_id = req1->fcoe_conn_id;
  1973. kcqe.completion_status = FCOE_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAILURE;
  1974. cqes[0] = (struct kcqe *) &kcqe;
  1975. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_FCOE, cqes, 1);
  1976. return ret;
  1977. }
  1978. static int cnic_bnx2x_fcoe_enable(struct cnic_dev *dev, struct kwqe *kwqe)
  1979. {
  1980. struct fcoe_kwqe_conn_enable_disable *req;
  1981. struct fcoe_conn_enable_disable_ramrod_params *fcoe_enable;
  1982. union l5cm_specific_data l5_data;
  1983. int ret;
  1984. u32 cid, l5_cid;
  1985. struct cnic_local *cp = dev->cnic_priv;
  1986. req = (struct fcoe_kwqe_conn_enable_disable *) kwqe;
  1987. cid = req->context_id;
  1988. l5_cid = req->conn_id + BNX2X_FCOE_L5_CID_BASE;
  1989. if (sizeof(*fcoe_enable) > CNIC_KWQ16_DATA_SIZE) {
  1990. netdev_err(dev->netdev, "fcoe_enable size too big\n");
  1991. return -ENOMEM;
  1992. }
  1993. fcoe_enable = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
  1994. if (!fcoe_enable)
  1995. return -ENOMEM;
  1996. memset(fcoe_enable, 0, sizeof(*fcoe_enable));
  1997. memcpy(&fcoe_enable->enable_disable_kwqe, req, sizeof(*req));
  1998. ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_ENABLE_CONN, cid,
  1999. FCOE_CONNECTION_TYPE, &l5_data);
  2000. return ret;
  2001. }
  2002. static int cnic_bnx2x_fcoe_disable(struct cnic_dev *dev, struct kwqe *kwqe)
  2003. {
  2004. struct fcoe_kwqe_conn_enable_disable *req;
  2005. struct fcoe_conn_enable_disable_ramrod_params *fcoe_disable;
  2006. union l5cm_specific_data l5_data;
  2007. int ret;
  2008. u32 cid, l5_cid;
  2009. struct cnic_local *cp = dev->cnic_priv;
  2010. req = (struct fcoe_kwqe_conn_enable_disable *) kwqe;
  2011. cid = req->context_id;
  2012. l5_cid = req->conn_id;
  2013. if (l5_cid >= dev->max_fcoe_conn)
  2014. return -EINVAL;
  2015. l5_cid += BNX2X_FCOE_L5_CID_BASE;
  2016. if (sizeof(*fcoe_disable) > CNIC_KWQ16_DATA_SIZE) {
  2017. netdev_err(dev->netdev, "fcoe_disable size too big\n");
  2018. return -ENOMEM;
  2019. }
  2020. fcoe_disable = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
  2021. if (!fcoe_disable)
  2022. return -ENOMEM;
  2023. memset(fcoe_disable, 0, sizeof(*fcoe_disable));
  2024. memcpy(&fcoe_disable->enable_disable_kwqe, req, sizeof(*req));
  2025. ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_DISABLE_CONN, cid,
  2026. FCOE_CONNECTION_TYPE, &l5_data);
  2027. return ret;
  2028. }
  2029. static int cnic_bnx2x_fcoe_destroy(struct cnic_dev *dev, struct kwqe *kwqe)
  2030. {
  2031. struct fcoe_kwqe_conn_destroy *req;
  2032. union l5cm_specific_data l5_data;
  2033. int ret;
  2034. u32 cid, l5_cid;
  2035. struct cnic_local *cp = dev->cnic_priv;
  2036. struct cnic_context *ctx;
  2037. struct fcoe_kcqe kcqe;
  2038. struct kcqe *cqes[1];
  2039. req = (struct fcoe_kwqe_conn_destroy *) kwqe;
  2040. cid = req->context_id;
  2041. l5_cid = req->conn_id;
  2042. if (l5_cid >= dev->max_fcoe_conn)
  2043. return -EINVAL;
  2044. l5_cid += BNX2X_FCOE_L5_CID_BASE;
  2045. ctx = &cp->ctx_tbl[l5_cid];
  2046. init_waitqueue_head(&ctx->waitq);
  2047. ctx->wait_cond = 0;
  2048. memset(&kcqe, 0, sizeof(kcqe));
  2049. kcqe.completion_status = FCOE_KCQE_COMPLETION_STATUS_ERROR;
  2050. memset(&l5_data, 0, sizeof(l5_data));
  2051. ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_TERMINATE_CONN, cid,
  2052. FCOE_CONNECTION_TYPE, &l5_data);
  2053. if (ret == 0) {
  2054. wait_event_timeout(ctx->waitq, ctx->wait_cond, CNIC_RAMROD_TMO);
  2055. if (ctx->wait_cond)
  2056. kcqe.completion_status = 0;
  2057. }
  2058. set_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags);
  2059. queue_delayed_work(cnic_wq, &cp->delete_task, msecs_to_jiffies(2000));
  2060. kcqe.op_code = FCOE_KCQE_OPCODE_DESTROY_CONN;
  2061. kcqe.fcoe_conn_id = req->conn_id;
  2062. kcqe.fcoe_conn_context_id = cid;
  2063. cqes[0] = (struct kcqe *) &kcqe;
  2064. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_FCOE, cqes, 1);
  2065. return ret;
  2066. }
  2067. static void cnic_bnx2x_delete_wait(struct cnic_dev *dev, u32 start_cid)
  2068. {
  2069. struct cnic_local *cp = dev->cnic_priv;
  2070. u32 i;
  2071. for (i = start_cid; i < cp->max_cid_space; i++) {
  2072. struct cnic_context *ctx = &cp->ctx_tbl[i];
  2073. int j;
  2074. while (test_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags))
  2075. msleep(10);
  2076. for (j = 0; j < 5; j++) {
  2077. if (!test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags))
  2078. break;
  2079. msleep(20);
  2080. }
  2081. if (test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags))
  2082. netdev_warn(dev->netdev, "CID %x not deleted\n",
  2083. ctx->cid);
  2084. }
  2085. }
  2086. static int cnic_bnx2x_fcoe_fw_destroy(struct cnic_dev *dev, struct kwqe *kwqe)
  2087. {
  2088. struct fcoe_kwqe_destroy *req;
  2089. union l5cm_specific_data l5_data;
  2090. struct cnic_local *cp = dev->cnic_priv;
  2091. int ret;
  2092. u32 cid;
  2093. cnic_bnx2x_delete_wait(dev, MAX_ISCSI_TBL_SZ);
  2094. req = (struct fcoe_kwqe_destroy *) kwqe;
  2095. cid = BNX2X_HW_CID(cp, cp->fcoe_init_cid);
  2096. memset(&l5_data, 0, sizeof(l5_data));
  2097. ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_DESTROY_FUNC, cid,
  2098. FCOE_CONNECTION_TYPE, &l5_data);
  2099. return ret;
  2100. }
  2101. static void cnic_bnx2x_kwqe_err(struct cnic_dev *dev, struct kwqe *kwqe)
  2102. {
  2103. struct cnic_local *cp = dev->cnic_priv;
  2104. struct kcqe kcqe;
  2105. struct kcqe *cqes[1];
  2106. u32 cid;
  2107. u32 opcode = KWQE_OPCODE(kwqe->kwqe_op_flag);
  2108. u32 layer_code = kwqe->kwqe_op_flag & KWQE_LAYER_MASK;
  2109. u32 kcqe_op;
  2110. int ulp_type;
  2111. cid = kwqe->kwqe_info0;
  2112. memset(&kcqe, 0, sizeof(kcqe));
  2113. if (layer_code == KWQE_FLAGS_LAYER_MASK_L5_FCOE) {
  2114. u32 l5_cid = 0;
  2115. ulp_type = CNIC_ULP_FCOE;
  2116. if (opcode == FCOE_KWQE_OPCODE_DISABLE_CONN) {
  2117. struct fcoe_kwqe_conn_enable_disable *req;
  2118. req = (struct fcoe_kwqe_conn_enable_disable *) kwqe;
  2119. kcqe_op = FCOE_KCQE_OPCODE_DISABLE_CONN;
  2120. cid = req->context_id;
  2121. l5_cid = req->conn_id;
  2122. } else if (opcode == FCOE_KWQE_OPCODE_DESTROY) {
  2123. kcqe_op = FCOE_KCQE_OPCODE_DESTROY_FUNC;
  2124. } else {
  2125. return;
  2126. }
  2127. kcqe.kcqe_op_flag = kcqe_op << KCQE_FLAGS_OPCODE_SHIFT;
  2128. kcqe.kcqe_op_flag |= KCQE_FLAGS_LAYER_MASK_L5_FCOE;
  2129. kcqe.kcqe_info1 = FCOE_KCQE_COMPLETION_STATUS_PARITY_ERROR;
  2130. kcqe.kcqe_info2 = cid;
  2131. kcqe.kcqe_info0 = l5_cid;
  2132. } else if (layer_code == KWQE_FLAGS_LAYER_MASK_L5_ISCSI) {
  2133. ulp_type = CNIC_ULP_ISCSI;
  2134. if (opcode == ISCSI_KWQE_OPCODE_UPDATE_CONN)
  2135. cid = kwqe->kwqe_info1;
  2136. kcqe.kcqe_op_flag = (opcode + 0x10) << KCQE_FLAGS_OPCODE_SHIFT;
  2137. kcqe.kcqe_op_flag |= KCQE_FLAGS_LAYER_MASK_L5_ISCSI;
  2138. kcqe.kcqe_info1 = ISCSI_KCQE_COMPLETION_STATUS_PARITY_ERR;
  2139. kcqe.kcqe_info2 = cid;
  2140. cnic_get_l5_cid(cp, BNX2X_SW_CID(cid), &kcqe.kcqe_info0);
  2141. } else if (layer_code == KWQE_FLAGS_LAYER_MASK_L4) {
  2142. struct l4_kcq *l4kcqe = (struct l4_kcq *) &kcqe;
  2143. ulp_type = CNIC_ULP_L4;
  2144. if (opcode == L4_KWQE_OPCODE_VALUE_CONNECT1)
  2145. kcqe_op = L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE;
  2146. else if (opcode == L4_KWQE_OPCODE_VALUE_RESET)
  2147. kcqe_op = L4_KCQE_OPCODE_VALUE_RESET_COMP;
  2148. else if (opcode == L4_KWQE_OPCODE_VALUE_CLOSE)
  2149. kcqe_op = L4_KCQE_OPCODE_VALUE_CLOSE_COMP;
  2150. else
  2151. return;
  2152. kcqe.kcqe_op_flag = (kcqe_op << KCQE_FLAGS_OPCODE_SHIFT) |
  2153. KCQE_FLAGS_LAYER_MASK_L4;
  2154. l4kcqe->status = L4_KCQE_COMPLETION_STATUS_PARITY_ERROR;
  2155. l4kcqe->cid = cid;
  2156. cnic_get_l5_cid(cp, BNX2X_SW_CID(cid), &l4kcqe->conn_id);
  2157. } else {
  2158. return;
  2159. }
  2160. cqes[0] = &kcqe;
  2161. cnic_reply_bnx2x_kcqes(dev, ulp_type, cqes, 1);
  2162. }
  2163. static int cnic_submit_bnx2x_iscsi_kwqes(struct cnic_dev *dev,
  2164. struct kwqe *wqes[], u32 num_wqes)
  2165. {
  2166. int i, work, ret;
  2167. u32 opcode;
  2168. struct kwqe *kwqe;
  2169. if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
  2170. return -EAGAIN; /* bnx2 is down */
  2171. for (i = 0; i < num_wqes; ) {
  2172. kwqe = wqes[i];
  2173. opcode = KWQE_OPCODE(kwqe->kwqe_op_flag);
  2174. work = 1;
  2175. switch (opcode) {
  2176. case ISCSI_KWQE_OPCODE_INIT1:
  2177. ret = cnic_bnx2x_iscsi_init1(dev, kwqe);
  2178. break;
  2179. case ISCSI_KWQE_OPCODE_INIT2:
  2180. ret = cnic_bnx2x_iscsi_init2(dev, kwqe);
  2181. break;
  2182. case ISCSI_KWQE_OPCODE_OFFLOAD_CONN1:
  2183. ret = cnic_bnx2x_iscsi_ofld1(dev, &wqes[i],
  2184. num_wqes - i, &work);
  2185. break;
  2186. case ISCSI_KWQE_OPCODE_UPDATE_CONN:
  2187. ret = cnic_bnx2x_iscsi_update(dev, kwqe);
  2188. break;
  2189. case ISCSI_KWQE_OPCODE_DESTROY_CONN:
  2190. ret = cnic_bnx2x_iscsi_destroy(dev, kwqe);
  2191. break;
  2192. case L4_KWQE_OPCODE_VALUE_CONNECT1:
  2193. ret = cnic_bnx2x_connect(dev, &wqes[i], num_wqes - i,
  2194. &work);
  2195. break;
  2196. case L4_KWQE_OPCODE_VALUE_CLOSE:
  2197. ret = cnic_bnx2x_close(dev, kwqe);
  2198. break;
  2199. case L4_KWQE_OPCODE_VALUE_RESET:
  2200. ret = cnic_bnx2x_reset(dev, kwqe);
  2201. break;
  2202. case L4_KWQE_OPCODE_VALUE_OFFLOAD_PG:
  2203. ret = cnic_bnx2x_offload_pg(dev, kwqe);
  2204. break;
  2205. case L4_KWQE_OPCODE_VALUE_UPDATE_PG:
  2206. ret = cnic_bnx2x_update_pg(dev, kwqe);
  2207. break;
  2208. case L4_KWQE_OPCODE_VALUE_UPLOAD_PG:
  2209. ret = 0;
  2210. break;
  2211. default:
  2212. ret = 0;
  2213. netdev_err(dev->netdev, "Unknown type of KWQE(0x%x)\n",
  2214. opcode);
  2215. break;
  2216. }
  2217. if (ret < 0) {
  2218. netdev_err(dev->netdev, "KWQE(0x%x) failed\n",
  2219. opcode);
  2220. /* Possibly bnx2x parity error, send completion
  2221. * to ulp drivers with error code to speed up
  2222. * cleanup and reset recovery.
  2223. */
  2224. if (ret == -EIO || ret == -EAGAIN)
  2225. cnic_bnx2x_kwqe_err(dev, kwqe);
  2226. }
  2227. i += work;
  2228. }
  2229. return 0;
  2230. }
  2231. static int cnic_submit_bnx2x_fcoe_kwqes(struct cnic_dev *dev,
  2232. struct kwqe *wqes[], u32 num_wqes)
  2233. {
  2234. struct cnic_local *cp = dev->cnic_priv;
  2235. int i, work, ret;
  2236. u32 opcode;
  2237. struct kwqe *kwqe;
  2238. if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
  2239. return -EAGAIN; /* bnx2 is down */
  2240. if (!BNX2X_CHIP_IS_E2_PLUS(cp->chip_id))
  2241. return -EINVAL;
  2242. for (i = 0; i < num_wqes; ) {
  2243. kwqe = wqes[i];
  2244. opcode = KWQE_OPCODE(kwqe->kwqe_op_flag);
  2245. work = 1;
  2246. switch (opcode) {
  2247. case FCOE_KWQE_OPCODE_INIT1:
  2248. ret = cnic_bnx2x_fcoe_init1(dev, &wqes[i],
  2249. num_wqes - i, &work);
  2250. break;
  2251. case FCOE_KWQE_OPCODE_OFFLOAD_CONN1:
  2252. ret = cnic_bnx2x_fcoe_ofld1(dev, &wqes[i],
  2253. num_wqes - i, &work);
  2254. break;
  2255. case FCOE_KWQE_OPCODE_ENABLE_CONN:
  2256. ret = cnic_bnx2x_fcoe_enable(dev, kwqe);
  2257. break;
  2258. case FCOE_KWQE_OPCODE_DISABLE_CONN:
  2259. ret = cnic_bnx2x_fcoe_disable(dev, kwqe);
  2260. break;
  2261. case FCOE_KWQE_OPCODE_DESTROY_CONN:
  2262. ret = cnic_bnx2x_fcoe_destroy(dev, kwqe);
  2263. break;
  2264. case FCOE_KWQE_OPCODE_DESTROY:
  2265. ret = cnic_bnx2x_fcoe_fw_destroy(dev, kwqe);
  2266. break;
  2267. case FCOE_KWQE_OPCODE_STAT:
  2268. ret = cnic_bnx2x_fcoe_stat(dev, kwqe);
  2269. break;
  2270. default:
  2271. ret = 0;
  2272. netdev_err(dev->netdev, "Unknown type of KWQE(0x%x)\n",
  2273. opcode);
  2274. break;
  2275. }
  2276. if (ret < 0) {
  2277. netdev_err(dev->netdev, "KWQE(0x%x) failed\n",
  2278. opcode);
  2279. /* Possibly bnx2x parity error, send completion
  2280. * to ulp drivers with error code to speed up
  2281. * cleanup and reset recovery.
  2282. */
  2283. if (ret == -EIO || ret == -EAGAIN)
  2284. cnic_bnx2x_kwqe_err(dev, kwqe);
  2285. }
  2286. i += work;
  2287. }
  2288. return 0;
  2289. }
  2290. static int cnic_submit_bnx2x_kwqes(struct cnic_dev *dev, struct kwqe *wqes[],
  2291. u32 num_wqes)
  2292. {
  2293. int ret = -EINVAL;
  2294. u32 layer_code;
  2295. if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
  2296. return -EAGAIN; /* bnx2x is down */
  2297. if (!num_wqes)
  2298. return 0;
  2299. layer_code = wqes[0]->kwqe_op_flag & KWQE_LAYER_MASK;
  2300. switch (layer_code) {
  2301. case KWQE_FLAGS_LAYER_MASK_L5_ISCSI:
  2302. case KWQE_FLAGS_LAYER_MASK_L4:
  2303. case KWQE_FLAGS_LAYER_MASK_L2:
  2304. ret = cnic_submit_bnx2x_iscsi_kwqes(dev, wqes, num_wqes);
  2305. break;
  2306. case KWQE_FLAGS_LAYER_MASK_L5_FCOE:
  2307. ret = cnic_submit_bnx2x_fcoe_kwqes(dev, wqes, num_wqes);
  2308. break;
  2309. }
  2310. return ret;
  2311. }
  2312. static inline u32 cnic_get_kcqe_layer_mask(u32 opflag)
  2313. {
  2314. if (unlikely(KCQE_OPCODE(opflag) == FCOE_RAMROD_CMD_ID_TERMINATE_CONN))
  2315. return KCQE_FLAGS_LAYER_MASK_L4;
  2316. return opflag & KCQE_FLAGS_LAYER_MASK;
  2317. }
  2318. static void service_kcqes(struct cnic_dev *dev, int num_cqes)
  2319. {
  2320. struct cnic_local *cp = dev->cnic_priv;
  2321. int i, j, comp = 0;
  2322. i = 0;
  2323. j = 1;
  2324. while (num_cqes) {
  2325. struct cnic_ulp_ops *ulp_ops;
  2326. int ulp_type;
  2327. u32 kcqe_op_flag = cp->completed_kcq[i]->kcqe_op_flag;
  2328. u32 kcqe_layer = cnic_get_kcqe_layer_mask(kcqe_op_flag);
  2329. if (unlikely(kcqe_op_flag & KCQE_RAMROD_COMPLETION))
  2330. comp++;
  2331. while (j < num_cqes) {
  2332. u32 next_op = cp->completed_kcq[i + j]->kcqe_op_flag;
  2333. if (cnic_get_kcqe_layer_mask(next_op) != kcqe_layer)
  2334. break;
  2335. if (unlikely(next_op & KCQE_RAMROD_COMPLETION))
  2336. comp++;
  2337. j++;
  2338. }
  2339. if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L5_RDMA)
  2340. ulp_type = CNIC_ULP_RDMA;
  2341. else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L5_ISCSI)
  2342. ulp_type = CNIC_ULP_ISCSI;
  2343. else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L5_FCOE)
  2344. ulp_type = CNIC_ULP_FCOE;
  2345. else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L4)
  2346. ulp_type = CNIC_ULP_L4;
  2347. else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L2)
  2348. goto end;
  2349. else {
  2350. netdev_err(dev->netdev, "Unknown type of KCQE(0x%x)\n",
  2351. kcqe_op_flag);
  2352. goto end;
  2353. }
  2354. rcu_read_lock();
  2355. ulp_ops = rcu_dereference(cp->ulp_ops[ulp_type]);
  2356. if (likely(ulp_ops)) {
  2357. ulp_ops->indicate_kcqes(cp->ulp_handle[ulp_type],
  2358. cp->completed_kcq + i, j);
  2359. }
  2360. rcu_read_unlock();
  2361. end:
  2362. num_cqes -= j;
  2363. i += j;
  2364. j = 1;
  2365. }
  2366. if (unlikely(comp))
  2367. cnic_spq_completion(dev, DRV_CTL_RET_L5_SPQ_CREDIT_CMD, comp);
  2368. }
  2369. static int cnic_get_kcqes(struct cnic_dev *dev, struct kcq_info *info)
  2370. {
  2371. struct cnic_local *cp = dev->cnic_priv;
  2372. u16 i, ri, hw_prod, last;
  2373. struct kcqe *kcqe;
  2374. int kcqe_cnt = 0, last_cnt = 0;
  2375. i = ri = last = info->sw_prod_idx;
  2376. ri &= MAX_KCQ_IDX;
  2377. hw_prod = *info->hw_prod_idx_ptr;
  2378. hw_prod = info->hw_idx(hw_prod);
  2379. while ((i != hw_prod) && (kcqe_cnt < MAX_COMPLETED_KCQE)) {
  2380. kcqe = &info->kcq[KCQ_PG(ri)][KCQ_IDX(ri)];
  2381. cp->completed_kcq[kcqe_cnt++] = kcqe;
  2382. i = info->next_idx(i);
  2383. ri = i & MAX_KCQ_IDX;
  2384. if (likely(!(kcqe->kcqe_op_flag & KCQE_FLAGS_NEXT))) {
  2385. last_cnt = kcqe_cnt;
  2386. last = i;
  2387. }
  2388. }
  2389. info->sw_prod_idx = last;
  2390. return last_cnt;
  2391. }
  2392. static int cnic_l2_completion(struct cnic_local *cp)
  2393. {
  2394. u16 hw_cons, sw_cons;
  2395. struct cnic_uio_dev *udev = cp->udev;
  2396. union eth_rx_cqe *cqe, *cqe_ring = (union eth_rx_cqe *)
  2397. (udev->l2_ring + (2 * BCM_PAGE_SIZE));
  2398. u32 cmd;
  2399. int comp = 0;
  2400. if (!test_bit(CNIC_F_BNX2X_CLASS, &cp->dev->flags))
  2401. return 0;
  2402. hw_cons = *cp->rx_cons_ptr;
  2403. if ((hw_cons & BNX2X_MAX_RCQ_DESC_CNT) == BNX2X_MAX_RCQ_DESC_CNT)
  2404. hw_cons++;
  2405. sw_cons = cp->rx_cons;
  2406. while (sw_cons != hw_cons) {
  2407. u8 cqe_fp_flags;
  2408. cqe = &cqe_ring[sw_cons & BNX2X_MAX_RCQ_DESC_CNT];
  2409. cqe_fp_flags = cqe->fast_path_cqe.type_error_flags;
  2410. if (cqe_fp_flags & ETH_FAST_PATH_RX_CQE_TYPE) {
  2411. cmd = le32_to_cpu(cqe->ramrod_cqe.conn_and_cmd_data);
  2412. cmd >>= COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT;
  2413. if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP ||
  2414. cmd == RAMROD_CMD_ID_ETH_HALT)
  2415. comp++;
  2416. }
  2417. sw_cons = BNX2X_NEXT_RCQE(sw_cons);
  2418. }
  2419. return comp;
  2420. }
  2421. static void cnic_chk_pkt_rings(struct cnic_local *cp)
  2422. {
  2423. u16 rx_cons, tx_cons;
  2424. int comp = 0;
  2425. if (!test_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags))
  2426. return;
  2427. rx_cons = *cp->rx_cons_ptr;
  2428. tx_cons = *cp->tx_cons_ptr;
  2429. if (cp->tx_cons != tx_cons || cp->rx_cons != rx_cons) {
  2430. if (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags))
  2431. comp = cnic_l2_completion(cp);
  2432. cp->tx_cons = tx_cons;
  2433. cp->rx_cons = rx_cons;
  2434. if (cp->udev)
  2435. uio_event_notify(&cp->udev->cnic_uinfo);
  2436. }
  2437. if (comp)
  2438. clear_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags);
  2439. }
  2440. static u32 cnic_service_bnx2_queues(struct cnic_dev *dev)
  2441. {
  2442. struct cnic_local *cp = dev->cnic_priv;
  2443. u32 status_idx = (u16) *cp->kcq1.status_idx_ptr;
  2444. int kcqe_cnt;
  2445. /* status block index must be read before reading other fields */
  2446. rmb();
  2447. cp->kwq_con_idx = *cp->kwq_con_idx_ptr;
  2448. while ((kcqe_cnt = cnic_get_kcqes(dev, &cp->kcq1))) {
  2449. service_kcqes(dev, kcqe_cnt);
  2450. /* Tell compiler that status_blk fields can change. */
  2451. barrier();
  2452. status_idx = (u16) *cp->kcq1.status_idx_ptr;
  2453. /* status block index must be read first */
  2454. rmb();
  2455. cp->kwq_con_idx = *cp->kwq_con_idx_ptr;
  2456. }
  2457. CNIC_WR16(dev, cp->kcq1.io_addr, cp->kcq1.sw_prod_idx);
  2458. cnic_chk_pkt_rings(cp);
  2459. return status_idx;
  2460. }
  2461. static int cnic_service_bnx2(void *data, void *status_blk)
  2462. {
  2463. struct cnic_dev *dev = data;
  2464. if (unlikely(!test_bit(CNIC_F_CNIC_UP, &dev->flags))) {
  2465. struct status_block *sblk = status_blk;
  2466. return sblk->status_idx;
  2467. }
  2468. return cnic_service_bnx2_queues(dev);
  2469. }
  2470. static void cnic_service_bnx2_msix(unsigned long data)
  2471. {
  2472. struct cnic_dev *dev = (struct cnic_dev *) data;
  2473. struct cnic_local *cp = dev->cnic_priv;
  2474. cp->last_status_idx = cnic_service_bnx2_queues(dev);
  2475. CNIC_WR(dev, BNX2_PCICFG_INT_ACK_CMD, cp->int_num |
  2476. BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | cp->last_status_idx);
  2477. }
  2478. static void cnic_doirq(struct cnic_dev *dev)
  2479. {
  2480. struct cnic_local *cp = dev->cnic_priv;
  2481. if (likely(test_bit(CNIC_F_CNIC_UP, &dev->flags))) {
  2482. u16 prod = cp->kcq1.sw_prod_idx & MAX_KCQ_IDX;
  2483. prefetch(cp->status_blk.gen);
  2484. prefetch(&cp->kcq1.kcq[KCQ_PG(prod)][KCQ_IDX(prod)]);
  2485. tasklet_schedule(&cp->cnic_irq_task);
  2486. }
  2487. }
  2488. static irqreturn_t cnic_irq(int irq, void *dev_instance)
  2489. {
  2490. struct cnic_dev *dev = dev_instance;
  2491. struct cnic_local *cp = dev->cnic_priv;
  2492. if (cp->ack_int)
  2493. cp->ack_int(dev);
  2494. cnic_doirq(dev);
  2495. return IRQ_HANDLED;
  2496. }
  2497. static inline void cnic_ack_bnx2x_int(struct cnic_dev *dev, u8 id, u8 storm,
  2498. u16 index, u8 op, u8 update)
  2499. {
  2500. struct cnic_local *cp = dev->cnic_priv;
  2501. u32 hc_addr = (HC_REG_COMMAND_REG + CNIC_PORT(cp) * 32 +
  2502. COMMAND_REG_INT_ACK);
  2503. struct igu_ack_register igu_ack;
  2504. igu_ack.status_block_index = index;
  2505. igu_ack.sb_id_and_flags =
  2506. ((id << IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT) |
  2507. (storm << IGU_ACK_REGISTER_STORM_ID_SHIFT) |
  2508. (update << IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT) |
  2509. (op << IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT));
  2510. CNIC_WR(dev, hc_addr, (*(u32 *)&igu_ack));
  2511. }
  2512. static void cnic_ack_igu_sb(struct cnic_dev *dev, u8 igu_sb_id, u8 segment,
  2513. u16 index, u8 op, u8 update)
  2514. {
  2515. struct igu_regular cmd_data;
  2516. u32 igu_addr = BAR_IGU_INTMEM + (IGU_CMD_INT_ACK_BASE + igu_sb_id) * 8;
  2517. cmd_data.sb_id_and_flags =
  2518. (index << IGU_REGULAR_SB_INDEX_SHIFT) |
  2519. (segment << IGU_REGULAR_SEGMENT_ACCESS_SHIFT) |
  2520. (update << IGU_REGULAR_BUPDATE_SHIFT) |
  2521. (op << IGU_REGULAR_ENABLE_INT_SHIFT);
  2522. CNIC_WR(dev, igu_addr, cmd_data.sb_id_and_flags);
  2523. }
  2524. static void cnic_ack_bnx2x_msix(struct cnic_dev *dev)
  2525. {
  2526. struct cnic_local *cp = dev->cnic_priv;
  2527. cnic_ack_bnx2x_int(dev, cp->bnx2x_igu_sb_id, CSTORM_ID, 0,
  2528. IGU_INT_DISABLE, 0);
  2529. }
  2530. static void cnic_ack_bnx2x_e2_msix(struct cnic_dev *dev)
  2531. {
  2532. struct cnic_local *cp = dev->cnic_priv;
  2533. cnic_ack_igu_sb(dev, cp->bnx2x_igu_sb_id, IGU_SEG_ACCESS_DEF, 0,
  2534. IGU_INT_DISABLE, 0);
  2535. }
  2536. static u32 cnic_service_bnx2x_kcq(struct cnic_dev *dev, struct kcq_info *info)
  2537. {
  2538. u32 last_status = *info->status_idx_ptr;
  2539. int kcqe_cnt;
  2540. /* status block index must be read before reading the KCQ */
  2541. rmb();
  2542. while ((kcqe_cnt = cnic_get_kcqes(dev, info))) {
  2543. service_kcqes(dev, kcqe_cnt);
  2544. /* Tell compiler that sblk fields can change. */
  2545. barrier();
  2546. last_status = *info->status_idx_ptr;
  2547. /* status block index must be read before reading the KCQ */
  2548. rmb();
  2549. }
  2550. return last_status;
  2551. }
  2552. static void cnic_service_bnx2x_bh(unsigned long data)
  2553. {
  2554. struct cnic_dev *dev = (struct cnic_dev *) data;
  2555. struct cnic_local *cp = dev->cnic_priv;
  2556. u32 status_idx, new_status_idx;
  2557. if (unlikely(!test_bit(CNIC_F_CNIC_UP, &dev->flags)))
  2558. return;
  2559. while (1) {
  2560. status_idx = cnic_service_bnx2x_kcq(dev, &cp->kcq1);
  2561. CNIC_WR16(dev, cp->kcq1.io_addr,
  2562. cp->kcq1.sw_prod_idx + MAX_KCQ_IDX);
  2563. if (!BNX2X_CHIP_IS_E2_PLUS(cp->chip_id)) {
  2564. cnic_ack_bnx2x_int(dev, cp->bnx2x_igu_sb_id, USTORM_ID,
  2565. status_idx, IGU_INT_ENABLE, 1);
  2566. break;
  2567. }
  2568. new_status_idx = cnic_service_bnx2x_kcq(dev, &cp->kcq2);
  2569. if (new_status_idx != status_idx)
  2570. continue;
  2571. CNIC_WR16(dev, cp->kcq2.io_addr, cp->kcq2.sw_prod_idx +
  2572. MAX_KCQ_IDX);
  2573. cnic_ack_igu_sb(dev, cp->bnx2x_igu_sb_id, IGU_SEG_ACCESS_DEF,
  2574. status_idx, IGU_INT_ENABLE, 1);
  2575. break;
  2576. }
  2577. }
  2578. static int cnic_service_bnx2x(void *data, void *status_blk)
  2579. {
  2580. struct cnic_dev *dev = data;
  2581. struct cnic_local *cp = dev->cnic_priv;
  2582. if (!(cp->ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX))
  2583. cnic_doirq(dev);
  2584. cnic_chk_pkt_rings(cp);
  2585. return 0;
  2586. }
  2587. static void cnic_ulp_stop_one(struct cnic_local *cp, int if_type)
  2588. {
  2589. struct cnic_ulp_ops *ulp_ops;
  2590. if (if_type == CNIC_ULP_ISCSI)
  2591. cnic_send_nlmsg(cp, ISCSI_KEVENT_IF_DOWN, NULL);
  2592. mutex_lock(&cnic_lock);
  2593. ulp_ops = rcu_dereference_protected(cp->ulp_ops[if_type],
  2594. lockdep_is_held(&cnic_lock));
  2595. if (!ulp_ops) {
  2596. mutex_unlock(&cnic_lock);
  2597. return;
  2598. }
  2599. set_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
  2600. mutex_unlock(&cnic_lock);
  2601. if (test_and_clear_bit(ULP_F_START, &cp->ulp_flags[if_type]))
  2602. ulp_ops->cnic_stop(cp->ulp_handle[if_type]);
  2603. clear_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
  2604. }
  2605. static void cnic_ulp_stop(struct cnic_dev *dev)
  2606. {
  2607. struct cnic_local *cp = dev->cnic_priv;
  2608. int if_type;
  2609. for (if_type = 0; if_type < MAX_CNIC_ULP_TYPE; if_type++)
  2610. cnic_ulp_stop_one(cp, if_type);
  2611. }
  2612. static void cnic_ulp_start(struct cnic_dev *dev)
  2613. {
  2614. struct cnic_local *cp = dev->cnic_priv;
  2615. int if_type;
  2616. for (if_type = 0; if_type < MAX_CNIC_ULP_TYPE; if_type++) {
  2617. struct cnic_ulp_ops *ulp_ops;
  2618. mutex_lock(&cnic_lock);
  2619. ulp_ops = rcu_dereference_protected(cp->ulp_ops[if_type],
  2620. lockdep_is_held(&cnic_lock));
  2621. if (!ulp_ops || !ulp_ops->cnic_start) {
  2622. mutex_unlock(&cnic_lock);
  2623. continue;
  2624. }
  2625. set_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
  2626. mutex_unlock(&cnic_lock);
  2627. if (!test_and_set_bit(ULP_F_START, &cp->ulp_flags[if_type]))
  2628. ulp_ops->cnic_start(cp->ulp_handle[if_type]);
  2629. clear_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
  2630. }
  2631. }
  2632. static int cnic_copy_ulp_stats(struct cnic_dev *dev, int ulp_type)
  2633. {
  2634. struct cnic_local *cp = dev->cnic_priv;
  2635. struct cnic_ulp_ops *ulp_ops;
  2636. int rc;
  2637. mutex_lock(&cnic_lock);
  2638. ulp_ops = cnic_ulp_tbl_prot(ulp_type);
  2639. if (ulp_ops && ulp_ops->cnic_get_stats)
  2640. rc = ulp_ops->cnic_get_stats(cp->ulp_handle[ulp_type]);
  2641. else
  2642. rc = -ENODEV;
  2643. mutex_unlock(&cnic_lock);
  2644. return rc;
  2645. }
  2646. static int cnic_ctl(void *data, struct cnic_ctl_info *info)
  2647. {
  2648. struct cnic_dev *dev = data;
  2649. int ulp_type = CNIC_ULP_ISCSI;
  2650. switch (info->cmd) {
  2651. case CNIC_CTL_STOP_CMD:
  2652. cnic_hold(dev);
  2653. cnic_ulp_stop(dev);
  2654. cnic_stop_hw(dev);
  2655. cnic_put(dev);
  2656. break;
  2657. case CNIC_CTL_START_CMD:
  2658. cnic_hold(dev);
  2659. if (!cnic_start_hw(dev))
  2660. cnic_ulp_start(dev);
  2661. cnic_put(dev);
  2662. break;
  2663. case CNIC_CTL_STOP_ISCSI_CMD: {
  2664. struct cnic_local *cp = dev->cnic_priv;
  2665. set_bit(CNIC_LCL_FL_STOP_ISCSI, &cp->cnic_local_flags);
  2666. queue_delayed_work(cnic_wq, &cp->delete_task, 0);
  2667. break;
  2668. }
  2669. case CNIC_CTL_COMPLETION_CMD: {
  2670. struct cnic_ctl_completion *comp = &info->data.comp;
  2671. u32 cid = BNX2X_SW_CID(comp->cid);
  2672. u32 l5_cid;
  2673. struct cnic_local *cp = dev->cnic_priv;
  2674. if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
  2675. break;
  2676. if (cnic_get_l5_cid(cp, cid, &l5_cid) == 0) {
  2677. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  2678. if (unlikely(comp->error)) {
  2679. set_bit(CTX_FL_CID_ERROR, &ctx->ctx_flags);
  2680. netdev_err(dev->netdev,
  2681. "CID %x CFC delete comp error %x\n",
  2682. cid, comp->error);
  2683. }
  2684. ctx->wait_cond = 1;
  2685. wake_up(&ctx->waitq);
  2686. }
  2687. break;
  2688. }
  2689. case CNIC_CTL_FCOE_STATS_GET_CMD:
  2690. ulp_type = CNIC_ULP_FCOE;
  2691. /* fall through */
  2692. case CNIC_CTL_ISCSI_STATS_GET_CMD:
  2693. cnic_hold(dev);
  2694. cnic_copy_ulp_stats(dev, ulp_type);
  2695. cnic_put(dev);
  2696. break;
  2697. default:
  2698. return -EINVAL;
  2699. }
  2700. return 0;
  2701. }
  2702. static void cnic_ulp_init(struct cnic_dev *dev)
  2703. {
  2704. int i;
  2705. struct cnic_local *cp = dev->cnic_priv;
  2706. for (i = 0; i < MAX_CNIC_ULP_TYPE_EXT; i++) {
  2707. struct cnic_ulp_ops *ulp_ops;
  2708. mutex_lock(&cnic_lock);
  2709. ulp_ops = cnic_ulp_tbl_prot(i);
  2710. if (!ulp_ops || !ulp_ops->cnic_init) {
  2711. mutex_unlock(&cnic_lock);
  2712. continue;
  2713. }
  2714. ulp_get(ulp_ops);
  2715. mutex_unlock(&cnic_lock);
  2716. if (!test_and_set_bit(ULP_F_INIT, &cp->ulp_flags[i]))
  2717. ulp_ops->cnic_init(dev);
  2718. ulp_put(ulp_ops);
  2719. }
  2720. }
  2721. static void cnic_ulp_exit(struct cnic_dev *dev)
  2722. {
  2723. int i;
  2724. struct cnic_local *cp = dev->cnic_priv;
  2725. for (i = 0; i < MAX_CNIC_ULP_TYPE_EXT; i++) {
  2726. struct cnic_ulp_ops *ulp_ops;
  2727. mutex_lock(&cnic_lock);
  2728. ulp_ops = cnic_ulp_tbl_prot(i);
  2729. if (!ulp_ops || !ulp_ops->cnic_exit) {
  2730. mutex_unlock(&cnic_lock);
  2731. continue;
  2732. }
  2733. ulp_get(ulp_ops);
  2734. mutex_unlock(&cnic_lock);
  2735. if (test_and_clear_bit(ULP_F_INIT, &cp->ulp_flags[i]))
  2736. ulp_ops->cnic_exit(dev);
  2737. ulp_put(ulp_ops);
  2738. }
  2739. }
  2740. static int cnic_cm_offload_pg(struct cnic_sock *csk)
  2741. {
  2742. struct cnic_dev *dev = csk->dev;
  2743. struct l4_kwq_offload_pg *l4kwqe;
  2744. struct kwqe *wqes[1];
  2745. l4kwqe = (struct l4_kwq_offload_pg *) &csk->kwqe1;
  2746. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2747. wqes[0] = (struct kwqe *) l4kwqe;
  2748. l4kwqe->op_code = L4_KWQE_OPCODE_VALUE_OFFLOAD_PG;
  2749. l4kwqe->flags =
  2750. L4_LAYER_CODE << L4_KWQ_OFFLOAD_PG_LAYER_CODE_SHIFT;
  2751. l4kwqe->l2hdr_nbytes = ETH_HLEN;
  2752. l4kwqe->da0 = csk->ha[0];
  2753. l4kwqe->da1 = csk->ha[1];
  2754. l4kwqe->da2 = csk->ha[2];
  2755. l4kwqe->da3 = csk->ha[3];
  2756. l4kwqe->da4 = csk->ha[4];
  2757. l4kwqe->da5 = csk->ha[5];
  2758. l4kwqe->sa0 = dev->mac_addr[0];
  2759. l4kwqe->sa1 = dev->mac_addr[1];
  2760. l4kwqe->sa2 = dev->mac_addr[2];
  2761. l4kwqe->sa3 = dev->mac_addr[3];
  2762. l4kwqe->sa4 = dev->mac_addr[4];
  2763. l4kwqe->sa5 = dev->mac_addr[5];
  2764. l4kwqe->etype = ETH_P_IP;
  2765. l4kwqe->ipid_start = DEF_IPID_START;
  2766. l4kwqe->host_opaque = csk->l5_cid;
  2767. if (csk->vlan_id) {
  2768. l4kwqe->pg_flags |= L4_KWQ_OFFLOAD_PG_VLAN_TAGGING;
  2769. l4kwqe->vlan_tag = csk->vlan_id;
  2770. l4kwqe->l2hdr_nbytes += 4;
  2771. }
  2772. return dev->submit_kwqes(dev, wqes, 1);
  2773. }
  2774. static int cnic_cm_update_pg(struct cnic_sock *csk)
  2775. {
  2776. struct cnic_dev *dev = csk->dev;
  2777. struct l4_kwq_update_pg *l4kwqe;
  2778. struct kwqe *wqes[1];
  2779. l4kwqe = (struct l4_kwq_update_pg *) &csk->kwqe1;
  2780. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2781. wqes[0] = (struct kwqe *) l4kwqe;
  2782. l4kwqe->opcode = L4_KWQE_OPCODE_VALUE_UPDATE_PG;
  2783. l4kwqe->flags =
  2784. L4_LAYER_CODE << L4_KWQ_UPDATE_PG_LAYER_CODE_SHIFT;
  2785. l4kwqe->pg_cid = csk->pg_cid;
  2786. l4kwqe->da0 = csk->ha[0];
  2787. l4kwqe->da1 = csk->ha[1];
  2788. l4kwqe->da2 = csk->ha[2];
  2789. l4kwqe->da3 = csk->ha[3];
  2790. l4kwqe->da4 = csk->ha[4];
  2791. l4kwqe->da5 = csk->ha[5];
  2792. l4kwqe->pg_host_opaque = csk->l5_cid;
  2793. l4kwqe->pg_valids = L4_KWQ_UPDATE_PG_VALIDS_DA;
  2794. return dev->submit_kwqes(dev, wqes, 1);
  2795. }
  2796. static int cnic_cm_upload_pg(struct cnic_sock *csk)
  2797. {
  2798. struct cnic_dev *dev = csk->dev;
  2799. struct l4_kwq_upload *l4kwqe;
  2800. struct kwqe *wqes[1];
  2801. l4kwqe = (struct l4_kwq_upload *) &csk->kwqe1;
  2802. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2803. wqes[0] = (struct kwqe *) l4kwqe;
  2804. l4kwqe->opcode = L4_KWQE_OPCODE_VALUE_UPLOAD_PG;
  2805. l4kwqe->flags =
  2806. L4_LAYER_CODE << L4_KWQ_UPLOAD_LAYER_CODE_SHIFT;
  2807. l4kwqe->cid = csk->pg_cid;
  2808. return dev->submit_kwqes(dev, wqes, 1);
  2809. }
  2810. static int cnic_cm_conn_req(struct cnic_sock *csk)
  2811. {
  2812. struct cnic_dev *dev = csk->dev;
  2813. struct l4_kwq_connect_req1 *l4kwqe1;
  2814. struct l4_kwq_connect_req2 *l4kwqe2;
  2815. struct l4_kwq_connect_req3 *l4kwqe3;
  2816. struct kwqe *wqes[3];
  2817. u8 tcp_flags = 0;
  2818. int num_wqes = 2;
  2819. l4kwqe1 = (struct l4_kwq_connect_req1 *) &csk->kwqe1;
  2820. l4kwqe2 = (struct l4_kwq_connect_req2 *) &csk->kwqe2;
  2821. l4kwqe3 = (struct l4_kwq_connect_req3 *) &csk->kwqe3;
  2822. memset(l4kwqe1, 0, sizeof(*l4kwqe1));
  2823. memset(l4kwqe2, 0, sizeof(*l4kwqe2));
  2824. memset(l4kwqe3, 0, sizeof(*l4kwqe3));
  2825. l4kwqe3->op_code = L4_KWQE_OPCODE_VALUE_CONNECT3;
  2826. l4kwqe3->flags =
  2827. L4_LAYER_CODE << L4_KWQ_CONNECT_REQ3_LAYER_CODE_SHIFT;
  2828. l4kwqe3->ka_timeout = csk->ka_timeout;
  2829. l4kwqe3->ka_interval = csk->ka_interval;
  2830. l4kwqe3->ka_max_probe_count = csk->ka_max_probe_count;
  2831. l4kwqe3->tos = csk->tos;
  2832. l4kwqe3->ttl = csk->ttl;
  2833. l4kwqe3->snd_seq_scale = csk->snd_seq_scale;
  2834. l4kwqe3->pmtu = csk->mtu;
  2835. l4kwqe3->rcv_buf = csk->rcv_buf;
  2836. l4kwqe3->snd_buf = csk->snd_buf;
  2837. l4kwqe3->seed = csk->seed;
  2838. wqes[0] = (struct kwqe *) l4kwqe1;
  2839. if (test_bit(SK_F_IPV6, &csk->flags)) {
  2840. wqes[1] = (struct kwqe *) l4kwqe2;
  2841. wqes[2] = (struct kwqe *) l4kwqe3;
  2842. num_wqes = 3;
  2843. l4kwqe1->conn_flags = L4_KWQ_CONNECT_REQ1_IP_V6;
  2844. l4kwqe2->op_code = L4_KWQE_OPCODE_VALUE_CONNECT2;
  2845. l4kwqe2->flags =
  2846. L4_KWQ_CONNECT_REQ2_LINKED_WITH_NEXT |
  2847. L4_LAYER_CODE << L4_KWQ_CONNECT_REQ2_LAYER_CODE_SHIFT;
  2848. l4kwqe2->src_ip_v6_2 = be32_to_cpu(csk->src_ip[1]);
  2849. l4kwqe2->src_ip_v6_3 = be32_to_cpu(csk->src_ip[2]);
  2850. l4kwqe2->src_ip_v6_4 = be32_to_cpu(csk->src_ip[3]);
  2851. l4kwqe2->dst_ip_v6_2 = be32_to_cpu(csk->dst_ip[1]);
  2852. l4kwqe2->dst_ip_v6_3 = be32_to_cpu(csk->dst_ip[2]);
  2853. l4kwqe2->dst_ip_v6_4 = be32_to_cpu(csk->dst_ip[3]);
  2854. l4kwqe3->mss = l4kwqe3->pmtu - sizeof(struct ipv6hdr) -
  2855. sizeof(struct tcphdr);
  2856. } else {
  2857. wqes[1] = (struct kwqe *) l4kwqe3;
  2858. l4kwqe3->mss = l4kwqe3->pmtu - sizeof(struct iphdr) -
  2859. sizeof(struct tcphdr);
  2860. }
  2861. l4kwqe1->op_code = L4_KWQE_OPCODE_VALUE_CONNECT1;
  2862. l4kwqe1->flags =
  2863. (L4_LAYER_CODE << L4_KWQ_CONNECT_REQ1_LAYER_CODE_SHIFT) |
  2864. L4_KWQ_CONNECT_REQ3_LINKED_WITH_NEXT;
  2865. l4kwqe1->cid = csk->cid;
  2866. l4kwqe1->pg_cid = csk->pg_cid;
  2867. l4kwqe1->src_ip = be32_to_cpu(csk->src_ip[0]);
  2868. l4kwqe1->dst_ip = be32_to_cpu(csk->dst_ip[0]);
  2869. l4kwqe1->src_port = be16_to_cpu(csk->src_port);
  2870. l4kwqe1->dst_port = be16_to_cpu(csk->dst_port);
  2871. if (csk->tcp_flags & SK_TCP_NO_DELAY_ACK)
  2872. tcp_flags |= L4_KWQ_CONNECT_REQ1_NO_DELAY_ACK;
  2873. if (csk->tcp_flags & SK_TCP_KEEP_ALIVE)
  2874. tcp_flags |= L4_KWQ_CONNECT_REQ1_KEEP_ALIVE;
  2875. if (csk->tcp_flags & SK_TCP_NAGLE)
  2876. tcp_flags |= L4_KWQ_CONNECT_REQ1_NAGLE_ENABLE;
  2877. if (csk->tcp_flags & SK_TCP_TIMESTAMP)
  2878. tcp_flags |= L4_KWQ_CONNECT_REQ1_TIME_STAMP;
  2879. if (csk->tcp_flags & SK_TCP_SACK)
  2880. tcp_flags |= L4_KWQ_CONNECT_REQ1_SACK;
  2881. if (csk->tcp_flags & SK_TCP_SEG_SCALING)
  2882. tcp_flags |= L4_KWQ_CONNECT_REQ1_SEG_SCALING;
  2883. l4kwqe1->tcp_flags = tcp_flags;
  2884. return dev->submit_kwqes(dev, wqes, num_wqes);
  2885. }
  2886. static int cnic_cm_close_req(struct cnic_sock *csk)
  2887. {
  2888. struct cnic_dev *dev = csk->dev;
  2889. struct l4_kwq_close_req *l4kwqe;
  2890. struct kwqe *wqes[1];
  2891. l4kwqe = (struct l4_kwq_close_req *) &csk->kwqe2;
  2892. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2893. wqes[0] = (struct kwqe *) l4kwqe;
  2894. l4kwqe->op_code = L4_KWQE_OPCODE_VALUE_CLOSE;
  2895. l4kwqe->flags = L4_LAYER_CODE << L4_KWQ_CLOSE_REQ_LAYER_CODE_SHIFT;
  2896. l4kwqe->cid = csk->cid;
  2897. return dev->submit_kwqes(dev, wqes, 1);
  2898. }
  2899. static int cnic_cm_abort_req(struct cnic_sock *csk)
  2900. {
  2901. struct cnic_dev *dev = csk->dev;
  2902. struct l4_kwq_reset_req *l4kwqe;
  2903. struct kwqe *wqes[1];
  2904. l4kwqe = (struct l4_kwq_reset_req *) &csk->kwqe2;
  2905. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2906. wqes[0] = (struct kwqe *) l4kwqe;
  2907. l4kwqe->op_code = L4_KWQE_OPCODE_VALUE_RESET;
  2908. l4kwqe->flags = L4_LAYER_CODE << L4_KWQ_RESET_REQ_LAYER_CODE_SHIFT;
  2909. l4kwqe->cid = csk->cid;
  2910. return dev->submit_kwqes(dev, wqes, 1);
  2911. }
  2912. static int cnic_cm_create(struct cnic_dev *dev, int ulp_type, u32 cid,
  2913. u32 l5_cid, struct cnic_sock **csk, void *context)
  2914. {
  2915. struct cnic_local *cp = dev->cnic_priv;
  2916. struct cnic_sock *csk1;
  2917. if (l5_cid >= MAX_CM_SK_TBL_SZ)
  2918. return -EINVAL;
  2919. if (cp->ctx_tbl) {
  2920. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  2921. if (test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags))
  2922. return -EAGAIN;
  2923. }
  2924. csk1 = &cp->csk_tbl[l5_cid];
  2925. if (atomic_read(&csk1->ref_count))
  2926. return -EAGAIN;
  2927. if (test_and_set_bit(SK_F_INUSE, &csk1->flags))
  2928. return -EBUSY;
  2929. csk1->dev = dev;
  2930. csk1->cid = cid;
  2931. csk1->l5_cid = l5_cid;
  2932. csk1->ulp_type = ulp_type;
  2933. csk1->context = context;
  2934. csk1->ka_timeout = DEF_KA_TIMEOUT;
  2935. csk1->ka_interval = DEF_KA_INTERVAL;
  2936. csk1->ka_max_probe_count = DEF_KA_MAX_PROBE_COUNT;
  2937. csk1->tos = DEF_TOS;
  2938. csk1->ttl = DEF_TTL;
  2939. csk1->snd_seq_scale = DEF_SND_SEQ_SCALE;
  2940. csk1->rcv_buf = DEF_RCV_BUF;
  2941. csk1->snd_buf = DEF_SND_BUF;
  2942. csk1->seed = DEF_SEED;
  2943. *csk = csk1;
  2944. return 0;
  2945. }
  2946. static void cnic_cm_cleanup(struct cnic_sock *csk)
  2947. {
  2948. if (csk->src_port) {
  2949. struct cnic_dev *dev = csk->dev;
  2950. struct cnic_local *cp = dev->cnic_priv;
  2951. cnic_free_id(&cp->csk_port_tbl, be16_to_cpu(csk->src_port));
  2952. csk->src_port = 0;
  2953. }
  2954. }
  2955. static void cnic_close_conn(struct cnic_sock *csk)
  2956. {
  2957. if (test_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags)) {
  2958. cnic_cm_upload_pg(csk);
  2959. clear_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags);
  2960. }
  2961. cnic_cm_cleanup(csk);
  2962. }
  2963. static int cnic_cm_destroy(struct cnic_sock *csk)
  2964. {
  2965. if (!cnic_in_use(csk))
  2966. return -EINVAL;
  2967. csk_hold(csk);
  2968. clear_bit(SK_F_INUSE, &csk->flags);
  2969. smp_mb__after_clear_bit();
  2970. while (atomic_read(&csk->ref_count) != 1)
  2971. msleep(1);
  2972. cnic_cm_cleanup(csk);
  2973. csk->flags = 0;
  2974. csk_put(csk);
  2975. return 0;
  2976. }
  2977. static inline u16 cnic_get_vlan(struct net_device *dev,
  2978. struct net_device **vlan_dev)
  2979. {
  2980. if (dev->priv_flags & IFF_802_1Q_VLAN) {
  2981. *vlan_dev = vlan_dev_real_dev(dev);
  2982. return vlan_dev_vlan_id(dev);
  2983. }
  2984. *vlan_dev = dev;
  2985. return 0;
  2986. }
  2987. static int cnic_get_v4_route(struct sockaddr_in *dst_addr,
  2988. struct dst_entry **dst)
  2989. {
  2990. #if defined(CONFIG_INET)
  2991. struct rtable *rt;
  2992. rt = ip_route_output(&init_net, dst_addr->sin_addr.s_addr, 0, 0, 0);
  2993. if (!IS_ERR(rt)) {
  2994. *dst = &rt->dst;
  2995. return 0;
  2996. }
  2997. return PTR_ERR(rt);
  2998. #else
  2999. return -ENETUNREACH;
  3000. #endif
  3001. }
  3002. static int cnic_get_v6_route(struct sockaddr_in6 *dst_addr,
  3003. struct dst_entry **dst)
  3004. {
  3005. #if defined(CONFIG_IPV6) || (defined(CONFIG_IPV6_MODULE) && defined(MODULE))
  3006. struct flowi6 fl6;
  3007. memset(&fl6, 0, sizeof(fl6));
  3008. fl6.daddr = dst_addr->sin6_addr;
  3009. if (ipv6_addr_type(&fl6.daddr) & IPV6_ADDR_LINKLOCAL)
  3010. fl6.flowi6_oif = dst_addr->sin6_scope_id;
  3011. *dst = ip6_route_output(&init_net, NULL, &fl6);
  3012. if ((*dst)->error) {
  3013. dst_release(*dst);
  3014. *dst = NULL;
  3015. return -ENETUNREACH;
  3016. } else
  3017. return 0;
  3018. #endif
  3019. return -ENETUNREACH;
  3020. }
  3021. static struct cnic_dev *cnic_cm_select_dev(struct sockaddr_in *dst_addr,
  3022. int ulp_type)
  3023. {
  3024. struct cnic_dev *dev = NULL;
  3025. struct dst_entry *dst;
  3026. struct net_device *netdev = NULL;
  3027. int err = -ENETUNREACH;
  3028. if (dst_addr->sin_family == AF_INET)
  3029. err = cnic_get_v4_route(dst_addr, &dst);
  3030. else if (dst_addr->sin_family == AF_INET6) {
  3031. struct sockaddr_in6 *dst_addr6 =
  3032. (struct sockaddr_in6 *) dst_addr;
  3033. err = cnic_get_v6_route(dst_addr6, &dst);
  3034. } else
  3035. return NULL;
  3036. if (err)
  3037. return NULL;
  3038. if (!dst->dev)
  3039. goto done;
  3040. cnic_get_vlan(dst->dev, &netdev);
  3041. dev = cnic_from_netdev(netdev);
  3042. done:
  3043. dst_release(dst);
  3044. if (dev)
  3045. cnic_put(dev);
  3046. return dev;
  3047. }
  3048. static int cnic_resolve_addr(struct cnic_sock *csk, struct cnic_sockaddr *saddr)
  3049. {
  3050. struct cnic_dev *dev = csk->dev;
  3051. struct cnic_local *cp = dev->cnic_priv;
  3052. return cnic_send_nlmsg(cp, ISCSI_KEVENT_PATH_REQ, csk);
  3053. }
  3054. static int cnic_get_route(struct cnic_sock *csk, struct cnic_sockaddr *saddr)
  3055. {
  3056. struct cnic_dev *dev = csk->dev;
  3057. struct cnic_local *cp = dev->cnic_priv;
  3058. int is_v6, rc = 0;
  3059. struct dst_entry *dst = NULL;
  3060. struct net_device *realdev;
  3061. __be16 local_port;
  3062. u32 port_id;
  3063. if (saddr->local.v6.sin6_family == AF_INET6 &&
  3064. saddr->remote.v6.sin6_family == AF_INET6)
  3065. is_v6 = 1;
  3066. else if (saddr->local.v4.sin_family == AF_INET &&
  3067. saddr->remote.v4.sin_family == AF_INET)
  3068. is_v6 = 0;
  3069. else
  3070. return -EINVAL;
  3071. clear_bit(SK_F_IPV6, &csk->flags);
  3072. if (is_v6) {
  3073. set_bit(SK_F_IPV6, &csk->flags);
  3074. cnic_get_v6_route(&saddr->remote.v6, &dst);
  3075. memcpy(&csk->dst_ip[0], &saddr->remote.v6.sin6_addr,
  3076. sizeof(struct in6_addr));
  3077. csk->dst_port = saddr->remote.v6.sin6_port;
  3078. local_port = saddr->local.v6.sin6_port;
  3079. } else {
  3080. cnic_get_v4_route(&saddr->remote.v4, &dst);
  3081. csk->dst_ip[0] = saddr->remote.v4.sin_addr.s_addr;
  3082. csk->dst_port = saddr->remote.v4.sin_port;
  3083. local_port = saddr->local.v4.sin_port;
  3084. }
  3085. csk->vlan_id = 0;
  3086. csk->mtu = dev->netdev->mtu;
  3087. if (dst && dst->dev) {
  3088. u16 vlan = cnic_get_vlan(dst->dev, &realdev);
  3089. if (realdev == dev->netdev) {
  3090. csk->vlan_id = vlan;
  3091. csk->mtu = dst_mtu(dst);
  3092. }
  3093. }
  3094. port_id = be16_to_cpu(local_port);
  3095. if (port_id >= CNIC_LOCAL_PORT_MIN &&
  3096. port_id < CNIC_LOCAL_PORT_MAX) {
  3097. if (cnic_alloc_id(&cp->csk_port_tbl, port_id))
  3098. port_id = 0;
  3099. } else
  3100. port_id = 0;
  3101. if (!port_id) {
  3102. port_id = cnic_alloc_new_id(&cp->csk_port_tbl);
  3103. if (port_id == -1) {
  3104. rc = -ENOMEM;
  3105. goto err_out;
  3106. }
  3107. local_port = cpu_to_be16(port_id);
  3108. }
  3109. csk->src_port = local_port;
  3110. err_out:
  3111. dst_release(dst);
  3112. return rc;
  3113. }
  3114. static void cnic_init_csk_state(struct cnic_sock *csk)
  3115. {
  3116. csk->state = 0;
  3117. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  3118. clear_bit(SK_F_CLOSING, &csk->flags);
  3119. }
  3120. static int cnic_cm_connect(struct cnic_sock *csk, struct cnic_sockaddr *saddr)
  3121. {
  3122. struct cnic_local *cp = csk->dev->cnic_priv;
  3123. int err = 0;
  3124. if (cp->ethdev->drv_state & CNIC_DRV_STATE_NO_ISCSI)
  3125. return -EOPNOTSUPP;
  3126. if (!cnic_in_use(csk))
  3127. return -EINVAL;
  3128. if (test_and_set_bit(SK_F_CONNECT_START, &csk->flags))
  3129. return -EINVAL;
  3130. cnic_init_csk_state(csk);
  3131. err = cnic_get_route(csk, saddr);
  3132. if (err)
  3133. goto err_out;
  3134. err = cnic_resolve_addr(csk, saddr);
  3135. if (!err)
  3136. return 0;
  3137. err_out:
  3138. clear_bit(SK_F_CONNECT_START, &csk->flags);
  3139. return err;
  3140. }
  3141. static int cnic_cm_abort(struct cnic_sock *csk)
  3142. {
  3143. struct cnic_local *cp = csk->dev->cnic_priv;
  3144. u32 opcode = L4_KCQE_OPCODE_VALUE_RESET_COMP;
  3145. if (!cnic_in_use(csk))
  3146. return -EINVAL;
  3147. if (cnic_abort_prep(csk))
  3148. return cnic_cm_abort_req(csk);
  3149. /* Getting here means that we haven't started connect, or
  3150. * connect was not successful.
  3151. */
  3152. cp->close_conn(csk, opcode);
  3153. if (csk->state != opcode)
  3154. return -EALREADY;
  3155. return 0;
  3156. }
  3157. static int cnic_cm_close(struct cnic_sock *csk)
  3158. {
  3159. if (!cnic_in_use(csk))
  3160. return -EINVAL;
  3161. if (cnic_close_prep(csk)) {
  3162. csk->state = L4_KCQE_OPCODE_VALUE_CLOSE_COMP;
  3163. return cnic_cm_close_req(csk);
  3164. } else {
  3165. return -EALREADY;
  3166. }
  3167. return 0;
  3168. }
  3169. static void cnic_cm_upcall(struct cnic_local *cp, struct cnic_sock *csk,
  3170. u8 opcode)
  3171. {
  3172. struct cnic_ulp_ops *ulp_ops;
  3173. int ulp_type = csk->ulp_type;
  3174. rcu_read_lock();
  3175. ulp_ops = rcu_dereference(cp->ulp_ops[ulp_type]);
  3176. if (ulp_ops) {
  3177. if (opcode == L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE)
  3178. ulp_ops->cm_connect_complete(csk);
  3179. else if (opcode == L4_KCQE_OPCODE_VALUE_CLOSE_COMP)
  3180. ulp_ops->cm_close_complete(csk);
  3181. else if (opcode == L4_KCQE_OPCODE_VALUE_RESET_RECEIVED)
  3182. ulp_ops->cm_remote_abort(csk);
  3183. else if (opcode == L4_KCQE_OPCODE_VALUE_RESET_COMP)
  3184. ulp_ops->cm_abort_complete(csk);
  3185. else if (opcode == L4_KCQE_OPCODE_VALUE_CLOSE_RECEIVED)
  3186. ulp_ops->cm_remote_close(csk);
  3187. }
  3188. rcu_read_unlock();
  3189. }
  3190. static int cnic_cm_set_pg(struct cnic_sock *csk)
  3191. {
  3192. if (cnic_offld_prep(csk)) {
  3193. if (test_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags))
  3194. cnic_cm_update_pg(csk);
  3195. else
  3196. cnic_cm_offload_pg(csk);
  3197. }
  3198. return 0;
  3199. }
  3200. static void cnic_cm_process_offld_pg(struct cnic_dev *dev, struct l4_kcq *kcqe)
  3201. {
  3202. struct cnic_local *cp = dev->cnic_priv;
  3203. u32 l5_cid = kcqe->pg_host_opaque;
  3204. u8 opcode = kcqe->op_code;
  3205. struct cnic_sock *csk = &cp->csk_tbl[l5_cid];
  3206. csk_hold(csk);
  3207. if (!cnic_in_use(csk))
  3208. goto done;
  3209. if (opcode == L4_KCQE_OPCODE_VALUE_UPDATE_PG) {
  3210. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  3211. goto done;
  3212. }
  3213. /* Possible PG kcqe status: SUCCESS, OFFLOADED_PG, or CTX_ALLOC_FAIL */
  3214. if (kcqe->status == L4_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAIL) {
  3215. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  3216. cnic_cm_upcall(cp, csk,
  3217. L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE);
  3218. goto done;
  3219. }
  3220. csk->pg_cid = kcqe->pg_cid;
  3221. set_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags);
  3222. cnic_cm_conn_req(csk);
  3223. done:
  3224. csk_put(csk);
  3225. }
  3226. static void cnic_process_fcoe_term_conn(struct cnic_dev *dev, struct kcqe *kcqe)
  3227. {
  3228. struct cnic_local *cp = dev->cnic_priv;
  3229. struct fcoe_kcqe *fc_kcqe = (struct fcoe_kcqe *) kcqe;
  3230. u32 l5_cid = fc_kcqe->fcoe_conn_id + BNX2X_FCOE_L5_CID_BASE;
  3231. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  3232. ctx->timestamp = jiffies;
  3233. ctx->wait_cond = 1;
  3234. wake_up(&ctx->waitq);
  3235. }
  3236. static void cnic_cm_process_kcqe(struct cnic_dev *dev, struct kcqe *kcqe)
  3237. {
  3238. struct cnic_local *cp = dev->cnic_priv;
  3239. struct l4_kcq *l4kcqe = (struct l4_kcq *) kcqe;
  3240. u8 opcode = l4kcqe->op_code;
  3241. u32 l5_cid;
  3242. struct cnic_sock *csk;
  3243. if (opcode == FCOE_RAMROD_CMD_ID_TERMINATE_CONN) {
  3244. cnic_process_fcoe_term_conn(dev, kcqe);
  3245. return;
  3246. }
  3247. if (opcode == L4_KCQE_OPCODE_VALUE_OFFLOAD_PG ||
  3248. opcode == L4_KCQE_OPCODE_VALUE_UPDATE_PG) {
  3249. cnic_cm_process_offld_pg(dev, l4kcqe);
  3250. return;
  3251. }
  3252. l5_cid = l4kcqe->conn_id;
  3253. if (opcode & 0x80)
  3254. l5_cid = l4kcqe->cid;
  3255. if (l5_cid >= MAX_CM_SK_TBL_SZ)
  3256. return;
  3257. csk = &cp->csk_tbl[l5_cid];
  3258. csk_hold(csk);
  3259. if (!cnic_in_use(csk)) {
  3260. csk_put(csk);
  3261. return;
  3262. }
  3263. switch (opcode) {
  3264. case L5CM_RAMROD_CMD_ID_TCP_CONNECT:
  3265. if (l4kcqe->status != 0) {
  3266. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  3267. cnic_cm_upcall(cp, csk,
  3268. L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE);
  3269. }
  3270. break;
  3271. case L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE:
  3272. if (l4kcqe->status == 0)
  3273. set_bit(SK_F_OFFLD_COMPLETE, &csk->flags);
  3274. else if (l4kcqe->status ==
  3275. L4_KCQE_COMPLETION_STATUS_PARITY_ERROR)
  3276. set_bit(SK_F_HW_ERR, &csk->flags);
  3277. smp_mb__before_clear_bit();
  3278. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  3279. cnic_cm_upcall(cp, csk, opcode);
  3280. break;
  3281. case L4_KCQE_OPCODE_VALUE_RESET_RECEIVED:
  3282. case L4_KCQE_OPCODE_VALUE_CLOSE_COMP:
  3283. case L4_KCQE_OPCODE_VALUE_RESET_COMP:
  3284. case L5CM_RAMROD_CMD_ID_SEARCHER_DELETE:
  3285. case L5CM_RAMROD_CMD_ID_TERMINATE_OFFLOAD:
  3286. if (l4kcqe->status == L4_KCQE_COMPLETION_STATUS_PARITY_ERROR)
  3287. set_bit(SK_F_HW_ERR, &csk->flags);
  3288. cp->close_conn(csk, opcode);
  3289. break;
  3290. case L4_KCQE_OPCODE_VALUE_CLOSE_RECEIVED:
  3291. /* after we already sent CLOSE_REQ */
  3292. if (test_bit(CNIC_F_BNX2X_CLASS, &dev->flags) &&
  3293. !test_bit(SK_F_OFFLD_COMPLETE, &csk->flags) &&
  3294. csk->state == L4_KCQE_OPCODE_VALUE_CLOSE_COMP)
  3295. cp->close_conn(csk, L4_KCQE_OPCODE_VALUE_RESET_COMP);
  3296. else
  3297. cnic_cm_upcall(cp, csk, opcode);
  3298. break;
  3299. }
  3300. csk_put(csk);
  3301. }
  3302. static void cnic_cm_indicate_kcqe(void *data, struct kcqe *kcqe[], u32 num)
  3303. {
  3304. struct cnic_dev *dev = data;
  3305. int i;
  3306. for (i = 0; i < num; i++)
  3307. cnic_cm_process_kcqe(dev, kcqe[i]);
  3308. }
  3309. static struct cnic_ulp_ops cm_ulp_ops = {
  3310. .indicate_kcqes = cnic_cm_indicate_kcqe,
  3311. };
  3312. static void cnic_cm_free_mem(struct cnic_dev *dev)
  3313. {
  3314. struct cnic_local *cp = dev->cnic_priv;
  3315. kfree(cp->csk_tbl);
  3316. cp->csk_tbl = NULL;
  3317. cnic_free_id_tbl(&cp->csk_port_tbl);
  3318. }
  3319. static int cnic_cm_alloc_mem(struct cnic_dev *dev)
  3320. {
  3321. struct cnic_local *cp = dev->cnic_priv;
  3322. u32 port_id;
  3323. cp->csk_tbl = kzalloc(sizeof(struct cnic_sock) * MAX_CM_SK_TBL_SZ,
  3324. GFP_KERNEL);
  3325. if (!cp->csk_tbl)
  3326. return -ENOMEM;
  3327. port_id = random32();
  3328. port_id %= CNIC_LOCAL_PORT_RANGE;
  3329. if (cnic_init_id_tbl(&cp->csk_port_tbl, CNIC_LOCAL_PORT_RANGE,
  3330. CNIC_LOCAL_PORT_MIN, port_id)) {
  3331. cnic_cm_free_mem(dev);
  3332. return -ENOMEM;
  3333. }
  3334. return 0;
  3335. }
  3336. static int cnic_ready_to_close(struct cnic_sock *csk, u32 opcode)
  3337. {
  3338. if (test_and_clear_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) {
  3339. /* Unsolicited RESET_COMP or RESET_RECEIVED */
  3340. opcode = L4_KCQE_OPCODE_VALUE_RESET_RECEIVED;
  3341. csk->state = opcode;
  3342. }
  3343. /* 1. If event opcode matches the expected event in csk->state
  3344. * 2. If the expected event is CLOSE_COMP or RESET_COMP, we accept any
  3345. * event
  3346. * 3. If the expected event is 0, meaning the connection was never
  3347. * never established, we accept the opcode from cm_abort.
  3348. */
  3349. if (opcode == csk->state || csk->state == 0 ||
  3350. csk->state == L4_KCQE_OPCODE_VALUE_CLOSE_COMP ||
  3351. csk->state == L4_KCQE_OPCODE_VALUE_RESET_COMP) {
  3352. if (!test_and_set_bit(SK_F_CLOSING, &csk->flags)) {
  3353. if (csk->state == 0)
  3354. csk->state = opcode;
  3355. return 1;
  3356. }
  3357. }
  3358. return 0;
  3359. }
  3360. static void cnic_close_bnx2_conn(struct cnic_sock *csk, u32 opcode)
  3361. {
  3362. struct cnic_dev *dev = csk->dev;
  3363. struct cnic_local *cp = dev->cnic_priv;
  3364. if (opcode == L4_KCQE_OPCODE_VALUE_RESET_RECEIVED) {
  3365. cnic_cm_upcall(cp, csk, opcode);
  3366. return;
  3367. }
  3368. clear_bit(SK_F_CONNECT_START, &csk->flags);
  3369. cnic_close_conn(csk);
  3370. csk->state = opcode;
  3371. cnic_cm_upcall(cp, csk, opcode);
  3372. }
  3373. static void cnic_cm_stop_bnx2_hw(struct cnic_dev *dev)
  3374. {
  3375. }
  3376. static int cnic_cm_init_bnx2_hw(struct cnic_dev *dev)
  3377. {
  3378. u32 seed;
  3379. seed = random32();
  3380. cnic_ctx_wr(dev, 45, 0, seed);
  3381. return 0;
  3382. }
  3383. static void cnic_close_bnx2x_conn(struct cnic_sock *csk, u32 opcode)
  3384. {
  3385. struct cnic_dev *dev = csk->dev;
  3386. struct cnic_local *cp = dev->cnic_priv;
  3387. struct cnic_context *ctx = &cp->ctx_tbl[csk->l5_cid];
  3388. union l5cm_specific_data l5_data;
  3389. u32 cmd = 0;
  3390. int close_complete = 0;
  3391. switch (opcode) {
  3392. case L4_KCQE_OPCODE_VALUE_RESET_RECEIVED:
  3393. case L4_KCQE_OPCODE_VALUE_CLOSE_COMP:
  3394. case L4_KCQE_OPCODE_VALUE_RESET_COMP:
  3395. if (cnic_ready_to_close(csk, opcode)) {
  3396. if (test_bit(SK_F_HW_ERR, &csk->flags))
  3397. close_complete = 1;
  3398. else if (test_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags))
  3399. cmd = L5CM_RAMROD_CMD_ID_SEARCHER_DELETE;
  3400. else
  3401. close_complete = 1;
  3402. }
  3403. break;
  3404. case L5CM_RAMROD_CMD_ID_SEARCHER_DELETE:
  3405. cmd = L5CM_RAMROD_CMD_ID_TERMINATE_OFFLOAD;
  3406. break;
  3407. case L5CM_RAMROD_CMD_ID_TERMINATE_OFFLOAD:
  3408. close_complete = 1;
  3409. break;
  3410. }
  3411. if (cmd) {
  3412. memset(&l5_data, 0, sizeof(l5_data));
  3413. cnic_submit_kwqe_16(dev, cmd, csk->cid, ISCSI_CONNECTION_TYPE,
  3414. &l5_data);
  3415. } else if (close_complete) {
  3416. ctx->timestamp = jiffies;
  3417. cnic_close_conn(csk);
  3418. cnic_cm_upcall(cp, csk, csk->state);
  3419. }
  3420. }
  3421. static void cnic_cm_stop_bnx2x_hw(struct cnic_dev *dev)
  3422. {
  3423. struct cnic_local *cp = dev->cnic_priv;
  3424. if (!cp->ctx_tbl)
  3425. return;
  3426. if (!netif_running(dev->netdev))
  3427. return;
  3428. cnic_bnx2x_delete_wait(dev, 0);
  3429. cancel_delayed_work(&cp->delete_task);
  3430. flush_workqueue(cnic_wq);
  3431. if (atomic_read(&cp->iscsi_conn) != 0)
  3432. netdev_warn(dev->netdev, "%d iSCSI connections not destroyed\n",
  3433. atomic_read(&cp->iscsi_conn));
  3434. }
  3435. static int cnic_cm_init_bnx2x_hw(struct cnic_dev *dev)
  3436. {
  3437. struct cnic_local *cp = dev->cnic_priv;
  3438. u32 pfid = cp->pfid;
  3439. u32 port = CNIC_PORT(cp);
  3440. cnic_init_bnx2x_mac(dev);
  3441. cnic_bnx2x_set_tcp_timestamp(dev, 1);
  3442. CNIC_WR16(dev, BAR_XSTRORM_INTMEM +
  3443. XSTORM_ISCSI_LOCAL_VLAN_OFFSET(pfid), 0);
  3444. CNIC_WR(dev, BAR_XSTRORM_INTMEM +
  3445. XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_ENABLED_OFFSET(port), 1);
  3446. CNIC_WR(dev, BAR_XSTRORM_INTMEM +
  3447. XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_MAX_COUNT_OFFSET(port),
  3448. DEF_MAX_DA_COUNT);
  3449. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  3450. XSTORM_ISCSI_TCP_VARS_TTL_OFFSET(pfid), DEF_TTL);
  3451. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  3452. XSTORM_ISCSI_TCP_VARS_TOS_OFFSET(pfid), DEF_TOS);
  3453. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  3454. XSTORM_ISCSI_TCP_VARS_ADV_WND_SCL_OFFSET(pfid), 2);
  3455. CNIC_WR(dev, BAR_XSTRORM_INTMEM +
  3456. XSTORM_TCP_TX_SWS_TIMER_VAL_OFFSET(pfid), DEF_SWS_TIMER);
  3457. CNIC_WR(dev, BAR_TSTRORM_INTMEM + TSTORM_TCP_MAX_CWND_OFFSET(pfid),
  3458. DEF_MAX_CWND);
  3459. return 0;
  3460. }
  3461. static void cnic_delete_task(struct work_struct *work)
  3462. {
  3463. struct cnic_local *cp;
  3464. struct cnic_dev *dev;
  3465. u32 i;
  3466. int need_resched = 0;
  3467. cp = container_of(work, struct cnic_local, delete_task.work);
  3468. dev = cp->dev;
  3469. if (test_and_clear_bit(CNIC_LCL_FL_STOP_ISCSI, &cp->cnic_local_flags)) {
  3470. struct drv_ctl_info info;
  3471. cnic_ulp_stop_one(cp, CNIC_ULP_ISCSI);
  3472. info.cmd = DRV_CTL_ISCSI_STOPPED_CMD;
  3473. cp->ethdev->drv_ctl(dev->netdev, &info);
  3474. }
  3475. for (i = 0; i < cp->max_cid_space; i++) {
  3476. struct cnic_context *ctx = &cp->ctx_tbl[i];
  3477. int err;
  3478. if (!test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags) ||
  3479. !test_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags))
  3480. continue;
  3481. if (!time_after(jiffies, ctx->timestamp + (2 * HZ))) {
  3482. need_resched = 1;
  3483. continue;
  3484. }
  3485. if (!test_and_clear_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags))
  3486. continue;
  3487. err = cnic_bnx2x_destroy_ramrod(dev, i);
  3488. cnic_free_bnx2x_conn_resc(dev, i);
  3489. if (!err) {
  3490. if (ctx->ulp_proto_id == CNIC_ULP_ISCSI)
  3491. atomic_dec(&cp->iscsi_conn);
  3492. clear_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags);
  3493. }
  3494. }
  3495. if (need_resched)
  3496. queue_delayed_work(cnic_wq, &cp->delete_task,
  3497. msecs_to_jiffies(10));
  3498. }
  3499. static int cnic_cm_open(struct cnic_dev *dev)
  3500. {
  3501. struct cnic_local *cp = dev->cnic_priv;
  3502. int err;
  3503. err = cnic_cm_alloc_mem(dev);
  3504. if (err)
  3505. return err;
  3506. err = cp->start_cm(dev);
  3507. if (err)
  3508. goto err_out;
  3509. INIT_DELAYED_WORK(&cp->delete_task, cnic_delete_task);
  3510. dev->cm_create = cnic_cm_create;
  3511. dev->cm_destroy = cnic_cm_destroy;
  3512. dev->cm_connect = cnic_cm_connect;
  3513. dev->cm_abort = cnic_cm_abort;
  3514. dev->cm_close = cnic_cm_close;
  3515. dev->cm_select_dev = cnic_cm_select_dev;
  3516. cp->ulp_handle[CNIC_ULP_L4] = dev;
  3517. rcu_assign_pointer(cp->ulp_ops[CNIC_ULP_L4], &cm_ulp_ops);
  3518. return 0;
  3519. err_out:
  3520. cnic_cm_free_mem(dev);
  3521. return err;
  3522. }
  3523. static int cnic_cm_shutdown(struct cnic_dev *dev)
  3524. {
  3525. struct cnic_local *cp = dev->cnic_priv;
  3526. int i;
  3527. if (!cp->csk_tbl)
  3528. return 0;
  3529. for (i = 0; i < MAX_CM_SK_TBL_SZ; i++) {
  3530. struct cnic_sock *csk = &cp->csk_tbl[i];
  3531. clear_bit(SK_F_INUSE, &csk->flags);
  3532. cnic_cm_cleanup(csk);
  3533. }
  3534. cnic_cm_free_mem(dev);
  3535. return 0;
  3536. }
  3537. static void cnic_init_context(struct cnic_dev *dev, u32 cid)
  3538. {
  3539. u32 cid_addr;
  3540. int i;
  3541. cid_addr = GET_CID_ADDR(cid);
  3542. for (i = 0; i < CTX_SIZE; i += 4)
  3543. cnic_ctx_wr(dev, cid_addr, i, 0);
  3544. }
  3545. static int cnic_setup_5709_context(struct cnic_dev *dev, int valid)
  3546. {
  3547. struct cnic_local *cp = dev->cnic_priv;
  3548. int ret = 0, i;
  3549. u32 valid_bit = valid ? BNX2_CTX_HOST_PAGE_TBL_DATA0_VALID : 0;
  3550. if (CHIP_NUM(cp) != CHIP_NUM_5709)
  3551. return 0;
  3552. for (i = 0; i < cp->ctx_blks; i++) {
  3553. int j;
  3554. u32 idx = cp->ctx_arr[i].cid / cp->cids_per_blk;
  3555. u32 val;
  3556. memset(cp->ctx_arr[i].ctx, 0, BCM_PAGE_SIZE);
  3557. CNIC_WR(dev, BNX2_CTX_HOST_PAGE_TBL_DATA0,
  3558. (cp->ctx_arr[i].mapping & 0xffffffff) | valid_bit);
  3559. CNIC_WR(dev, BNX2_CTX_HOST_PAGE_TBL_DATA1,
  3560. (u64) cp->ctx_arr[i].mapping >> 32);
  3561. CNIC_WR(dev, BNX2_CTX_HOST_PAGE_TBL_CTRL, idx |
  3562. BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ);
  3563. for (j = 0; j < 10; j++) {
  3564. val = CNIC_RD(dev, BNX2_CTX_HOST_PAGE_TBL_CTRL);
  3565. if (!(val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ))
  3566. break;
  3567. udelay(5);
  3568. }
  3569. if (val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) {
  3570. ret = -EBUSY;
  3571. break;
  3572. }
  3573. }
  3574. return ret;
  3575. }
  3576. static void cnic_free_irq(struct cnic_dev *dev)
  3577. {
  3578. struct cnic_local *cp = dev->cnic_priv;
  3579. struct cnic_eth_dev *ethdev = cp->ethdev;
  3580. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  3581. cp->disable_int_sync(dev);
  3582. tasklet_kill(&cp->cnic_irq_task);
  3583. free_irq(ethdev->irq_arr[0].vector, dev);
  3584. }
  3585. }
  3586. static int cnic_request_irq(struct cnic_dev *dev)
  3587. {
  3588. struct cnic_local *cp = dev->cnic_priv;
  3589. struct cnic_eth_dev *ethdev = cp->ethdev;
  3590. int err;
  3591. err = request_irq(ethdev->irq_arr[0].vector, cnic_irq, 0, "cnic", dev);
  3592. if (err)
  3593. tasklet_disable(&cp->cnic_irq_task);
  3594. return err;
  3595. }
  3596. static int cnic_init_bnx2_irq(struct cnic_dev *dev)
  3597. {
  3598. struct cnic_local *cp = dev->cnic_priv;
  3599. struct cnic_eth_dev *ethdev = cp->ethdev;
  3600. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  3601. int err, i = 0;
  3602. int sblk_num = cp->status_blk_num;
  3603. u32 base = ((sblk_num - 1) * BNX2_HC_SB_CONFIG_SIZE) +
  3604. BNX2_HC_SB_CONFIG_1;
  3605. CNIC_WR(dev, base, BNX2_HC_SB_CONFIG_1_ONE_SHOT);
  3606. CNIC_WR(dev, base + BNX2_HC_COMP_PROD_TRIP_OFF, (2 << 16) | 8);
  3607. CNIC_WR(dev, base + BNX2_HC_COM_TICKS_OFF, (64 << 16) | 220);
  3608. CNIC_WR(dev, base + BNX2_HC_CMD_TICKS_OFF, (64 << 16) | 220);
  3609. cp->last_status_idx = cp->status_blk.bnx2->status_idx;
  3610. tasklet_init(&cp->cnic_irq_task, cnic_service_bnx2_msix,
  3611. (unsigned long) dev);
  3612. err = cnic_request_irq(dev);
  3613. if (err)
  3614. return err;
  3615. while (cp->status_blk.bnx2->status_completion_producer_index &&
  3616. i < 10) {
  3617. CNIC_WR(dev, BNX2_HC_COALESCE_NOW,
  3618. 1 << (11 + sblk_num));
  3619. udelay(10);
  3620. i++;
  3621. barrier();
  3622. }
  3623. if (cp->status_blk.bnx2->status_completion_producer_index) {
  3624. cnic_free_irq(dev);
  3625. goto failed;
  3626. }
  3627. } else {
  3628. struct status_block *sblk = cp->status_blk.gen;
  3629. u32 hc_cmd = CNIC_RD(dev, BNX2_HC_COMMAND);
  3630. int i = 0;
  3631. while (sblk->status_completion_producer_index && i < 10) {
  3632. CNIC_WR(dev, BNX2_HC_COMMAND,
  3633. hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
  3634. udelay(10);
  3635. i++;
  3636. barrier();
  3637. }
  3638. if (sblk->status_completion_producer_index)
  3639. goto failed;
  3640. }
  3641. return 0;
  3642. failed:
  3643. netdev_err(dev->netdev, "KCQ index not resetting to 0\n");
  3644. return -EBUSY;
  3645. }
  3646. static void cnic_enable_bnx2_int(struct cnic_dev *dev)
  3647. {
  3648. struct cnic_local *cp = dev->cnic_priv;
  3649. struct cnic_eth_dev *ethdev = cp->ethdev;
  3650. if (!(ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX))
  3651. return;
  3652. CNIC_WR(dev, BNX2_PCICFG_INT_ACK_CMD, cp->int_num |
  3653. BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | cp->last_status_idx);
  3654. }
  3655. static void cnic_disable_bnx2_int_sync(struct cnic_dev *dev)
  3656. {
  3657. struct cnic_local *cp = dev->cnic_priv;
  3658. struct cnic_eth_dev *ethdev = cp->ethdev;
  3659. if (!(ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX))
  3660. return;
  3661. CNIC_WR(dev, BNX2_PCICFG_INT_ACK_CMD, cp->int_num |
  3662. BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
  3663. CNIC_RD(dev, BNX2_PCICFG_INT_ACK_CMD);
  3664. synchronize_irq(ethdev->irq_arr[0].vector);
  3665. }
  3666. static void cnic_init_bnx2_tx_ring(struct cnic_dev *dev)
  3667. {
  3668. struct cnic_local *cp = dev->cnic_priv;
  3669. struct cnic_eth_dev *ethdev = cp->ethdev;
  3670. struct cnic_uio_dev *udev = cp->udev;
  3671. u32 cid_addr, tx_cid, sb_id;
  3672. u32 val, offset0, offset1, offset2, offset3;
  3673. int i;
  3674. struct tx_bd *txbd;
  3675. dma_addr_t buf_map, ring_map = udev->l2_ring_map;
  3676. struct status_block *s_blk = cp->status_blk.gen;
  3677. sb_id = cp->status_blk_num;
  3678. tx_cid = 20;
  3679. cp->tx_cons_ptr = &s_blk->status_tx_quick_consumer_index2;
  3680. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  3681. struct status_block_msix *sblk = cp->status_blk.bnx2;
  3682. tx_cid = TX_TSS_CID + sb_id - 1;
  3683. CNIC_WR(dev, BNX2_TSCH_TSS_CFG, (sb_id << 24) |
  3684. (TX_TSS_CID << 7));
  3685. cp->tx_cons_ptr = &sblk->status_tx_quick_consumer_index;
  3686. }
  3687. cp->tx_cons = *cp->tx_cons_ptr;
  3688. cid_addr = GET_CID_ADDR(tx_cid);
  3689. if (CHIP_NUM(cp) == CHIP_NUM_5709) {
  3690. u32 cid_addr2 = GET_CID_ADDR(tx_cid + 4) + 0x40;
  3691. for (i = 0; i < PHY_CTX_SIZE; i += 4)
  3692. cnic_ctx_wr(dev, cid_addr2, i, 0);
  3693. offset0 = BNX2_L2CTX_TYPE_XI;
  3694. offset1 = BNX2_L2CTX_CMD_TYPE_XI;
  3695. offset2 = BNX2_L2CTX_TBDR_BHADDR_HI_XI;
  3696. offset3 = BNX2_L2CTX_TBDR_BHADDR_LO_XI;
  3697. } else {
  3698. cnic_init_context(dev, tx_cid);
  3699. cnic_init_context(dev, tx_cid + 1);
  3700. offset0 = BNX2_L2CTX_TYPE;
  3701. offset1 = BNX2_L2CTX_CMD_TYPE;
  3702. offset2 = BNX2_L2CTX_TBDR_BHADDR_HI;
  3703. offset3 = BNX2_L2CTX_TBDR_BHADDR_LO;
  3704. }
  3705. val = BNX2_L2CTX_TYPE_TYPE_L2 | BNX2_L2CTX_TYPE_SIZE_L2;
  3706. cnic_ctx_wr(dev, cid_addr, offset0, val);
  3707. val = BNX2_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16);
  3708. cnic_ctx_wr(dev, cid_addr, offset1, val);
  3709. txbd = udev->l2_ring;
  3710. buf_map = udev->l2_buf_map;
  3711. for (i = 0; i < MAX_TX_DESC_CNT; i++, txbd++) {
  3712. txbd->tx_bd_haddr_hi = (u64) buf_map >> 32;
  3713. txbd->tx_bd_haddr_lo = (u64) buf_map & 0xffffffff;
  3714. }
  3715. val = (u64) ring_map >> 32;
  3716. cnic_ctx_wr(dev, cid_addr, offset2, val);
  3717. txbd->tx_bd_haddr_hi = val;
  3718. val = (u64) ring_map & 0xffffffff;
  3719. cnic_ctx_wr(dev, cid_addr, offset3, val);
  3720. txbd->tx_bd_haddr_lo = val;
  3721. }
  3722. static void cnic_init_bnx2_rx_ring(struct cnic_dev *dev)
  3723. {
  3724. struct cnic_local *cp = dev->cnic_priv;
  3725. struct cnic_eth_dev *ethdev = cp->ethdev;
  3726. struct cnic_uio_dev *udev = cp->udev;
  3727. u32 cid_addr, sb_id, val, coal_reg, coal_val;
  3728. int i;
  3729. struct rx_bd *rxbd;
  3730. struct status_block *s_blk = cp->status_blk.gen;
  3731. dma_addr_t ring_map = udev->l2_ring_map;
  3732. sb_id = cp->status_blk_num;
  3733. cnic_init_context(dev, 2);
  3734. cp->rx_cons_ptr = &s_blk->status_rx_quick_consumer_index2;
  3735. coal_reg = BNX2_HC_COMMAND;
  3736. coal_val = CNIC_RD(dev, coal_reg);
  3737. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  3738. struct status_block_msix *sblk = cp->status_blk.bnx2;
  3739. cp->rx_cons_ptr = &sblk->status_rx_quick_consumer_index;
  3740. coal_reg = BNX2_HC_COALESCE_NOW;
  3741. coal_val = 1 << (11 + sb_id);
  3742. }
  3743. i = 0;
  3744. while (!(*cp->rx_cons_ptr != 0) && i < 10) {
  3745. CNIC_WR(dev, coal_reg, coal_val);
  3746. udelay(10);
  3747. i++;
  3748. barrier();
  3749. }
  3750. cp->rx_cons = *cp->rx_cons_ptr;
  3751. cid_addr = GET_CID_ADDR(2);
  3752. val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE |
  3753. BNX2_L2CTX_CTX_TYPE_SIZE_L2 | (0x02 << 8);
  3754. cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_CTX_TYPE, val);
  3755. if (sb_id == 0)
  3756. val = 2 << BNX2_L2CTX_L2_STATUSB_NUM_SHIFT;
  3757. else
  3758. val = BNX2_L2CTX_L2_STATUSB_NUM(sb_id);
  3759. cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_HOST_BDIDX, val);
  3760. rxbd = udev->l2_ring + BCM_PAGE_SIZE;
  3761. for (i = 0; i < MAX_RX_DESC_CNT; i++, rxbd++) {
  3762. dma_addr_t buf_map;
  3763. int n = (i % cp->l2_rx_ring_size) + 1;
  3764. buf_map = udev->l2_buf_map + (n * cp->l2_single_buf_size);
  3765. rxbd->rx_bd_len = cp->l2_single_buf_size;
  3766. rxbd->rx_bd_flags = RX_BD_FLAGS_START | RX_BD_FLAGS_END;
  3767. rxbd->rx_bd_haddr_hi = (u64) buf_map >> 32;
  3768. rxbd->rx_bd_haddr_lo = (u64) buf_map & 0xffffffff;
  3769. }
  3770. val = (u64) (ring_map + BCM_PAGE_SIZE) >> 32;
  3771. cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_NX_BDHADDR_HI, val);
  3772. rxbd->rx_bd_haddr_hi = val;
  3773. val = (u64) (ring_map + BCM_PAGE_SIZE) & 0xffffffff;
  3774. cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_NX_BDHADDR_LO, val);
  3775. rxbd->rx_bd_haddr_lo = val;
  3776. val = cnic_reg_rd_ind(dev, BNX2_RXP_SCRATCH_RXP_FLOOD);
  3777. cnic_reg_wr_ind(dev, BNX2_RXP_SCRATCH_RXP_FLOOD, val | (1 << 2));
  3778. }
  3779. static void cnic_shutdown_bnx2_rx_ring(struct cnic_dev *dev)
  3780. {
  3781. struct kwqe *wqes[1], l2kwqe;
  3782. memset(&l2kwqe, 0, sizeof(l2kwqe));
  3783. wqes[0] = &l2kwqe;
  3784. l2kwqe.kwqe_op_flag = (L2_LAYER_CODE << KWQE_LAYER_SHIFT) |
  3785. (L2_KWQE_OPCODE_VALUE_FLUSH <<
  3786. KWQE_OPCODE_SHIFT) | 2;
  3787. dev->submit_kwqes(dev, wqes, 1);
  3788. }
  3789. static void cnic_set_bnx2_mac(struct cnic_dev *dev)
  3790. {
  3791. struct cnic_local *cp = dev->cnic_priv;
  3792. u32 val;
  3793. val = cp->func << 2;
  3794. cp->shmem_base = cnic_reg_rd_ind(dev, BNX2_SHM_HDR_ADDR_0 + val);
  3795. val = cnic_reg_rd_ind(dev, cp->shmem_base +
  3796. BNX2_PORT_HW_CFG_ISCSI_MAC_UPPER);
  3797. dev->mac_addr[0] = (u8) (val >> 8);
  3798. dev->mac_addr[1] = (u8) val;
  3799. CNIC_WR(dev, BNX2_EMAC_MAC_MATCH4, val);
  3800. val = cnic_reg_rd_ind(dev, cp->shmem_base +
  3801. BNX2_PORT_HW_CFG_ISCSI_MAC_LOWER);
  3802. dev->mac_addr[2] = (u8) (val >> 24);
  3803. dev->mac_addr[3] = (u8) (val >> 16);
  3804. dev->mac_addr[4] = (u8) (val >> 8);
  3805. dev->mac_addr[5] = (u8) val;
  3806. CNIC_WR(dev, BNX2_EMAC_MAC_MATCH5, val);
  3807. val = 4 | BNX2_RPM_SORT_USER2_BC_EN;
  3808. if (CHIP_NUM(cp) != CHIP_NUM_5709)
  3809. val |= BNX2_RPM_SORT_USER2_PROM_VLAN;
  3810. CNIC_WR(dev, BNX2_RPM_SORT_USER2, 0x0);
  3811. CNIC_WR(dev, BNX2_RPM_SORT_USER2, val);
  3812. CNIC_WR(dev, BNX2_RPM_SORT_USER2, val | BNX2_RPM_SORT_USER2_ENA);
  3813. }
  3814. static int cnic_start_bnx2_hw(struct cnic_dev *dev)
  3815. {
  3816. struct cnic_local *cp = dev->cnic_priv;
  3817. struct cnic_eth_dev *ethdev = cp->ethdev;
  3818. struct status_block *sblk = cp->status_blk.gen;
  3819. u32 val, kcq_cid_addr, kwq_cid_addr;
  3820. int err;
  3821. cnic_set_bnx2_mac(dev);
  3822. val = CNIC_RD(dev, BNX2_MQ_CONFIG);
  3823. val &= ~BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE;
  3824. if (BCM_PAGE_BITS > 12)
  3825. val |= (12 - 8) << 4;
  3826. else
  3827. val |= (BCM_PAGE_BITS - 8) << 4;
  3828. CNIC_WR(dev, BNX2_MQ_CONFIG, val);
  3829. CNIC_WR(dev, BNX2_HC_COMP_PROD_TRIP, (2 << 16) | 8);
  3830. CNIC_WR(dev, BNX2_HC_COM_TICKS, (64 << 16) | 220);
  3831. CNIC_WR(dev, BNX2_HC_CMD_TICKS, (64 << 16) | 220);
  3832. err = cnic_setup_5709_context(dev, 1);
  3833. if (err)
  3834. return err;
  3835. cnic_init_context(dev, KWQ_CID);
  3836. cnic_init_context(dev, KCQ_CID);
  3837. kwq_cid_addr = GET_CID_ADDR(KWQ_CID);
  3838. cp->kwq_io_addr = MB_GET_CID_ADDR(KWQ_CID) + L5_KRNLQ_HOST_QIDX;
  3839. cp->max_kwq_idx = MAX_KWQ_IDX;
  3840. cp->kwq_prod_idx = 0;
  3841. cp->kwq_con_idx = 0;
  3842. set_bit(CNIC_LCL_FL_KWQ_INIT, &cp->cnic_local_flags);
  3843. if (CHIP_NUM(cp) == CHIP_NUM_5706 || CHIP_NUM(cp) == CHIP_NUM_5708)
  3844. cp->kwq_con_idx_ptr = &sblk->status_rx_quick_consumer_index15;
  3845. else
  3846. cp->kwq_con_idx_ptr = &sblk->status_cmd_consumer_index;
  3847. /* Initialize the kernel work queue context. */
  3848. val = KRNLQ_TYPE_TYPE_KRNLQ | KRNLQ_SIZE_TYPE_SIZE |
  3849. (BCM_PAGE_BITS - 8) | KRNLQ_FLAGS_QE_SELF_SEQ;
  3850. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_TYPE, val);
  3851. val = (BCM_PAGE_SIZE / sizeof(struct kwqe) - 1) << 16;
  3852. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_QE_SELF_SEQ_MAX, val);
  3853. val = ((BCM_PAGE_SIZE / sizeof(struct kwqe)) << 16) | KWQ_PAGE_CNT;
  3854. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_PGTBL_NPAGES, val);
  3855. val = (u32) ((u64) cp->kwq_info.pgtbl_map >> 32);
  3856. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_PGTBL_HADDR_HI, val);
  3857. val = (u32) cp->kwq_info.pgtbl_map;
  3858. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_PGTBL_HADDR_LO, val);
  3859. kcq_cid_addr = GET_CID_ADDR(KCQ_CID);
  3860. cp->kcq1.io_addr = MB_GET_CID_ADDR(KCQ_CID) + L5_KRNLQ_HOST_QIDX;
  3861. cp->kcq1.sw_prod_idx = 0;
  3862. cp->kcq1.hw_prod_idx_ptr =
  3863. &sblk->status_completion_producer_index;
  3864. cp->kcq1.status_idx_ptr = &sblk->status_idx;
  3865. /* Initialize the kernel complete queue context. */
  3866. val = KRNLQ_TYPE_TYPE_KRNLQ | KRNLQ_SIZE_TYPE_SIZE |
  3867. (BCM_PAGE_BITS - 8) | KRNLQ_FLAGS_QE_SELF_SEQ;
  3868. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_TYPE, val);
  3869. val = (BCM_PAGE_SIZE / sizeof(struct kcqe) - 1) << 16;
  3870. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_QE_SELF_SEQ_MAX, val);
  3871. val = ((BCM_PAGE_SIZE / sizeof(struct kcqe)) << 16) | KCQ_PAGE_CNT;
  3872. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_PGTBL_NPAGES, val);
  3873. val = (u32) ((u64) cp->kcq1.dma.pgtbl_map >> 32);
  3874. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_PGTBL_HADDR_HI, val);
  3875. val = (u32) cp->kcq1.dma.pgtbl_map;
  3876. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_PGTBL_HADDR_LO, val);
  3877. cp->int_num = 0;
  3878. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  3879. struct status_block_msix *msblk = cp->status_blk.bnx2;
  3880. u32 sb_id = cp->status_blk_num;
  3881. u32 sb = BNX2_L2CTX_L5_STATUSB_NUM(sb_id);
  3882. cp->kcq1.hw_prod_idx_ptr =
  3883. &msblk->status_completion_producer_index;
  3884. cp->kcq1.status_idx_ptr = &msblk->status_idx;
  3885. cp->kwq_con_idx_ptr = &msblk->status_cmd_consumer_index;
  3886. cp->int_num = sb_id << BNX2_PCICFG_INT_ACK_CMD_INT_NUM_SHIFT;
  3887. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_HOST_QIDX, sb);
  3888. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_HOST_QIDX, sb);
  3889. }
  3890. /* Enable Commnad Scheduler notification when we write to the
  3891. * host producer index of the kernel contexts. */
  3892. CNIC_WR(dev, BNX2_MQ_KNL_CMD_MASK1, 2);
  3893. /* Enable Command Scheduler notification when we write to either
  3894. * the Send Queue or Receive Queue producer indexes of the kernel
  3895. * bypass contexts. */
  3896. CNIC_WR(dev, BNX2_MQ_KNL_BYP_CMD_MASK1, 7);
  3897. CNIC_WR(dev, BNX2_MQ_KNL_BYP_WRITE_MASK1, 7);
  3898. /* Notify COM when the driver post an application buffer. */
  3899. CNIC_WR(dev, BNX2_MQ_KNL_RX_V2P_MASK2, 0x2000);
  3900. /* Set the CP and COM doorbells. These two processors polls the
  3901. * doorbell for a non zero value before running. This must be done
  3902. * after setting up the kernel queue contexts. */
  3903. cnic_reg_wr_ind(dev, BNX2_CP_SCRATCH + 0x20, 1);
  3904. cnic_reg_wr_ind(dev, BNX2_COM_SCRATCH + 0x20, 1);
  3905. cnic_init_bnx2_tx_ring(dev);
  3906. cnic_init_bnx2_rx_ring(dev);
  3907. err = cnic_init_bnx2_irq(dev);
  3908. if (err) {
  3909. netdev_err(dev->netdev, "cnic_init_irq failed\n");
  3910. cnic_reg_wr_ind(dev, BNX2_CP_SCRATCH + 0x20, 0);
  3911. cnic_reg_wr_ind(dev, BNX2_COM_SCRATCH + 0x20, 0);
  3912. return err;
  3913. }
  3914. return 0;
  3915. }
  3916. static void cnic_setup_bnx2x_context(struct cnic_dev *dev)
  3917. {
  3918. struct cnic_local *cp = dev->cnic_priv;
  3919. struct cnic_eth_dev *ethdev = cp->ethdev;
  3920. u32 start_offset = ethdev->ctx_tbl_offset;
  3921. int i;
  3922. for (i = 0; i < cp->ctx_blks; i++) {
  3923. struct cnic_ctx *ctx = &cp->ctx_arr[i];
  3924. dma_addr_t map = ctx->mapping;
  3925. if (cp->ctx_align) {
  3926. unsigned long mask = cp->ctx_align - 1;
  3927. map = (map + mask) & ~mask;
  3928. }
  3929. cnic_ctx_tbl_wr(dev, start_offset + i, map);
  3930. }
  3931. }
  3932. static int cnic_init_bnx2x_irq(struct cnic_dev *dev)
  3933. {
  3934. struct cnic_local *cp = dev->cnic_priv;
  3935. struct cnic_eth_dev *ethdev = cp->ethdev;
  3936. int err = 0;
  3937. tasklet_init(&cp->cnic_irq_task, cnic_service_bnx2x_bh,
  3938. (unsigned long) dev);
  3939. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX)
  3940. err = cnic_request_irq(dev);
  3941. return err;
  3942. }
  3943. static inline void cnic_storm_memset_hc_disable(struct cnic_dev *dev,
  3944. u16 sb_id, u8 sb_index,
  3945. u8 disable)
  3946. {
  3947. u32 addr = BAR_CSTRORM_INTMEM +
  3948. CSTORM_STATUS_BLOCK_DATA_OFFSET(sb_id) +
  3949. offsetof(struct hc_status_block_data_e1x, index_data) +
  3950. sizeof(struct hc_index_data)*sb_index +
  3951. offsetof(struct hc_index_data, flags);
  3952. u16 flags = CNIC_RD16(dev, addr);
  3953. /* clear and set */
  3954. flags &= ~HC_INDEX_DATA_HC_ENABLED;
  3955. flags |= (((~disable) << HC_INDEX_DATA_HC_ENABLED_SHIFT) &
  3956. HC_INDEX_DATA_HC_ENABLED);
  3957. CNIC_WR16(dev, addr, flags);
  3958. }
  3959. static void cnic_enable_bnx2x_int(struct cnic_dev *dev)
  3960. {
  3961. struct cnic_local *cp = dev->cnic_priv;
  3962. u8 sb_id = cp->status_blk_num;
  3963. CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
  3964. CSTORM_STATUS_BLOCK_DATA_OFFSET(sb_id) +
  3965. offsetof(struct hc_status_block_data_e1x, index_data) +
  3966. sizeof(struct hc_index_data)*HC_INDEX_ISCSI_EQ_CONS +
  3967. offsetof(struct hc_index_data, timeout), 64 / 4);
  3968. cnic_storm_memset_hc_disable(dev, sb_id, HC_INDEX_ISCSI_EQ_CONS, 0);
  3969. }
  3970. static void cnic_disable_bnx2x_int_sync(struct cnic_dev *dev)
  3971. {
  3972. }
  3973. static void cnic_init_bnx2x_tx_ring(struct cnic_dev *dev,
  3974. struct client_init_ramrod_data *data)
  3975. {
  3976. struct cnic_local *cp = dev->cnic_priv;
  3977. struct cnic_uio_dev *udev = cp->udev;
  3978. union eth_tx_bd_types *txbd = (union eth_tx_bd_types *) udev->l2_ring;
  3979. dma_addr_t buf_map, ring_map = udev->l2_ring_map;
  3980. struct host_sp_status_block *sb = cp->bnx2x_def_status_blk;
  3981. int i;
  3982. u32 cli = cp->ethdev->iscsi_l2_client_id;
  3983. u32 val;
  3984. memset(txbd, 0, BCM_PAGE_SIZE);
  3985. buf_map = udev->l2_buf_map;
  3986. for (i = 0; i < MAX_TX_DESC_CNT; i += 3, txbd += 3) {
  3987. struct eth_tx_start_bd *start_bd = &txbd->start_bd;
  3988. struct eth_tx_bd *reg_bd = &((txbd + 2)->reg_bd);
  3989. start_bd->addr_hi = cpu_to_le32((u64) buf_map >> 32);
  3990. start_bd->addr_lo = cpu_to_le32(buf_map & 0xffffffff);
  3991. reg_bd->addr_hi = start_bd->addr_hi;
  3992. reg_bd->addr_lo = start_bd->addr_lo + 0x10;
  3993. start_bd->nbytes = cpu_to_le16(0x10);
  3994. start_bd->nbd = cpu_to_le16(3);
  3995. start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
  3996. start_bd->general_data = (UNICAST_ADDRESS <<
  3997. ETH_TX_START_BD_ETH_ADDR_TYPE_SHIFT);
  3998. start_bd->general_data |= (1 << ETH_TX_START_BD_HDR_NBDS_SHIFT);
  3999. }
  4000. val = (u64) ring_map >> 32;
  4001. txbd->next_bd.addr_hi = cpu_to_le32(val);
  4002. data->tx.tx_bd_page_base.hi = cpu_to_le32(val);
  4003. val = (u64) ring_map & 0xffffffff;
  4004. txbd->next_bd.addr_lo = cpu_to_le32(val);
  4005. data->tx.tx_bd_page_base.lo = cpu_to_le32(val);
  4006. /* Other ramrod params */
  4007. data->tx.tx_sb_index_number = HC_SP_INDEX_ETH_ISCSI_CQ_CONS;
  4008. data->tx.tx_status_block_id = BNX2X_DEF_SB_ID;
  4009. /* reset xstorm per client statistics */
  4010. if (cli < MAX_STAT_COUNTER_ID) {
  4011. data->general.statistics_zero_flg = 1;
  4012. data->general.statistics_en_flg = 1;
  4013. data->general.statistics_counter_id = cli;
  4014. }
  4015. cp->tx_cons_ptr =
  4016. &sb->sp_sb.index_values[HC_SP_INDEX_ETH_ISCSI_CQ_CONS];
  4017. }
  4018. static void cnic_init_bnx2x_rx_ring(struct cnic_dev *dev,
  4019. struct client_init_ramrod_data *data)
  4020. {
  4021. struct cnic_local *cp = dev->cnic_priv;
  4022. struct cnic_uio_dev *udev = cp->udev;
  4023. struct eth_rx_bd *rxbd = (struct eth_rx_bd *) (udev->l2_ring +
  4024. BCM_PAGE_SIZE);
  4025. struct eth_rx_cqe_next_page *rxcqe = (struct eth_rx_cqe_next_page *)
  4026. (udev->l2_ring + (2 * BCM_PAGE_SIZE));
  4027. struct host_sp_status_block *sb = cp->bnx2x_def_status_blk;
  4028. int i;
  4029. u32 cli = cp->ethdev->iscsi_l2_client_id;
  4030. int cl_qzone_id = BNX2X_CL_QZONE_ID(cp, cli);
  4031. u32 val;
  4032. dma_addr_t ring_map = udev->l2_ring_map;
  4033. /* General data */
  4034. data->general.client_id = cli;
  4035. data->general.activate_flg = 1;
  4036. data->general.sp_client_id = cli;
  4037. data->general.mtu = cpu_to_le16(cp->l2_single_buf_size - 14);
  4038. data->general.func_id = cp->pfid;
  4039. for (i = 0; i < BNX2X_MAX_RX_DESC_CNT; i++, rxbd++) {
  4040. dma_addr_t buf_map;
  4041. int n = (i % cp->l2_rx_ring_size) + 1;
  4042. buf_map = udev->l2_buf_map + (n * cp->l2_single_buf_size);
  4043. rxbd->addr_hi = cpu_to_le32((u64) buf_map >> 32);
  4044. rxbd->addr_lo = cpu_to_le32(buf_map & 0xffffffff);
  4045. }
  4046. val = (u64) (ring_map + BCM_PAGE_SIZE) >> 32;
  4047. rxbd->addr_hi = cpu_to_le32(val);
  4048. data->rx.bd_page_base.hi = cpu_to_le32(val);
  4049. val = (u64) (ring_map + BCM_PAGE_SIZE) & 0xffffffff;
  4050. rxbd->addr_lo = cpu_to_le32(val);
  4051. data->rx.bd_page_base.lo = cpu_to_le32(val);
  4052. rxcqe += BNX2X_MAX_RCQ_DESC_CNT;
  4053. val = (u64) (ring_map + (2 * BCM_PAGE_SIZE)) >> 32;
  4054. rxcqe->addr_hi = cpu_to_le32(val);
  4055. data->rx.cqe_page_base.hi = cpu_to_le32(val);
  4056. val = (u64) (ring_map + (2 * BCM_PAGE_SIZE)) & 0xffffffff;
  4057. rxcqe->addr_lo = cpu_to_le32(val);
  4058. data->rx.cqe_page_base.lo = cpu_to_le32(val);
  4059. /* Other ramrod params */
  4060. data->rx.client_qzone_id = cl_qzone_id;
  4061. data->rx.rx_sb_index_number = HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS;
  4062. data->rx.status_block_id = BNX2X_DEF_SB_ID;
  4063. data->rx.cache_line_alignment_log_size = L1_CACHE_SHIFT;
  4064. data->rx.max_bytes_on_bd = cpu_to_le16(cp->l2_single_buf_size);
  4065. data->rx.outer_vlan_removal_enable_flg = 1;
  4066. data->rx.silent_vlan_removal_flg = 1;
  4067. data->rx.silent_vlan_value = 0;
  4068. data->rx.silent_vlan_mask = 0xffff;
  4069. cp->rx_cons_ptr =
  4070. &sb->sp_sb.index_values[HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS];
  4071. cp->rx_cons = *cp->rx_cons_ptr;
  4072. }
  4073. static void cnic_init_bnx2x_kcq(struct cnic_dev *dev)
  4074. {
  4075. struct cnic_local *cp = dev->cnic_priv;
  4076. u32 pfid = cp->pfid;
  4077. cp->kcq1.io_addr = BAR_CSTRORM_INTMEM +
  4078. CSTORM_ISCSI_EQ_PROD_OFFSET(pfid, 0);
  4079. cp->kcq1.sw_prod_idx = 0;
  4080. if (BNX2X_CHIP_IS_E2_PLUS(cp->chip_id)) {
  4081. struct host_hc_status_block_e2 *sb = cp->status_blk.gen;
  4082. cp->kcq1.hw_prod_idx_ptr =
  4083. &sb->sb.index_values[HC_INDEX_ISCSI_EQ_CONS];
  4084. cp->kcq1.status_idx_ptr =
  4085. &sb->sb.running_index[SM_RX_ID];
  4086. } else {
  4087. struct host_hc_status_block_e1x *sb = cp->status_blk.gen;
  4088. cp->kcq1.hw_prod_idx_ptr =
  4089. &sb->sb.index_values[HC_INDEX_ISCSI_EQ_CONS];
  4090. cp->kcq1.status_idx_ptr =
  4091. &sb->sb.running_index[SM_RX_ID];
  4092. }
  4093. if (BNX2X_CHIP_IS_E2_PLUS(cp->chip_id)) {
  4094. struct host_hc_status_block_e2 *sb = cp->status_blk.gen;
  4095. cp->kcq2.io_addr = BAR_USTRORM_INTMEM +
  4096. USTORM_FCOE_EQ_PROD_OFFSET(pfid);
  4097. cp->kcq2.sw_prod_idx = 0;
  4098. cp->kcq2.hw_prod_idx_ptr =
  4099. &sb->sb.index_values[HC_INDEX_FCOE_EQ_CONS];
  4100. cp->kcq2.status_idx_ptr =
  4101. &sb->sb.running_index[SM_RX_ID];
  4102. }
  4103. }
  4104. static int cnic_start_bnx2x_hw(struct cnic_dev *dev)
  4105. {
  4106. struct cnic_local *cp = dev->cnic_priv;
  4107. struct cnic_eth_dev *ethdev = cp->ethdev;
  4108. int func = CNIC_FUNC(cp), ret;
  4109. u32 pfid;
  4110. dev->stats_addr = ethdev->addr_drv_info_to_mcp;
  4111. cp->port_mode = CHIP_PORT_MODE_NONE;
  4112. if (BNX2X_CHIP_IS_E2_PLUS(cp->chip_id)) {
  4113. u32 val;
  4114. pci_read_config_dword(dev->pcidev, PCICFG_ME_REGISTER, &val);
  4115. cp->func = (u8) ((val & ME_REG_ABS_PF_NUM) >>
  4116. ME_REG_ABS_PF_NUM_SHIFT);
  4117. func = CNIC_FUNC(cp);
  4118. val = CNIC_RD(dev, MISC_REG_PORT4MODE_EN_OVWR);
  4119. if (!(val & 1))
  4120. val = CNIC_RD(dev, MISC_REG_PORT4MODE_EN);
  4121. else
  4122. val = (val >> 1) & 1;
  4123. if (val) {
  4124. cp->port_mode = CHIP_4_PORT_MODE;
  4125. cp->pfid = func >> 1;
  4126. } else {
  4127. cp->port_mode = CHIP_2_PORT_MODE;
  4128. cp->pfid = func & 0x6;
  4129. }
  4130. } else {
  4131. cp->pfid = func;
  4132. }
  4133. pfid = cp->pfid;
  4134. ret = cnic_init_id_tbl(&cp->cid_tbl, MAX_ISCSI_TBL_SZ,
  4135. cp->iscsi_start_cid, 0);
  4136. if (ret)
  4137. return -ENOMEM;
  4138. if (BNX2X_CHIP_IS_E2_PLUS(cp->chip_id)) {
  4139. ret = cnic_init_id_tbl(&cp->fcoe_cid_tbl, dev->max_fcoe_conn,
  4140. cp->fcoe_start_cid, 0);
  4141. if (ret)
  4142. return -ENOMEM;
  4143. }
  4144. cp->bnx2x_igu_sb_id = ethdev->irq_arr[0].status_blk_num2;
  4145. cnic_init_bnx2x_kcq(dev);
  4146. /* Only 1 EQ */
  4147. CNIC_WR16(dev, cp->kcq1.io_addr, MAX_KCQ_IDX);
  4148. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  4149. CSTORM_ISCSI_EQ_CONS_OFFSET(pfid, 0), 0);
  4150. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  4151. CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_OFFSET(pfid, 0),
  4152. cp->kcq1.dma.pg_map_arr[1] & 0xffffffff);
  4153. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  4154. CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_OFFSET(pfid, 0) + 4,
  4155. (u64) cp->kcq1.dma.pg_map_arr[1] >> 32);
  4156. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  4157. CSTORM_ISCSI_EQ_NEXT_EQE_ADDR_OFFSET(pfid, 0),
  4158. cp->kcq1.dma.pg_map_arr[0] & 0xffffffff);
  4159. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  4160. CSTORM_ISCSI_EQ_NEXT_EQE_ADDR_OFFSET(pfid, 0) + 4,
  4161. (u64) cp->kcq1.dma.pg_map_arr[0] >> 32);
  4162. CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
  4163. CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_VALID_OFFSET(pfid, 0), 1);
  4164. CNIC_WR16(dev, BAR_CSTRORM_INTMEM +
  4165. CSTORM_ISCSI_EQ_SB_NUM_OFFSET(pfid, 0), cp->status_blk_num);
  4166. CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
  4167. CSTORM_ISCSI_EQ_SB_INDEX_OFFSET(pfid, 0),
  4168. HC_INDEX_ISCSI_EQ_CONS);
  4169. CNIC_WR(dev, BAR_USTRORM_INTMEM +
  4170. USTORM_ISCSI_GLOBAL_BUF_PHYS_ADDR_OFFSET(pfid),
  4171. cp->gbl_buf_info.pg_map_arr[0] & 0xffffffff);
  4172. CNIC_WR(dev, BAR_USTRORM_INTMEM +
  4173. USTORM_ISCSI_GLOBAL_BUF_PHYS_ADDR_OFFSET(pfid) + 4,
  4174. (u64) cp->gbl_buf_info.pg_map_arr[0] >> 32);
  4175. CNIC_WR(dev, BAR_TSTRORM_INTMEM +
  4176. TSTORM_ISCSI_TCP_LOCAL_ADV_WND_OFFSET(pfid), DEF_RCV_BUF);
  4177. cnic_setup_bnx2x_context(dev);
  4178. ret = cnic_init_bnx2x_irq(dev);
  4179. if (ret)
  4180. return ret;
  4181. return 0;
  4182. }
  4183. static void cnic_init_rings(struct cnic_dev *dev)
  4184. {
  4185. struct cnic_local *cp = dev->cnic_priv;
  4186. struct cnic_uio_dev *udev = cp->udev;
  4187. if (test_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags))
  4188. return;
  4189. if (test_bit(CNIC_F_BNX2_CLASS, &dev->flags)) {
  4190. cnic_init_bnx2_tx_ring(dev);
  4191. cnic_init_bnx2_rx_ring(dev);
  4192. set_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags);
  4193. } else if (test_bit(CNIC_F_BNX2X_CLASS, &dev->flags)) {
  4194. u32 cli = cp->ethdev->iscsi_l2_client_id;
  4195. u32 cid = cp->ethdev->iscsi_l2_cid;
  4196. u32 cl_qzone_id;
  4197. struct client_init_ramrod_data *data;
  4198. union l5cm_specific_data l5_data;
  4199. struct ustorm_eth_rx_producers rx_prods = {0};
  4200. u32 off, i, *cid_ptr;
  4201. rx_prods.bd_prod = 0;
  4202. rx_prods.cqe_prod = BNX2X_MAX_RCQ_DESC_CNT;
  4203. barrier();
  4204. cl_qzone_id = BNX2X_CL_QZONE_ID(cp, cli);
  4205. off = BAR_USTRORM_INTMEM +
  4206. (BNX2X_CHIP_IS_E2_PLUS(cp->chip_id) ?
  4207. USTORM_RX_PRODS_E2_OFFSET(cl_qzone_id) :
  4208. USTORM_RX_PRODS_E1X_OFFSET(CNIC_PORT(cp), cli));
  4209. for (i = 0; i < sizeof(struct ustorm_eth_rx_producers) / 4; i++)
  4210. CNIC_WR(dev, off + i * 4, ((u32 *) &rx_prods)[i]);
  4211. set_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags);
  4212. data = udev->l2_buf;
  4213. cid_ptr = udev->l2_buf + 12;
  4214. memset(data, 0, sizeof(*data));
  4215. cnic_init_bnx2x_tx_ring(dev, data);
  4216. cnic_init_bnx2x_rx_ring(dev, data);
  4217. l5_data.phy_address.lo = udev->l2_buf_map & 0xffffffff;
  4218. l5_data.phy_address.hi = (u64) udev->l2_buf_map >> 32;
  4219. set_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags);
  4220. cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_ETH_CLIENT_SETUP,
  4221. cid, ETH_CONNECTION_TYPE, &l5_data);
  4222. i = 0;
  4223. while (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags) &&
  4224. ++i < 10)
  4225. msleep(1);
  4226. if (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags))
  4227. netdev_err(dev->netdev,
  4228. "iSCSI CLIENT_SETUP did not complete\n");
  4229. cnic_spq_completion(dev, DRV_CTL_RET_L2_SPQ_CREDIT_CMD, 1);
  4230. cnic_ring_ctl(dev, cid, cli, 1);
  4231. *cid_ptr = cid;
  4232. }
  4233. }
  4234. static void cnic_shutdown_rings(struct cnic_dev *dev)
  4235. {
  4236. struct cnic_local *cp = dev->cnic_priv;
  4237. struct cnic_uio_dev *udev = cp->udev;
  4238. void *rx_ring;
  4239. if (!test_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags))
  4240. return;
  4241. if (test_bit(CNIC_F_BNX2_CLASS, &dev->flags)) {
  4242. cnic_shutdown_bnx2_rx_ring(dev);
  4243. } else if (test_bit(CNIC_F_BNX2X_CLASS, &dev->flags)) {
  4244. u32 cli = cp->ethdev->iscsi_l2_client_id;
  4245. u32 cid = cp->ethdev->iscsi_l2_cid;
  4246. union l5cm_specific_data l5_data;
  4247. int i;
  4248. cnic_ring_ctl(dev, cid, cli, 0);
  4249. set_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags);
  4250. l5_data.phy_address.lo = cli;
  4251. l5_data.phy_address.hi = 0;
  4252. cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_ETH_HALT,
  4253. cid, ETH_CONNECTION_TYPE, &l5_data);
  4254. i = 0;
  4255. while (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags) &&
  4256. ++i < 10)
  4257. msleep(1);
  4258. if (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags))
  4259. netdev_err(dev->netdev,
  4260. "iSCSI CLIENT_HALT did not complete\n");
  4261. cnic_spq_completion(dev, DRV_CTL_RET_L2_SPQ_CREDIT_CMD, 1);
  4262. memset(&l5_data, 0, sizeof(l5_data));
  4263. cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_COMMON_CFC_DEL,
  4264. cid, NONE_CONNECTION_TYPE, &l5_data);
  4265. msleep(10);
  4266. }
  4267. clear_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags);
  4268. rx_ring = udev->l2_ring + BCM_PAGE_SIZE;
  4269. memset(rx_ring, 0, BCM_PAGE_SIZE);
  4270. }
  4271. static int cnic_register_netdev(struct cnic_dev *dev)
  4272. {
  4273. struct cnic_local *cp = dev->cnic_priv;
  4274. struct cnic_eth_dev *ethdev = cp->ethdev;
  4275. int err;
  4276. if (!ethdev)
  4277. return -ENODEV;
  4278. if (ethdev->drv_state & CNIC_DRV_STATE_REGD)
  4279. return 0;
  4280. err = ethdev->drv_register_cnic(dev->netdev, cp->cnic_ops, dev);
  4281. if (err)
  4282. netdev_err(dev->netdev, "register_cnic failed\n");
  4283. return err;
  4284. }
  4285. static void cnic_unregister_netdev(struct cnic_dev *dev)
  4286. {
  4287. struct cnic_local *cp = dev->cnic_priv;
  4288. struct cnic_eth_dev *ethdev = cp->ethdev;
  4289. if (!ethdev)
  4290. return;
  4291. ethdev->drv_unregister_cnic(dev->netdev);
  4292. }
  4293. static int cnic_start_hw(struct cnic_dev *dev)
  4294. {
  4295. struct cnic_local *cp = dev->cnic_priv;
  4296. struct cnic_eth_dev *ethdev = cp->ethdev;
  4297. int err;
  4298. if (test_bit(CNIC_F_CNIC_UP, &dev->flags))
  4299. return -EALREADY;
  4300. dev->regview = ethdev->io_base;
  4301. pci_dev_get(dev->pcidev);
  4302. cp->func = PCI_FUNC(dev->pcidev->devfn);
  4303. cp->status_blk.gen = ethdev->irq_arr[0].status_blk;
  4304. cp->status_blk_num = ethdev->irq_arr[0].status_blk_num;
  4305. err = cp->alloc_resc(dev);
  4306. if (err) {
  4307. netdev_err(dev->netdev, "allocate resource failure\n");
  4308. goto err1;
  4309. }
  4310. err = cp->start_hw(dev);
  4311. if (err)
  4312. goto err1;
  4313. err = cnic_cm_open(dev);
  4314. if (err)
  4315. goto err1;
  4316. set_bit(CNIC_F_CNIC_UP, &dev->flags);
  4317. cp->enable_int(dev);
  4318. return 0;
  4319. err1:
  4320. cp->free_resc(dev);
  4321. pci_dev_put(dev->pcidev);
  4322. return err;
  4323. }
  4324. static void cnic_stop_bnx2_hw(struct cnic_dev *dev)
  4325. {
  4326. cnic_disable_bnx2_int_sync(dev);
  4327. cnic_reg_wr_ind(dev, BNX2_CP_SCRATCH + 0x20, 0);
  4328. cnic_reg_wr_ind(dev, BNX2_COM_SCRATCH + 0x20, 0);
  4329. cnic_init_context(dev, KWQ_CID);
  4330. cnic_init_context(dev, KCQ_CID);
  4331. cnic_setup_5709_context(dev, 0);
  4332. cnic_free_irq(dev);
  4333. cnic_free_resc(dev);
  4334. }
  4335. static void cnic_stop_bnx2x_hw(struct cnic_dev *dev)
  4336. {
  4337. struct cnic_local *cp = dev->cnic_priv;
  4338. cnic_free_irq(dev);
  4339. *cp->kcq1.hw_prod_idx_ptr = 0;
  4340. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  4341. CSTORM_ISCSI_EQ_CONS_OFFSET(cp->pfid, 0), 0);
  4342. CNIC_WR16(dev, cp->kcq1.io_addr, 0);
  4343. cnic_free_resc(dev);
  4344. }
  4345. static void cnic_stop_hw(struct cnic_dev *dev)
  4346. {
  4347. if (test_bit(CNIC_F_CNIC_UP, &dev->flags)) {
  4348. struct cnic_local *cp = dev->cnic_priv;
  4349. int i = 0;
  4350. /* Need to wait for the ring shutdown event to complete
  4351. * before clearing the CNIC_UP flag.
  4352. */
  4353. while (cp->udev->uio_dev != -1 && i < 15) {
  4354. msleep(100);
  4355. i++;
  4356. }
  4357. cnic_shutdown_rings(dev);
  4358. cp->stop_cm(dev);
  4359. clear_bit(CNIC_F_CNIC_UP, &dev->flags);
  4360. RCU_INIT_POINTER(cp->ulp_ops[CNIC_ULP_L4], NULL);
  4361. synchronize_rcu();
  4362. cnic_cm_shutdown(dev);
  4363. cp->stop_hw(dev);
  4364. pci_dev_put(dev->pcidev);
  4365. }
  4366. }
  4367. static void cnic_free_dev(struct cnic_dev *dev)
  4368. {
  4369. int i = 0;
  4370. while ((atomic_read(&dev->ref_count) != 0) && i < 10) {
  4371. msleep(100);
  4372. i++;
  4373. }
  4374. if (atomic_read(&dev->ref_count) != 0)
  4375. netdev_err(dev->netdev, "Failed waiting for ref count to go to zero\n");
  4376. netdev_info(dev->netdev, "Removed CNIC device\n");
  4377. dev_put(dev->netdev);
  4378. kfree(dev);
  4379. }
  4380. static struct cnic_dev *cnic_alloc_dev(struct net_device *dev,
  4381. struct pci_dev *pdev)
  4382. {
  4383. struct cnic_dev *cdev;
  4384. struct cnic_local *cp;
  4385. int alloc_size;
  4386. alloc_size = sizeof(struct cnic_dev) + sizeof(struct cnic_local);
  4387. cdev = kzalloc(alloc_size , GFP_KERNEL);
  4388. if (cdev == NULL) {
  4389. netdev_err(dev, "allocate dev struct failure\n");
  4390. return NULL;
  4391. }
  4392. cdev->netdev = dev;
  4393. cdev->cnic_priv = (char *)cdev + sizeof(struct cnic_dev);
  4394. cdev->register_device = cnic_register_device;
  4395. cdev->unregister_device = cnic_unregister_device;
  4396. cdev->iscsi_nl_msg_recv = cnic_iscsi_nl_msg_recv;
  4397. cp = cdev->cnic_priv;
  4398. cp->dev = cdev;
  4399. cp->l2_single_buf_size = 0x400;
  4400. cp->l2_rx_ring_size = 3;
  4401. spin_lock_init(&cp->cnic_ulp_lock);
  4402. netdev_info(dev, "Added CNIC device\n");
  4403. return cdev;
  4404. }
  4405. static struct cnic_dev *init_bnx2_cnic(struct net_device *dev)
  4406. {
  4407. struct pci_dev *pdev;
  4408. struct cnic_dev *cdev;
  4409. struct cnic_local *cp;
  4410. struct cnic_eth_dev *ethdev = NULL;
  4411. struct cnic_eth_dev *(*probe)(struct net_device *) = NULL;
  4412. probe = symbol_get(bnx2_cnic_probe);
  4413. if (probe) {
  4414. ethdev = (*probe)(dev);
  4415. symbol_put(bnx2_cnic_probe);
  4416. }
  4417. if (!ethdev)
  4418. return NULL;
  4419. pdev = ethdev->pdev;
  4420. if (!pdev)
  4421. return NULL;
  4422. dev_hold(dev);
  4423. pci_dev_get(pdev);
  4424. if ((pdev->device == PCI_DEVICE_ID_NX2_5709 ||
  4425. pdev->device == PCI_DEVICE_ID_NX2_5709S) &&
  4426. (pdev->revision < 0x10)) {
  4427. pci_dev_put(pdev);
  4428. goto cnic_err;
  4429. }
  4430. pci_dev_put(pdev);
  4431. cdev = cnic_alloc_dev(dev, pdev);
  4432. if (cdev == NULL)
  4433. goto cnic_err;
  4434. set_bit(CNIC_F_BNX2_CLASS, &cdev->flags);
  4435. cdev->submit_kwqes = cnic_submit_bnx2_kwqes;
  4436. cp = cdev->cnic_priv;
  4437. cp->ethdev = ethdev;
  4438. cdev->pcidev = pdev;
  4439. cp->chip_id = ethdev->chip_id;
  4440. cdev->max_iscsi_conn = ethdev->max_iscsi_conn;
  4441. cp->cnic_ops = &cnic_bnx2_ops;
  4442. cp->start_hw = cnic_start_bnx2_hw;
  4443. cp->stop_hw = cnic_stop_bnx2_hw;
  4444. cp->setup_pgtbl = cnic_setup_page_tbl;
  4445. cp->alloc_resc = cnic_alloc_bnx2_resc;
  4446. cp->free_resc = cnic_free_resc;
  4447. cp->start_cm = cnic_cm_init_bnx2_hw;
  4448. cp->stop_cm = cnic_cm_stop_bnx2_hw;
  4449. cp->enable_int = cnic_enable_bnx2_int;
  4450. cp->disable_int_sync = cnic_disable_bnx2_int_sync;
  4451. cp->close_conn = cnic_close_bnx2_conn;
  4452. return cdev;
  4453. cnic_err:
  4454. dev_put(dev);
  4455. return NULL;
  4456. }
  4457. static struct cnic_dev *init_bnx2x_cnic(struct net_device *dev)
  4458. {
  4459. struct pci_dev *pdev;
  4460. struct cnic_dev *cdev;
  4461. struct cnic_local *cp;
  4462. struct cnic_eth_dev *ethdev = NULL;
  4463. struct cnic_eth_dev *(*probe)(struct net_device *) = NULL;
  4464. probe = symbol_get(bnx2x_cnic_probe);
  4465. if (probe) {
  4466. ethdev = (*probe)(dev);
  4467. symbol_put(bnx2x_cnic_probe);
  4468. }
  4469. if (!ethdev)
  4470. return NULL;
  4471. pdev = ethdev->pdev;
  4472. if (!pdev)
  4473. return NULL;
  4474. dev_hold(dev);
  4475. cdev = cnic_alloc_dev(dev, pdev);
  4476. if (cdev == NULL) {
  4477. dev_put(dev);
  4478. return NULL;
  4479. }
  4480. set_bit(CNIC_F_BNX2X_CLASS, &cdev->flags);
  4481. cdev->submit_kwqes = cnic_submit_bnx2x_kwqes;
  4482. cp = cdev->cnic_priv;
  4483. cp->ethdev = ethdev;
  4484. cdev->pcidev = pdev;
  4485. cp->chip_id = ethdev->chip_id;
  4486. cdev->stats_addr = ethdev->addr_drv_info_to_mcp;
  4487. if (!(ethdev->drv_state & CNIC_DRV_STATE_NO_ISCSI))
  4488. cdev->max_iscsi_conn = ethdev->max_iscsi_conn;
  4489. if (BNX2X_CHIP_IS_E2_PLUS(cp->chip_id) &&
  4490. !(ethdev->drv_state & CNIC_DRV_STATE_NO_FCOE))
  4491. cdev->max_fcoe_conn = ethdev->max_fcoe_conn;
  4492. if (cdev->max_fcoe_conn > BNX2X_FCOE_NUM_CONNECTIONS)
  4493. cdev->max_fcoe_conn = BNX2X_FCOE_NUM_CONNECTIONS;
  4494. memcpy(cdev->mac_addr, ethdev->iscsi_mac, 6);
  4495. cp->cnic_ops = &cnic_bnx2x_ops;
  4496. cp->start_hw = cnic_start_bnx2x_hw;
  4497. cp->stop_hw = cnic_stop_bnx2x_hw;
  4498. cp->setup_pgtbl = cnic_setup_page_tbl_le;
  4499. cp->alloc_resc = cnic_alloc_bnx2x_resc;
  4500. cp->free_resc = cnic_free_resc;
  4501. cp->start_cm = cnic_cm_init_bnx2x_hw;
  4502. cp->stop_cm = cnic_cm_stop_bnx2x_hw;
  4503. cp->enable_int = cnic_enable_bnx2x_int;
  4504. cp->disable_int_sync = cnic_disable_bnx2x_int_sync;
  4505. if (BNX2X_CHIP_IS_E2_PLUS(cp->chip_id))
  4506. cp->ack_int = cnic_ack_bnx2x_e2_msix;
  4507. else
  4508. cp->ack_int = cnic_ack_bnx2x_msix;
  4509. cp->close_conn = cnic_close_bnx2x_conn;
  4510. return cdev;
  4511. }
  4512. static struct cnic_dev *is_cnic_dev(struct net_device *dev)
  4513. {
  4514. struct ethtool_drvinfo drvinfo;
  4515. struct cnic_dev *cdev = NULL;
  4516. if (dev->ethtool_ops && dev->ethtool_ops->get_drvinfo) {
  4517. memset(&drvinfo, 0, sizeof(drvinfo));
  4518. dev->ethtool_ops->get_drvinfo(dev, &drvinfo);
  4519. if (!strcmp(drvinfo.driver, "bnx2"))
  4520. cdev = init_bnx2_cnic(dev);
  4521. if (!strcmp(drvinfo.driver, "bnx2x"))
  4522. cdev = init_bnx2x_cnic(dev);
  4523. if (cdev) {
  4524. write_lock(&cnic_dev_lock);
  4525. list_add(&cdev->list, &cnic_dev_list);
  4526. write_unlock(&cnic_dev_lock);
  4527. }
  4528. }
  4529. return cdev;
  4530. }
  4531. static void cnic_rcv_netevent(struct cnic_local *cp, unsigned long event,
  4532. u16 vlan_id)
  4533. {
  4534. int if_type;
  4535. rcu_read_lock();
  4536. for (if_type = 0; if_type < MAX_CNIC_ULP_TYPE; if_type++) {
  4537. struct cnic_ulp_ops *ulp_ops;
  4538. void *ctx;
  4539. ulp_ops = rcu_dereference(cp->ulp_ops[if_type]);
  4540. if (!ulp_ops || !ulp_ops->indicate_netevent)
  4541. continue;
  4542. ctx = cp->ulp_handle[if_type];
  4543. ulp_ops->indicate_netevent(ctx, event, vlan_id);
  4544. }
  4545. rcu_read_unlock();
  4546. }
  4547. /**
  4548. * netdev event handler
  4549. */
  4550. static int cnic_netdev_event(struct notifier_block *this, unsigned long event,
  4551. void *ptr)
  4552. {
  4553. struct net_device *netdev = ptr;
  4554. struct cnic_dev *dev;
  4555. int new_dev = 0;
  4556. dev = cnic_from_netdev(netdev);
  4557. if (!dev && (event == NETDEV_REGISTER || netif_running(netdev))) {
  4558. /* Check for the hot-plug device */
  4559. dev = is_cnic_dev(netdev);
  4560. if (dev) {
  4561. new_dev = 1;
  4562. cnic_hold(dev);
  4563. }
  4564. }
  4565. if (dev) {
  4566. struct cnic_local *cp = dev->cnic_priv;
  4567. if (new_dev)
  4568. cnic_ulp_init(dev);
  4569. else if (event == NETDEV_UNREGISTER)
  4570. cnic_ulp_exit(dev);
  4571. if (event == NETDEV_UP || (new_dev && netif_running(netdev))) {
  4572. if (cnic_register_netdev(dev) != 0) {
  4573. cnic_put(dev);
  4574. goto done;
  4575. }
  4576. if (!cnic_start_hw(dev))
  4577. cnic_ulp_start(dev);
  4578. }
  4579. cnic_rcv_netevent(cp, event, 0);
  4580. if (event == NETDEV_GOING_DOWN) {
  4581. cnic_ulp_stop(dev);
  4582. cnic_stop_hw(dev);
  4583. cnic_unregister_netdev(dev);
  4584. } else if (event == NETDEV_UNREGISTER) {
  4585. write_lock(&cnic_dev_lock);
  4586. list_del_init(&dev->list);
  4587. write_unlock(&cnic_dev_lock);
  4588. cnic_put(dev);
  4589. cnic_free_dev(dev);
  4590. goto done;
  4591. }
  4592. cnic_put(dev);
  4593. } else {
  4594. struct net_device *realdev;
  4595. u16 vid;
  4596. vid = cnic_get_vlan(netdev, &realdev);
  4597. if (realdev) {
  4598. dev = cnic_from_netdev(realdev);
  4599. if (dev) {
  4600. vid |= VLAN_TAG_PRESENT;
  4601. cnic_rcv_netevent(dev->cnic_priv, event, vid);
  4602. cnic_put(dev);
  4603. }
  4604. }
  4605. }
  4606. done:
  4607. return NOTIFY_DONE;
  4608. }
  4609. static struct notifier_block cnic_netdev_notifier = {
  4610. .notifier_call = cnic_netdev_event
  4611. };
  4612. static void cnic_release(void)
  4613. {
  4614. struct cnic_dev *dev;
  4615. struct cnic_uio_dev *udev;
  4616. while (!list_empty(&cnic_dev_list)) {
  4617. dev = list_entry(cnic_dev_list.next, struct cnic_dev, list);
  4618. if (test_bit(CNIC_F_CNIC_UP, &dev->flags)) {
  4619. cnic_ulp_stop(dev);
  4620. cnic_stop_hw(dev);
  4621. }
  4622. cnic_ulp_exit(dev);
  4623. cnic_unregister_netdev(dev);
  4624. list_del_init(&dev->list);
  4625. cnic_free_dev(dev);
  4626. }
  4627. while (!list_empty(&cnic_udev_list)) {
  4628. udev = list_entry(cnic_udev_list.next, struct cnic_uio_dev,
  4629. list);
  4630. cnic_free_uio(udev);
  4631. }
  4632. }
  4633. static int __init cnic_init(void)
  4634. {
  4635. int rc = 0;
  4636. pr_info("%s", version);
  4637. rc = register_netdevice_notifier(&cnic_netdev_notifier);
  4638. if (rc) {
  4639. cnic_release();
  4640. return rc;
  4641. }
  4642. cnic_wq = create_singlethread_workqueue("cnic_wq");
  4643. if (!cnic_wq) {
  4644. cnic_release();
  4645. unregister_netdevice_notifier(&cnic_netdev_notifier);
  4646. return -ENOMEM;
  4647. }
  4648. return 0;
  4649. }
  4650. static void __exit cnic_exit(void)
  4651. {
  4652. unregister_netdevice_notifier(&cnic_netdev_notifier);
  4653. cnic_release();
  4654. destroy_workqueue(cnic_wq);
  4655. }
  4656. module_init(cnic_init);
  4657. module_exit(cnic_exit);