cx23885.h 18 KB

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  1. /*
  2. * Driver for the Conexant CX23885 PCIe bridge
  3. *
  4. * Copyright (c) 2006 Steven Toth <stoth@linuxtv.org>
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; either version 2 of the License, or
  9. * (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. *
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  20. */
  21. #include <linux/pci.h>
  22. #include <linux/i2c.h>
  23. #include <linux/i2c-algo-bit.h>
  24. #include <linux/kdev_t.h>
  25. #include <linux/slab.h>
  26. #include <media/v4l2-device.h>
  27. #include <media/tuner.h>
  28. #include <media/tveeprom.h>
  29. #include <media/videobuf-dma-sg.h>
  30. #include <media/videobuf-dvb.h>
  31. #include <media/rc-core.h>
  32. #include "btcx-risc.h"
  33. #include "cx23885-reg.h"
  34. #include "media/cx2341x.h"
  35. #include <linux/version.h>
  36. #include <linux/mutex.h>
  37. #define CX23885_VERSION_CODE KERNEL_VERSION(0, 0, 2)
  38. #define UNSET (-1U)
  39. #define CX23885_MAXBOARDS 8
  40. /* Max number of inputs by card */
  41. #define MAX_CX23885_INPUT 8
  42. #define INPUT(nr) (&cx23885_boards[dev->board].input[nr])
  43. #define RESOURCE_OVERLAY 1
  44. #define RESOURCE_VIDEO 2
  45. #define RESOURCE_VBI 4
  46. #define BUFFER_TIMEOUT (HZ) /* 0.5 seconds */
  47. #define CX23885_BOARD_NOAUTO UNSET
  48. #define CX23885_BOARD_UNKNOWN 0
  49. #define CX23885_BOARD_HAUPPAUGE_HVR1800lp 1
  50. #define CX23885_BOARD_HAUPPAUGE_HVR1800 2
  51. #define CX23885_BOARD_HAUPPAUGE_HVR1250 3
  52. #define CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP 4
  53. #define CX23885_BOARD_HAUPPAUGE_HVR1500Q 5
  54. #define CX23885_BOARD_HAUPPAUGE_HVR1500 6
  55. #define CX23885_BOARD_HAUPPAUGE_HVR1200 7
  56. #define CX23885_BOARD_HAUPPAUGE_HVR1700 8
  57. #define CX23885_BOARD_HAUPPAUGE_HVR1400 9
  58. #define CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP 10
  59. #define CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP 11
  60. #define CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H 12
  61. #define CX23885_BOARD_COMPRO_VIDEOMATE_E650F 13
  62. #define CX23885_BOARD_TBS_6920 14
  63. #define CX23885_BOARD_TEVII_S470 15
  64. #define CX23885_BOARD_DVBWORLD_2005 16
  65. #define CX23885_BOARD_NETUP_DUAL_DVBS2_CI 17
  66. #define CX23885_BOARD_HAUPPAUGE_HVR1270 18
  67. #define CX23885_BOARD_HAUPPAUGE_HVR1275 19
  68. #define CX23885_BOARD_HAUPPAUGE_HVR1255 20
  69. #define CX23885_BOARD_HAUPPAUGE_HVR1210 21
  70. #define CX23885_BOARD_MYGICA_X8506 22
  71. #define CX23885_BOARD_MAGICPRO_PROHDTVE2 23
  72. #define CX23885_BOARD_HAUPPAUGE_HVR1850 24
  73. #define CX23885_BOARD_COMPRO_VIDEOMATE_E800 25
  74. #define CX23885_BOARD_HAUPPAUGE_HVR1290 26
  75. #define CX23885_BOARD_MYGICA_X8558PRO 27
  76. #define CX23885_BOARD_LEADTEK_WINFAST_PXTV1200 28
  77. #define CX23885_BOARD_GOTVIEW_X5_3D_HYBRID 29
  78. #define CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF 30
  79. #define GPIO_0 0x00000001
  80. #define GPIO_1 0x00000002
  81. #define GPIO_2 0x00000004
  82. #define GPIO_3 0x00000008
  83. #define GPIO_4 0x00000010
  84. #define GPIO_5 0x00000020
  85. #define GPIO_6 0x00000040
  86. #define GPIO_7 0x00000080
  87. #define GPIO_8 0x00000100
  88. #define GPIO_9 0x00000200
  89. #define GPIO_10 0x00000400
  90. #define GPIO_11 0x00000800
  91. #define GPIO_12 0x00001000
  92. #define GPIO_13 0x00002000
  93. #define GPIO_14 0x00004000
  94. #define GPIO_15 0x00008000
  95. /* Currently unsupported by the driver: PAL/H, NTSC/Kr, SECAM B/G/H/LC */
  96. #define CX23885_NORMS (\
  97. V4L2_STD_NTSC_M | V4L2_STD_NTSC_M_JP | V4L2_STD_NTSC_443 | \
  98. V4L2_STD_PAL_BG | V4L2_STD_PAL_DK | V4L2_STD_PAL_I | \
  99. V4L2_STD_PAL_M | V4L2_STD_PAL_N | V4L2_STD_PAL_Nc | \
  100. V4L2_STD_PAL_60 | V4L2_STD_SECAM_L | V4L2_STD_SECAM_DK)
  101. struct cx23885_fmt {
  102. char *name;
  103. u32 fourcc; /* v4l2 format id */
  104. int depth;
  105. int flags;
  106. u32 cxformat;
  107. };
  108. struct cx23885_ctrl {
  109. struct v4l2_queryctrl v;
  110. u32 off;
  111. u32 reg;
  112. u32 mask;
  113. u32 shift;
  114. };
  115. struct cx23885_tvnorm {
  116. char *name;
  117. v4l2_std_id id;
  118. u32 cxiformat;
  119. u32 cxoformat;
  120. };
  121. struct cx23885_fh {
  122. struct cx23885_dev *dev;
  123. enum v4l2_buf_type type;
  124. int radio;
  125. u32 resources;
  126. /* video overlay */
  127. struct v4l2_window win;
  128. struct v4l2_clip *clips;
  129. unsigned int nclips;
  130. /* video capture */
  131. struct cx23885_fmt *fmt;
  132. unsigned int width, height;
  133. /* vbi capture */
  134. struct videobuf_queue vidq;
  135. struct videobuf_queue vbiq;
  136. /* MPEG Encoder specifics ONLY */
  137. struct videobuf_queue mpegq;
  138. atomic_t v4l_reading;
  139. };
  140. enum cx23885_itype {
  141. CX23885_VMUX_COMPOSITE1 = 1,
  142. CX23885_VMUX_COMPOSITE2,
  143. CX23885_VMUX_COMPOSITE3,
  144. CX23885_VMUX_COMPOSITE4,
  145. CX23885_VMUX_SVIDEO,
  146. CX23885_VMUX_COMPONENT,
  147. CX23885_VMUX_TELEVISION,
  148. CX23885_VMUX_CABLE,
  149. CX23885_VMUX_DVB,
  150. CX23885_VMUX_DEBUG,
  151. CX23885_RADIO,
  152. };
  153. enum cx23885_src_sel_type {
  154. CX23885_SRC_SEL_EXT_656_VIDEO = 0,
  155. CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO
  156. };
  157. /* buffer for one video frame */
  158. struct cx23885_buffer {
  159. /* common v4l buffer stuff -- must be first */
  160. struct videobuf_buffer vb;
  161. /* cx23885 specific */
  162. unsigned int bpl;
  163. struct btcx_riscmem risc;
  164. struct cx23885_fmt *fmt;
  165. u32 count;
  166. };
  167. struct cx23885_input {
  168. enum cx23885_itype type;
  169. unsigned int vmux;
  170. u32 gpio0, gpio1, gpio2, gpio3;
  171. };
  172. typedef enum {
  173. CX23885_MPEG_UNDEFINED = 0,
  174. CX23885_MPEG_DVB,
  175. CX23885_ANALOG_VIDEO,
  176. CX23885_MPEG_ENCODER,
  177. } port_t;
  178. struct cx23885_board {
  179. char *name;
  180. port_t porta, portb, portc;
  181. unsigned int tuner_type;
  182. unsigned int radio_type;
  183. unsigned char tuner_addr;
  184. unsigned char radio_addr;
  185. /* Vendors can and do run the PCIe bridge at different
  186. * clock rates, driven physically by crystals on the PCBs.
  187. * The core has to accomodate this. This allows the user
  188. * to add new boards with new frequencys. The value is
  189. * expressed in Hz.
  190. *
  191. * The core framework will default this value based on
  192. * current designs, but it can vary.
  193. */
  194. u32 clk_freq;
  195. struct cx23885_input input[MAX_CX23885_INPUT];
  196. int ci_type; /* for NetUP */
  197. };
  198. struct cx23885_subid {
  199. u16 subvendor;
  200. u16 subdevice;
  201. u32 card;
  202. };
  203. struct cx23885_i2c {
  204. struct cx23885_dev *dev;
  205. int nr;
  206. /* i2c i/o */
  207. struct i2c_adapter i2c_adap;
  208. struct i2c_algo_bit_data i2c_algo;
  209. struct i2c_client i2c_client;
  210. u32 i2c_rc;
  211. /* 885 registers used for raw addess */
  212. u32 i2c_period;
  213. u32 reg_ctrl;
  214. u32 reg_stat;
  215. u32 reg_addr;
  216. u32 reg_rdata;
  217. u32 reg_wdata;
  218. };
  219. struct cx23885_dmaqueue {
  220. struct list_head active;
  221. struct list_head queued;
  222. struct timer_list timeout;
  223. struct btcx_riscmem stopper;
  224. u32 count;
  225. };
  226. struct cx23885_tsport {
  227. struct cx23885_dev *dev;
  228. int nr;
  229. int sram_chno;
  230. struct videobuf_dvb_frontends frontends;
  231. /* dma queues */
  232. struct cx23885_dmaqueue mpegq;
  233. u32 ts_packet_size;
  234. u32 ts_packet_count;
  235. int width;
  236. int height;
  237. spinlock_t slock;
  238. /* registers */
  239. u32 reg_gpcnt;
  240. u32 reg_gpcnt_ctl;
  241. u32 reg_dma_ctl;
  242. u32 reg_lngth;
  243. u32 reg_hw_sop_ctrl;
  244. u32 reg_gen_ctrl;
  245. u32 reg_bd_pkt_status;
  246. u32 reg_sop_status;
  247. u32 reg_fifo_ovfl_stat;
  248. u32 reg_vld_misc;
  249. u32 reg_ts_clk_en;
  250. u32 reg_ts_int_msk;
  251. u32 reg_ts_int_stat;
  252. u32 reg_src_sel;
  253. /* Default register vals */
  254. int pci_irqmask;
  255. u32 dma_ctl_val;
  256. u32 ts_int_msk_val;
  257. u32 gen_ctrl_val;
  258. u32 ts_clk_en_val;
  259. u32 src_sel_val;
  260. u32 vld_misc_val;
  261. u32 hw_sop_ctrl_val;
  262. /* Allow a single tsport to have multiple frontends */
  263. u32 num_frontends;
  264. void (*gate_ctrl)(struct cx23885_tsport *port, int open);
  265. void *port_priv;
  266. };
  267. struct cx23885_kernel_ir {
  268. struct cx23885_dev *cx;
  269. char *name;
  270. char *phys;
  271. struct rc_dev *rc;
  272. };
  273. struct cx23885_dev {
  274. atomic_t refcount;
  275. struct v4l2_device v4l2_dev;
  276. /* pci stuff */
  277. struct pci_dev *pci;
  278. unsigned char pci_rev, pci_lat;
  279. int pci_bus, pci_slot;
  280. u32 __iomem *lmmio;
  281. u8 __iomem *bmmio;
  282. int pci_irqmask;
  283. spinlock_t pci_irqmask_lock; /* protects mask reg too */
  284. int hwrevision;
  285. /* This valud is board specific and is used to configure the
  286. * AV core so we see nice clean and stable video and audio. */
  287. u32 clk_freq;
  288. /* I2C adapters: Master 1 & 2 (External) & Master 3 (Internal only) */
  289. struct cx23885_i2c i2c_bus[3];
  290. int nr;
  291. struct mutex lock;
  292. struct mutex gpio_lock;
  293. /* board details */
  294. unsigned int board;
  295. char name[32];
  296. struct cx23885_tsport ts1, ts2;
  297. /* sram configuration */
  298. struct sram_channel *sram_channels;
  299. enum {
  300. CX23885_BRIDGE_UNDEFINED = 0,
  301. CX23885_BRIDGE_885 = 885,
  302. CX23885_BRIDGE_887 = 887,
  303. CX23885_BRIDGE_888 = 888,
  304. } bridge;
  305. /* Analog video */
  306. u32 resources;
  307. unsigned int input;
  308. u32 tvaudio;
  309. v4l2_std_id tvnorm;
  310. unsigned int tuner_type;
  311. unsigned char tuner_addr;
  312. unsigned int radio_type;
  313. unsigned char radio_addr;
  314. unsigned int has_radio;
  315. struct v4l2_subdev *sd_cx25840;
  316. struct work_struct cx25840_work;
  317. /* Infrared */
  318. struct v4l2_subdev *sd_ir;
  319. struct work_struct ir_rx_work;
  320. unsigned long ir_rx_notifications;
  321. struct work_struct ir_tx_work;
  322. unsigned long ir_tx_notifications;
  323. struct cx23885_kernel_ir *kernel_ir;
  324. atomic_t ir_input_stopping;
  325. /* V4l */
  326. u32 freq;
  327. struct video_device *video_dev;
  328. struct video_device *vbi_dev;
  329. struct video_device *radio_dev;
  330. struct cx23885_dmaqueue vidq;
  331. struct cx23885_dmaqueue vbiq;
  332. spinlock_t slock;
  333. /* MPEG Encoder ONLY settings */
  334. u32 cx23417_mailbox;
  335. struct cx2341x_mpeg_params mpeg_params;
  336. struct video_device *v4l_device;
  337. atomic_t v4l_reader_count;
  338. struct cx23885_tvnorm encodernorm;
  339. };
  340. static inline struct cx23885_dev *to_cx23885(struct v4l2_device *v4l2_dev)
  341. {
  342. return container_of(v4l2_dev, struct cx23885_dev, v4l2_dev);
  343. }
  344. #define call_all(dev, o, f, args...) \
  345. v4l2_device_call_all(&dev->v4l2_dev, 0, o, f, ##args)
  346. #define CX23885_HW_888_IR (1 << 0)
  347. #define CX23885_HW_AV_CORE (1 << 1)
  348. #define call_hw(dev, grpid, o, f, args...) \
  349. v4l2_device_call_all(&dev->v4l2_dev, grpid, o, f, ##args)
  350. extern struct v4l2_subdev *cx23885_find_hw(struct cx23885_dev *dev, u32 hw);
  351. #define SRAM_CH01 0 /* Video A */
  352. #define SRAM_CH02 1 /* VBI A */
  353. #define SRAM_CH03 2 /* Video B */
  354. #define SRAM_CH04 3 /* Transport via B */
  355. #define SRAM_CH05 4 /* VBI B */
  356. #define SRAM_CH06 5 /* Video C */
  357. #define SRAM_CH07 6 /* Transport via C */
  358. #define SRAM_CH08 7 /* Audio Internal A */
  359. #define SRAM_CH09 8 /* Audio Internal B */
  360. #define SRAM_CH10 9 /* Audio External */
  361. #define SRAM_CH11 10 /* COMB_3D_N */
  362. #define SRAM_CH12 11 /* Comb 3D N1 */
  363. #define SRAM_CH13 12 /* Comb 3D N2 */
  364. #define SRAM_CH14 13 /* MOE Vid */
  365. #define SRAM_CH15 14 /* MOE RSLT */
  366. struct sram_channel {
  367. char *name;
  368. u32 cmds_start;
  369. u32 ctrl_start;
  370. u32 cdt;
  371. u32 fifo_start;
  372. u32 fifo_size;
  373. u32 ptr1_reg;
  374. u32 ptr2_reg;
  375. u32 cnt1_reg;
  376. u32 cnt2_reg;
  377. u32 jumponly;
  378. };
  379. /* ----------------------------------------------------------- */
  380. #define cx_read(reg) readl(dev->lmmio + ((reg)>>2))
  381. #define cx_write(reg, value) writel((value), dev->lmmio + ((reg)>>2))
  382. #define cx_andor(reg, mask, value) \
  383. writel((readl(dev->lmmio+((reg)>>2)) & ~(mask)) |\
  384. ((value) & (mask)), dev->lmmio+((reg)>>2))
  385. #define cx_set(reg, bit) cx_andor((reg), (bit), (bit))
  386. #define cx_clear(reg, bit) cx_andor((reg), (bit), 0)
  387. /* ----------------------------------------------------------- */
  388. /* cx23885-core.c */
  389. extern int cx23885_sram_channel_setup(struct cx23885_dev *dev,
  390. struct sram_channel *ch,
  391. unsigned int bpl, u32 risc);
  392. extern void cx23885_sram_channel_dump(struct cx23885_dev *dev,
  393. struct sram_channel *ch);
  394. extern int cx23885_risc_stopper(struct pci_dev *pci, struct btcx_riscmem *risc,
  395. u32 reg, u32 mask, u32 value);
  396. extern int cx23885_risc_buffer(struct pci_dev *pci, struct btcx_riscmem *risc,
  397. struct scatterlist *sglist,
  398. unsigned int top_offset, unsigned int bottom_offset,
  399. unsigned int bpl, unsigned int padding, unsigned int lines);
  400. void cx23885_cancel_buffers(struct cx23885_tsport *port);
  401. extern int cx23885_restart_queue(struct cx23885_tsport *port,
  402. struct cx23885_dmaqueue *q);
  403. extern void cx23885_wakeup(struct cx23885_tsport *port,
  404. struct cx23885_dmaqueue *q, u32 count);
  405. extern void cx23885_gpio_set(struct cx23885_dev *dev, u32 mask);
  406. extern void cx23885_gpio_clear(struct cx23885_dev *dev, u32 mask);
  407. extern u32 cx23885_gpio_get(struct cx23885_dev *dev, u32 mask);
  408. extern void cx23885_gpio_enable(struct cx23885_dev *dev, u32 mask,
  409. int asoutput);
  410. extern void cx23885_irq_add_enable(struct cx23885_dev *dev, u32 mask);
  411. extern void cx23885_irq_enable(struct cx23885_dev *dev, u32 mask);
  412. extern void cx23885_irq_disable(struct cx23885_dev *dev, u32 mask);
  413. extern void cx23885_irq_remove(struct cx23885_dev *dev, u32 mask);
  414. /* ----------------------------------------------------------- */
  415. /* cx23885-cards.c */
  416. extern struct cx23885_board cx23885_boards[];
  417. extern const unsigned int cx23885_bcount;
  418. extern struct cx23885_subid cx23885_subids[];
  419. extern const unsigned int cx23885_idcount;
  420. extern int cx23885_tuner_callback(void *priv, int component,
  421. int command, int arg);
  422. extern void cx23885_card_list(struct cx23885_dev *dev);
  423. extern int cx23885_ir_init(struct cx23885_dev *dev);
  424. extern void cx23885_ir_pci_int_enable(struct cx23885_dev *dev);
  425. extern void cx23885_ir_fini(struct cx23885_dev *dev);
  426. extern void cx23885_gpio_setup(struct cx23885_dev *dev);
  427. extern void cx23885_card_setup(struct cx23885_dev *dev);
  428. extern void cx23885_card_setup_pre_i2c(struct cx23885_dev *dev);
  429. extern int cx23885_dvb_register(struct cx23885_tsport *port);
  430. extern int cx23885_dvb_unregister(struct cx23885_tsport *port);
  431. extern int cx23885_buf_prepare(struct videobuf_queue *q,
  432. struct cx23885_tsport *port,
  433. struct cx23885_buffer *buf,
  434. enum v4l2_field field);
  435. extern void cx23885_buf_queue(struct cx23885_tsport *port,
  436. struct cx23885_buffer *buf);
  437. extern void cx23885_free_buffer(struct videobuf_queue *q,
  438. struct cx23885_buffer *buf);
  439. /* ----------------------------------------------------------- */
  440. /* cx23885-video.c */
  441. /* Video */
  442. extern int cx23885_video_register(struct cx23885_dev *dev);
  443. extern void cx23885_video_unregister(struct cx23885_dev *dev);
  444. extern int cx23885_video_irq(struct cx23885_dev *dev, u32 status);
  445. /* ----------------------------------------------------------- */
  446. /* cx23885-vbi.c */
  447. extern int cx23885_vbi_fmt(struct file *file, void *priv,
  448. struct v4l2_format *f);
  449. extern void cx23885_vbi_timeout(unsigned long data);
  450. extern struct videobuf_queue_ops cx23885_vbi_qops;
  451. /* cx23885-i2c.c */
  452. extern int cx23885_i2c_register(struct cx23885_i2c *bus);
  453. extern int cx23885_i2c_unregister(struct cx23885_i2c *bus);
  454. extern void cx23885_av_clk(struct cx23885_dev *dev, int enable);
  455. /* ----------------------------------------------------------- */
  456. /* cx23885-417.c */
  457. extern int cx23885_417_register(struct cx23885_dev *dev);
  458. extern void cx23885_417_unregister(struct cx23885_dev *dev);
  459. extern int cx23885_irq_417(struct cx23885_dev *dev, u32 status);
  460. extern void cx23885_417_check_encoder(struct cx23885_dev *dev);
  461. extern void cx23885_mc417_init(struct cx23885_dev *dev);
  462. extern int mc417_memory_read(struct cx23885_dev *dev, u32 address, u32 *value);
  463. extern int mc417_memory_write(struct cx23885_dev *dev, u32 address, u32 value);
  464. extern int mc417_register_read(struct cx23885_dev *dev,
  465. u16 address, u32 *value);
  466. extern int mc417_register_write(struct cx23885_dev *dev,
  467. u16 address, u32 value);
  468. extern void mc417_gpio_set(struct cx23885_dev *dev, u32 mask);
  469. extern void mc417_gpio_clear(struct cx23885_dev *dev, u32 mask);
  470. extern void mc417_gpio_enable(struct cx23885_dev *dev, u32 mask, int asoutput);
  471. /* ----------------------------------------------------------- */
  472. /* tv norms */
  473. static inline unsigned int norm_maxw(v4l2_std_id norm)
  474. {
  475. return (norm & (V4L2_STD_MN & ~V4L2_STD_PAL_Nc)) ? 720 : 768;
  476. }
  477. static inline unsigned int norm_maxh(v4l2_std_id norm)
  478. {
  479. return (norm & V4L2_STD_625_50) ? 576 : 480;
  480. }
  481. static inline unsigned int norm_swidth(v4l2_std_id norm)
  482. {
  483. return (norm & (V4L2_STD_MN & ~V4L2_STD_PAL_Nc)) ? 754 : 922;
  484. }