cx23885-dvb.c 34 KB

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  1. /*
  2. * Driver for the Conexant CX23885 PCIe bridge
  3. *
  4. * Copyright (c) 2006 Steven Toth <stoth@linuxtv.org>
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; either version 2 of the License, or
  9. * (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. *
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  20. */
  21. #include <linux/module.h>
  22. #include <linux/init.h>
  23. #include <linux/device.h>
  24. #include <linux/fs.h>
  25. #include <linux/kthread.h>
  26. #include <linux/file.h>
  27. #include <linux/suspend.h>
  28. #include "cx23885.h"
  29. #include <media/v4l2-common.h>
  30. #include "dvb_ca_en50221.h"
  31. #include "s5h1409.h"
  32. #include "s5h1411.h"
  33. #include "mt2131.h"
  34. #include "tda8290.h"
  35. #include "tda18271.h"
  36. #include "lgdt330x.h"
  37. #include "xc5000.h"
  38. #include "max2165.h"
  39. #include "tda10048.h"
  40. #include "tuner-xc2028.h"
  41. #include "tuner-simple.h"
  42. #include "dib7000p.h"
  43. #include "dibx000_common.h"
  44. #include "zl10353.h"
  45. #include "stv0900.h"
  46. #include "stv0900_reg.h"
  47. #include "stv6110.h"
  48. #include "lnbh24.h"
  49. #include "cx24116.h"
  50. #include "cimax2.h"
  51. #include "lgs8gxx.h"
  52. #include "netup-eeprom.h"
  53. #include "netup-init.h"
  54. #include "lgdt3305.h"
  55. #include "atbm8830.h"
  56. #include "ds3000.h"
  57. #include "cx23885-f300.h"
  58. #include "altera-ci.h"
  59. #include "stv0367.h"
  60. static unsigned int debug;
  61. #define dprintk(level, fmt, arg...)\
  62. do { if (debug >= level)\
  63. printk(KERN_DEBUG "%s/0: " fmt, dev->name, ## arg);\
  64. } while (0)
  65. /* ------------------------------------------------------------------ */
  66. static unsigned int alt_tuner;
  67. module_param(alt_tuner, int, 0644);
  68. MODULE_PARM_DESC(alt_tuner, "Enable alternate tuner configuration");
  69. DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr);
  70. /* ------------------------------------------------------------------ */
  71. static int dvb_buf_setup(struct videobuf_queue *q,
  72. unsigned int *count, unsigned int *size)
  73. {
  74. struct cx23885_tsport *port = q->priv_data;
  75. port->ts_packet_size = 188 * 4;
  76. port->ts_packet_count = 32;
  77. *size = port->ts_packet_size * port->ts_packet_count;
  78. *count = 32;
  79. return 0;
  80. }
  81. static int dvb_buf_prepare(struct videobuf_queue *q,
  82. struct videobuf_buffer *vb, enum v4l2_field field)
  83. {
  84. struct cx23885_tsport *port = q->priv_data;
  85. return cx23885_buf_prepare(q, port, (struct cx23885_buffer *)vb, field);
  86. }
  87. static void dvb_buf_queue(struct videobuf_queue *q, struct videobuf_buffer *vb)
  88. {
  89. struct cx23885_tsport *port = q->priv_data;
  90. cx23885_buf_queue(port, (struct cx23885_buffer *)vb);
  91. }
  92. static void dvb_buf_release(struct videobuf_queue *q,
  93. struct videobuf_buffer *vb)
  94. {
  95. cx23885_free_buffer(q, (struct cx23885_buffer *)vb);
  96. }
  97. static void cx23885_dvb_gate_ctrl(struct cx23885_tsport *port, int open)
  98. {
  99. struct videobuf_dvb_frontends *f;
  100. struct videobuf_dvb_frontend *fe;
  101. f = &port->frontends;
  102. if (f->gate <= 1) /* undefined or fe0 */
  103. fe = videobuf_dvb_get_frontend(f, 1);
  104. else
  105. fe = videobuf_dvb_get_frontend(f, f->gate);
  106. if (fe && fe->dvb.frontend && fe->dvb.frontend->ops.i2c_gate_ctrl)
  107. fe->dvb.frontend->ops.i2c_gate_ctrl(fe->dvb.frontend, open);
  108. }
  109. static struct videobuf_queue_ops dvb_qops = {
  110. .buf_setup = dvb_buf_setup,
  111. .buf_prepare = dvb_buf_prepare,
  112. .buf_queue = dvb_buf_queue,
  113. .buf_release = dvb_buf_release,
  114. };
  115. static struct s5h1409_config hauppauge_generic_config = {
  116. .demod_address = 0x32 >> 1,
  117. .output_mode = S5H1409_SERIAL_OUTPUT,
  118. .gpio = S5H1409_GPIO_ON,
  119. .qam_if = 44000,
  120. .inversion = S5H1409_INVERSION_OFF,
  121. .status_mode = S5H1409_DEMODLOCKING,
  122. .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
  123. };
  124. static struct tda10048_config hauppauge_hvr1200_config = {
  125. .demod_address = 0x10 >> 1,
  126. .output_mode = TDA10048_SERIAL_OUTPUT,
  127. .fwbulkwritelen = TDA10048_BULKWRITE_200,
  128. .inversion = TDA10048_INVERSION_ON,
  129. .dtv6_if_freq_khz = TDA10048_IF_3300,
  130. .dtv7_if_freq_khz = TDA10048_IF_3800,
  131. .dtv8_if_freq_khz = TDA10048_IF_4300,
  132. .clk_freq_khz = TDA10048_CLK_16000,
  133. };
  134. static struct tda10048_config hauppauge_hvr1210_config = {
  135. .demod_address = 0x10 >> 1,
  136. .output_mode = TDA10048_SERIAL_OUTPUT,
  137. .fwbulkwritelen = TDA10048_BULKWRITE_200,
  138. .inversion = TDA10048_INVERSION_ON,
  139. .dtv6_if_freq_khz = TDA10048_IF_3300,
  140. .dtv7_if_freq_khz = TDA10048_IF_3500,
  141. .dtv8_if_freq_khz = TDA10048_IF_4000,
  142. .clk_freq_khz = TDA10048_CLK_16000,
  143. };
  144. static struct s5h1409_config hauppauge_ezqam_config = {
  145. .demod_address = 0x32 >> 1,
  146. .output_mode = S5H1409_SERIAL_OUTPUT,
  147. .gpio = S5H1409_GPIO_OFF,
  148. .qam_if = 4000,
  149. .inversion = S5H1409_INVERSION_ON,
  150. .status_mode = S5H1409_DEMODLOCKING,
  151. .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
  152. };
  153. static struct s5h1409_config hauppauge_hvr1800lp_config = {
  154. .demod_address = 0x32 >> 1,
  155. .output_mode = S5H1409_SERIAL_OUTPUT,
  156. .gpio = S5H1409_GPIO_OFF,
  157. .qam_if = 44000,
  158. .inversion = S5H1409_INVERSION_OFF,
  159. .status_mode = S5H1409_DEMODLOCKING,
  160. .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
  161. };
  162. static struct s5h1409_config hauppauge_hvr1500_config = {
  163. .demod_address = 0x32 >> 1,
  164. .output_mode = S5H1409_SERIAL_OUTPUT,
  165. .gpio = S5H1409_GPIO_OFF,
  166. .inversion = S5H1409_INVERSION_OFF,
  167. .status_mode = S5H1409_DEMODLOCKING,
  168. .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
  169. };
  170. static struct mt2131_config hauppauge_generic_tunerconfig = {
  171. 0x61
  172. };
  173. static struct lgdt330x_config fusionhdtv_5_express = {
  174. .demod_address = 0x0e,
  175. .demod_chip = LGDT3303,
  176. .serial_mpeg = 0x40,
  177. };
  178. static struct s5h1409_config hauppauge_hvr1500q_config = {
  179. .demod_address = 0x32 >> 1,
  180. .output_mode = S5H1409_SERIAL_OUTPUT,
  181. .gpio = S5H1409_GPIO_ON,
  182. .qam_if = 44000,
  183. .inversion = S5H1409_INVERSION_OFF,
  184. .status_mode = S5H1409_DEMODLOCKING,
  185. .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
  186. };
  187. static struct s5h1409_config dvico_s5h1409_config = {
  188. .demod_address = 0x32 >> 1,
  189. .output_mode = S5H1409_SERIAL_OUTPUT,
  190. .gpio = S5H1409_GPIO_ON,
  191. .qam_if = 44000,
  192. .inversion = S5H1409_INVERSION_OFF,
  193. .status_mode = S5H1409_DEMODLOCKING,
  194. .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
  195. };
  196. static struct s5h1411_config dvico_s5h1411_config = {
  197. .output_mode = S5H1411_SERIAL_OUTPUT,
  198. .gpio = S5H1411_GPIO_ON,
  199. .qam_if = S5H1411_IF_44000,
  200. .vsb_if = S5H1411_IF_44000,
  201. .inversion = S5H1411_INVERSION_OFF,
  202. .status_mode = S5H1411_DEMODLOCKING,
  203. .mpeg_timing = S5H1411_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
  204. };
  205. static struct s5h1411_config hcw_s5h1411_config = {
  206. .output_mode = S5H1411_SERIAL_OUTPUT,
  207. .gpio = S5H1411_GPIO_OFF,
  208. .vsb_if = S5H1411_IF_44000,
  209. .qam_if = S5H1411_IF_4000,
  210. .inversion = S5H1411_INVERSION_ON,
  211. .status_mode = S5H1411_DEMODLOCKING,
  212. .mpeg_timing = S5H1411_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
  213. };
  214. static struct xc5000_config hauppauge_hvr1500q_tunerconfig = {
  215. .i2c_address = 0x61,
  216. .if_khz = 5380,
  217. };
  218. static struct xc5000_config dvico_xc5000_tunerconfig = {
  219. .i2c_address = 0x64,
  220. .if_khz = 5380,
  221. };
  222. static struct tda829x_config tda829x_no_probe = {
  223. .probe_tuner = TDA829X_DONT_PROBE,
  224. };
  225. static struct tda18271_std_map hauppauge_tda18271_std_map = {
  226. .atsc_6 = { .if_freq = 5380, .agc_mode = 3, .std = 3,
  227. .if_lvl = 6, .rfagc_top = 0x37 },
  228. .qam_6 = { .if_freq = 4000, .agc_mode = 3, .std = 0,
  229. .if_lvl = 6, .rfagc_top = 0x37 },
  230. };
  231. static struct tda18271_std_map hauppauge_hvr1200_tda18271_std_map = {
  232. .dvbt_6 = { .if_freq = 3300, .agc_mode = 3, .std = 4,
  233. .if_lvl = 1, .rfagc_top = 0x37, },
  234. .dvbt_7 = { .if_freq = 3800, .agc_mode = 3, .std = 5,
  235. .if_lvl = 1, .rfagc_top = 0x37, },
  236. .dvbt_8 = { .if_freq = 4300, .agc_mode = 3, .std = 6,
  237. .if_lvl = 1, .rfagc_top = 0x37, },
  238. };
  239. static struct tda18271_config hauppauge_tda18271_config = {
  240. .std_map = &hauppauge_tda18271_std_map,
  241. .gate = TDA18271_GATE_ANALOG,
  242. .output_opt = TDA18271_OUTPUT_LT_OFF,
  243. };
  244. static struct tda18271_config hauppauge_hvr1200_tuner_config = {
  245. .std_map = &hauppauge_hvr1200_tda18271_std_map,
  246. .gate = TDA18271_GATE_ANALOG,
  247. .output_opt = TDA18271_OUTPUT_LT_OFF,
  248. };
  249. static struct tda18271_config hauppauge_hvr1210_tuner_config = {
  250. .gate = TDA18271_GATE_DIGITAL,
  251. .output_opt = TDA18271_OUTPUT_LT_OFF,
  252. };
  253. static struct tda18271_std_map hauppauge_hvr127x_std_map = {
  254. .atsc_6 = { .if_freq = 3250, .agc_mode = 3, .std = 4,
  255. .if_lvl = 1, .rfagc_top = 0x58 },
  256. .qam_6 = { .if_freq = 4000, .agc_mode = 3, .std = 5,
  257. .if_lvl = 1, .rfagc_top = 0x58 },
  258. };
  259. static struct tda18271_config hauppauge_hvr127x_config = {
  260. .std_map = &hauppauge_hvr127x_std_map,
  261. .output_opt = TDA18271_OUTPUT_LT_OFF,
  262. };
  263. static struct lgdt3305_config hauppauge_lgdt3305_config = {
  264. .i2c_addr = 0x0e,
  265. .mpeg_mode = LGDT3305_MPEG_SERIAL,
  266. .tpclk_edge = LGDT3305_TPCLK_FALLING_EDGE,
  267. .tpvalid_polarity = LGDT3305_TP_VALID_HIGH,
  268. .deny_i2c_rptr = 1,
  269. .spectral_inversion = 1,
  270. .qam_if_khz = 4000,
  271. .vsb_if_khz = 3250,
  272. };
  273. static struct dibx000_agc_config xc3028_agc_config = {
  274. BAND_VHF | BAND_UHF, /* band_caps */
  275. /* P_agc_use_sd_mod1=0, P_agc_use_sd_mod2=0, P_agc_freq_pwm_div=0,
  276. * P_agc_inv_pwm1=0, P_agc_inv_pwm2=0,
  277. * P_agc_inh_dc_rv_est=0, P_agc_time_est=3, P_agc_freeze=0,
  278. * P_agc_nb_est=2, P_agc_write=0
  279. */
  280. (0 << 15) | (0 << 14) | (0 << 11) | (0 << 10) | (0 << 9) | (0 << 8) |
  281. (3 << 5) | (0 << 4) | (2 << 1) | (0 << 0), /* setup */
  282. 712, /* inv_gain */
  283. 21, /* time_stabiliz */
  284. 0, /* alpha_level */
  285. 118, /* thlock */
  286. 0, /* wbd_inv */
  287. 2867, /* wbd_ref */
  288. 0, /* wbd_sel */
  289. 2, /* wbd_alpha */
  290. 0, /* agc1_max */
  291. 0, /* agc1_min */
  292. 39718, /* agc2_max */
  293. 9930, /* agc2_min */
  294. 0, /* agc1_pt1 */
  295. 0, /* agc1_pt2 */
  296. 0, /* agc1_pt3 */
  297. 0, /* agc1_slope1 */
  298. 0, /* agc1_slope2 */
  299. 0, /* agc2_pt1 */
  300. 128, /* agc2_pt2 */
  301. 29, /* agc2_slope1 */
  302. 29, /* agc2_slope2 */
  303. 17, /* alpha_mant */
  304. 27, /* alpha_exp */
  305. 23, /* beta_mant */
  306. 51, /* beta_exp */
  307. 1, /* perform_agc_softsplit */
  308. };
  309. /* PLL Configuration for COFDM BW_MHz = 8.000000
  310. * With external clock = 30.000000 */
  311. static struct dibx000_bandwidth_config xc3028_bw_config = {
  312. 60000, /* internal */
  313. 30000, /* sampling */
  314. 1, /* pll_cfg: prediv */
  315. 8, /* pll_cfg: ratio */
  316. 3, /* pll_cfg: range */
  317. 1, /* pll_cfg: reset */
  318. 0, /* pll_cfg: bypass */
  319. 0, /* misc: refdiv */
  320. 0, /* misc: bypclk_div */
  321. 1, /* misc: IO_CLK_en_core */
  322. 1, /* misc: ADClkSrc */
  323. 0, /* misc: modulo */
  324. (3 << 14) | (1 << 12) | (524 << 0), /* sad_cfg: refsel, sel, freq_15k */
  325. (1 << 25) | 5816102, /* ifreq = 5.200000 MHz */
  326. 20452225, /* timf */
  327. 30000000 /* xtal_hz */
  328. };
  329. static struct dib7000p_config hauppauge_hvr1400_dib7000_config = {
  330. .output_mpeg2_in_188_bytes = 1,
  331. .hostbus_diversity = 1,
  332. .tuner_is_baseband = 0,
  333. .update_lna = NULL,
  334. .agc_config_count = 1,
  335. .agc = &xc3028_agc_config,
  336. .bw = &xc3028_bw_config,
  337. .gpio_dir = DIB7000P_GPIO_DEFAULT_DIRECTIONS,
  338. .gpio_val = DIB7000P_GPIO_DEFAULT_VALUES,
  339. .gpio_pwm_pos = DIB7000P_GPIO_DEFAULT_PWM_POS,
  340. .pwm_freq_div = 0,
  341. .agc_control = NULL,
  342. .spur_protect = 0,
  343. .output_mode = OUTMODE_MPEG2_SERIAL,
  344. };
  345. static struct zl10353_config dvico_fusionhdtv_xc3028 = {
  346. .demod_address = 0x0f,
  347. .if2 = 45600,
  348. .no_tuner = 1,
  349. .disable_i2c_gate_ctrl = 1,
  350. };
  351. static struct stv0900_reg stv0900_ts_regs[] = {
  352. { R0900_TSGENERAL, 0x00 },
  353. { R0900_P1_TSSPEED, 0x40 },
  354. { R0900_P2_TSSPEED, 0x40 },
  355. { R0900_P1_TSCFGM, 0xc0 },
  356. { R0900_P2_TSCFGM, 0xc0 },
  357. { R0900_P1_TSCFGH, 0xe0 },
  358. { R0900_P2_TSCFGH, 0xe0 },
  359. { R0900_P1_TSCFGL, 0x20 },
  360. { R0900_P2_TSCFGL, 0x20 },
  361. { 0xffff, 0xff }, /* terminate */
  362. };
  363. static struct stv0900_config netup_stv0900_config = {
  364. .demod_address = 0x68,
  365. .demod_mode = 1, /* dual */
  366. .xtal = 8000000,
  367. .clkmode = 3,/* 0-CLKI, 2-XTALI, else AUTO */
  368. .diseqc_mode = 2,/* 2/3 PWM */
  369. .ts_config_regs = stv0900_ts_regs,
  370. .tun1_maddress = 0,/* 0x60 */
  371. .tun2_maddress = 3,/* 0x63 */
  372. .tun1_adc = 1,/* 1 Vpp */
  373. .tun2_adc = 1,/* 1 Vpp */
  374. };
  375. static struct stv6110_config netup_stv6110_tunerconfig_a = {
  376. .i2c_address = 0x60,
  377. .mclk = 16000000,
  378. .clk_div = 1,
  379. .gain = 8, /* +16 dB - maximum gain */
  380. };
  381. static struct stv6110_config netup_stv6110_tunerconfig_b = {
  382. .i2c_address = 0x63,
  383. .mclk = 16000000,
  384. .clk_div = 1,
  385. .gain = 8, /* +16 dB - maximum gain */
  386. };
  387. static struct cx24116_config tbs_cx24116_config = {
  388. .demod_address = 0x55,
  389. };
  390. static struct ds3000_config tevii_ds3000_config = {
  391. .demod_address = 0x68,
  392. };
  393. static struct cx24116_config dvbworld_cx24116_config = {
  394. .demod_address = 0x05,
  395. };
  396. static struct lgs8gxx_config mygica_x8506_lgs8gl5_config = {
  397. .prod = LGS8GXX_PROD_LGS8GL5,
  398. .demod_address = 0x19,
  399. .serial_ts = 0,
  400. .ts_clk_pol = 1,
  401. .ts_clk_gated = 1,
  402. .if_clk_freq = 30400, /* 30.4 MHz */
  403. .if_freq = 5380, /* 5.38 MHz */
  404. .if_neg_center = 1,
  405. .ext_adc = 0,
  406. .adc_signed = 0,
  407. .if_neg_edge = 0,
  408. };
  409. static struct xc5000_config mygica_x8506_xc5000_config = {
  410. .i2c_address = 0x61,
  411. .if_khz = 5380,
  412. };
  413. static int cx23885_dvb_set_frontend(struct dvb_frontend *fe,
  414. struct dvb_frontend_parameters *param)
  415. {
  416. struct cx23885_tsport *port = fe->dvb->priv;
  417. struct cx23885_dev *dev = port->dev;
  418. switch (dev->board) {
  419. case CX23885_BOARD_HAUPPAUGE_HVR1275:
  420. switch (param->u.vsb.modulation) {
  421. case VSB_8:
  422. cx23885_gpio_clear(dev, GPIO_5);
  423. break;
  424. case QAM_64:
  425. case QAM_256:
  426. default:
  427. cx23885_gpio_set(dev, GPIO_5);
  428. break;
  429. }
  430. break;
  431. case CX23885_BOARD_MYGICA_X8506:
  432. case CX23885_BOARD_MAGICPRO_PROHDTVE2:
  433. /* Select Digital TV */
  434. cx23885_gpio_set(dev, GPIO_0);
  435. break;
  436. }
  437. return 0;
  438. }
  439. static int cx23885_dvb_fe_ioctl_override(struct dvb_frontend *fe,
  440. unsigned int cmd, void *parg,
  441. unsigned int stage)
  442. {
  443. int err = 0;
  444. switch (stage) {
  445. case DVB_FE_IOCTL_PRE:
  446. switch (cmd) {
  447. case FE_SET_FRONTEND:
  448. err = cx23885_dvb_set_frontend(fe,
  449. (struct dvb_frontend_parameters *) parg);
  450. break;
  451. }
  452. break;
  453. case DVB_FE_IOCTL_POST:
  454. /* no post-ioctl handling required */
  455. break;
  456. }
  457. return err;
  458. };
  459. static struct lgs8gxx_config magicpro_prohdtve2_lgs8g75_config = {
  460. .prod = LGS8GXX_PROD_LGS8G75,
  461. .demod_address = 0x19,
  462. .serial_ts = 0,
  463. .ts_clk_pol = 1,
  464. .ts_clk_gated = 1,
  465. .if_clk_freq = 30400, /* 30.4 MHz */
  466. .if_freq = 6500, /* 6.50 MHz */
  467. .if_neg_center = 1,
  468. .ext_adc = 0,
  469. .adc_signed = 1,
  470. .adc_vpp = 2, /* 1.6 Vpp */
  471. .if_neg_edge = 1,
  472. };
  473. static struct xc5000_config magicpro_prohdtve2_xc5000_config = {
  474. .i2c_address = 0x61,
  475. .if_khz = 6500,
  476. };
  477. static struct atbm8830_config mygica_x8558pro_atbm8830_cfg1 = {
  478. .prod = ATBM8830_PROD_8830,
  479. .demod_address = 0x44,
  480. .serial_ts = 0,
  481. .ts_sampling_edge = 1,
  482. .ts_clk_gated = 0,
  483. .osc_clk_freq = 30400, /* in kHz */
  484. .if_freq = 0, /* zero IF */
  485. .zif_swap_iq = 1,
  486. .agc_min = 0x2E,
  487. .agc_max = 0xFF,
  488. .agc_hold_loop = 0,
  489. };
  490. static struct max2165_config mygic_x8558pro_max2165_cfg1 = {
  491. .i2c_address = 0x60,
  492. .osc_clk = 20
  493. };
  494. static struct atbm8830_config mygica_x8558pro_atbm8830_cfg2 = {
  495. .prod = ATBM8830_PROD_8830,
  496. .demod_address = 0x44,
  497. .serial_ts = 1,
  498. .ts_sampling_edge = 1,
  499. .ts_clk_gated = 0,
  500. .osc_clk_freq = 30400, /* in kHz */
  501. .if_freq = 0, /* zero IF */
  502. .zif_swap_iq = 1,
  503. .agc_min = 0x2E,
  504. .agc_max = 0xFF,
  505. .agc_hold_loop = 0,
  506. };
  507. static struct max2165_config mygic_x8558pro_max2165_cfg2 = {
  508. .i2c_address = 0x60,
  509. .osc_clk = 20
  510. };
  511. static struct stv0367_config netup_stv0367_config[] = {
  512. {
  513. .demod_address = 0x1c,
  514. .xtal = 27000000,
  515. .if_khz = 4500,
  516. .if_iq_mode = 0,
  517. .ts_mode = 1,
  518. .clk_pol = 0,
  519. }, {
  520. .demod_address = 0x1d,
  521. .xtal = 27000000,
  522. .if_khz = 4500,
  523. .if_iq_mode = 0,
  524. .ts_mode = 1,
  525. .clk_pol = 0,
  526. },
  527. };
  528. static struct xc5000_config netup_xc5000_config[] = {
  529. {
  530. .i2c_address = 0x61,
  531. .if_khz = 4500,
  532. }, {
  533. .i2c_address = 0x64,
  534. .if_khz = 4500,
  535. },
  536. };
  537. int netup_altera_fpga_rw(void *device, int flag, int data, int read)
  538. {
  539. struct cx23885_dev *dev = (struct cx23885_dev *)device;
  540. unsigned long timeout = jiffies + msecs_to_jiffies(1);
  541. int mem = 0;
  542. cx_set(MC417_RWD, ALT_RD | ALT_WR | ALT_CS);
  543. if (read)
  544. cx_set(MC417_OEN, ALT_DATA);
  545. else {
  546. cx_clear(MC417_OEN, ALT_DATA);/* D0-D7 out */
  547. mem = cx_read(MC417_RWD);
  548. mem &= ~ALT_DATA;
  549. mem |= (data & ALT_DATA);
  550. cx_write(MC417_RWD, mem);
  551. }
  552. if (flag)
  553. cx_set(MC417_RWD, ALT_AD_RG);/* ADDR */
  554. else
  555. cx_clear(MC417_RWD, ALT_AD_RG);/* VAL */
  556. cx_clear(MC417_RWD, ALT_CS);/* ~CS */
  557. if (read)
  558. cx_clear(MC417_RWD, ALT_RD);
  559. else
  560. cx_clear(MC417_RWD, ALT_WR);
  561. for (;;) {
  562. mem = cx_read(MC417_RWD);
  563. if ((mem & ALT_RDY) == 0)
  564. break;
  565. if (time_after(jiffies, timeout))
  566. break;
  567. udelay(1);
  568. }
  569. cx_set(MC417_RWD, ALT_RD | ALT_WR | ALT_CS);
  570. if (read)
  571. return mem & ALT_DATA;
  572. return 0;
  573. };
  574. static int dvb_register(struct cx23885_tsport *port)
  575. {
  576. struct cx23885_dev *dev = port->dev;
  577. struct cx23885_i2c *i2c_bus = NULL, *i2c_bus2 = NULL;
  578. struct videobuf_dvb_frontend *fe0, *fe1 = NULL;
  579. int mfe_shared = 0; /* bus not shared by default */
  580. int ret;
  581. /* Get the first frontend */
  582. fe0 = videobuf_dvb_get_frontend(&port->frontends, 1);
  583. if (!fe0)
  584. return -EINVAL;
  585. /* init struct videobuf_dvb */
  586. fe0->dvb.name = dev->name;
  587. /* multi-frontend gate control is undefined or defaults to fe0 */
  588. port->frontends.gate = 0;
  589. /* Sets the gate control callback to be used by i2c command calls */
  590. port->gate_ctrl = cx23885_dvb_gate_ctrl;
  591. /* init frontend */
  592. switch (dev->board) {
  593. case CX23885_BOARD_HAUPPAUGE_HVR1250:
  594. i2c_bus = &dev->i2c_bus[0];
  595. fe0->dvb.frontend = dvb_attach(s5h1409_attach,
  596. &hauppauge_generic_config,
  597. &i2c_bus->i2c_adap);
  598. if (fe0->dvb.frontend != NULL) {
  599. dvb_attach(mt2131_attach, fe0->dvb.frontend,
  600. &i2c_bus->i2c_adap,
  601. &hauppauge_generic_tunerconfig, 0);
  602. }
  603. break;
  604. case CX23885_BOARD_HAUPPAUGE_HVR1270:
  605. case CX23885_BOARD_HAUPPAUGE_HVR1275:
  606. i2c_bus = &dev->i2c_bus[0];
  607. fe0->dvb.frontend = dvb_attach(lgdt3305_attach,
  608. &hauppauge_lgdt3305_config,
  609. &i2c_bus->i2c_adap);
  610. if (fe0->dvb.frontend != NULL) {
  611. dvb_attach(tda18271_attach, fe0->dvb.frontend,
  612. 0x60, &dev->i2c_bus[1].i2c_adap,
  613. &hauppauge_hvr127x_config);
  614. }
  615. break;
  616. case CX23885_BOARD_HAUPPAUGE_HVR1255:
  617. i2c_bus = &dev->i2c_bus[0];
  618. fe0->dvb.frontend = dvb_attach(s5h1411_attach,
  619. &hcw_s5h1411_config,
  620. &i2c_bus->i2c_adap);
  621. if (fe0->dvb.frontend != NULL) {
  622. dvb_attach(tda18271_attach, fe0->dvb.frontend,
  623. 0x60, &dev->i2c_bus[1].i2c_adap,
  624. &hauppauge_tda18271_config);
  625. }
  626. break;
  627. case CX23885_BOARD_HAUPPAUGE_HVR1800:
  628. i2c_bus = &dev->i2c_bus[0];
  629. switch (alt_tuner) {
  630. case 1:
  631. fe0->dvb.frontend =
  632. dvb_attach(s5h1409_attach,
  633. &hauppauge_ezqam_config,
  634. &i2c_bus->i2c_adap);
  635. if (fe0->dvb.frontend != NULL) {
  636. dvb_attach(tda829x_attach, fe0->dvb.frontend,
  637. &dev->i2c_bus[1].i2c_adap, 0x42,
  638. &tda829x_no_probe);
  639. dvb_attach(tda18271_attach, fe0->dvb.frontend,
  640. 0x60, &dev->i2c_bus[1].i2c_adap,
  641. &hauppauge_tda18271_config);
  642. }
  643. break;
  644. case 0:
  645. default:
  646. fe0->dvb.frontend =
  647. dvb_attach(s5h1409_attach,
  648. &hauppauge_generic_config,
  649. &i2c_bus->i2c_adap);
  650. if (fe0->dvb.frontend != NULL)
  651. dvb_attach(mt2131_attach, fe0->dvb.frontend,
  652. &i2c_bus->i2c_adap,
  653. &hauppauge_generic_tunerconfig, 0);
  654. break;
  655. }
  656. break;
  657. case CX23885_BOARD_HAUPPAUGE_HVR1800lp:
  658. i2c_bus = &dev->i2c_bus[0];
  659. fe0->dvb.frontend = dvb_attach(s5h1409_attach,
  660. &hauppauge_hvr1800lp_config,
  661. &i2c_bus->i2c_adap);
  662. if (fe0->dvb.frontend != NULL) {
  663. dvb_attach(mt2131_attach, fe0->dvb.frontend,
  664. &i2c_bus->i2c_adap,
  665. &hauppauge_generic_tunerconfig, 0);
  666. }
  667. break;
  668. case CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP:
  669. i2c_bus = &dev->i2c_bus[0];
  670. fe0->dvb.frontend = dvb_attach(lgdt330x_attach,
  671. &fusionhdtv_5_express,
  672. &i2c_bus->i2c_adap);
  673. if (fe0->dvb.frontend != NULL) {
  674. dvb_attach(simple_tuner_attach, fe0->dvb.frontend,
  675. &i2c_bus->i2c_adap, 0x61,
  676. TUNER_LG_TDVS_H06XF);
  677. }
  678. break;
  679. case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
  680. i2c_bus = &dev->i2c_bus[1];
  681. fe0->dvb.frontend = dvb_attach(s5h1409_attach,
  682. &hauppauge_hvr1500q_config,
  683. &dev->i2c_bus[0].i2c_adap);
  684. if (fe0->dvb.frontend != NULL)
  685. dvb_attach(xc5000_attach, fe0->dvb.frontend,
  686. &i2c_bus->i2c_adap,
  687. &hauppauge_hvr1500q_tunerconfig);
  688. break;
  689. case CX23885_BOARD_HAUPPAUGE_HVR1500:
  690. i2c_bus = &dev->i2c_bus[1];
  691. fe0->dvb.frontend = dvb_attach(s5h1409_attach,
  692. &hauppauge_hvr1500_config,
  693. &dev->i2c_bus[0].i2c_adap);
  694. if (fe0->dvb.frontend != NULL) {
  695. struct dvb_frontend *fe;
  696. struct xc2028_config cfg = {
  697. .i2c_adap = &i2c_bus->i2c_adap,
  698. .i2c_addr = 0x61,
  699. };
  700. static struct xc2028_ctrl ctl = {
  701. .fname = XC2028_DEFAULT_FIRMWARE,
  702. .max_len = 64,
  703. .demod = XC3028_FE_OREN538,
  704. };
  705. fe = dvb_attach(xc2028_attach,
  706. fe0->dvb.frontend, &cfg);
  707. if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
  708. fe->ops.tuner_ops.set_config(fe, &ctl);
  709. }
  710. break;
  711. case CX23885_BOARD_HAUPPAUGE_HVR1200:
  712. case CX23885_BOARD_HAUPPAUGE_HVR1700:
  713. i2c_bus = &dev->i2c_bus[0];
  714. fe0->dvb.frontend = dvb_attach(tda10048_attach,
  715. &hauppauge_hvr1200_config,
  716. &i2c_bus->i2c_adap);
  717. if (fe0->dvb.frontend != NULL) {
  718. dvb_attach(tda829x_attach, fe0->dvb.frontend,
  719. &dev->i2c_bus[1].i2c_adap, 0x42,
  720. &tda829x_no_probe);
  721. dvb_attach(tda18271_attach, fe0->dvb.frontend,
  722. 0x60, &dev->i2c_bus[1].i2c_adap,
  723. &hauppauge_hvr1200_tuner_config);
  724. }
  725. break;
  726. case CX23885_BOARD_HAUPPAUGE_HVR1210:
  727. i2c_bus = &dev->i2c_bus[0];
  728. fe0->dvb.frontend = dvb_attach(tda10048_attach,
  729. &hauppauge_hvr1210_config,
  730. &i2c_bus->i2c_adap);
  731. if (fe0->dvb.frontend != NULL) {
  732. dvb_attach(tda18271_attach, fe0->dvb.frontend,
  733. 0x60, &dev->i2c_bus[1].i2c_adap,
  734. &hauppauge_hvr1210_tuner_config);
  735. }
  736. break;
  737. case CX23885_BOARD_HAUPPAUGE_HVR1400:
  738. i2c_bus = &dev->i2c_bus[0];
  739. fe0->dvb.frontend = dvb_attach(dib7000p_attach,
  740. &i2c_bus->i2c_adap,
  741. 0x12, &hauppauge_hvr1400_dib7000_config);
  742. if (fe0->dvb.frontend != NULL) {
  743. struct dvb_frontend *fe;
  744. struct xc2028_config cfg = {
  745. .i2c_adap = &dev->i2c_bus[1].i2c_adap,
  746. .i2c_addr = 0x64,
  747. };
  748. static struct xc2028_ctrl ctl = {
  749. .fname = XC3028L_DEFAULT_FIRMWARE,
  750. .max_len = 64,
  751. .demod = 5000,
  752. /* This is true for all demods with
  753. v36 firmware? */
  754. .type = XC2028_D2633,
  755. };
  756. fe = dvb_attach(xc2028_attach,
  757. fe0->dvb.frontend, &cfg);
  758. if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
  759. fe->ops.tuner_ops.set_config(fe, &ctl);
  760. }
  761. break;
  762. case CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP:
  763. i2c_bus = &dev->i2c_bus[port->nr - 1];
  764. fe0->dvb.frontend = dvb_attach(s5h1409_attach,
  765. &dvico_s5h1409_config,
  766. &i2c_bus->i2c_adap);
  767. if (fe0->dvb.frontend == NULL)
  768. fe0->dvb.frontend = dvb_attach(s5h1411_attach,
  769. &dvico_s5h1411_config,
  770. &i2c_bus->i2c_adap);
  771. if (fe0->dvb.frontend != NULL)
  772. dvb_attach(xc5000_attach, fe0->dvb.frontend,
  773. &i2c_bus->i2c_adap,
  774. &dvico_xc5000_tunerconfig);
  775. break;
  776. case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP: {
  777. i2c_bus = &dev->i2c_bus[port->nr - 1];
  778. fe0->dvb.frontend = dvb_attach(zl10353_attach,
  779. &dvico_fusionhdtv_xc3028,
  780. &i2c_bus->i2c_adap);
  781. if (fe0->dvb.frontend != NULL) {
  782. struct dvb_frontend *fe;
  783. struct xc2028_config cfg = {
  784. .i2c_adap = &i2c_bus->i2c_adap,
  785. .i2c_addr = 0x61,
  786. };
  787. static struct xc2028_ctrl ctl = {
  788. .fname = XC2028_DEFAULT_FIRMWARE,
  789. .max_len = 64,
  790. .demod = XC3028_FE_ZARLINK456,
  791. };
  792. fe = dvb_attach(xc2028_attach, fe0->dvb.frontend,
  793. &cfg);
  794. if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
  795. fe->ops.tuner_ops.set_config(fe, &ctl);
  796. }
  797. break;
  798. }
  799. case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H:
  800. case CX23885_BOARD_COMPRO_VIDEOMATE_E650F:
  801. case CX23885_BOARD_COMPRO_VIDEOMATE_E800:
  802. i2c_bus = &dev->i2c_bus[0];
  803. fe0->dvb.frontend = dvb_attach(zl10353_attach,
  804. &dvico_fusionhdtv_xc3028,
  805. &i2c_bus->i2c_adap);
  806. if (fe0->dvb.frontend != NULL) {
  807. struct dvb_frontend *fe;
  808. struct xc2028_config cfg = {
  809. .i2c_adap = &dev->i2c_bus[1].i2c_adap,
  810. .i2c_addr = 0x61,
  811. };
  812. static struct xc2028_ctrl ctl = {
  813. .fname = XC2028_DEFAULT_FIRMWARE,
  814. .max_len = 64,
  815. .demod = XC3028_FE_ZARLINK456,
  816. };
  817. fe = dvb_attach(xc2028_attach, fe0->dvb.frontend,
  818. &cfg);
  819. if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
  820. fe->ops.tuner_ops.set_config(fe, &ctl);
  821. }
  822. break;
  823. case CX23885_BOARD_TBS_6920:
  824. i2c_bus = &dev->i2c_bus[1];
  825. fe0->dvb.frontend = dvb_attach(cx24116_attach,
  826. &tbs_cx24116_config,
  827. &i2c_bus->i2c_adap);
  828. if (fe0->dvb.frontend != NULL)
  829. fe0->dvb.frontend->ops.set_voltage = f300_set_voltage;
  830. break;
  831. case CX23885_BOARD_TEVII_S470:
  832. i2c_bus = &dev->i2c_bus[1];
  833. fe0->dvb.frontend = dvb_attach(ds3000_attach,
  834. &tevii_ds3000_config,
  835. &i2c_bus->i2c_adap);
  836. if (fe0->dvb.frontend != NULL)
  837. fe0->dvb.frontend->ops.set_voltage = f300_set_voltage;
  838. break;
  839. case CX23885_BOARD_DVBWORLD_2005:
  840. i2c_bus = &dev->i2c_bus[1];
  841. fe0->dvb.frontend = dvb_attach(cx24116_attach,
  842. &dvbworld_cx24116_config,
  843. &i2c_bus->i2c_adap);
  844. break;
  845. case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
  846. i2c_bus = &dev->i2c_bus[0];
  847. switch (port->nr) {
  848. /* port B */
  849. case 1:
  850. fe0->dvb.frontend = dvb_attach(stv0900_attach,
  851. &netup_stv0900_config,
  852. &i2c_bus->i2c_adap, 0);
  853. if (fe0->dvb.frontend != NULL) {
  854. if (dvb_attach(stv6110_attach,
  855. fe0->dvb.frontend,
  856. &netup_stv6110_tunerconfig_a,
  857. &i2c_bus->i2c_adap)) {
  858. if (!dvb_attach(lnbh24_attach,
  859. fe0->dvb.frontend,
  860. &i2c_bus->i2c_adap,
  861. LNBH24_PCL | LNBH24_TTX,
  862. LNBH24_TEN, 0x09))
  863. printk(KERN_ERR
  864. "No LNBH24 found!\n");
  865. }
  866. }
  867. break;
  868. /* port C */
  869. case 2:
  870. fe0->dvb.frontend = dvb_attach(stv0900_attach,
  871. &netup_stv0900_config,
  872. &i2c_bus->i2c_adap, 1);
  873. if (fe0->dvb.frontend != NULL) {
  874. if (dvb_attach(stv6110_attach,
  875. fe0->dvb.frontend,
  876. &netup_stv6110_tunerconfig_b,
  877. &i2c_bus->i2c_adap)) {
  878. if (!dvb_attach(lnbh24_attach,
  879. fe0->dvb.frontend,
  880. &i2c_bus->i2c_adap,
  881. LNBH24_PCL | LNBH24_TTX,
  882. LNBH24_TEN, 0x0a))
  883. printk(KERN_ERR
  884. "No LNBH24 found!\n");
  885. }
  886. }
  887. break;
  888. }
  889. break;
  890. case CX23885_BOARD_MYGICA_X8506:
  891. i2c_bus = &dev->i2c_bus[0];
  892. i2c_bus2 = &dev->i2c_bus[1];
  893. fe0->dvb.frontend = dvb_attach(lgs8gxx_attach,
  894. &mygica_x8506_lgs8gl5_config,
  895. &i2c_bus->i2c_adap);
  896. if (fe0->dvb.frontend != NULL) {
  897. dvb_attach(xc5000_attach,
  898. fe0->dvb.frontend,
  899. &i2c_bus2->i2c_adap,
  900. &mygica_x8506_xc5000_config);
  901. }
  902. break;
  903. case CX23885_BOARD_MAGICPRO_PROHDTVE2:
  904. i2c_bus = &dev->i2c_bus[0];
  905. i2c_bus2 = &dev->i2c_bus[1];
  906. fe0->dvb.frontend = dvb_attach(lgs8gxx_attach,
  907. &magicpro_prohdtve2_lgs8g75_config,
  908. &i2c_bus->i2c_adap);
  909. if (fe0->dvb.frontend != NULL) {
  910. dvb_attach(xc5000_attach,
  911. fe0->dvb.frontend,
  912. &i2c_bus2->i2c_adap,
  913. &magicpro_prohdtve2_xc5000_config);
  914. }
  915. break;
  916. case CX23885_BOARD_HAUPPAUGE_HVR1850:
  917. case CX23885_BOARD_HAUPPAUGE_HVR1290:
  918. i2c_bus = &dev->i2c_bus[0];
  919. fe0->dvb.frontend = dvb_attach(s5h1411_attach,
  920. &hcw_s5h1411_config,
  921. &i2c_bus->i2c_adap);
  922. if (fe0->dvb.frontend != NULL)
  923. dvb_attach(tda18271_attach, fe0->dvb.frontend,
  924. 0x60, &dev->i2c_bus[0].i2c_adap,
  925. &hauppauge_tda18271_config);
  926. break;
  927. case CX23885_BOARD_MYGICA_X8558PRO:
  928. switch (port->nr) {
  929. /* port B */
  930. case 1:
  931. i2c_bus = &dev->i2c_bus[0];
  932. fe0->dvb.frontend = dvb_attach(atbm8830_attach,
  933. &mygica_x8558pro_atbm8830_cfg1,
  934. &i2c_bus->i2c_adap);
  935. if (fe0->dvb.frontend != NULL) {
  936. dvb_attach(max2165_attach,
  937. fe0->dvb.frontend,
  938. &i2c_bus->i2c_adap,
  939. &mygic_x8558pro_max2165_cfg1);
  940. }
  941. break;
  942. /* port C */
  943. case 2:
  944. i2c_bus = &dev->i2c_bus[1];
  945. fe0->dvb.frontend = dvb_attach(atbm8830_attach,
  946. &mygica_x8558pro_atbm8830_cfg2,
  947. &i2c_bus->i2c_adap);
  948. if (fe0->dvb.frontend != NULL) {
  949. dvb_attach(max2165_attach,
  950. fe0->dvb.frontend,
  951. &i2c_bus->i2c_adap,
  952. &mygic_x8558pro_max2165_cfg2);
  953. }
  954. break;
  955. }
  956. break;
  957. case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF:
  958. i2c_bus = &dev->i2c_bus[0];
  959. mfe_shared = 1;/* MFE */
  960. port->frontends.gate = 0;/* not clear for me yet */
  961. /* ports B, C */
  962. /* MFE frontend 1 DVB-T */
  963. fe0->dvb.frontend = dvb_attach(stv0367ter_attach,
  964. &netup_stv0367_config[port->nr - 1],
  965. &i2c_bus->i2c_adap);
  966. if (fe0->dvb.frontend != NULL)
  967. if (NULL == dvb_attach(xc5000_attach,
  968. fe0->dvb.frontend,
  969. &i2c_bus->i2c_adap,
  970. &netup_xc5000_config[port->nr - 1]))
  971. goto frontend_detach;
  972. /* MFE frontend 2 */
  973. fe1 = videobuf_dvb_get_frontend(&port->frontends, 2);
  974. if (fe1 == NULL)
  975. goto frontend_detach;
  976. /* DVB-C init */
  977. fe1->dvb.frontend = dvb_attach(stv0367cab_attach,
  978. &netup_stv0367_config[port->nr - 1],
  979. &i2c_bus->i2c_adap);
  980. if (fe1->dvb.frontend != NULL) {
  981. fe1->dvb.frontend->id = 1;
  982. if (NULL == dvb_attach(xc5000_attach,
  983. fe1->dvb.frontend,
  984. &i2c_bus->i2c_adap,
  985. &netup_xc5000_config[port->nr - 1]))
  986. goto frontend_detach;
  987. }
  988. break;
  989. default:
  990. printk(KERN_INFO "%s: The frontend of your DVB/ATSC card "
  991. " isn't supported yet\n",
  992. dev->name);
  993. break;
  994. }
  995. if ((NULL == fe0->dvb.frontend) || (fe1 && NULL == fe1->dvb.frontend)) {
  996. printk(KERN_ERR "%s: frontend initialization failed\n",
  997. dev->name);
  998. goto frontend_detach;
  999. }
  1000. /* define general-purpose callback pointer */
  1001. fe0->dvb.frontend->callback = cx23885_tuner_callback;
  1002. if (fe1)
  1003. fe1->dvb.frontend->callback = cx23885_tuner_callback;
  1004. #if 0
  1005. /* Ensure all frontends negotiate bus access */
  1006. fe0->dvb.frontend->ops.ts_bus_ctrl = cx23885_dvb_bus_ctrl;
  1007. if (fe1)
  1008. fe1->dvb.frontend->ops.ts_bus_ctrl = cx23885_dvb_bus_ctrl;
  1009. #endif
  1010. /* Put the analog decoder in standby to keep it quiet */
  1011. call_all(dev, core, s_power, 0);
  1012. if (fe0->dvb.frontend->ops.analog_ops.standby)
  1013. fe0->dvb.frontend->ops.analog_ops.standby(fe0->dvb.frontend);
  1014. /* register everything */
  1015. ret = videobuf_dvb_register_bus(&port->frontends, THIS_MODULE, port,
  1016. &dev->pci->dev, adapter_nr, mfe_shared,
  1017. cx23885_dvb_fe_ioctl_override);
  1018. if (ret)
  1019. goto frontend_detach;
  1020. /* init CI & MAC */
  1021. switch (dev->board) {
  1022. case CX23885_BOARD_NETUP_DUAL_DVBS2_CI: {
  1023. static struct netup_card_info cinfo;
  1024. netup_get_card_info(&dev->i2c_bus[0].i2c_adap, &cinfo);
  1025. memcpy(port->frontends.adapter.proposed_mac,
  1026. cinfo.port[port->nr - 1].mac, 6);
  1027. printk(KERN_INFO "NetUP Dual DVB-S2 CI card port%d MAC=%pM\n",
  1028. port->nr, port->frontends.adapter.proposed_mac);
  1029. netup_ci_init(port);
  1030. break;
  1031. }
  1032. case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF: {
  1033. struct altera_ci_config netup_ci_cfg = {
  1034. .dev = dev,/* magic number to identify*/
  1035. .adapter = &port->frontends.adapter,/* for CI */
  1036. .demux = &fe0->dvb.demux,/* for hw pid filter */
  1037. .fpga_rw = netup_altera_fpga_rw,
  1038. };
  1039. altera_ci_init(&netup_ci_cfg, port->nr);
  1040. break;
  1041. }
  1042. case CX23885_BOARD_TEVII_S470: {
  1043. u8 eeprom[256]; /* 24C02 i2c eeprom */
  1044. if (port->nr != 1)
  1045. break;
  1046. /* Read entire EEPROM */
  1047. dev->i2c_bus[0].i2c_client.addr = 0xa0 >> 1;
  1048. tveeprom_read(&dev->i2c_bus[0].i2c_client, eeprom, sizeof(eeprom));
  1049. printk(KERN_INFO "TeVii S470 MAC= %pM\n", eeprom + 0xa0);
  1050. memcpy(port->frontends.adapter.proposed_mac, eeprom + 0xa0, 6);
  1051. break;
  1052. }
  1053. }
  1054. return ret;
  1055. frontend_detach:
  1056. port->gate_ctrl = NULL;
  1057. videobuf_dvb_dealloc_frontends(&port->frontends);
  1058. return -EINVAL;
  1059. }
  1060. int cx23885_dvb_register(struct cx23885_tsport *port)
  1061. {
  1062. struct videobuf_dvb_frontend *fe0;
  1063. struct cx23885_dev *dev = port->dev;
  1064. int err, i;
  1065. /* Here we need to allocate the correct number of frontends,
  1066. * as reflected in the cards struct. The reality is that currently
  1067. * no cx23885 boards support this - yet. But, if we don't modify this
  1068. * code then the second frontend would never be allocated (later)
  1069. * and fail with error before the attach in dvb_register().
  1070. * Without these changes we risk an OOPS later. The changes here
  1071. * are for safety, and should provide a good foundation for the
  1072. * future addition of any multi-frontend cx23885 based boards.
  1073. */
  1074. printk(KERN_INFO "%s() allocating %d frontend(s)\n", __func__,
  1075. port->num_frontends);
  1076. for (i = 1; i <= port->num_frontends; i++) {
  1077. if (videobuf_dvb_alloc_frontend(
  1078. &port->frontends, i) == NULL) {
  1079. printk(KERN_ERR "%s() failed to alloc\n", __func__);
  1080. return -ENOMEM;
  1081. }
  1082. fe0 = videobuf_dvb_get_frontend(&port->frontends, i);
  1083. if (!fe0)
  1084. err = -EINVAL;
  1085. dprintk(1, "%s\n", __func__);
  1086. dprintk(1, " ->probed by Card=%d Name=%s, PCI %02x:%02x\n",
  1087. dev->board,
  1088. dev->name,
  1089. dev->pci_bus,
  1090. dev->pci_slot);
  1091. err = -ENODEV;
  1092. /* dvb stuff */
  1093. /* We have to init the queue for each frontend on a port. */
  1094. printk(KERN_INFO "%s: cx23885 based dvb card\n", dev->name);
  1095. videobuf_queue_sg_init(&fe0->dvb.dvbq, &dvb_qops,
  1096. &dev->pci->dev, &port->slock,
  1097. V4L2_BUF_TYPE_VIDEO_CAPTURE, V4L2_FIELD_TOP,
  1098. sizeof(struct cx23885_buffer), port, NULL);
  1099. }
  1100. err = dvb_register(port);
  1101. if (err != 0)
  1102. printk(KERN_ERR "%s() dvb_register failed err = %d\n",
  1103. __func__, err);
  1104. return err;
  1105. }
  1106. int cx23885_dvb_unregister(struct cx23885_tsport *port)
  1107. {
  1108. struct videobuf_dvb_frontend *fe0;
  1109. /* FIXME: in an error condition where the we have
  1110. * an expected number of frontends (attach problem)
  1111. * then this might not clean up correctly, if 1
  1112. * is invalid.
  1113. * This comment only applies to future boards IF they
  1114. * implement MFE support.
  1115. */
  1116. fe0 = videobuf_dvb_get_frontend(&port->frontends, 1);
  1117. if (fe0->dvb.frontend)
  1118. videobuf_dvb_unregister_bus(&port->frontends);
  1119. switch (port->dev->board) {
  1120. case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
  1121. netup_ci_exit(port);
  1122. break;
  1123. case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF:
  1124. altera_ci_release(port->dev, port->nr);
  1125. break;
  1126. }
  1127. port->gate_ctrl = NULL;
  1128. return 0;
  1129. }