cpsw.txt 3.5 KB

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  1. TI SoC Ethernet Switch Controller Device Tree Bindings
  2. ------------------------------------------------------
  3. Required properties:
  4. - compatible : Should be "ti,cpsw"
  5. - reg : physical base address and size of the cpsw
  6. registers map
  7. - interrupts : property with a value describing the interrupt
  8. number
  9. - interrupt-parent : The parent interrupt controller
  10. - cpdma_channels : Specifies number of channels in CPDMA
  11. - host_port_no : Specifies host port shift
  12. - cpdma_reg_ofs : Specifies CPDMA submodule register offset
  13. - cpdma_sram_ofs : Specifies CPDMA SRAM offset
  14. - ale_reg_ofs : Specifies ALE submodule register offset
  15. - ale_entries : Specifies No of entries ALE can hold
  16. - host_port_reg_ofs : Specifies host port register offset
  17. - hw_stats_reg_ofs : Specifies hardware statistics register offset
  18. - cpts_reg_ofs : Specifies the offset of the CPTS registers
  19. - bd_ram_ofs : Specifies internal desciptor RAM offset
  20. - bd_ram_size : Specifies internal descriptor RAM size
  21. - rx_descs : Specifies number of Rx descriptors
  22. - mac_control : Specifies Default MAC control register content
  23. for the specific platform
  24. - slaves : Specifies number for slaves
  25. - cpts_active_slave : Specifies the slave to use for time stamping
  26. - slave_reg_ofs : Specifies slave register offset
  27. - sliver_reg_ofs : Specifies slave sliver register offset
  28. - phy_id : Specifies slave phy id
  29. - mac-address : Specifies slave MAC address
  30. Optional properties:
  31. - ti,hwmods : Must be "cpgmac0"
  32. - no_bd_ram : Must be 0 or 1
  33. Note: "ti,hwmods" field is used to fetch the base address and irq
  34. resources from TI, omap hwmod data base during device registration.
  35. Future plan is to migrate hwmod data base contents into device tree
  36. blob so that, all the required data will be used from device tree dts
  37. file.
  38. Examples:
  39. mac: ethernet@4A100000 {
  40. compatible = "ti,cpsw";
  41. reg = <0x4A100000 0x1000>;
  42. interrupts = <55 0x4>;
  43. interrupt-parent = <&intc>;
  44. cpdma_channels = <8>;
  45. host_port_no = <0>;
  46. cpdma_reg_ofs = <0x800>;
  47. cpdma_sram_ofs = <0xa00>;
  48. ale_reg_ofs = <0xd00>;
  49. ale_entries = <1024>;
  50. host_port_reg_ofs = <0x108>;
  51. hw_stats_reg_ofs = <0x900>;
  52. cpts_reg_ofs = <0xc00>;
  53. bd_ram_ofs = <0x2000>;
  54. bd_ram_size = <0x2000>;
  55. no_bd_ram = <0>;
  56. rx_descs = <64>;
  57. mac_control = <0x20>;
  58. slaves = <2>;
  59. cpts_active_slave = <0>;
  60. cpsw_emac0: slave@0 {
  61. slave_reg_ofs = <0x200>;
  62. sliver_reg_ofs = <0xd80>;
  63. phy_id = "davinci_mdio.16:00";
  64. /* Filled in by U-Boot */
  65. mac-address = [ 00 00 00 00 00 00 ];
  66. };
  67. cpsw_emac1: slave@1 {
  68. slave_reg_ofs = <0x300>;
  69. sliver_reg_ofs = <0xdc0>;
  70. phy_id = "davinci_mdio.16:01";
  71. /* Filled in by U-Boot */
  72. mac-address = [ 00 00 00 00 00 00 ];
  73. };
  74. };
  75. (or)
  76. mac: ethernet@4A100000 {
  77. compatible = "ti,cpsw";
  78. ti,hwmods = "cpgmac0";
  79. cpdma_channels = <8>;
  80. host_port_no = <0>;
  81. cpdma_reg_ofs = <0x800>;
  82. cpdma_sram_ofs = <0xa00>;
  83. ale_reg_ofs = <0xd00>;
  84. ale_entries = <1024>;
  85. host_port_reg_ofs = <0x108>;
  86. hw_stats_reg_ofs = <0x900>;
  87. cpts_reg_ofs = <0xc00>;
  88. bd_ram_ofs = <0x2000>;
  89. bd_ram_size = <0x2000>;
  90. no_bd_ram = <0>;
  91. rx_descs = <64>;
  92. mac_control = <0x20>;
  93. slaves = <2>;
  94. cpts_active_slave = <0>;
  95. cpsw_emac0: slave@0 {
  96. slave_reg_ofs = <0x200>;
  97. sliver_reg_ofs = <0xd80>;
  98. phy_id = "davinci_mdio.16:00";
  99. /* Filled in by U-Boot */
  100. mac-address = [ 00 00 00 00 00 00 ];
  101. };
  102. cpsw_emac1: slave@1 {
  103. slave_reg_ofs = <0x300>;
  104. sliver_reg_ofs = <0xdc0>;
  105. phy_id = "davinci_mdio.16:01";
  106. /* Filled in by U-Boot */
  107. mac-address = [ 00 00 00 00 00 00 ];
  108. };
  109. };