btmrvl_sdio.h 3.1 KB

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  1. /**
  2. * Marvell BT-over-SDIO driver: SDIO interface related definitions
  3. *
  4. * Copyright (C) 2009, Marvell International Ltd.
  5. *
  6. * This software file (the "File") is distributed by Marvell International
  7. * Ltd. under the terms of the GNU General Public License Version 2, June 1991
  8. * (the "License"). You may use, redistribute and/or modify this File in
  9. * accordance with the terms and conditions of the License, a copy of which
  10. * is available by writing to the Free Software Foundation, Inc.,
  11. * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA or on the
  12. * worldwide web at http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt.
  13. *
  14. *
  15. * THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE
  16. * IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE
  17. * ARE EXPRESSLY DISCLAIMED. The License provides additional details about
  18. * this warranty disclaimer.
  19. *
  20. **/
  21. #ifndef _BTMRVL_SDIO_H_
  22. #define _BTMRVL_SDIO_H_
  23. #define SDIO_HEADER_LEN 4
  24. /* SD block size can not bigger than 64 due to buf size limit in firmware */
  25. /* define SD block size for data Tx/Rx */
  26. #define SDIO_BLOCK_SIZE 64
  27. /* Number of blocks for firmware transfer */
  28. #define FIRMWARE_TRANSFER_NBLOCK 2
  29. /* This is for firmware specific length */
  30. #define FW_EXTRA_LEN 36
  31. #define MRVDRV_SIZE_OF_CMD_BUFFER (2 * 1024)
  32. #define MRVDRV_BT_RX_PACKET_BUFFER_SIZE \
  33. (HCI_MAX_FRAME_SIZE + FW_EXTRA_LEN)
  34. #define ALLOC_BUF_SIZE (((max_t (int, MRVDRV_BT_RX_PACKET_BUFFER_SIZE, \
  35. MRVDRV_SIZE_OF_CMD_BUFFER) + SDIO_HEADER_LEN \
  36. + SDIO_BLOCK_SIZE - 1) / SDIO_BLOCK_SIZE) \
  37. * SDIO_BLOCK_SIZE)
  38. /* The number of times to try when polling for status */
  39. #define MAX_POLL_TRIES 100
  40. /* Max retry number of CMD53 write */
  41. #define MAX_WRITE_IOMEM_RETRY 2
  42. /* Host Control Registers */
  43. #define IO_PORT_0_REG 0x00
  44. #define IO_PORT_1_REG 0x01
  45. #define IO_PORT_2_REG 0x02
  46. #define CONFIG_REG 0x03
  47. #define HOST_POWER_UP BIT(1)
  48. #define HOST_CMD53_FIN BIT(2)
  49. #define HOST_INT_MASK_REG 0x04
  50. #define HIM_DISABLE 0xff
  51. #define HIM_ENABLE (BIT(0) | BIT(1))
  52. #define HOST_INTSTATUS_REG 0x05
  53. #define UP_LD_HOST_INT_STATUS BIT(0)
  54. #define DN_LD_HOST_INT_STATUS BIT(1)
  55. /* Card Control Registers */
  56. #define SQ_READ_BASE_ADDRESS_A0_REG 0x10
  57. #define SQ_READ_BASE_ADDRESS_A1_REG 0x11
  58. #define CARD_STATUS_REG 0x20
  59. #define DN_LD_CARD_RDY BIT(0)
  60. #define CARD_IO_READY BIT(3)
  61. #define CARD_FW_STATUS0_REG 0x40
  62. #define CARD_FW_STATUS1_REG 0x41
  63. #define FIRMWARE_READY 0xfedc
  64. #define CARD_RX_LEN_REG 0x42
  65. #define CARD_RX_UNIT_REG 0x43
  66. struct btmrvl_sdio_card {
  67. struct sdio_func *func;
  68. u32 ioport;
  69. const char *helper;
  70. const char *firmware;
  71. u8 rx_unit;
  72. struct btmrvl_private *priv;
  73. };
  74. struct btmrvl_sdio_device {
  75. unsigned short dev_id;
  76. const char *helper;
  77. const char *firmware;
  78. };
  79. /* Platform specific DMA alignment */
  80. #define BTSDIO_DMA_ALIGN 8
  81. /* Macros for Data Alignment : size */
  82. #define ALIGN_SZ(p, a) \
  83. (((p) + ((a) - 1)) & ~((a) - 1))
  84. /* Macros for Data Alignment : address */
  85. #define ALIGN_ADDR(p, a) \
  86. ((((u32)(p)) + (((u32)(a)) - 1)) & ~(((u32)(a)) - 1))
  87. #endif /* _BTMRVL_SDIO_H_ */