twl6030-irq.c 12 KB

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  1. /*
  2. * twl6030-irq.c - TWL6030 irq support
  3. *
  4. * Copyright (C) 2005-2009 Texas Instruments, Inc.
  5. *
  6. * Modifications to defer interrupt handling to a kernel thread:
  7. * Copyright (C) 2006 MontaVista Software, Inc.
  8. *
  9. * Based on tlv320aic23.c:
  10. * Copyright (c) by Kai Svahn <kai.svahn@nokia.com>
  11. *
  12. * Code cleanup and modifications to IRQ handler.
  13. * by syed khasim <x0khasim@ti.com>
  14. *
  15. * TWL6030 specific code and IRQ handling changes by
  16. * Jagadeesh Bhaskar Pakaravoor <j-pakaravoor@ti.com>
  17. * Balaji T K <balajitk@ti.com>
  18. *
  19. * This program is free software; you can redistribute it and/or modify
  20. * it under the terms of the GNU General Public License as published by
  21. * the Free Software Foundation; either version 2 of the License, or
  22. * (at your option) any later version.
  23. *
  24. * This program is distributed in the hope that it will be useful,
  25. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  26. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  27. * GNU General Public License for more details.
  28. *
  29. * You should have received a copy of the GNU General Public License
  30. * along with this program; if not, write to the Free Software
  31. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  32. */
  33. #include <linux/init.h>
  34. #include <linux/export.h>
  35. #include <linux/interrupt.h>
  36. #include <linux/irq.h>
  37. #include <linux/kthread.h>
  38. #include <linux/i2c/twl.h>
  39. #include <linux/platform_device.h>
  40. #include <linux/suspend.h>
  41. #include <linux/of.h>
  42. #include <linux/irqdomain.h>
  43. #include "twl-core.h"
  44. /*
  45. * TWL6030 (unlike its predecessors, which had two level interrupt handling)
  46. * three interrupt registers INT_STS_A, INT_STS_B and INT_STS_C.
  47. * It exposes status bits saying who has raised an interrupt. There are
  48. * three mask registers that corresponds to these status registers, that
  49. * enables/disables these interrupts.
  50. *
  51. * We set up IRQs starting at a platform-specified base. An interrupt map table,
  52. * specifies mapping between interrupt number and the associated module.
  53. *
  54. */
  55. #define TWL6030_NR_IRQS 20
  56. static int twl6030_interrupt_mapping[24] = {
  57. PWR_INTR_OFFSET, /* Bit 0 PWRON */
  58. PWR_INTR_OFFSET, /* Bit 1 RPWRON */
  59. PWR_INTR_OFFSET, /* Bit 2 BAT_VLOW */
  60. RTC_INTR_OFFSET, /* Bit 3 RTC_ALARM */
  61. RTC_INTR_OFFSET, /* Bit 4 RTC_PERIOD */
  62. HOTDIE_INTR_OFFSET, /* Bit 5 HOT_DIE */
  63. SMPSLDO_INTR_OFFSET, /* Bit 6 VXXX_SHORT */
  64. SMPSLDO_INTR_OFFSET, /* Bit 7 VMMC_SHORT */
  65. SMPSLDO_INTR_OFFSET, /* Bit 8 VUSIM_SHORT */
  66. BATDETECT_INTR_OFFSET, /* Bit 9 BAT */
  67. SIMDETECT_INTR_OFFSET, /* Bit 10 SIM */
  68. MMCDETECT_INTR_OFFSET, /* Bit 11 MMC */
  69. RSV_INTR_OFFSET, /* Bit 12 Reserved */
  70. MADC_INTR_OFFSET, /* Bit 13 GPADC_RT_EOC */
  71. MADC_INTR_OFFSET, /* Bit 14 GPADC_SW_EOC */
  72. GASGAUGE_INTR_OFFSET, /* Bit 15 CC_AUTOCAL */
  73. USBOTG_INTR_OFFSET, /* Bit 16 ID_WKUP */
  74. USBOTG_INTR_OFFSET, /* Bit 17 VBUS_WKUP */
  75. USBOTG_INTR_OFFSET, /* Bit 18 ID */
  76. USB_PRES_INTR_OFFSET, /* Bit 19 VBUS */
  77. CHARGER_INTR_OFFSET, /* Bit 20 CHRG_CTRL */
  78. CHARGERFAULT_INTR_OFFSET, /* Bit 21 EXT_CHRG */
  79. CHARGERFAULT_INTR_OFFSET, /* Bit 22 INT_CHRG */
  80. RSV_INTR_OFFSET, /* Bit 23 Reserved */
  81. };
  82. /*----------------------------------------------------------------------*/
  83. static unsigned twl6030_irq_base;
  84. static int twl_irq;
  85. static bool twl_irq_wake_enabled;
  86. static struct completion irq_event;
  87. static atomic_t twl6030_wakeirqs = ATOMIC_INIT(0);
  88. static int twl6030_irq_pm_notifier(struct notifier_block *notifier,
  89. unsigned long pm_event, void *unused)
  90. {
  91. int chained_wakeups;
  92. switch (pm_event) {
  93. case PM_SUSPEND_PREPARE:
  94. chained_wakeups = atomic_read(&twl6030_wakeirqs);
  95. if (chained_wakeups && !twl_irq_wake_enabled) {
  96. if (enable_irq_wake(twl_irq))
  97. pr_err("twl6030 IRQ wake enable failed\n");
  98. else
  99. twl_irq_wake_enabled = true;
  100. } else if (!chained_wakeups && twl_irq_wake_enabled) {
  101. disable_irq_wake(twl_irq);
  102. twl_irq_wake_enabled = false;
  103. }
  104. disable_irq(twl_irq);
  105. break;
  106. case PM_POST_SUSPEND:
  107. enable_irq(twl_irq);
  108. break;
  109. default:
  110. break;
  111. }
  112. return NOTIFY_DONE;
  113. }
  114. static struct notifier_block twl6030_irq_pm_notifier_block = {
  115. .notifier_call = twl6030_irq_pm_notifier,
  116. };
  117. /*
  118. * This thread processes interrupts reported by the Primary Interrupt Handler.
  119. */
  120. static int twl6030_irq_thread(void *data)
  121. {
  122. long irq = (long)data;
  123. static unsigned i2c_errors;
  124. static const unsigned max_i2c_errors = 100;
  125. int ret;
  126. while (!kthread_should_stop()) {
  127. int i;
  128. union {
  129. u8 bytes[4];
  130. u32 int_sts;
  131. } sts;
  132. /* Wait for IRQ, then read PIH irq status (also blocking) */
  133. wait_for_completion_interruptible(&irq_event);
  134. /* read INT_STS_A, B and C in one shot using a burst read */
  135. ret = twl_i2c_read(TWL_MODULE_PIH, sts.bytes,
  136. REG_INT_STS_A, 3);
  137. if (ret) {
  138. pr_warning("twl6030: I2C error %d reading PIH ISR\n",
  139. ret);
  140. if (++i2c_errors >= max_i2c_errors) {
  141. printk(KERN_ERR "Maximum I2C error count"
  142. " exceeded. Terminating %s.\n",
  143. __func__);
  144. break;
  145. }
  146. complete(&irq_event);
  147. continue;
  148. }
  149. sts.bytes[3] = 0; /* Only 24 bits are valid*/
  150. /*
  151. * Since VBUS status bit is not reliable for VBUS disconnect
  152. * use CHARGER VBUS detection status bit instead.
  153. */
  154. if (sts.bytes[2] & 0x10)
  155. sts.bytes[2] |= 0x08;
  156. for (i = 0; sts.int_sts; sts.int_sts >>= 1, i++) {
  157. local_irq_disable();
  158. if (sts.int_sts & 0x1) {
  159. int module_irq = twl6030_irq_base +
  160. twl6030_interrupt_mapping[i];
  161. generic_handle_irq(module_irq);
  162. }
  163. local_irq_enable();
  164. }
  165. /*
  166. * NOTE:
  167. * Simulation confirms that documentation is wrong w.r.t the
  168. * interrupt status clear operation. A single *byte* write to
  169. * any one of STS_A to STS_C register results in all three
  170. * STS registers being reset. Since it does not matter which
  171. * value is written, all three registers are cleared on a
  172. * single byte write, so we just use 0x0 to clear.
  173. */
  174. ret = twl_i2c_write_u8(TWL_MODULE_PIH, 0x00, REG_INT_STS_A);
  175. if (ret)
  176. pr_warning("twl6030: I2C error in clearing PIH ISR\n");
  177. enable_irq(irq);
  178. }
  179. return 0;
  180. }
  181. /*
  182. * handle_twl6030_int() is the desc->handle method for the twl6030 interrupt.
  183. * This is a chained interrupt, so there is no desc->action method for it.
  184. * Now we need to query the interrupt controller in the twl6030 to determine
  185. * which module is generating the interrupt request. However, we can't do i2c
  186. * transactions in interrupt context, so we must defer that work to a kernel
  187. * thread. All we do here is acknowledge and mask the interrupt and wakeup
  188. * the kernel thread.
  189. */
  190. static irqreturn_t handle_twl6030_pih(int irq, void *devid)
  191. {
  192. disable_irq_nosync(irq);
  193. complete(devid);
  194. return IRQ_HANDLED;
  195. }
  196. /*----------------------------------------------------------------------*/
  197. static inline void activate_irq(int irq)
  198. {
  199. #ifdef CONFIG_ARM
  200. /* ARM requires an extra step to clear IRQ_NOREQUEST, which it
  201. * sets on behalf of every irq_chip. Also sets IRQ_NOPROBE.
  202. */
  203. set_irq_flags(irq, IRQF_VALID);
  204. #else
  205. /* same effect on other architectures */
  206. irq_set_noprobe(irq);
  207. #endif
  208. }
  209. static int twl6030_irq_set_wake(struct irq_data *d, unsigned int on)
  210. {
  211. if (on)
  212. atomic_inc(&twl6030_wakeirqs);
  213. else
  214. atomic_dec(&twl6030_wakeirqs);
  215. return 0;
  216. }
  217. int twl6030_interrupt_unmask(u8 bit_mask, u8 offset)
  218. {
  219. int ret;
  220. u8 unmask_value;
  221. ret = twl_i2c_read_u8(TWL_MODULE_PIH, &unmask_value,
  222. REG_INT_STS_A + offset);
  223. unmask_value &= (~(bit_mask));
  224. ret |= twl_i2c_write_u8(TWL_MODULE_PIH, unmask_value,
  225. REG_INT_STS_A + offset); /* unmask INT_MSK_A/B/C */
  226. return ret;
  227. }
  228. EXPORT_SYMBOL(twl6030_interrupt_unmask);
  229. int twl6030_interrupt_mask(u8 bit_mask, u8 offset)
  230. {
  231. int ret;
  232. u8 mask_value;
  233. ret = twl_i2c_read_u8(TWL_MODULE_PIH, &mask_value,
  234. REG_INT_STS_A + offset);
  235. mask_value |= (bit_mask);
  236. ret |= twl_i2c_write_u8(TWL_MODULE_PIH, mask_value,
  237. REG_INT_STS_A + offset); /* mask INT_MSK_A/B/C */
  238. return ret;
  239. }
  240. EXPORT_SYMBOL(twl6030_interrupt_mask);
  241. int twl6030_mmc_card_detect_config(void)
  242. {
  243. int ret;
  244. u8 reg_val = 0;
  245. /* Unmasking the Card detect Interrupt line for MMC1 from Phoenix */
  246. twl6030_interrupt_unmask(TWL6030_MMCDETECT_INT_MASK,
  247. REG_INT_MSK_LINE_B);
  248. twl6030_interrupt_unmask(TWL6030_MMCDETECT_INT_MASK,
  249. REG_INT_MSK_STS_B);
  250. /*
  251. * Initially Configuring MMC_CTRL for receiving interrupts &
  252. * Card status on TWL6030 for MMC1
  253. */
  254. ret = twl_i2c_read_u8(TWL6030_MODULE_ID0, &reg_val, TWL6030_MMCCTRL);
  255. if (ret < 0) {
  256. pr_err("twl6030: Failed to read MMCCTRL, error %d\n", ret);
  257. return ret;
  258. }
  259. reg_val &= ~VMMC_AUTO_OFF;
  260. reg_val |= SW_FC;
  261. ret = twl_i2c_write_u8(TWL6030_MODULE_ID0, reg_val, TWL6030_MMCCTRL);
  262. if (ret < 0) {
  263. pr_err("twl6030: Failed to write MMCCTRL, error %d\n", ret);
  264. return ret;
  265. }
  266. /* Configuring PullUp-PullDown register */
  267. ret = twl_i2c_read_u8(TWL6030_MODULE_ID0, &reg_val,
  268. TWL6030_CFG_INPUT_PUPD3);
  269. if (ret < 0) {
  270. pr_err("twl6030: Failed to read CFG_INPUT_PUPD3, error %d\n",
  271. ret);
  272. return ret;
  273. }
  274. reg_val &= ~(MMC_PU | MMC_PD);
  275. ret = twl_i2c_write_u8(TWL6030_MODULE_ID0, reg_val,
  276. TWL6030_CFG_INPUT_PUPD3);
  277. if (ret < 0) {
  278. pr_err("twl6030: Failed to write CFG_INPUT_PUPD3, error %d\n",
  279. ret);
  280. return ret;
  281. }
  282. return twl6030_irq_base + MMCDETECT_INTR_OFFSET;
  283. }
  284. EXPORT_SYMBOL(twl6030_mmc_card_detect_config);
  285. int twl6030_mmc_card_detect(struct device *dev, int slot)
  286. {
  287. int ret = -EIO;
  288. u8 read_reg = 0;
  289. struct platform_device *pdev = to_platform_device(dev);
  290. if (pdev->id) {
  291. /* TWL6030 provide's Card detect support for
  292. * only MMC1 controller.
  293. */
  294. pr_err("Unknown MMC controller %d in %s\n", pdev->id, __func__);
  295. return ret;
  296. }
  297. /*
  298. * BIT0 of MMC_CTRL on TWL6030 provides card status for MMC1
  299. * 0 - Card not present ,1 - Card present
  300. */
  301. ret = twl_i2c_read_u8(TWL6030_MODULE_ID0, &read_reg,
  302. TWL6030_MMCCTRL);
  303. if (ret >= 0)
  304. ret = read_reg & STS_MMC;
  305. return ret;
  306. }
  307. EXPORT_SYMBOL(twl6030_mmc_card_detect);
  308. int twl6030_init_irq(struct device *dev, int irq_num)
  309. {
  310. struct device_node *node = dev->of_node;
  311. int nr_irqs, irq_base, irq_end;
  312. int status = 0;
  313. int i;
  314. struct task_struct *task;
  315. int ret;
  316. u8 mask[4];
  317. static struct irq_chip twl6030_irq_chip;
  318. nr_irqs = TWL6030_NR_IRQS;
  319. irq_base = irq_alloc_descs(-1, 0, nr_irqs, 0);
  320. if (IS_ERR_VALUE(irq_base)) {
  321. dev_err(dev, "Fail to allocate IRQ descs\n");
  322. return irq_base;
  323. }
  324. irq_domain_add_legacy(node, nr_irqs, irq_base, 0,
  325. &irq_domain_simple_ops, NULL);
  326. irq_end = irq_base + nr_irqs;
  327. mask[1] = 0xFF;
  328. mask[2] = 0xFF;
  329. mask[3] = 0xFF;
  330. ret = twl_i2c_write(TWL_MODULE_PIH, &mask[0],
  331. REG_INT_MSK_LINE_A, 3); /* MASK ALL INT LINES */
  332. ret = twl_i2c_write(TWL_MODULE_PIH, &mask[0],
  333. REG_INT_MSK_STS_A, 3); /* MASK ALL INT STS */
  334. ret = twl_i2c_write(TWL_MODULE_PIH, &mask[0],
  335. REG_INT_STS_A, 3); /* clear INT_STS_A,B,C */
  336. twl6030_irq_base = irq_base;
  337. /* install an irq handler for each of the modules;
  338. * clone dummy irq_chip since PIH can't *do* anything
  339. */
  340. twl6030_irq_chip = dummy_irq_chip;
  341. twl6030_irq_chip.name = "twl6030";
  342. twl6030_irq_chip.irq_set_type = NULL;
  343. twl6030_irq_chip.irq_set_wake = twl6030_irq_set_wake;
  344. for (i = irq_base; i < irq_end; i++) {
  345. irq_set_chip_and_handler(i, &twl6030_irq_chip,
  346. handle_simple_irq);
  347. irq_set_chip_data(i, (void *)irq_num);
  348. activate_irq(i);
  349. }
  350. pr_info("twl6030: %s (irq %d) chaining IRQs %d..%d\n", "PIH",
  351. irq_num, irq_base, irq_end);
  352. /* install an irq handler to demultiplex the TWL6030 interrupt */
  353. init_completion(&irq_event);
  354. status = request_irq(irq_num, handle_twl6030_pih, 0,
  355. "TWL6030-PIH", &irq_event);
  356. if (status < 0) {
  357. pr_err("twl6030: could not claim irq%d: %d\n", irq_num, status);
  358. goto fail_irq;
  359. }
  360. task = kthread_run(twl6030_irq_thread, (void *)irq_num, "twl6030-irq");
  361. if (IS_ERR(task)) {
  362. pr_err("twl6030: could not create irq %d thread!\n", irq_num);
  363. status = PTR_ERR(task);
  364. goto fail_kthread;
  365. }
  366. twl_irq = irq_num;
  367. register_pm_notifier(&twl6030_irq_pm_notifier_block);
  368. return irq_base;
  369. fail_kthread:
  370. free_irq(irq_num, &irq_event);
  371. fail_irq:
  372. for (i = irq_base; i < irq_end; i++)
  373. irq_set_chip_and_handler(i, NULL, NULL);
  374. return status;
  375. }
  376. int twl6030_exit_irq(void)
  377. {
  378. unregister_pm_notifier(&twl6030_irq_pm_notifier_block);
  379. if (twl6030_irq_base) {
  380. pr_err("twl6030: can't yet clean up IRQs?\n");
  381. return -ENOSYS;
  382. }
  383. return 0;
  384. }