cpu-imx5.c 3.7 KB

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  1. /*
  2. * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
  3. *
  4. * The code contained herein is licensed under the GNU General Public
  5. * License. You may obtain a copy of the GNU General Public License
  6. * Version 2 or later at the following locations:
  7. *
  8. * http://www.opensource.org/licenses/gpl-license.html
  9. * http://www.gnu.org/copyleft/gpl.html
  10. *
  11. * This file contains the CPU initialization code.
  12. */
  13. #include <linux/types.h>
  14. #include <linux/kernel.h>
  15. #include <linux/init.h>
  16. #include <linux/module.h>
  17. #include <mach/hardware.h>
  18. #include <asm/io.h>
  19. static int mx5_cpu_rev = -1;
  20. #define IIM_SREV 0x24
  21. #define MX50_HW_ADADIG_DIGPROG 0xB0
  22. static int get_mx51_srev(void)
  23. {
  24. void __iomem *iim_base = MX51_IO_ADDRESS(MX51_IIM_BASE_ADDR);
  25. u32 rev = readl(iim_base + IIM_SREV) & 0xff;
  26. switch (rev) {
  27. case 0x0:
  28. return IMX_CHIP_REVISION_2_0;
  29. case 0x10:
  30. return IMX_CHIP_REVISION_3_0;
  31. default:
  32. return IMX_CHIP_REVISION_UNKNOWN;
  33. }
  34. }
  35. /*
  36. * Returns:
  37. * the silicon revision of the cpu
  38. * -EINVAL - not a mx51
  39. */
  40. int mx51_revision(void)
  41. {
  42. if (!cpu_is_mx51())
  43. return -EINVAL;
  44. if (mx5_cpu_rev == -1)
  45. mx5_cpu_rev = get_mx51_srev();
  46. return mx5_cpu_rev;
  47. }
  48. EXPORT_SYMBOL(mx51_revision);
  49. #ifdef CONFIG_NEON
  50. /*
  51. * All versions of the silicon before Rev. 3 have broken NEON implementations.
  52. * Dependent on link order - so the assumption is that vfp_init is called
  53. * before us.
  54. */
  55. static int __init mx51_neon_fixup(void)
  56. {
  57. if (!cpu_is_mx51())
  58. return 0;
  59. if (mx51_revision() < IMX_CHIP_REVISION_3_0 && (elf_hwcap & HWCAP_NEON)) {
  60. elf_hwcap &= ~HWCAP_NEON;
  61. pr_info("Turning off NEON support, detected broken NEON implementation\n");
  62. }
  63. return 0;
  64. }
  65. late_initcall(mx51_neon_fixup);
  66. #endif
  67. static int get_mx53_srev(void)
  68. {
  69. void __iomem *iim_base = MX51_IO_ADDRESS(MX53_IIM_BASE_ADDR);
  70. u32 rev = readl(iim_base + IIM_SREV) & 0xff;
  71. switch (rev) {
  72. case 0x0:
  73. return IMX_CHIP_REVISION_1_0;
  74. case 0x2:
  75. return IMX_CHIP_REVISION_2_0;
  76. case 0x3:
  77. return IMX_CHIP_REVISION_2_1;
  78. default:
  79. return IMX_CHIP_REVISION_UNKNOWN;
  80. }
  81. }
  82. /*
  83. * Returns:
  84. * the silicon revision of the cpu
  85. * -EINVAL - not a mx53
  86. */
  87. int mx53_revision(void)
  88. {
  89. if (!cpu_is_mx53())
  90. return -EINVAL;
  91. if (mx5_cpu_rev == -1)
  92. mx5_cpu_rev = get_mx53_srev();
  93. return mx5_cpu_rev;
  94. }
  95. EXPORT_SYMBOL(mx53_revision);
  96. static int get_mx50_srev(void)
  97. {
  98. void __iomem *anatop = ioremap(MX50_ANATOP_BASE_ADDR, SZ_8K);
  99. u32 rev;
  100. if (!anatop) {
  101. mx5_cpu_rev = -EINVAL;
  102. return 0;
  103. }
  104. rev = readl(anatop + MX50_HW_ADADIG_DIGPROG);
  105. rev &= 0xff;
  106. iounmap(anatop);
  107. if (rev == 0x0)
  108. return IMX_CHIP_REVISION_1_0;
  109. else if (rev == 0x1)
  110. return IMX_CHIP_REVISION_1_1;
  111. return 0;
  112. }
  113. /*
  114. * Returns:
  115. * the silicon revision of the cpu
  116. * -EINVAL - not a mx50
  117. */
  118. int mx50_revision(void)
  119. {
  120. if (!cpu_is_mx50())
  121. return -EINVAL;
  122. if (mx5_cpu_rev == -1)
  123. mx5_cpu_rev = get_mx50_srev();
  124. return mx5_cpu_rev;
  125. }
  126. EXPORT_SYMBOL(mx50_revision);
  127. static int __init post_cpu_init(void)
  128. {
  129. unsigned int reg;
  130. void __iomem *base;
  131. if (cpu_is_mx51() || cpu_is_mx53()) {
  132. if (cpu_is_mx51())
  133. base = MX51_IO_ADDRESS(MX51_AIPS1_BASE_ADDR);
  134. else
  135. base = MX53_IO_ADDRESS(MX53_AIPS1_BASE_ADDR);
  136. __raw_writel(0x0, base + 0x40);
  137. __raw_writel(0x0, base + 0x44);
  138. __raw_writel(0x0, base + 0x48);
  139. __raw_writel(0x0, base + 0x4C);
  140. reg = __raw_readl(base + 0x50) & 0x00FFFFFF;
  141. __raw_writel(reg, base + 0x50);
  142. if (cpu_is_mx51())
  143. base = MX51_IO_ADDRESS(MX51_AIPS2_BASE_ADDR);
  144. else
  145. base = MX53_IO_ADDRESS(MX53_AIPS2_BASE_ADDR);
  146. __raw_writel(0x0, base + 0x40);
  147. __raw_writel(0x0, base + 0x44);
  148. __raw_writel(0x0, base + 0x48);
  149. __raw_writel(0x0, base + 0x4C);
  150. reg = __raw_readl(base + 0x50) & 0x00FFFFFF;
  151. __raw_writel(reg, base + 0x50);
  152. }
  153. return 0;
  154. }
  155. postcore_initcall(post_cpu_init);