main.c 51 KB

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  1. /*
  2. * Copyright (c) 2008-2011 Atheros Communications Inc.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for any
  5. * purpose with or without fee is hereby granted, provided that the above
  6. * copyright notice and this permission notice appear in all copies.
  7. *
  8. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  9. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15. */
  16. #include <linux/nl80211.h>
  17. #include <linux/delay.h>
  18. #include "ath9k.h"
  19. #include "btcoex.h"
  20. static u8 parse_mpdudensity(u8 mpdudensity)
  21. {
  22. /*
  23. * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
  24. * 0 for no restriction
  25. * 1 for 1/4 us
  26. * 2 for 1/2 us
  27. * 3 for 1 us
  28. * 4 for 2 us
  29. * 5 for 4 us
  30. * 6 for 8 us
  31. * 7 for 16 us
  32. */
  33. switch (mpdudensity) {
  34. case 0:
  35. return 0;
  36. case 1:
  37. case 2:
  38. case 3:
  39. /* Our lower layer calculations limit our precision to
  40. 1 microsecond */
  41. return 1;
  42. case 4:
  43. return 2;
  44. case 5:
  45. return 4;
  46. case 6:
  47. return 8;
  48. case 7:
  49. return 16;
  50. default:
  51. return 0;
  52. }
  53. }
  54. static bool ath9k_has_pending_frames(struct ath_softc *sc, struct ath_txq *txq)
  55. {
  56. bool pending = false;
  57. spin_lock_bh(&txq->axq_lock);
  58. if (txq->axq_depth || !list_empty(&txq->axq_acq))
  59. pending = true;
  60. spin_unlock_bh(&txq->axq_lock);
  61. return pending;
  62. }
  63. static bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode)
  64. {
  65. unsigned long flags;
  66. bool ret;
  67. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  68. ret = ath9k_hw_setpower(sc->sc_ah, mode);
  69. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  70. return ret;
  71. }
  72. void ath9k_ps_wakeup(struct ath_softc *sc)
  73. {
  74. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  75. unsigned long flags;
  76. enum ath9k_power_mode power_mode;
  77. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  78. if (++sc->ps_usecount != 1)
  79. goto unlock;
  80. power_mode = sc->sc_ah->power_mode;
  81. ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
  82. /*
  83. * While the hardware is asleep, the cycle counters contain no
  84. * useful data. Better clear them now so that they don't mess up
  85. * survey data results.
  86. */
  87. if (power_mode != ATH9K_PM_AWAKE) {
  88. spin_lock(&common->cc_lock);
  89. ath_hw_cycle_counters_update(common);
  90. memset(&common->cc_survey, 0, sizeof(common->cc_survey));
  91. memset(&common->cc_ani, 0, sizeof(common->cc_ani));
  92. spin_unlock(&common->cc_lock);
  93. }
  94. unlock:
  95. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  96. }
  97. void ath9k_ps_restore(struct ath_softc *sc)
  98. {
  99. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  100. enum ath9k_power_mode mode;
  101. unsigned long flags;
  102. bool reset;
  103. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  104. if (--sc->ps_usecount != 0)
  105. goto unlock;
  106. if (sc->ps_idle) {
  107. ath9k_hw_setrxabort(sc->sc_ah, 1);
  108. ath9k_hw_stopdmarecv(sc->sc_ah, &reset);
  109. mode = ATH9K_PM_FULL_SLEEP;
  110. } else if (sc->ps_enabled &&
  111. !(sc->ps_flags & (PS_WAIT_FOR_BEACON |
  112. PS_WAIT_FOR_CAB |
  113. PS_WAIT_FOR_PSPOLL_DATA |
  114. PS_WAIT_FOR_TX_ACK))) {
  115. mode = ATH9K_PM_NETWORK_SLEEP;
  116. } else {
  117. goto unlock;
  118. }
  119. spin_lock(&common->cc_lock);
  120. ath_hw_cycle_counters_update(common);
  121. spin_unlock(&common->cc_lock);
  122. ath9k_hw_setpower(sc->sc_ah, mode);
  123. unlock:
  124. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  125. }
  126. static void __ath_cancel_work(struct ath_softc *sc)
  127. {
  128. cancel_work_sync(&sc->paprd_work);
  129. cancel_work_sync(&sc->hw_check_work);
  130. cancel_delayed_work_sync(&sc->tx_complete_work);
  131. cancel_delayed_work_sync(&sc->hw_pll_work);
  132. }
  133. static void ath_cancel_work(struct ath_softc *sc)
  134. {
  135. __ath_cancel_work(sc);
  136. cancel_work_sync(&sc->hw_reset_work);
  137. }
  138. static void ath_restart_work(struct ath_softc *sc)
  139. {
  140. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  141. ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
  142. if (AR_SREV_9485(sc->sc_ah) || AR_SREV_9340(sc->sc_ah))
  143. ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work,
  144. msecs_to_jiffies(ATH_PLL_WORK_INTERVAL));
  145. ath_start_rx_poll(sc, 3);
  146. if (!common->disable_ani)
  147. ath_start_ani(common);
  148. }
  149. static bool ath_prepare_reset(struct ath_softc *sc, bool retry_tx, bool flush)
  150. {
  151. struct ath_hw *ah = sc->sc_ah;
  152. struct ath_common *common = ath9k_hw_common(ah);
  153. bool ret = true;
  154. ieee80211_stop_queues(sc->hw);
  155. sc->hw_busy_count = 0;
  156. del_timer_sync(&common->ani.timer);
  157. del_timer_sync(&sc->rx_poll_timer);
  158. ath9k_debug_samp_bb_mac(sc);
  159. ath9k_hw_disable_interrupts(ah);
  160. if (!ath_stoprecv(sc))
  161. ret = false;
  162. if (!ath_drain_all_txq(sc, retry_tx))
  163. ret = false;
  164. if (!flush) {
  165. if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
  166. ath_rx_tasklet(sc, 1, true);
  167. ath_rx_tasklet(sc, 1, false);
  168. } else {
  169. ath_flushrecv(sc);
  170. }
  171. return ret;
  172. }
  173. static bool ath_complete_reset(struct ath_softc *sc, bool start)
  174. {
  175. struct ath_hw *ah = sc->sc_ah;
  176. struct ath_common *common = ath9k_hw_common(ah);
  177. if (ath_startrecv(sc) != 0) {
  178. ath_err(common, "Unable to restart recv logic\n");
  179. return false;
  180. }
  181. ath9k_cmn_update_txpow(ah, sc->curtxpow,
  182. sc->config.txpowlimit, &sc->curtxpow);
  183. ath9k_hw_set_interrupts(ah);
  184. ath9k_hw_enable_interrupts(ah);
  185. if (!(sc->hw->conf.flags & IEEE80211_CONF_OFFCHANNEL) && start) {
  186. if (test_bit(SC_OP_BEACONS, &sc->sc_flags))
  187. ath_set_beacon(sc);
  188. ath_restart_work(sc);
  189. }
  190. if ((ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB) && sc->ant_rx != 3)
  191. ath_ant_comb_update(sc);
  192. ieee80211_wake_queues(sc->hw);
  193. return true;
  194. }
  195. static int ath_reset_internal(struct ath_softc *sc, struct ath9k_channel *hchan,
  196. bool retry_tx)
  197. {
  198. struct ath_hw *ah = sc->sc_ah;
  199. struct ath_common *common = ath9k_hw_common(ah);
  200. struct ath9k_hw_cal_data *caldata = NULL;
  201. bool fastcc = true;
  202. bool flush = false;
  203. int r;
  204. __ath_cancel_work(sc);
  205. spin_lock_bh(&sc->sc_pcu_lock);
  206. if (!(sc->hw->conf.flags & IEEE80211_CONF_OFFCHANNEL)) {
  207. fastcc = false;
  208. caldata = &sc->caldata;
  209. }
  210. if (!hchan) {
  211. fastcc = false;
  212. flush = true;
  213. hchan = ah->curchan;
  214. }
  215. if (!ath_prepare_reset(sc, retry_tx, flush))
  216. fastcc = false;
  217. ath_dbg(common, CONFIG, "Reset to %u MHz, HT40: %d fastcc: %d\n",
  218. hchan->channel, IS_CHAN_HT40(hchan), fastcc);
  219. r = ath9k_hw_reset(ah, hchan, caldata, fastcc);
  220. if (r) {
  221. ath_err(common,
  222. "Unable to reset channel, reset status %d\n", r);
  223. goto out;
  224. }
  225. if (!ath_complete_reset(sc, true))
  226. r = -EIO;
  227. out:
  228. spin_unlock_bh(&sc->sc_pcu_lock);
  229. return r;
  230. }
  231. /*
  232. * Set/change channels. If the channel is really being changed, it's done
  233. * by reseting the chip. To accomplish this we must first cleanup any pending
  234. * DMA, then restart stuff.
  235. */
  236. static int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
  237. struct ath9k_channel *hchan)
  238. {
  239. int r;
  240. if (test_bit(SC_OP_INVALID, &sc->sc_flags))
  241. return -EIO;
  242. r = ath_reset_internal(sc, hchan, false);
  243. return r;
  244. }
  245. static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta,
  246. struct ieee80211_vif *vif)
  247. {
  248. struct ath_node *an;
  249. an = (struct ath_node *)sta->drv_priv;
  250. #ifdef CONFIG_ATH9K_DEBUGFS
  251. spin_lock(&sc->nodes_lock);
  252. list_add(&an->list, &sc->nodes);
  253. spin_unlock(&sc->nodes_lock);
  254. #endif
  255. an->sta = sta;
  256. an->vif = vif;
  257. if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
  258. ath_tx_node_init(sc, an);
  259. an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR +
  260. sta->ht_cap.ampdu_factor);
  261. an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density);
  262. }
  263. }
  264. static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
  265. {
  266. struct ath_node *an = (struct ath_node *)sta->drv_priv;
  267. #ifdef CONFIG_ATH9K_DEBUGFS
  268. spin_lock(&sc->nodes_lock);
  269. list_del(&an->list);
  270. spin_unlock(&sc->nodes_lock);
  271. an->sta = NULL;
  272. #endif
  273. if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT)
  274. ath_tx_node_cleanup(sc, an);
  275. }
  276. void ath9k_tasklet(unsigned long data)
  277. {
  278. struct ath_softc *sc = (struct ath_softc *)data;
  279. struct ath_hw *ah = sc->sc_ah;
  280. struct ath_common *common = ath9k_hw_common(ah);
  281. u32 status = sc->intrstatus;
  282. u32 rxmask;
  283. ath9k_ps_wakeup(sc);
  284. spin_lock(&sc->sc_pcu_lock);
  285. if ((status & ATH9K_INT_FATAL) ||
  286. (status & ATH9K_INT_BB_WATCHDOG)) {
  287. #ifdef CONFIG_ATH9K_DEBUGFS
  288. enum ath_reset_type type;
  289. if (status & ATH9K_INT_FATAL)
  290. type = RESET_TYPE_FATAL_INT;
  291. else
  292. type = RESET_TYPE_BB_WATCHDOG;
  293. RESET_STAT_INC(sc, type);
  294. #endif
  295. ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
  296. goto out;
  297. }
  298. if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) {
  299. /*
  300. * TSF sync does not look correct; remain awake to sync with
  301. * the next Beacon.
  302. */
  303. ath_dbg(common, PS, "TSFOOR - Sync with next Beacon\n");
  304. sc->ps_flags |= PS_WAIT_FOR_BEACON | PS_BEACON_SYNC;
  305. }
  306. if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
  307. rxmask = (ATH9K_INT_RXHP | ATH9K_INT_RXLP | ATH9K_INT_RXEOL |
  308. ATH9K_INT_RXORN);
  309. else
  310. rxmask = (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
  311. if (status & rxmask) {
  312. /* Check for high priority Rx first */
  313. if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
  314. (status & ATH9K_INT_RXHP))
  315. ath_rx_tasklet(sc, 0, true);
  316. ath_rx_tasklet(sc, 0, false);
  317. }
  318. if (status & ATH9K_INT_TX) {
  319. if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
  320. ath_tx_edma_tasklet(sc);
  321. else
  322. ath_tx_tasklet(sc);
  323. }
  324. ath9k_btcoex_handle_interrupt(sc, status);
  325. out:
  326. /* re-enable hardware interrupt */
  327. ath9k_hw_enable_interrupts(ah);
  328. spin_unlock(&sc->sc_pcu_lock);
  329. ath9k_ps_restore(sc);
  330. }
  331. irqreturn_t ath_isr(int irq, void *dev)
  332. {
  333. #define SCHED_INTR ( \
  334. ATH9K_INT_FATAL | \
  335. ATH9K_INT_BB_WATCHDOG | \
  336. ATH9K_INT_RXORN | \
  337. ATH9K_INT_RXEOL | \
  338. ATH9K_INT_RX | \
  339. ATH9K_INT_RXLP | \
  340. ATH9K_INT_RXHP | \
  341. ATH9K_INT_TX | \
  342. ATH9K_INT_BMISS | \
  343. ATH9K_INT_CST | \
  344. ATH9K_INT_TSFOOR | \
  345. ATH9K_INT_GENTIMER | \
  346. ATH9K_INT_MCI)
  347. struct ath_softc *sc = dev;
  348. struct ath_hw *ah = sc->sc_ah;
  349. struct ath_common *common = ath9k_hw_common(ah);
  350. enum ath9k_int status;
  351. bool sched = false;
  352. /*
  353. * The hardware is not ready/present, don't
  354. * touch anything. Note this can happen early
  355. * on if the IRQ is shared.
  356. */
  357. if (test_bit(SC_OP_INVALID, &sc->sc_flags))
  358. return IRQ_NONE;
  359. /* shared irq, not for us */
  360. if (!ath9k_hw_intrpend(ah))
  361. return IRQ_NONE;
  362. /*
  363. * Figure out the reason(s) for the interrupt. Note
  364. * that the hal returns a pseudo-ISR that may include
  365. * bits we haven't explicitly enabled so we mask the
  366. * value to insure we only process bits we requested.
  367. */
  368. ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */
  369. status &= ah->imask; /* discard unasked-for bits */
  370. /*
  371. * If there are no status bits set, then this interrupt was not
  372. * for me (should have been caught above).
  373. */
  374. if (!status)
  375. return IRQ_NONE;
  376. /* Cache the status */
  377. sc->intrstatus = status;
  378. if (status & SCHED_INTR)
  379. sched = true;
  380. /*
  381. * If a FATAL or RXORN interrupt is received, we have to reset the
  382. * chip immediately.
  383. */
  384. if ((status & ATH9K_INT_FATAL) || ((status & ATH9K_INT_RXORN) &&
  385. !(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)))
  386. goto chip_reset;
  387. if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
  388. (status & ATH9K_INT_BB_WATCHDOG)) {
  389. spin_lock(&common->cc_lock);
  390. ath_hw_cycle_counters_update(common);
  391. ar9003_hw_bb_watchdog_dbg_info(ah);
  392. spin_unlock(&common->cc_lock);
  393. goto chip_reset;
  394. }
  395. if (status & ATH9K_INT_SWBA)
  396. tasklet_schedule(&sc->bcon_tasklet);
  397. if (status & ATH9K_INT_TXURN)
  398. ath9k_hw_updatetxtriglevel(ah, true);
  399. if (status & ATH9K_INT_RXEOL) {
  400. ah->imask &= ~(ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
  401. ath9k_hw_set_interrupts(ah);
  402. }
  403. if (status & ATH9K_INT_MIB) {
  404. /*
  405. * Disable interrupts until we service the MIB
  406. * interrupt; otherwise it will continue to
  407. * fire.
  408. */
  409. ath9k_hw_disable_interrupts(ah);
  410. /*
  411. * Let the hal handle the event. We assume
  412. * it will clear whatever condition caused
  413. * the interrupt.
  414. */
  415. spin_lock(&common->cc_lock);
  416. ath9k_hw_proc_mib_event(ah);
  417. spin_unlock(&common->cc_lock);
  418. ath9k_hw_enable_interrupts(ah);
  419. }
  420. if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
  421. if (status & ATH9K_INT_TIM_TIMER) {
  422. if (ATH_DBG_WARN_ON_ONCE(sc->ps_idle))
  423. goto chip_reset;
  424. /* Clear RxAbort bit so that we can
  425. * receive frames */
  426. ath9k_setpower(sc, ATH9K_PM_AWAKE);
  427. ath9k_hw_setrxabort(sc->sc_ah, 0);
  428. sc->ps_flags |= PS_WAIT_FOR_BEACON;
  429. }
  430. chip_reset:
  431. ath_debug_stat_interrupt(sc, status);
  432. if (sched) {
  433. /* turn off every interrupt */
  434. ath9k_hw_disable_interrupts(ah);
  435. tasklet_schedule(&sc->intr_tq);
  436. }
  437. return IRQ_HANDLED;
  438. #undef SCHED_INTR
  439. }
  440. static int ath_reset(struct ath_softc *sc, bool retry_tx)
  441. {
  442. int r;
  443. ath9k_ps_wakeup(sc);
  444. r = ath_reset_internal(sc, NULL, retry_tx);
  445. if (retry_tx) {
  446. int i;
  447. for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
  448. if (ATH_TXQ_SETUP(sc, i)) {
  449. spin_lock_bh(&sc->tx.txq[i].axq_lock);
  450. ath_txq_schedule(sc, &sc->tx.txq[i]);
  451. spin_unlock_bh(&sc->tx.txq[i].axq_lock);
  452. }
  453. }
  454. }
  455. ath9k_ps_restore(sc);
  456. return r;
  457. }
  458. void ath_reset_work(struct work_struct *work)
  459. {
  460. struct ath_softc *sc = container_of(work, struct ath_softc, hw_reset_work);
  461. ath_reset(sc, true);
  462. }
  463. /**********************/
  464. /* mac80211 callbacks */
  465. /**********************/
  466. static int ath9k_start(struct ieee80211_hw *hw)
  467. {
  468. struct ath_softc *sc = hw->priv;
  469. struct ath_hw *ah = sc->sc_ah;
  470. struct ath_common *common = ath9k_hw_common(ah);
  471. struct ieee80211_channel *curchan = hw->conf.channel;
  472. struct ath9k_channel *init_channel;
  473. int r;
  474. ath_dbg(common, CONFIG,
  475. "Starting driver with initial channel: %d MHz\n",
  476. curchan->center_freq);
  477. ath9k_ps_wakeup(sc);
  478. mutex_lock(&sc->mutex);
  479. init_channel = ath9k_cmn_get_curchannel(hw, ah);
  480. /* Reset SERDES registers */
  481. ath9k_hw_configpcipowersave(ah, false);
  482. /*
  483. * The basic interface to setting the hardware in a good
  484. * state is ``reset''. On return the hardware is known to
  485. * be powered up and with interrupts disabled. This must
  486. * be followed by initialization of the appropriate bits
  487. * and then setup of the interrupt mask.
  488. */
  489. spin_lock_bh(&sc->sc_pcu_lock);
  490. atomic_set(&ah->intr_ref_cnt, -1);
  491. r = ath9k_hw_reset(ah, init_channel, ah->caldata, false);
  492. if (r) {
  493. ath_err(common,
  494. "Unable to reset hardware; reset status %d (freq %u MHz)\n",
  495. r, curchan->center_freq);
  496. spin_unlock_bh(&sc->sc_pcu_lock);
  497. goto mutex_unlock;
  498. }
  499. /* Setup our intr mask. */
  500. ah->imask = ATH9K_INT_TX | ATH9K_INT_RXEOL |
  501. ATH9K_INT_RXORN | ATH9K_INT_FATAL |
  502. ATH9K_INT_GLOBAL;
  503. if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
  504. ah->imask |= ATH9K_INT_RXHP |
  505. ATH9K_INT_RXLP |
  506. ATH9K_INT_BB_WATCHDOG;
  507. else
  508. ah->imask |= ATH9K_INT_RX;
  509. ah->imask |= ATH9K_INT_GTT;
  510. if (ah->caps.hw_caps & ATH9K_HW_CAP_HT)
  511. ah->imask |= ATH9K_INT_CST;
  512. ath_mci_enable(sc);
  513. clear_bit(SC_OP_INVALID, &sc->sc_flags);
  514. sc->sc_ah->is_monitoring = false;
  515. if (!ath_complete_reset(sc, false)) {
  516. r = -EIO;
  517. spin_unlock_bh(&sc->sc_pcu_lock);
  518. goto mutex_unlock;
  519. }
  520. if (ah->led_pin >= 0) {
  521. ath9k_hw_cfg_output(ah, ah->led_pin,
  522. AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
  523. ath9k_hw_set_gpio(ah, ah->led_pin, 0);
  524. }
  525. /*
  526. * Reset key cache to sane defaults (all entries cleared) instead of
  527. * semi-random values after suspend/resume.
  528. */
  529. ath9k_cmn_init_crypto(sc->sc_ah);
  530. spin_unlock_bh(&sc->sc_pcu_lock);
  531. ath9k_start_btcoex(sc);
  532. if (ah->caps.pcie_lcr_extsync_en && common->bus_ops->extn_synch_en)
  533. common->bus_ops->extn_synch_en(common);
  534. mutex_unlock:
  535. mutex_unlock(&sc->mutex);
  536. ath9k_ps_restore(sc);
  537. return r;
  538. }
  539. static void ath9k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
  540. {
  541. struct ath_softc *sc = hw->priv;
  542. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  543. struct ath_tx_control txctl;
  544. struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
  545. if (sc->ps_enabled) {
  546. /*
  547. * mac80211 does not set PM field for normal data frames, so we
  548. * need to update that based on the current PS mode.
  549. */
  550. if (ieee80211_is_data(hdr->frame_control) &&
  551. !ieee80211_is_nullfunc(hdr->frame_control) &&
  552. !ieee80211_has_pm(hdr->frame_control)) {
  553. ath_dbg(common, PS,
  554. "Add PM=1 for a TX frame while in PS mode\n");
  555. hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
  556. }
  557. }
  558. if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_NETWORK_SLEEP)) {
  559. /*
  560. * We are using PS-Poll and mac80211 can request TX while in
  561. * power save mode. Need to wake up hardware for the TX to be
  562. * completed and if needed, also for RX of buffered frames.
  563. */
  564. ath9k_ps_wakeup(sc);
  565. if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
  566. ath9k_hw_setrxabort(sc->sc_ah, 0);
  567. if (ieee80211_is_pspoll(hdr->frame_control)) {
  568. ath_dbg(common, PS,
  569. "Sending PS-Poll to pick a buffered frame\n");
  570. sc->ps_flags |= PS_WAIT_FOR_PSPOLL_DATA;
  571. } else {
  572. ath_dbg(common, PS, "Wake up to complete TX\n");
  573. sc->ps_flags |= PS_WAIT_FOR_TX_ACK;
  574. }
  575. /*
  576. * The actual restore operation will happen only after
  577. * the ps_flags bit is cleared. We are just dropping
  578. * the ps_usecount here.
  579. */
  580. ath9k_ps_restore(sc);
  581. }
  582. /*
  583. * Cannot tx while the hardware is in full sleep, it first needs a full
  584. * chip reset to recover from that
  585. */
  586. if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_FULL_SLEEP)) {
  587. ath_err(common, "TX while HW is in FULL_SLEEP mode\n");
  588. goto exit;
  589. }
  590. memset(&txctl, 0, sizeof(struct ath_tx_control));
  591. txctl.txq = sc->tx.txq_map[skb_get_queue_mapping(skb)];
  592. ath_dbg(common, XMIT, "transmitting packet, skb: %p\n", skb);
  593. if (ath_tx_start(hw, skb, &txctl) != 0) {
  594. ath_dbg(common, XMIT, "TX failed\n");
  595. TX_STAT_INC(txctl.txq->axq_qnum, txfailed);
  596. goto exit;
  597. }
  598. return;
  599. exit:
  600. dev_kfree_skb_any(skb);
  601. }
  602. static void ath9k_stop(struct ieee80211_hw *hw)
  603. {
  604. struct ath_softc *sc = hw->priv;
  605. struct ath_hw *ah = sc->sc_ah;
  606. struct ath_common *common = ath9k_hw_common(ah);
  607. bool prev_idle;
  608. mutex_lock(&sc->mutex);
  609. ath_cancel_work(sc);
  610. del_timer_sync(&sc->rx_poll_timer);
  611. if (test_bit(SC_OP_INVALID, &sc->sc_flags)) {
  612. ath_dbg(common, ANY, "Device not present\n");
  613. mutex_unlock(&sc->mutex);
  614. return;
  615. }
  616. /* Ensure HW is awake when we try to shut it down. */
  617. ath9k_ps_wakeup(sc);
  618. ath9k_stop_btcoex(sc);
  619. spin_lock_bh(&sc->sc_pcu_lock);
  620. /* prevent tasklets to enable interrupts once we disable them */
  621. ah->imask &= ~ATH9K_INT_GLOBAL;
  622. /* make sure h/w will not generate any interrupt
  623. * before setting the invalid flag. */
  624. ath9k_hw_disable_interrupts(ah);
  625. spin_unlock_bh(&sc->sc_pcu_lock);
  626. /* we can now sync irq and kill any running tasklets, since we already
  627. * disabled interrupts and not holding a spin lock */
  628. synchronize_irq(sc->irq);
  629. tasklet_kill(&sc->intr_tq);
  630. tasklet_kill(&sc->bcon_tasklet);
  631. prev_idle = sc->ps_idle;
  632. sc->ps_idle = true;
  633. spin_lock_bh(&sc->sc_pcu_lock);
  634. if (ah->led_pin >= 0) {
  635. ath9k_hw_set_gpio(ah, ah->led_pin, 1);
  636. ath9k_hw_cfg_gpio_input(ah, ah->led_pin);
  637. }
  638. ath_prepare_reset(sc, false, true);
  639. if (sc->rx.frag) {
  640. dev_kfree_skb_any(sc->rx.frag);
  641. sc->rx.frag = NULL;
  642. }
  643. if (!ah->curchan)
  644. ah->curchan = ath9k_cmn_get_curchannel(hw, ah);
  645. ath9k_hw_reset(ah, ah->curchan, ah->caldata, false);
  646. ath9k_hw_phy_disable(ah);
  647. ath9k_hw_configpcipowersave(ah, true);
  648. spin_unlock_bh(&sc->sc_pcu_lock);
  649. ath9k_ps_restore(sc);
  650. set_bit(SC_OP_INVALID, &sc->sc_flags);
  651. sc->ps_idle = prev_idle;
  652. mutex_unlock(&sc->mutex);
  653. ath_dbg(common, CONFIG, "Driver halt\n");
  654. }
  655. bool ath9k_uses_beacons(int type)
  656. {
  657. switch (type) {
  658. case NL80211_IFTYPE_AP:
  659. case NL80211_IFTYPE_ADHOC:
  660. case NL80211_IFTYPE_MESH_POINT:
  661. return true;
  662. default:
  663. return false;
  664. }
  665. }
  666. static void ath9k_reclaim_beacon(struct ath_softc *sc,
  667. struct ieee80211_vif *vif)
  668. {
  669. struct ath_vif *avp = (void *)vif->drv_priv;
  670. ath9k_set_beaconing_status(sc, false);
  671. ath_beacon_return(sc, avp);
  672. ath9k_set_beaconing_status(sc, true);
  673. }
  674. static void ath9k_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
  675. {
  676. struct ath9k_vif_iter_data *iter_data = data;
  677. int i;
  678. if (iter_data->hw_macaddr)
  679. for (i = 0; i < ETH_ALEN; i++)
  680. iter_data->mask[i] &=
  681. ~(iter_data->hw_macaddr[i] ^ mac[i]);
  682. switch (vif->type) {
  683. case NL80211_IFTYPE_AP:
  684. iter_data->naps++;
  685. break;
  686. case NL80211_IFTYPE_STATION:
  687. iter_data->nstations++;
  688. break;
  689. case NL80211_IFTYPE_ADHOC:
  690. iter_data->nadhocs++;
  691. break;
  692. case NL80211_IFTYPE_MESH_POINT:
  693. iter_data->nmeshes++;
  694. break;
  695. case NL80211_IFTYPE_WDS:
  696. iter_data->nwds++;
  697. break;
  698. default:
  699. break;
  700. }
  701. }
  702. /* Called with sc->mutex held. */
  703. void ath9k_calculate_iter_data(struct ieee80211_hw *hw,
  704. struct ieee80211_vif *vif,
  705. struct ath9k_vif_iter_data *iter_data)
  706. {
  707. struct ath_softc *sc = hw->priv;
  708. struct ath_hw *ah = sc->sc_ah;
  709. struct ath_common *common = ath9k_hw_common(ah);
  710. /*
  711. * Use the hardware MAC address as reference, the hardware uses it
  712. * together with the BSSID mask when matching addresses.
  713. */
  714. memset(iter_data, 0, sizeof(*iter_data));
  715. iter_data->hw_macaddr = common->macaddr;
  716. memset(&iter_data->mask, 0xff, ETH_ALEN);
  717. if (vif)
  718. ath9k_vif_iter(iter_data, vif->addr, vif);
  719. /* Get list of all active MAC addresses */
  720. ieee80211_iterate_active_interfaces_atomic(sc->hw, ath9k_vif_iter,
  721. iter_data);
  722. }
  723. /* Called with sc->mutex held. */
  724. static void ath9k_calculate_summary_state(struct ieee80211_hw *hw,
  725. struct ieee80211_vif *vif)
  726. {
  727. struct ath_softc *sc = hw->priv;
  728. struct ath_hw *ah = sc->sc_ah;
  729. struct ath_common *common = ath9k_hw_common(ah);
  730. struct ath9k_vif_iter_data iter_data;
  731. ath9k_calculate_iter_data(hw, vif, &iter_data);
  732. /* Set BSSID mask. */
  733. memcpy(common->bssidmask, iter_data.mask, ETH_ALEN);
  734. ath_hw_setbssidmask(common);
  735. /* Set op-mode & TSF */
  736. if (iter_data.naps > 0) {
  737. ath9k_hw_set_tsfadjust(ah, 1);
  738. set_bit(SC_OP_TSF_RESET, &sc->sc_flags);
  739. ah->opmode = NL80211_IFTYPE_AP;
  740. } else {
  741. ath9k_hw_set_tsfadjust(ah, 0);
  742. clear_bit(SC_OP_TSF_RESET, &sc->sc_flags);
  743. if (iter_data.nmeshes)
  744. ah->opmode = NL80211_IFTYPE_MESH_POINT;
  745. else if (iter_data.nwds)
  746. ah->opmode = NL80211_IFTYPE_AP;
  747. else if (iter_data.nadhocs)
  748. ah->opmode = NL80211_IFTYPE_ADHOC;
  749. else
  750. ah->opmode = NL80211_IFTYPE_STATION;
  751. }
  752. /*
  753. * Enable MIB interrupts when there are hardware phy counters.
  754. */
  755. if ((iter_data.nstations + iter_data.nadhocs + iter_data.nmeshes) > 0) {
  756. if (ah->config.enable_ani)
  757. ah->imask |= ATH9K_INT_MIB;
  758. ah->imask |= ATH9K_INT_TSFOOR;
  759. } else {
  760. ah->imask &= ~ATH9K_INT_MIB;
  761. ah->imask &= ~ATH9K_INT_TSFOOR;
  762. }
  763. ath9k_hw_set_interrupts(ah);
  764. /* Set up ANI */
  765. if (iter_data.naps > 0) {
  766. sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
  767. if (!common->disable_ani) {
  768. set_bit(SC_OP_ANI_RUN, &sc->sc_flags);
  769. ath_start_ani(common);
  770. }
  771. } else {
  772. clear_bit(SC_OP_ANI_RUN, &sc->sc_flags);
  773. del_timer_sync(&common->ani.timer);
  774. }
  775. }
  776. /* Called with sc->mutex held, vif counts set up properly. */
  777. static void ath9k_do_vif_add_setup(struct ieee80211_hw *hw,
  778. struct ieee80211_vif *vif)
  779. {
  780. struct ath_softc *sc = hw->priv;
  781. ath9k_calculate_summary_state(hw, vif);
  782. if (ath9k_uses_beacons(vif->type)) {
  783. /* Reserve a beacon slot for the vif */
  784. ath9k_set_beaconing_status(sc, false);
  785. ath_beacon_alloc(sc, vif);
  786. ath9k_set_beaconing_status(sc, true);
  787. }
  788. }
  789. static int ath9k_add_interface(struct ieee80211_hw *hw,
  790. struct ieee80211_vif *vif)
  791. {
  792. struct ath_softc *sc = hw->priv;
  793. struct ath_hw *ah = sc->sc_ah;
  794. struct ath_common *common = ath9k_hw_common(ah);
  795. int ret = 0;
  796. ath9k_ps_wakeup(sc);
  797. mutex_lock(&sc->mutex);
  798. switch (vif->type) {
  799. case NL80211_IFTYPE_STATION:
  800. case NL80211_IFTYPE_WDS:
  801. case NL80211_IFTYPE_ADHOC:
  802. case NL80211_IFTYPE_AP:
  803. case NL80211_IFTYPE_MESH_POINT:
  804. break;
  805. default:
  806. ath_err(common, "Interface type %d not yet supported\n",
  807. vif->type);
  808. ret = -EOPNOTSUPP;
  809. goto out;
  810. }
  811. if (ath9k_uses_beacons(vif->type)) {
  812. if (sc->nbcnvifs >= ATH_BCBUF) {
  813. ath_err(common, "Not enough beacon buffers when adding"
  814. " new interface of type: %i\n",
  815. vif->type);
  816. ret = -ENOBUFS;
  817. goto out;
  818. }
  819. }
  820. if ((ah->opmode == NL80211_IFTYPE_ADHOC) ||
  821. ((vif->type == NL80211_IFTYPE_ADHOC) &&
  822. sc->nvifs > 0)) {
  823. ath_err(common, "Cannot create ADHOC interface when other"
  824. " interfaces already exist.\n");
  825. ret = -EINVAL;
  826. goto out;
  827. }
  828. ath_dbg(common, CONFIG, "Attach a VIF of type: %d\n", vif->type);
  829. sc->nvifs++;
  830. ath9k_do_vif_add_setup(hw, vif);
  831. out:
  832. mutex_unlock(&sc->mutex);
  833. ath9k_ps_restore(sc);
  834. return ret;
  835. }
  836. static int ath9k_change_interface(struct ieee80211_hw *hw,
  837. struct ieee80211_vif *vif,
  838. enum nl80211_iftype new_type,
  839. bool p2p)
  840. {
  841. struct ath_softc *sc = hw->priv;
  842. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  843. int ret = 0;
  844. ath_dbg(common, CONFIG, "Change Interface\n");
  845. mutex_lock(&sc->mutex);
  846. ath9k_ps_wakeup(sc);
  847. /* See if new interface type is valid. */
  848. if ((new_type == NL80211_IFTYPE_ADHOC) &&
  849. (sc->nvifs > 1)) {
  850. ath_err(common, "When using ADHOC, it must be the only"
  851. " interface.\n");
  852. ret = -EINVAL;
  853. goto out;
  854. }
  855. if (ath9k_uses_beacons(new_type) &&
  856. !ath9k_uses_beacons(vif->type)) {
  857. if (sc->nbcnvifs >= ATH_BCBUF) {
  858. ath_err(common, "No beacon slot available\n");
  859. ret = -ENOBUFS;
  860. goto out;
  861. }
  862. }
  863. /* Clean up old vif stuff */
  864. if (ath9k_uses_beacons(vif->type))
  865. ath9k_reclaim_beacon(sc, vif);
  866. /* Add new settings */
  867. vif->type = new_type;
  868. vif->p2p = p2p;
  869. ath9k_do_vif_add_setup(hw, vif);
  870. out:
  871. ath9k_ps_restore(sc);
  872. mutex_unlock(&sc->mutex);
  873. return ret;
  874. }
  875. static void ath9k_remove_interface(struct ieee80211_hw *hw,
  876. struct ieee80211_vif *vif)
  877. {
  878. struct ath_softc *sc = hw->priv;
  879. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  880. ath_dbg(common, CONFIG, "Detach Interface\n");
  881. ath9k_ps_wakeup(sc);
  882. mutex_lock(&sc->mutex);
  883. sc->nvifs--;
  884. /* Reclaim beacon resources */
  885. if (ath9k_uses_beacons(vif->type))
  886. ath9k_reclaim_beacon(sc, vif);
  887. ath9k_calculate_summary_state(hw, NULL);
  888. mutex_unlock(&sc->mutex);
  889. ath9k_ps_restore(sc);
  890. }
  891. static void ath9k_enable_ps(struct ath_softc *sc)
  892. {
  893. struct ath_hw *ah = sc->sc_ah;
  894. struct ath_common *common = ath9k_hw_common(ah);
  895. sc->ps_enabled = true;
  896. if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
  897. if ((ah->imask & ATH9K_INT_TIM_TIMER) == 0) {
  898. ah->imask |= ATH9K_INT_TIM_TIMER;
  899. ath9k_hw_set_interrupts(ah);
  900. }
  901. ath9k_hw_setrxabort(ah, 1);
  902. }
  903. ath_dbg(common, PS, "PowerSave enabled\n");
  904. }
  905. static void ath9k_disable_ps(struct ath_softc *sc)
  906. {
  907. struct ath_hw *ah = sc->sc_ah;
  908. struct ath_common *common = ath9k_hw_common(ah);
  909. sc->ps_enabled = false;
  910. ath9k_hw_setpower(ah, ATH9K_PM_AWAKE);
  911. if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
  912. ath9k_hw_setrxabort(ah, 0);
  913. sc->ps_flags &= ~(PS_WAIT_FOR_BEACON |
  914. PS_WAIT_FOR_CAB |
  915. PS_WAIT_FOR_PSPOLL_DATA |
  916. PS_WAIT_FOR_TX_ACK);
  917. if (ah->imask & ATH9K_INT_TIM_TIMER) {
  918. ah->imask &= ~ATH9K_INT_TIM_TIMER;
  919. ath9k_hw_set_interrupts(ah);
  920. }
  921. }
  922. ath_dbg(common, PS, "PowerSave disabled\n");
  923. }
  924. static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
  925. {
  926. struct ath_softc *sc = hw->priv;
  927. struct ath_hw *ah = sc->sc_ah;
  928. struct ath_common *common = ath9k_hw_common(ah);
  929. struct ieee80211_conf *conf = &hw->conf;
  930. bool reset_channel = false;
  931. ath9k_ps_wakeup(sc);
  932. mutex_lock(&sc->mutex);
  933. if (changed & IEEE80211_CONF_CHANGE_IDLE) {
  934. sc->ps_idle = !!(conf->flags & IEEE80211_CONF_IDLE);
  935. if (sc->ps_idle)
  936. ath_cancel_work(sc);
  937. else
  938. /*
  939. * The chip needs a reset to properly wake up from
  940. * full sleep
  941. */
  942. reset_channel = ah->chip_fullsleep;
  943. }
  944. /*
  945. * We just prepare to enable PS. We have to wait until our AP has
  946. * ACK'd our null data frame to disable RX otherwise we'll ignore
  947. * those ACKs and end up retransmitting the same null data frames.
  948. * IEEE80211_CONF_CHANGE_PS is only passed by mac80211 for STA mode.
  949. */
  950. if (changed & IEEE80211_CONF_CHANGE_PS) {
  951. unsigned long flags;
  952. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  953. if (conf->flags & IEEE80211_CONF_PS)
  954. ath9k_enable_ps(sc);
  955. else
  956. ath9k_disable_ps(sc);
  957. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  958. }
  959. if (changed & IEEE80211_CONF_CHANGE_MONITOR) {
  960. if (conf->flags & IEEE80211_CONF_MONITOR) {
  961. ath_dbg(common, CONFIG, "Monitor mode is enabled\n");
  962. sc->sc_ah->is_monitoring = true;
  963. } else {
  964. ath_dbg(common, CONFIG, "Monitor mode is disabled\n");
  965. sc->sc_ah->is_monitoring = false;
  966. }
  967. }
  968. if ((changed & IEEE80211_CONF_CHANGE_CHANNEL) || reset_channel) {
  969. struct ieee80211_channel *curchan = hw->conf.channel;
  970. int pos = curchan->hw_value;
  971. int old_pos = -1;
  972. unsigned long flags;
  973. if (ah->curchan)
  974. old_pos = ah->curchan - &ah->channels[0];
  975. ath_dbg(common, CONFIG, "Set channel: %d MHz type: %d\n",
  976. curchan->center_freq, conf->channel_type);
  977. /* update survey stats for the old channel before switching */
  978. spin_lock_irqsave(&common->cc_lock, flags);
  979. ath_update_survey_stats(sc);
  980. spin_unlock_irqrestore(&common->cc_lock, flags);
  981. /*
  982. * Preserve the current channel values, before updating
  983. * the same channel
  984. */
  985. if (ah->curchan && (old_pos == pos))
  986. ath9k_hw_getnf(ah, ah->curchan);
  987. ath9k_cmn_update_ichannel(&sc->sc_ah->channels[pos],
  988. curchan, conf->channel_type);
  989. /*
  990. * If the operating channel changes, change the survey in-use flags
  991. * along with it.
  992. * Reset the survey data for the new channel, unless we're switching
  993. * back to the operating channel from an off-channel operation.
  994. */
  995. if (!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL) &&
  996. sc->cur_survey != &sc->survey[pos]) {
  997. if (sc->cur_survey)
  998. sc->cur_survey->filled &= ~SURVEY_INFO_IN_USE;
  999. sc->cur_survey = &sc->survey[pos];
  1000. memset(sc->cur_survey, 0, sizeof(struct survey_info));
  1001. sc->cur_survey->filled |= SURVEY_INFO_IN_USE;
  1002. } else if (!(sc->survey[pos].filled & SURVEY_INFO_IN_USE)) {
  1003. memset(&sc->survey[pos], 0, sizeof(struct survey_info));
  1004. }
  1005. if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) {
  1006. ath_err(common, "Unable to set channel\n");
  1007. mutex_unlock(&sc->mutex);
  1008. return -EINVAL;
  1009. }
  1010. /*
  1011. * The most recent snapshot of channel->noisefloor for the old
  1012. * channel is only available after the hardware reset. Copy it to
  1013. * the survey stats now.
  1014. */
  1015. if (old_pos >= 0)
  1016. ath_update_survey_nf(sc, old_pos);
  1017. }
  1018. if (changed & IEEE80211_CONF_CHANGE_POWER) {
  1019. ath_dbg(common, CONFIG, "Set power: %d\n", conf->power_level);
  1020. sc->config.txpowlimit = 2 * conf->power_level;
  1021. ath9k_cmn_update_txpow(ah, sc->curtxpow,
  1022. sc->config.txpowlimit, &sc->curtxpow);
  1023. }
  1024. mutex_unlock(&sc->mutex);
  1025. ath9k_ps_restore(sc);
  1026. return 0;
  1027. }
  1028. #define SUPPORTED_FILTERS \
  1029. (FIF_PROMISC_IN_BSS | \
  1030. FIF_ALLMULTI | \
  1031. FIF_CONTROL | \
  1032. FIF_PSPOLL | \
  1033. FIF_OTHER_BSS | \
  1034. FIF_BCN_PRBRESP_PROMISC | \
  1035. FIF_PROBE_REQ | \
  1036. FIF_FCSFAIL)
  1037. /* FIXME: sc->sc_full_reset ? */
  1038. static void ath9k_configure_filter(struct ieee80211_hw *hw,
  1039. unsigned int changed_flags,
  1040. unsigned int *total_flags,
  1041. u64 multicast)
  1042. {
  1043. struct ath_softc *sc = hw->priv;
  1044. u32 rfilt;
  1045. changed_flags &= SUPPORTED_FILTERS;
  1046. *total_flags &= SUPPORTED_FILTERS;
  1047. sc->rx.rxfilter = *total_flags;
  1048. ath9k_ps_wakeup(sc);
  1049. rfilt = ath_calcrxfilter(sc);
  1050. ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
  1051. ath9k_ps_restore(sc);
  1052. ath_dbg(ath9k_hw_common(sc->sc_ah), CONFIG, "Set HW RX filter: 0x%x\n",
  1053. rfilt);
  1054. }
  1055. static int ath9k_sta_add(struct ieee80211_hw *hw,
  1056. struct ieee80211_vif *vif,
  1057. struct ieee80211_sta *sta)
  1058. {
  1059. struct ath_softc *sc = hw->priv;
  1060. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1061. struct ath_node *an = (struct ath_node *) sta->drv_priv;
  1062. struct ieee80211_key_conf ps_key = { };
  1063. ath_node_attach(sc, sta, vif);
  1064. if (vif->type != NL80211_IFTYPE_AP &&
  1065. vif->type != NL80211_IFTYPE_AP_VLAN)
  1066. return 0;
  1067. an->ps_key = ath_key_config(common, vif, sta, &ps_key);
  1068. return 0;
  1069. }
  1070. static void ath9k_del_ps_key(struct ath_softc *sc,
  1071. struct ieee80211_vif *vif,
  1072. struct ieee80211_sta *sta)
  1073. {
  1074. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1075. struct ath_node *an = (struct ath_node *) sta->drv_priv;
  1076. struct ieee80211_key_conf ps_key = { .hw_key_idx = an->ps_key };
  1077. if (!an->ps_key)
  1078. return;
  1079. ath_key_delete(common, &ps_key);
  1080. }
  1081. static int ath9k_sta_remove(struct ieee80211_hw *hw,
  1082. struct ieee80211_vif *vif,
  1083. struct ieee80211_sta *sta)
  1084. {
  1085. struct ath_softc *sc = hw->priv;
  1086. ath9k_del_ps_key(sc, vif, sta);
  1087. ath_node_detach(sc, sta);
  1088. return 0;
  1089. }
  1090. static void ath9k_sta_notify(struct ieee80211_hw *hw,
  1091. struct ieee80211_vif *vif,
  1092. enum sta_notify_cmd cmd,
  1093. struct ieee80211_sta *sta)
  1094. {
  1095. struct ath_softc *sc = hw->priv;
  1096. struct ath_node *an = (struct ath_node *) sta->drv_priv;
  1097. if (!sta->ht_cap.ht_supported)
  1098. return;
  1099. switch (cmd) {
  1100. case STA_NOTIFY_SLEEP:
  1101. an->sleeping = true;
  1102. ath_tx_aggr_sleep(sta, sc, an);
  1103. break;
  1104. case STA_NOTIFY_AWAKE:
  1105. an->sleeping = false;
  1106. ath_tx_aggr_wakeup(sc, an);
  1107. break;
  1108. }
  1109. }
  1110. static int ath9k_conf_tx(struct ieee80211_hw *hw,
  1111. struct ieee80211_vif *vif, u16 queue,
  1112. const struct ieee80211_tx_queue_params *params)
  1113. {
  1114. struct ath_softc *sc = hw->priv;
  1115. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1116. struct ath_txq *txq;
  1117. struct ath9k_tx_queue_info qi;
  1118. int ret = 0;
  1119. if (queue >= WME_NUM_AC)
  1120. return 0;
  1121. txq = sc->tx.txq_map[queue];
  1122. ath9k_ps_wakeup(sc);
  1123. mutex_lock(&sc->mutex);
  1124. memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
  1125. qi.tqi_aifs = params->aifs;
  1126. qi.tqi_cwmin = params->cw_min;
  1127. qi.tqi_cwmax = params->cw_max;
  1128. qi.tqi_burstTime = params->txop;
  1129. ath_dbg(common, CONFIG,
  1130. "Configure tx [queue/halq] [%d/%d], aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
  1131. queue, txq->axq_qnum, params->aifs, params->cw_min,
  1132. params->cw_max, params->txop);
  1133. ret = ath_txq_update(sc, txq->axq_qnum, &qi);
  1134. if (ret)
  1135. ath_err(common, "TXQ Update failed\n");
  1136. if (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC)
  1137. if (queue == WME_AC_BE && !ret)
  1138. ath_beaconq_config(sc);
  1139. mutex_unlock(&sc->mutex);
  1140. ath9k_ps_restore(sc);
  1141. return ret;
  1142. }
  1143. static int ath9k_set_key(struct ieee80211_hw *hw,
  1144. enum set_key_cmd cmd,
  1145. struct ieee80211_vif *vif,
  1146. struct ieee80211_sta *sta,
  1147. struct ieee80211_key_conf *key)
  1148. {
  1149. struct ath_softc *sc = hw->priv;
  1150. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1151. int ret = 0;
  1152. if (ath9k_modparam_nohwcrypt)
  1153. return -ENOSPC;
  1154. if ((vif->type == NL80211_IFTYPE_ADHOC ||
  1155. vif->type == NL80211_IFTYPE_MESH_POINT) &&
  1156. (key->cipher == WLAN_CIPHER_SUITE_TKIP ||
  1157. key->cipher == WLAN_CIPHER_SUITE_CCMP) &&
  1158. !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
  1159. /*
  1160. * For now, disable hw crypto for the RSN IBSS group keys. This
  1161. * could be optimized in the future to use a modified key cache
  1162. * design to support per-STA RX GTK, but until that gets
  1163. * implemented, use of software crypto for group addressed
  1164. * frames is a acceptable to allow RSN IBSS to be used.
  1165. */
  1166. return -EOPNOTSUPP;
  1167. }
  1168. mutex_lock(&sc->mutex);
  1169. ath9k_ps_wakeup(sc);
  1170. ath_dbg(common, CONFIG, "Set HW Key\n");
  1171. switch (cmd) {
  1172. case SET_KEY:
  1173. if (sta)
  1174. ath9k_del_ps_key(sc, vif, sta);
  1175. ret = ath_key_config(common, vif, sta, key);
  1176. if (ret >= 0) {
  1177. key->hw_key_idx = ret;
  1178. /* push IV and Michael MIC generation to stack */
  1179. key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
  1180. if (key->cipher == WLAN_CIPHER_SUITE_TKIP)
  1181. key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
  1182. if (sc->sc_ah->sw_mgmt_crypto &&
  1183. key->cipher == WLAN_CIPHER_SUITE_CCMP)
  1184. key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
  1185. ret = 0;
  1186. }
  1187. break;
  1188. case DISABLE_KEY:
  1189. ath_key_delete(common, key);
  1190. break;
  1191. default:
  1192. ret = -EINVAL;
  1193. }
  1194. ath9k_ps_restore(sc);
  1195. mutex_unlock(&sc->mutex);
  1196. return ret;
  1197. }
  1198. static void ath9k_bss_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
  1199. {
  1200. struct ath_softc *sc = data;
  1201. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1202. struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
  1203. struct ath_vif *avp = (void *)vif->drv_priv;
  1204. /*
  1205. * Skip iteration if primary station vif's bss info
  1206. * was not changed
  1207. */
  1208. if (test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags))
  1209. return;
  1210. if (bss_conf->assoc) {
  1211. set_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags);
  1212. avp->primary_sta_vif = true;
  1213. memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
  1214. common->curaid = bss_conf->aid;
  1215. ath9k_hw_write_associd(sc->sc_ah);
  1216. ath_dbg(common, CONFIG, "Bss Info ASSOC %d, bssid: %pM\n",
  1217. bss_conf->aid, common->curbssid);
  1218. ath_beacon_config(sc, vif);
  1219. /*
  1220. * Request a re-configuration of Beacon related timers
  1221. * on the receipt of the first Beacon frame (i.e.,
  1222. * after time sync with the AP).
  1223. */
  1224. sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON;
  1225. /* Reset rssi stats */
  1226. sc->last_rssi = ATH_RSSI_DUMMY_MARKER;
  1227. sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
  1228. ath_start_rx_poll(sc, 3);
  1229. if (!common->disable_ani) {
  1230. set_bit(SC_OP_ANI_RUN, &sc->sc_flags);
  1231. ath_start_ani(common);
  1232. }
  1233. }
  1234. }
  1235. static void ath9k_config_bss(struct ath_softc *sc, struct ieee80211_vif *vif)
  1236. {
  1237. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1238. struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
  1239. struct ath_vif *avp = (void *)vif->drv_priv;
  1240. if (sc->sc_ah->opmode != NL80211_IFTYPE_STATION)
  1241. return;
  1242. /* Reconfigure bss info */
  1243. if (avp->primary_sta_vif && !bss_conf->assoc) {
  1244. ath_dbg(common, CONFIG, "Bss Info DISASSOC %d, bssid %pM\n",
  1245. common->curaid, common->curbssid);
  1246. clear_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags);
  1247. clear_bit(SC_OP_BEACONS, &sc->sc_flags);
  1248. avp->primary_sta_vif = false;
  1249. memset(common->curbssid, 0, ETH_ALEN);
  1250. common->curaid = 0;
  1251. }
  1252. ieee80211_iterate_active_interfaces_atomic(
  1253. sc->hw, ath9k_bss_iter, sc);
  1254. /*
  1255. * None of station vifs are associated.
  1256. * Clear bssid & aid
  1257. */
  1258. if (!test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags)) {
  1259. ath9k_hw_write_associd(sc->sc_ah);
  1260. clear_bit(SC_OP_ANI_RUN, &sc->sc_flags);
  1261. del_timer_sync(&common->ani.timer);
  1262. del_timer_sync(&sc->rx_poll_timer);
  1263. memset(&sc->caldata, 0, sizeof(sc->caldata));
  1264. }
  1265. }
  1266. static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
  1267. struct ieee80211_vif *vif,
  1268. struct ieee80211_bss_conf *bss_conf,
  1269. u32 changed)
  1270. {
  1271. struct ath_softc *sc = hw->priv;
  1272. struct ath_hw *ah = sc->sc_ah;
  1273. struct ath_common *common = ath9k_hw_common(ah);
  1274. struct ath_vif *avp = (void *)vif->drv_priv;
  1275. int slottime;
  1276. ath9k_ps_wakeup(sc);
  1277. mutex_lock(&sc->mutex);
  1278. if (changed & BSS_CHANGED_ASSOC) {
  1279. ath9k_config_bss(sc, vif);
  1280. ath_dbg(common, CONFIG, "BSSID: %pM aid: 0x%x\n",
  1281. common->curbssid, common->curaid);
  1282. }
  1283. if (changed & BSS_CHANGED_IBSS) {
  1284. /* There can be only one vif available */
  1285. memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
  1286. common->curaid = bss_conf->aid;
  1287. ath9k_hw_write_associd(sc->sc_ah);
  1288. if (bss_conf->ibss_joined) {
  1289. sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
  1290. if (!common->disable_ani) {
  1291. set_bit(SC_OP_ANI_RUN, &sc->sc_flags);
  1292. ath_start_ani(common);
  1293. }
  1294. } else {
  1295. clear_bit(SC_OP_ANI_RUN, &sc->sc_flags);
  1296. del_timer_sync(&common->ani.timer);
  1297. del_timer_sync(&sc->rx_poll_timer);
  1298. }
  1299. }
  1300. /*
  1301. * In case of AP mode, the HW TSF has to be reset
  1302. * when the beacon interval changes.
  1303. */
  1304. if ((changed & BSS_CHANGED_BEACON_INT) &&
  1305. (vif->type == NL80211_IFTYPE_AP))
  1306. set_bit(SC_OP_TSF_RESET, &sc->sc_flags);
  1307. /* Configure beaconing (AP, IBSS, MESH) */
  1308. if (ath9k_uses_beacons(vif->type) &&
  1309. ((changed & BSS_CHANGED_BEACON) ||
  1310. (changed & BSS_CHANGED_BEACON_ENABLED) ||
  1311. (changed & BSS_CHANGED_BEACON_INT))) {
  1312. ath9k_set_beaconing_status(sc, false);
  1313. if (bss_conf->enable_beacon)
  1314. ath_beacon_alloc(sc, vif);
  1315. else
  1316. avp->is_bslot_active = false;
  1317. ath_beacon_config(sc, vif);
  1318. ath9k_set_beaconing_status(sc, true);
  1319. }
  1320. if (changed & BSS_CHANGED_ERP_SLOT) {
  1321. if (bss_conf->use_short_slot)
  1322. slottime = 9;
  1323. else
  1324. slottime = 20;
  1325. if (vif->type == NL80211_IFTYPE_AP) {
  1326. /*
  1327. * Defer update, so that connected stations can adjust
  1328. * their settings at the same time.
  1329. * See beacon.c for more details
  1330. */
  1331. sc->beacon.slottime = slottime;
  1332. sc->beacon.updateslot = UPDATE;
  1333. } else {
  1334. ah->slottime = slottime;
  1335. ath9k_hw_init_global_settings(ah);
  1336. }
  1337. }
  1338. mutex_unlock(&sc->mutex);
  1339. ath9k_ps_restore(sc);
  1340. }
  1341. static u64 ath9k_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
  1342. {
  1343. struct ath_softc *sc = hw->priv;
  1344. u64 tsf;
  1345. mutex_lock(&sc->mutex);
  1346. ath9k_ps_wakeup(sc);
  1347. tsf = ath9k_hw_gettsf64(sc->sc_ah);
  1348. ath9k_ps_restore(sc);
  1349. mutex_unlock(&sc->mutex);
  1350. return tsf;
  1351. }
  1352. static void ath9k_set_tsf(struct ieee80211_hw *hw,
  1353. struct ieee80211_vif *vif,
  1354. u64 tsf)
  1355. {
  1356. struct ath_softc *sc = hw->priv;
  1357. mutex_lock(&sc->mutex);
  1358. ath9k_ps_wakeup(sc);
  1359. ath9k_hw_settsf64(sc->sc_ah, tsf);
  1360. ath9k_ps_restore(sc);
  1361. mutex_unlock(&sc->mutex);
  1362. }
  1363. static void ath9k_reset_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
  1364. {
  1365. struct ath_softc *sc = hw->priv;
  1366. mutex_lock(&sc->mutex);
  1367. ath9k_ps_wakeup(sc);
  1368. ath9k_hw_reset_tsf(sc->sc_ah);
  1369. ath9k_ps_restore(sc);
  1370. mutex_unlock(&sc->mutex);
  1371. }
  1372. static int ath9k_ampdu_action(struct ieee80211_hw *hw,
  1373. struct ieee80211_vif *vif,
  1374. enum ieee80211_ampdu_mlme_action action,
  1375. struct ieee80211_sta *sta,
  1376. u16 tid, u16 *ssn, u8 buf_size)
  1377. {
  1378. struct ath_softc *sc = hw->priv;
  1379. int ret = 0;
  1380. local_bh_disable();
  1381. switch (action) {
  1382. case IEEE80211_AMPDU_RX_START:
  1383. break;
  1384. case IEEE80211_AMPDU_RX_STOP:
  1385. break;
  1386. case IEEE80211_AMPDU_TX_START:
  1387. ath9k_ps_wakeup(sc);
  1388. ret = ath_tx_aggr_start(sc, sta, tid, ssn);
  1389. if (!ret)
  1390. ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
  1391. ath9k_ps_restore(sc);
  1392. break;
  1393. case IEEE80211_AMPDU_TX_STOP:
  1394. ath9k_ps_wakeup(sc);
  1395. ath_tx_aggr_stop(sc, sta, tid);
  1396. ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
  1397. ath9k_ps_restore(sc);
  1398. break;
  1399. case IEEE80211_AMPDU_TX_OPERATIONAL:
  1400. ath9k_ps_wakeup(sc);
  1401. ath_tx_aggr_resume(sc, sta, tid);
  1402. ath9k_ps_restore(sc);
  1403. break;
  1404. default:
  1405. ath_err(ath9k_hw_common(sc->sc_ah), "Unknown AMPDU action\n");
  1406. }
  1407. local_bh_enable();
  1408. return ret;
  1409. }
  1410. static int ath9k_get_survey(struct ieee80211_hw *hw, int idx,
  1411. struct survey_info *survey)
  1412. {
  1413. struct ath_softc *sc = hw->priv;
  1414. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1415. struct ieee80211_supported_band *sband;
  1416. struct ieee80211_channel *chan;
  1417. unsigned long flags;
  1418. int pos;
  1419. spin_lock_irqsave(&common->cc_lock, flags);
  1420. if (idx == 0)
  1421. ath_update_survey_stats(sc);
  1422. sband = hw->wiphy->bands[IEEE80211_BAND_2GHZ];
  1423. if (sband && idx >= sband->n_channels) {
  1424. idx -= sband->n_channels;
  1425. sband = NULL;
  1426. }
  1427. if (!sband)
  1428. sband = hw->wiphy->bands[IEEE80211_BAND_5GHZ];
  1429. if (!sband || idx >= sband->n_channels) {
  1430. spin_unlock_irqrestore(&common->cc_lock, flags);
  1431. return -ENOENT;
  1432. }
  1433. chan = &sband->channels[idx];
  1434. pos = chan->hw_value;
  1435. memcpy(survey, &sc->survey[pos], sizeof(*survey));
  1436. survey->channel = chan;
  1437. spin_unlock_irqrestore(&common->cc_lock, flags);
  1438. return 0;
  1439. }
  1440. static void ath9k_set_coverage_class(struct ieee80211_hw *hw, u8 coverage_class)
  1441. {
  1442. struct ath_softc *sc = hw->priv;
  1443. struct ath_hw *ah = sc->sc_ah;
  1444. mutex_lock(&sc->mutex);
  1445. ah->coverage_class = coverage_class;
  1446. ath9k_ps_wakeup(sc);
  1447. ath9k_hw_init_global_settings(ah);
  1448. ath9k_ps_restore(sc);
  1449. mutex_unlock(&sc->mutex);
  1450. }
  1451. static void ath9k_flush(struct ieee80211_hw *hw, bool drop)
  1452. {
  1453. struct ath_softc *sc = hw->priv;
  1454. struct ath_hw *ah = sc->sc_ah;
  1455. struct ath_common *common = ath9k_hw_common(ah);
  1456. int timeout = 200; /* ms */
  1457. int i, j;
  1458. bool drain_txq;
  1459. mutex_lock(&sc->mutex);
  1460. cancel_delayed_work_sync(&sc->tx_complete_work);
  1461. if (ah->ah_flags & AH_UNPLUGGED) {
  1462. ath_dbg(common, ANY, "Device has been unplugged!\n");
  1463. mutex_unlock(&sc->mutex);
  1464. return;
  1465. }
  1466. if (test_bit(SC_OP_INVALID, &sc->sc_flags)) {
  1467. ath_dbg(common, ANY, "Device not present\n");
  1468. mutex_unlock(&sc->mutex);
  1469. return;
  1470. }
  1471. for (j = 0; j < timeout; j++) {
  1472. bool npend = false;
  1473. if (j)
  1474. usleep_range(1000, 2000);
  1475. for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
  1476. if (!ATH_TXQ_SETUP(sc, i))
  1477. continue;
  1478. npend = ath9k_has_pending_frames(sc, &sc->tx.txq[i]);
  1479. if (npend)
  1480. break;
  1481. }
  1482. if (!npend)
  1483. break;
  1484. }
  1485. if (drop) {
  1486. ath9k_ps_wakeup(sc);
  1487. spin_lock_bh(&sc->sc_pcu_lock);
  1488. drain_txq = ath_drain_all_txq(sc, false);
  1489. spin_unlock_bh(&sc->sc_pcu_lock);
  1490. if (!drain_txq)
  1491. ath_reset(sc, false);
  1492. ath9k_ps_restore(sc);
  1493. ieee80211_wake_queues(hw);
  1494. }
  1495. ieee80211_queue_delayed_work(hw, &sc->tx_complete_work, 0);
  1496. mutex_unlock(&sc->mutex);
  1497. }
  1498. static bool ath9k_tx_frames_pending(struct ieee80211_hw *hw)
  1499. {
  1500. struct ath_softc *sc = hw->priv;
  1501. int i;
  1502. for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
  1503. if (!ATH_TXQ_SETUP(sc, i))
  1504. continue;
  1505. if (ath9k_has_pending_frames(sc, &sc->tx.txq[i]))
  1506. return true;
  1507. }
  1508. return false;
  1509. }
  1510. static int ath9k_tx_last_beacon(struct ieee80211_hw *hw)
  1511. {
  1512. struct ath_softc *sc = hw->priv;
  1513. struct ath_hw *ah = sc->sc_ah;
  1514. struct ieee80211_vif *vif;
  1515. struct ath_vif *avp;
  1516. struct ath_buf *bf;
  1517. struct ath_tx_status ts;
  1518. bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
  1519. int status;
  1520. vif = sc->beacon.bslot[0];
  1521. if (!vif)
  1522. return 0;
  1523. avp = (void *)vif->drv_priv;
  1524. if (!avp->is_bslot_active)
  1525. return 0;
  1526. if (!sc->beacon.tx_processed && !edma) {
  1527. tasklet_disable(&sc->bcon_tasklet);
  1528. bf = avp->av_bcbuf;
  1529. if (!bf || !bf->bf_mpdu)
  1530. goto skip;
  1531. status = ath9k_hw_txprocdesc(ah, bf->bf_desc, &ts);
  1532. if (status == -EINPROGRESS)
  1533. goto skip;
  1534. sc->beacon.tx_processed = true;
  1535. sc->beacon.tx_last = !(ts.ts_status & ATH9K_TXERR_MASK);
  1536. skip:
  1537. tasklet_enable(&sc->bcon_tasklet);
  1538. }
  1539. return sc->beacon.tx_last;
  1540. }
  1541. static int ath9k_get_stats(struct ieee80211_hw *hw,
  1542. struct ieee80211_low_level_stats *stats)
  1543. {
  1544. struct ath_softc *sc = hw->priv;
  1545. struct ath_hw *ah = sc->sc_ah;
  1546. struct ath9k_mib_stats *mib_stats = &ah->ah_mibStats;
  1547. stats->dot11ACKFailureCount = mib_stats->ackrcv_bad;
  1548. stats->dot11RTSFailureCount = mib_stats->rts_bad;
  1549. stats->dot11FCSErrorCount = mib_stats->fcs_bad;
  1550. stats->dot11RTSSuccessCount = mib_stats->rts_good;
  1551. return 0;
  1552. }
  1553. static u32 fill_chainmask(u32 cap, u32 new)
  1554. {
  1555. u32 filled = 0;
  1556. int i;
  1557. for (i = 0; cap && new; i++, cap >>= 1) {
  1558. if (!(cap & BIT(0)))
  1559. continue;
  1560. if (new & BIT(0))
  1561. filled |= BIT(i);
  1562. new >>= 1;
  1563. }
  1564. return filled;
  1565. }
  1566. static int ath9k_set_antenna(struct ieee80211_hw *hw, u32 tx_ant, u32 rx_ant)
  1567. {
  1568. struct ath_softc *sc = hw->priv;
  1569. struct ath_hw *ah = sc->sc_ah;
  1570. if (!rx_ant || !tx_ant)
  1571. return -EINVAL;
  1572. sc->ant_rx = rx_ant;
  1573. sc->ant_tx = tx_ant;
  1574. if (ah->caps.rx_chainmask == 1)
  1575. return 0;
  1576. /* AR9100 runs into calibration issues if not all rx chains are enabled */
  1577. if (AR_SREV_9100(ah))
  1578. ah->rxchainmask = 0x7;
  1579. else
  1580. ah->rxchainmask = fill_chainmask(ah->caps.rx_chainmask, rx_ant);
  1581. ah->txchainmask = fill_chainmask(ah->caps.tx_chainmask, tx_ant);
  1582. ath9k_reload_chainmask_settings(sc);
  1583. return 0;
  1584. }
  1585. static int ath9k_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant)
  1586. {
  1587. struct ath_softc *sc = hw->priv;
  1588. *tx_ant = sc->ant_tx;
  1589. *rx_ant = sc->ant_rx;
  1590. return 0;
  1591. }
  1592. #ifdef CONFIG_ATH9K_DEBUGFS
  1593. /* Ethtool support for get-stats */
  1594. #define AMKSTR(nm) #nm "_BE", #nm "_BK", #nm "_VI", #nm "_VO"
  1595. static const char ath9k_gstrings_stats[][ETH_GSTRING_LEN] = {
  1596. "tx_pkts_nic",
  1597. "tx_bytes_nic",
  1598. "rx_pkts_nic",
  1599. "rx_bytes_nic",
  1600. AMKSTR(d_tx_pkts),
  1601. AMKSTR(d_tx_bytes),
  1602. AMKSTR(d_tx_mpdus_queued),
  1603. AMKSTR(d_tx_mpdus_completed),
  1604. AMKSTR(d_tx_mpdu_xretries),
  1605. AMKSTR(d_tx_aggregates),
  1606. AMKSTR(d_tx_ampdus_queued_hw),
  1607. AMKSTR(d_tx_ampdus_queued_sw),
  1608. AMKSTR(d_tx_ampdus_completed),
  1609. AMKSTR(d_tx_ampdu_retries),
  1610. AMKSTR(d_tx_ampdu_xretries),
  1611. AMKSTR(d_tx_fifo_underrun),
  1612. AMKSTR(d_tx_op_exceeded),
  1613. AMKSTR(d_tx_timer_expiry),
  1614. AMKSTR(d_tx_desc_cfg_err),
  1615. AMKSTR(d_tx_data_underrun),
  1616. AMKSTR(d_tx_delim_underrun),
  1617. "d_rx_decrypt_crc_err",
  1618. "d_rx_phy_err",
  1619. "d_rx_mic_err",
  1620. "d_rx_pre_delim_crc_err",
  1621. "d_rx_post_delim_crc_err",
  1622. "d_rx_decrypt_busy_err",
  1623. "d_rx_phyerr_radar",
  1624. "d_rx_phyerr_ofdm_timing",
  1625. "d_rx_phyerr_cck_timing",
  1626. };
  1627. #define ATH9K_SSTATS_LEN ARRAY_SIZE(ath9k_gstrings_stats)
  1628. static void ath9k_get_et_strings(struct ieee80211_hw *hw,
  1629. struct ieee80211_vif *vif,
  1630. u32 sset, u8 *data)
  1631. {
  1632. if (sset == ETH_SS_STATS)
  1633. memcpy(data, *ath9k_gstrings_stats,
  1634. sizeof(ath9k_gstrings_stats));
  1635. }
  1636. static int ath9k_get_et_sset_count(struct ieee80211_hw *hw,
  1637. struct ieee80211_vif *vif, int sset)
  1638. {
  1639. if (sset == ETH_SS_STATS)
  1640. return ATH9K_SSTATS_LEN;
  1641. return 0;
  1642. }
  1643. #define PR_QNUM(_n) (sc->tx.txq_map[_n]->axq_qnum)
  1644. #define AWDATA(elem) \
  1645. do { \
  1646. data[i++] = sc->debug.stats.txstats[PR_QNUM(WME_AC_BE)].elem; \
  1647. data[i++] = sc->debug.stats.txstats[PR_QNUM(WME_AC_BK)].elem; \
  1648. data[i++] = sc->debug.stats.txstats[PR_QNUM(WME_AC_VI)].elem; \
  1649. data[i++] = sc->debug.stats.txstats[PR_QNUM(WME_AC_VO)].elem; \
  1650. } while (0)
  1651. #define AWDATA_RX(elem) \
  1652. do { \
  1653. data[i++] = sc->debug.stats.rxstats.elem; \
  1654. } while (0)
  1655. static void ath9k_get_et_stats(struct ieee80211_hw *hw,
  1656. struct ieee80211_vif *vif,
  1657. struct ethtool_stats *stats, u64 *data)
  1658. {
  1659. struct ath_softc *sc = hw->priv;
  1660. int i = 0;
  1661. data[i++] = (sc->debug.stats.txstats[PR_QNUM(WME_AC_BE)].tx_pkts_all +
  1662. sc->debug.stats.txstats[PR_QNUM(WME_AC_BK)].tx_pkts_all +
  1663. sc->debug.stats.txstats[PR_QNUM(WME_AC_VI)].tx_pkts_all +
  1664. sc->debug.stats.txstats[PR_QNUM(WME_AC_VO)].tx_pkts_all);
  1665. data[i++] = (sc->debug.stats.txstats[PR_QNUM(WME_AC_BE)].tx_bytes_all +
  1666. sc->debug.stats.txstats[PR_QNUM(WME_AC_BK)].tx_bytes_all +
  1667. sc->debug.stats.txstats[PR_QNUM(WME_AC_VI)].tx_bytes_all +
  1668. sc->debug.stats.txstats[PR_QNUM(WME_AC_VO)].tx_bytes_all);
  1669. AWDATA_RX(rx_pkts_all);
  1670. AWDATA_RX(rx_bytes_all);
  1671. AWDATA(tx_pkts_all);
  1672. AWDATA(tx_bytes_all);
  1673. AWDATA(queued);
  1674. AWDATA(completed);
  1675. AWDATA(xretries);
  1676. AWDATA(a_aggr);
  1677. AWDATA(a_queued_hw);
  1678. AWDATA(a_queued_sw);
  1679. AWDATA(a_completed);
  1680. AWDATA(a_retries);
  1681. AWDATA(a_xretries);
  1682. AWDATA(fifo_underrun);
  1683. AWDATA(xtxop);
  1684. AWDATA(timer_exp);
  1685. AWDATA(desc_cfg_err);
  1686. AWDATA(data_underrun);
  1687. AWDATA(delim_underrun);
  1688. AWDATA_RX(decrypt_crc_err);
  1689. AWDATA_RX(phy_err);
  1690. AWDATA_RX(mic_err);
  1691. AWDATA_RX(pre_delim_crc_err);
  1692. AWDATA_RX(post_delim_crc_err);
  1693. AWDATA_RX(decrypt_busy_err);
  1694. AWDATA_RX(phy_err_stats[ATH9K_PHYERR_RADAR]);
  1695. AWDATA_RX(phy_err_stats[ATH9K_PHYERR_OFDM_TIMING]);
  1696. AWDATA_RX(phy_err_stats[ATH9K_PHYERR_CCK_TIMING]);
  1697. WARN_ON(i != ATH9K_SSTATS_LEN);
  1698. }
  1699. /* End of ethtool get-stats functions */
  1700. #endif
  1701. struct ieee80211_ops ath9k_ops = {
  1702. .tx = ath9k_tx,
  1703. .start = ath9k_start,
  1704. .stop = ath9k_stop,
  1705. .add_interface = ath9k_add_interface,
  1706. .change_interface = ath9k_change_interface,
  1707. .remove_interface = ath9k_remove_interface,
  1708. .config = ath9k_config,
  1709. .configure_filter = ath9k_configure_filter,
  1710. .sta_add = ath9k_sta_add,
  1711. .sta_remove = ath9k_sta_remove,
  1712. .sta_notify = ath9k_sta_notify,
  1713. .conf_tx = ath9k_conf_tx,
  1714. .bss_info_changed = ath9k_bss_info_changed,
  1715. .set_key = ath9k_set_key,
  1716. .get_tsf = ath9k_get_tsf,
  1717. .set_tsf = ath9k_set_tsf,
  1718. .reset_tsf = ath9k_reset_tsf,
  1719. .ampdu_action = ath9k_ampdu_action,
  1720. .get_survey = ath9k_get_survey,
  1721. .rfkill_poll = ath9k_rfkill_poll_state,
  1722. .set_coverage_class = ath9k_set_coverage_class,
  1723. .flush = ath9k_flush,
  1724. .tx_frames_pending = ath9k_tx_frames_pending,
  1725. .tx_last_beacon = ath9k_tx_last_beacon,
  1726. .get_stats = ath9k_get_stats,
  1727. .set_antenna = ath9k_set_antenna,
  1728. .get_antenna = ath9k_get_antenna,
  1729. #ifdef CONFIG_ATH9K_DEBUGFS
  1730. .get_et_sset_count = ath9k_get_et_sset_count,
  1731. .get_et_stats = ath9k_get_et_stats,
  1732. .get_et_strings = ath9k_get_et_strings,
  1733. #endif
  1734. };