iwl3945-base.c 197 KB

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  1. /******************************************************************************
  2. *
  3. * Copyright(c) 2003 - 2009 Intel Corporation. All rights reserved.
  4. *
  5. * Portions of this file are derived from the ipw3945 project, as well
  6. * as portions of the ieee80211 subsystem header files.
  7. *
  8. * This program is free software; you can redistribute it and/or modify it
  9. * under the terms of version 2 of the GNU General Public License as
  10. * published by the Free Software Foundation.
  11. *
  12. * This program is distributed in the hope that it will be useful, but WITHOUT
  13. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  15. * more details.
  16. *
  17. * You should have received a copy of the GNU General Public License along with
  18. * this program; if not, write to the Free Software Foundation, Inc.,
  19. * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  20. *
  21. * The full GNU General Public License is included in this distribution in the
  22. * file called LICENSE.
  23. *
  24. * Contact Information:
  25. * Intel Linux Wireless <ilw@linux.intel.com>
  26. * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27. *
  28. *****************************************************************************/
  29. #include <linux/kernel.h>
  30. #include <linux/module.h>
  31. #include <linux/init.h>
  32. #include <linux/pci.h>
  33. #include <linux/dma-mapping.h>
  34. #include <linux/delay.h>
  35. #include <linux/skbuff.h>
  36. #include <linux/netdevice.h>
  37. #include <linux/wireless.h>
  38. #include <linux/firmware.h>
  39. #include <linux/etherdevice.h>
  40. #include <linux/if_arp.h>
  41. #include <net/ieee80211_radiotap.h>
  42. #include <net/lib80211.h>
  43. #include <net/mac80211.h>
  44. #include <asm/div64.h>
  45. #define DRV_NAME "iwl3945"
  46. #include "iwl-fh.h"
  47. #include "iwl-3945-fh.h"
  48. #include "iwl-commands.h"
  49. #include "iwl-3945.h"
  50. #include "iwl-helpers.h"
  51. #include "iwl-core.h"
  52. #include "iwl-dev.h"
  53. /*
  54. * module name, copyright, version, etc.
  55. */
  56. #define DRV_DESCRIPTION \
  57. "Intel(R) PRO/Wireless 3945ABG/BG Network Connection driver for Linux"
  58. #ifdef CONFIG_IWL3945_DEBUG
  59. #define VD "d"
  60. #else
  61. #define VD
  62. #endif
  63. #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
  64. #define VS "s"
  65. #else
  66. #define VS
  67. #endif
  68. #define IWL39_VERSION "1.2.26k" VD VS
  69. #define DRV_COPYRIGHT "Copyright(c) 2003-2009 Intel Corporation"
  70. #define DRV_AUTHOR "<ilw@linux.intel.com>"
  71. #define DRV_VERSION IWL39_VERSION
  72. MODULE_DESCRIPTION(DRV_DESCRIPTION);
  73. MODULE_VERSION(DRV_VERSION);
  74. MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
  75. MODULE_LICENSE("GPL");
  76. /* module parameters */
  77. struct iwl_mod_params iwl3945_mod_params = {
  78. .num_of_queues = IWL39_MAX_NUM_QUEUES,
  79. .sw_crypto = 1,
  80. /* the rest are 0 by default */
  81. };
  82. /*************** DMA-QUEUE-GENERAL-FUNCTIONS *****
  83. * DMA services
  84. *
  85. * Theory of operation
  86. *
  87. * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer
  88. * of buffer descriptors, each of which points to one or more data buffers for
  89. * the device to read from or fill. Driver and device exchange status of each
  90. * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty
  91. * entries in each circular buffer, to protect against confusing empty and full
  92. * queue states.
  93. *
  94. * The device reads or writes the data in the queues via the device's several
  95. * DMA/FIFO channels. Each queue is mapped to a single DMA channel.
  96. *
  97. * For Tx queue, there are low mark and high mark limits. If, after queuing
  98. * the packet for Tx, free space become < low mark, Tx queue stopped. When
  99. * reclaiming packets (on 'tx done IRQ), if free space become > high mark,
  100. * Tx queue resumed.
  101. *
  102. * The 3945 operates with six queues: One receive queue, one transmit queue
  103. * (#4) for sending commands to the device firmware, and four transmit queues
  104. * (#0-3) for data tx via EDCA. An additional 2 HCCA queues are unused.
  105. ***************************************************/
  106. /**
  107. * iwl3945_queue_init - Initialize queue's high/low-water and read/write indexes
  108. */
  109. static int iwl3945_queue_init(struct iwl_priv *priv, struct iwl_queue *q,
  110. int count, int slots_num, u32 id)
  111. {
  112. q->n_bd = count;
  113. q->n_window = slots_num;
  114. q->id = id;
  115. /* count must be power-of-two size, otherwise iwl_queue_inc_wrap
  116. * and iwl_queue_dec_wrap are broken. */
  117. BUG_ON(!is_power_of_2(count));
  118. /* slots_num must be power-of-two size, otherwise
  119. * get_cmd_index is broken. */
  120. BUG_ON(!is_power_of_2(slots_num));
  121. q->low_mark = q->n_window / 4;
  122. if (q->low_mark < 4)
  123. q->low_mark = 4;
  124. q->high_mark = q->n_window / 8;
  125. if (q->high_mark < 2)
  126. q->high_mark = 2;
  127. q->write_ptr = q->read_ptr = 0;
  128. return 0;
  129. }
  130. /**
  131. * iwl3945_tx_queue_alloc - Alloc driver data and TFD CB for one Tx/cmd queue
  132. */
  133. static int iwl3945_tx_queue_alloc(struct iwl_priv *priv,
  134. struct iwl_tx_queue *txq, u32 id)
  135. {
  136. struct pci_dev *dev = priv->pci_dev;
  137. /* Driver private data, only for Tx (not command) queues,
  138. * not shared with device. */
  139. if (id != IWL_CMD_QUEUE_NUM) {
  140. txq->txb = kmalloc(sizeof(txq->txb[0]) *
  141. TFD_QUEUE_SIZE_MAX, GFP_KERNEL);
  142. if (!txq->txb) {
  143. IWL_ERR(priv, "kmalloc for auxiliary BD "
  144. "structures failed\n");
  145. goto error;
  146. }
  147. } else
  148. txq->txb = NULL;
  149. /* Circular buffer of transmit frame descriptors (TFDs),
  150. * shared with device */
  151. txq->tfds39 = pci_alloc_consistent(dev,
  152. sizeof(txq->tfds39[0]) * TFD_QUEUE_SIZE_MAX,
  153. &txq->q.dma_addr);
  154. if (!txq->tfds39) {
  155. IWL_ERR(priv, "pci_alloc_consistent(%zd) failed\n",
  156. sizeof(txq->tfds39[0]) * TFD_QUEUE_SIZE_MAX);
  157. goto error;
  158. }
  159. txq->q.id = id;
  160. return 0;
  161. error:
  162. kfree(txq->txb);
  163. txq->txb = NULL;
  164. return -ENOMEM;
  165. }
  166. /**
  167. * iwl3945_tx_queue_init - Allocate and initialize one tx/cmd queue
  168. */
  169. int iwl3945_tx_queue_init(struct iwl_priv *priv,
  170. struct iwl_tx_queue *txq, int slots_num, u32 txq_id)
  171. {
  172. int len, i;
  173. int rc = 0;
  174. /*
  175. * Alloc buffer array for commands (Tx or other types of commands).
  176. * For the command queue (#4), allocate command space + one big
  177. * command for scan, since scan command is very huge; the system will
  178. * not have two scans at the same time, so only one is needed.
  179. * For data Tx queues (all other queues), no super-size command
  180. * space is needed.
  181. */
  182. len = sizeof(struct iwl_cmd);
  183. for (i = 0; i <= slots_num; i++) {
  184. if (i == slots_num) {
  185. if (txq_id == IWL_CMD_QUEUE_NUM)
  186. len += IWL_MAX_SCAN_SIZE;
  187. else
  188. continue;
  189. }
  190. txq->cmd[i] = kmalloc(len, GFP_KERNEL);
  191. if (!txq->cmd[i])
  192. goto err;
  193. }
  194. /* Alloc driver data array and TFD circular buffer */
  195. rc = iwl3945_tx_queue_alloc(priv, txq, txq_id);
  196. if (rc)
  197. goto err;
  198. txq->need_update = 0;
  199. /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
  200. * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */
  201. BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
  202. /* Initialize queue high/low-water, head/tail indexes */
  203. iwl3945_queue_init(priv, &txq->q, TFD_QUEUE_SIZE_MAX, slots_num, txq_id);
  204. /* Tell device where to find queue, enable DMA channel. */
  205. iwl3945_hw_tx_queue_init(priv, txq);
  206. return 0;
  207. err:
  208. for (i = 0; i < slots_num; i++) {
  209. kfree(txq->cmd[i]);
  210. txq->cmd[i] = NULL;
  211. }
  212. if (txq_id == IWL_CMD_QUEUE_NUM) {
  213. kfree(txq->cmd[slots_num]);
  214. txq->cmd[slots_num] = NULL;
  215. }
  216. return -ENOMEM;
  217. }
  218. /**
  219. * iwl3945_tx_queue_free - Deallocate DMA queue.
  220. * @txq: Transmit queue to deallocate.
  221. *
  222. * Empty queue by removing and destroying all BD's.
  223. * Free all buffers.
  224. * 0-fill, but do not free "txq" descriptor structure.
  225. */
  226. void iwl3945_tx_queue_free(struct iwl_priv *priv, struct iwl_tx_queue *txq)
  227. {
  228. struct iwl_queue *q = &txq->q;
  229. struct pci_dev *dev = priv->pci_dev;
  230. int len, i;
  231. if (q->n_bd == 0)
  232. return;
  233. /* first, empty all BD's */
  234. for (; q->write_ptr != q->read_ptr;
  235. q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd))
  236. priv->cfg->ops->lib->txq_free_tfd(priv, txq);
  237. len = sizeof(struct iwl_cmd) * q->n_window;
  238. if (q->id == IWL_CMD_QUEUE_NUM)
  239. len += IWL_MAX_SCAN_SIZE;
  240. /* De-alloc array of command/tx buffers */
  241. for (i = 0; i < TFD_TX_CMD_SLOTS; i++)
  242. kfree(txq->cmd[i]);
  243. /* De-alloc circular buffer of TFDs */
  244. if (txq->q.n_bd)
  245. pci_free_consistent(dev, sizeof(struct iwl3945_tfd) *
  246. txq->q.n_bd, txq->tfds39, txq->q.dma_addr);
  247. /* De-alloc array of per-TFD driver data */
  248. kfree(txq->txb);
  249. txq->txb = NULL;
  250. /* 0-fill queue descriptor structure */
  251. memset(txq, 0, sizeof(*txq));
  252. }
  253. /*************** STATION TABLE MANAGEMENT ****
  254. * mac80211 should be examined to determine if sta_info is duplicating
  255. * the functionality provided here
  256. */
  257. /**************************************************************/
  258. #if 0 /* temporary disable till we add real remove station */
  259. /**
  260. * iwl3945_remove_station - Remove driver's knowledge of station.
  261. *
  262. * NOTE: This does not remove station from device's station table.
  263. */
  264. static u8 iwl3945_remove_station(struct iwl_priv *priv, const u8 *addr, int is_ap)
  265. {
  266. int index = IWL_INVALID_STATION;
  267. int i;
  268. unsigned long flags;
  269. spin_lock_irqsave(&priv->sta_lock, flags);
  270. if (is_ap)
  271. index = IWL_AP_ID;
  272. else if (is_broadcast_ether_addr(addr))
  273. index = priv->hw_params.bcast_sta_id;
  274. else
  275. for (i = IWL_STA_ID; i < priv->hw_params.max_stations; i++)
  276. if (priv->stations_39[i].used &&
  277. !compare_ether_addr(priv->stations_39[i].sta.sta.addr,
  278. addr)) {
  279. index = i;
  280. break;
  281. }
  282. if (unlikely(index == IWL_INVALID_STATION))
  283. goto out;
  284. if (priv->stations_39[index].used) {
  285. priv->stations_39[index].used = 0;
  286. priv->num_stations--;
  287. }
  288. BUG_ON(priv->num_stations < 0);
  289. out:
  290. spin_unlock_irqrestore(&priv->sta_lock, flags);
  291. return 0;
  292. }
  293. #endif
  294. /**
  295. * iwl3945_clear_stations_table - Clear the driver's station table
  296. *
  297. * NOTE: This does not clear or otherwise alter the device's station table.
  298. */
  299. static void iwl3945_clear_stations_table(struct iwl_priv *priv)
  300. {
  301. unsigned long flags;
  302. spin_lock_irqsave(&priv->sta_lock, flags);
  303. priv->num_stations = 0;
  304. memset(priv->stations_39, 0, sizeof(priv->stations_39));
  305. spin_unlock_irqrestore(&priv->sta_lock, flags);
  306. }
  307. /**
  308. * iwl3945_add_station - Add station to station tables in driver and device
  309. */
  310. u8 iwl3945_add_station(struct iwl_priv *priv, const u8 *addr, int is_ap, u8 flags)
  311. {
  312. int i;
  313. int index = IWL_INVALID_STATION;
  314. struct iwl3945_station_entry *station;
  315. unsigned long flags_spin;
  316. u8 rate;
  317. spin_lock_irqsave(&priv->sta_lock, flags_spin);
  318. if (is_ap)
  319. index = IWL_AP_ID;
  320. else if (is_broadcast_ether_addr(addr))
  321. index = priv->hw_params.bcast_sta_id;
  322. else
  323. for (i = IWL_STA_ID; i < priv->hw_params.max_stations; i++) {
  324. if (!compare_ether_addr(priv->stations_39[i].sta.sta.addr,
  325. addr)) {
  326. index = i;
  327. break;
  328. }
  329. if (!priv->stations_39[i].used &&
  330. index == IWL_INVALID_STATION)
  331. index = i;
  332. }
  333. /* These two conditions has the same outcome but keep them separate
  334. since they have different meaning */
  335. if (unlikely(index == IWL_INVALID_STATION)) {
  336. spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
  337. return index;
  338. }
  339. if (priv->stations_39[index].used &&
  340. !compare_ether_addr(priv->stations_39[index].sta.sta.addr, addr)) {
  341. spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
  342. return index;
  343. }
  344. IWL_DEBUG_ASSOC("Add STA ID %d: %pM\n", index, addr);
  345. station = &priv->stations_39[index];
  346. station->used = 1;
  347. priv->num_stations++;
  348. /* Set up the REPLY_ADD_STA command to send to device */
  349. memset(&station->sta, 0, sizeof(struct iwl3945_addsta_cmd));
  350. memcpy(station->sta.sta.addr, addr, ETH_ALEN);
  351. station->sta.mode = 0;
  352. station->sta.sta.sta_id = index;
  353. station->sta.station_flags = 0;
  354. if (priv->band == IEEE80211_BAND_5GHZ)
  355. rate = IWL_RATE_6M_PLCP;
  356. else
  357. rate = IWL_RATE_1M_PLCP;
  358. /* Turn on both antennas for the station... */
  359. station->sta.rate_n_flags =
  360. iwl3945_hw_set_rate_n_flags(rate, RATE_MCS_ANT_AB_MSK);
  361. spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
  362. /* Add station to device's station table */
  363. iwl3945_send_add_station(priv, &station->sta, flags);
  364. return index;
  365. }
  366. int iwl3945_send_statistics_request(struct iwl_priv *priv)
  367. {
  368. u32 val = 0;
  369. struct iwl_host_cmd cmd = {
  370. .id = REPLY_STATISTICS_CMD,
  371. .len = sizeof(val),
  372. .data = &val,
  373. };
  374. return iwl_send_cmd_sync(priv, &cmd);
  375. }
  376. /**
  377. * iwl3945_set_rxon_channel - Set the phymode and channel values in staging RXON
  378. * @band: 2.4 or 5 GHz band
  379. * @channel: Any channel valid for the requested band
  380. * In addition to setting the staging RXON, priv->band is also set.
  381. *
  382. * NOTE: Does not commit to the hardware; it sets appropriate bit fields
  383. * in the staging RXON flag structure based on the band
  384. */
  385. static int iwl3945_set_rxon_channel(struct iwl_priv *priv,
  386. enum ieee80211_band band,
  387. u16 channel)
  388. {
  389. if (!iwl3945_get_channel_info(priv, band, channel)) {
  390. IWL_DEBUG_INFO("Could not set channel to %d [%d]\n",
  391. channel, band);
  392. return -EINVAL;
  393. }
  394. if ((le16_to_cpu(priv->staging39_rxon.channel) == channel) &&
  395. (priv->band == band))
  396. return 0;
  397. priv->staging39_rxon.channel = cpu_to_le16(channel);
  398. if (band == IEEE80211_BAND_5GHZ)
  399. priv->staging39_rxon.flags &= ~RXON_FLG_BAND_24G_MSK;
  400. else
  401. priv->staging39_rxon.flags |= RXON_FLG_BAND_24G_MSK;
  402. priv->band = band;
  403. IWL_DEBUG_INFO("Staging channel set to %d [%d]\n", channel, band);
  404. return 0;
  405. }
  406. /**
  407. * iwl3945_check_rxon_cmd - validate RXON structure is valid
  408. *
  409. * NOTE: This is really only useful during development and can eventually
  410. * be #ifdef'd out once the driver is stable and folks aren't actively
  411. * making changes
  412. */
  413. static int iwl3945_check_rxon_cmd(struct iwl_priv *priv)
  414. {
  415. int error = 0;
  416. int counter = 1;
  417. struct iwl3945_rxon_cmd *rxon = &priv->staging39_rxon;
  418. if (rxon->flags & RXON_FLG_BAND_24G_MSK) {
  419. error |= le32_to_cpu(rxon->flags &
  420. (RXON_FLG_TGJ_NARROW_BAND_MSK |
  421. RXON_FLG_RADAR_DETECT_MSK));
  422. if (error)
  423. IWL_WARN(priv, "check 24G fields %d | %d\n",
  424. counter++, error);
  425. } else {
  426. error |= (rxon->flags & RXON_FLG_SHORT_SLOT_MSK) ?
  427. 0 : le32_to_cpu(RXON_FLG_SHORT_SLOT_MSK);
  428. if (error)
  429. IWL_WARN(priv, "check 52 fields %d | %d\n",
  430. counter++, error);
  431. error |= le32_to_cpu(rxon->flags & RXON_FLG_CCK_MSK);
  432. if (error)
  433. IWL_WARN(priv, "check 52 CCK %d | %d\n",
  434. counter++, error);
  435. }
  436. error |= (rxon->node_addr[0] | rxon->bssid_addr[0]) & 0x1;
  437. if (error)
  438. IWL_WARN(priv, "check mac addr %d | %d\n", counter++, error);
  439. /* make sure basic rates 6Mbps and 1Mbps are supported */
  440. error |= (((rxon->ofdm_basic_rates & IWL_RATE_6M_MASK) == 0) &&
  441. ((rxon->cck_basic_rates & IWL_RATE_1M_MASK) == 0));
  442. if (error)
  443. IWL_WARN(priv, "check basic rate %d | %d\n", counter++, error);
  444. error |= (le16_to_cpu(rxon->assoc_id) > 2007);
  445. if (error)
  446. IWL_WARN(priv, "check assoc id %d | %d\n", counter++, error);
  447. error |= ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK))
  448. == (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK));
  449. if (error)
  450. IWL_WARN(priv, "check CCK and short slot %d | %d\n",
  451. counter++, error);
  452. error |= ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK))
  453. == (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK));
  454. if (error)
  455. IWL_WARN(priv, "check CCK & auto detect %d | %d\n",
  456. counter++, error);
  457. error |= ((rxon->flags & (RXON_FLG_AUTO_DETECT_MSK |
  458. RXON_FLG_TGG_PROTECT_MSK)) == RXON_FLG_TGG_PROTECT_MSK);
  459. if (error)
  460. IWL_WARN(priv, "check TGG and auto detect %d | %d\n",
  461. counter++, error);
  462. if ((rxon->flags & RXON_FLG_DIS_DIV_MSK))
  463. error |= ((rxon->flags & (RXON_FLG_ANT_B_MSK |
  464. RXON_FLG_ANT_A_MSK)) == 0);
  465. if (error)
  466. IWL_WARN(priv, "check antenna %d %d\n", counter++, error);
  467. if (error)
  468. IWL_WARN(priv, "Tuning to channel %d\n",
  469. le16_to_cpu(rxon->channel));
  470. if (error) {
  471. IWL_ERR(priv, "Not a valid rxon_assoc_cmd field values\n");
  472. return -1;
  473. }
  474. return 0;
  475. }
  476. /**
  477. * iwl3945_full_rxon_required - check if full RXON (vs RXON_ASSOC) cmd is needed
  478. * @priv: staging_rxon is compared to active_rxon
  479. *
  480. * If the RXON structure is changing enough to require a new tune,
  481. * or is clearing the RXON_FILTER_ASSOC_MSK, then return 1 to indicate that
  482. * a new tune (full RXON command, rather than RXON_ASSOC cmd) is required.
  483. */
  484. static int iwl3945_full_rxon_required(struct iwl_priv *priv)
  485. {
  486. /* These items are only settable from the full RXON command */
  487. if (!(iwl3945_is_associated(priv)) ||
  488. compare_ether_addr(priv->staging39_rxon.bssid_addr,
  489. priv->active39_rxon.bssid_addr) ||
  490. compare_ether_addr(priv->staging39_rxon.node_addr,
  491. priv->active39_rxon.node_addr) ||
  492. compare_ether_addr(priv->staging39_rxon.wlap_bssid_addr,
  493. priv->active39_rxon.wlap_bssid_addr) ||
  494. (priv->staging39_rxon.dev_type != priv->active39_rxon.dev_type) ||
  495. (priv->staging39_rxon.channel != priv->active39_rxon.channel) ||
  496. (priv->staging39_rxon.air_propagation !=
  497. priv->active39_rxon.air_propagation) ||
  498. (priv->staging39_rxon.assoc_id != priv->active39_rxon.assoc_id))
  499. return 1;
  500. /* flags, filter_flags, ofdm_basic_rates, and cck_basic_rates can
  501. * be updated with the RXON_ASSOC command -- however only some
  502. * flag transitions are allowed using RXON_ASSOC */
  503. /* Check if we are not switching bands */
  504. if ((priv->staging39_rxon.flags & RXON_FLG_BAND_24G_MSK) !=
  505. (priv->active39_rxon.flags & RXON_FLG_BAND_24G_MSK))
  506. return 1;
  507. /* Check if we are switching association toggle */
  508. if ((priv->staging39_rxon.filter_flags & RXON_FILTER_ASSOC_MSK) !=
  509. (priv->active39_rxon.filter_flags & RXON_FILTER_ASSOC_MSK))
  510. return 1;
  511. return 0;
  512. }
  513. static int iwl3945_send_rxon_assoc(struct iwl_priv *priv)
  514. {
  515. int rc = 0;
  516. struct iwl_rx_packet *res = NULL;
  517. struct iwl3945_rxon_assoc_cmd rxon_assoc;
  518. struct iwl_host_cmd cmd = {
  519. .id = REPLY_RXON_ASSOC,
  520. .len = sizeof(rxon_assoc),
  521. .meta.flags = CMD_WANT_SKB,
  522. .data = &rxon_assoc,
  523. };
  524. const struct iwl3945_rxon_cmd *rxon1 = &priv->staging39_rxon;
  525. const struct iwl3945_rxon_cmd *rxon2 = &priv->active39_rxon;
  526. if ((rxon1->flags == rxon2->flags) &&
  527. (rxon1->filter_flags == rxon2->filter_flags) &&
  528. (rxon1->cck_basic_rates == rxon2->cck_basic_rates) &&
  529. (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) {
  530. IWL_DEBUG_INFO("Using current RXON_ASSOC. Not resending.\n");
  531. return 0;
  532. }
  533. rxon_assoc.flags = priv->staging39_rxon.flags;
  534. rxon_assoc.filter_flags = priv->staging39_rxon.filter_flags;
  535. rxon_assoc.ofdm_basic_rates = priv->staging39_rxon.ofdm_basic_rates;
  536. rxon_assoc.cck_basic_rates = priv->staging39_rxon.cck_basic_rates;
  537. rxon_assoc.reserved = 0;
  538. rc = iwl_send_cmd_sync(priv, &cmd);
  539. if (rc)
  540. return rc;
  541. res = (struct iwl_rx_packet *)cmd.meta.u.skb->data;
  542. if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
  543. IWL_ERR(priv, "Bad return from REPLY_RXON_ASSOC command\n");
  544. rc = -EIO;
  545. }
  546. priv->alloc_rxb_skb--;
  547. dev_kfree_skb_any(cmd.meta.u.skb);
  548. return rc;
  549. }
  550. /**
  551. * iwl3945_commit_rxon - commit staging_rxon to hardware
  552. *
  553. * The RXON command in staging_rxon is committed to the hardware and
  554. * the active_rxon structure is updated with the new data. This
  555. * function correctly transitions out of the RXON_ASSOC_MSK state if
  556. * a HW tune is required based on the RXON structure changes.
  557. */
  558. static int iwl3945_commit_rxon(struct iwl_priv *priv)
  559. {
  560. /* cast away the const for active_rxon in this function */
  561. struct iwl3945_rxon_cmd *active_rxon = (void *)&priv->active39_rxon;
  562. int rc = 0;
  563. if (!iwl_is_alive(priv))
  564. return -1;
  565. /* always get timestamp with Rx frame */
  566. priv->staging39_rxon.flags |= RXON_FLG_TSF2HOST_MSK;
  567. /* select antenna */
  568. priv->staging39_rxon.flags &=
  569. ~(RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_SEL_MSK);
  570. priv->staging39_rxon.flags |= iwl3945_get_antenna_flags(priv);
  571. rc = iwl3945_check_rxon_cmd(priv);
  572. if (rc) {
  573. IWL_ERR(priv, "Invalid RXON configuration. Not committing.\n");
  574. return -EINVAL;
  575. }
  576. /* If we don't need to send a full RXON, we can use
  577. * iwl3945_rxon_assoc_cmd which is used to reconfigure filter
  578. * and other flags for the current radio configuration. */
  579. if (!iwl3945_full_rxon_required(priv)) {
  580. rc = iwl3945_send_rxon_assoc(priv);
  581. if (rc) {
  582. IWL_ERR(priv, "Error setting RXON_ASSOC "
  583. "configuration (%d).\n", rc);
  584. return rc;
  585. }
  586. memcpy(active_rxon, &priv->staging39_rxon, sizeof(*active_rxon));
  587. return 0;
  588. }
  589. /* If we are currently associated and the new config requires
  590. * an RXON_ASSOC and the new config wants the associated mask enabled,
  591. * we must clear the associated from the active configuration
  592. * before we apply the new config */
  593. if (iwl3945_is_associated(priv) &&
  594. (priv->staging39_rxon.filter_flags & RXON_FILTER_ASSOC_MSK)) {
  595. IWL_DEBUG_INFO("Toggling associated bit on current RXON\n");
  596. active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  597. rc = iwl_send_cmd_pdu(priv, REPLY_RXON,
  598. sizeof(struct iwl3945_rxon_cmd),
  599. &priv->active39_rxon);
  600. /* If the mask clearing failed then we set
  601. * active_rxon back to what it was previously */
  602. if (rc) {
  603. active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
  604. IWL_ERR(priv, "Error clearing ASSOC_MSK on current "
  605. "configuration (%d).\n", rc);
  606. return rc;
  607. }
  608. }
  609. IWL_DEBUG_INFO("Sending RXON\n"
  610. "* with%s RXON_FILTER_ASSOC_MSK\n"
  611. "* channel = %d\n"
  612. "* bssid = %pM\n",
  613. ((priv->staging39_rxon.filter_flags &
  614. RXON_FILTER_ASSOC_MSK) ? "" : "out"),
  615. le16_to_cpu(priv->staging39_rxon.channel),
  616. priv->staging_rxon.bssid_addr);
  617. /* Apply the new configuration */
  618. rc = iwl_send_cmd_pdu(priv, REPLY_RXON,
  619. sizeof(struct iwl3945_rxon_cmd), &priv->staging39_rxon);
  620. if (rc) {
  621. IWL_ERR(priv, "Error setting new configuration (%d).\n", rc);
  622. return rc;
  623. }
  624. memcpy(active_rxon, &priv->staging39_rxon, sizeof(*active_rxon));
  625. iwl3945_clear_stations_table(priv);
  626. /* If we issue a new RXON command which required a tune then we must
  627. * send a new TXPOWER command or we won't be able to Tx any frames */
  628. rc = priv->cfg->ops->lib->send_tx_power(priv);
  629. if (rc) {
  630. IWL_ERR(priv, "Error setting Tx power (%d).\n", rc);
  631. return rc;
  632. }
  633. /* Add the broadcast address so we can send broadcast frames */
  634. if (iwl3945_add_station(priv, iwl_bcast_addr, 0, 0) ==
  635. IWL_INVALID_STATION) {
  636. IWL_ERR(priv, "Error adding BROADCAST address for transmit.\n");
  637. return -EIO;
  638. }
  639. /* If we have set the ASSOC_MSK and we are in BSS mode then
  640. * add the IWL_AP_ID to the station rate table */
  641. if (iwl3945_is_associated(priv) &&
  642. (priv->iw_mode == NL80211_IFTYPE_STATION))
  643. if (iwl3945_add_station(priv, priv->active39_rxon.bssid_addr, 1, 0)
  644. == IWL_INVALID_STATION) {
  645. IWL_ERR(priv, "Error adding AP address for transmit\n");
  646. return -EIO;
  647. }
  648. /* Init the hardware's rate fallback order based on the band */
  649. rc = iwl3945_init_hw_rate_table(priv);
  650. if (rc) {
  651. IWL_ERR(priv, "Error setting HW rate table: %02X\n", rc);
  652. return -EIO;
  653. }
  654. return 0;
  655. }
  656. static int iwl3945_send_bt_config(struct iwl_priv *priv)
  657. {
  658. struct iwl_bt_cmd bt_cmd = {
  659. .flags = 3,
  660. .lead_time = 0xAA,
  661. .max_kill = 1,
  662. .kill_ack_mask = 0,
  663. .kill_cts_mask = 0,
  664. };
  665. return iwl_send_cmd_pdu(priv, REPLY_BT_CONFIG,
  666. sizeof(bt_cmd), &bt_cmd);
  667. }
  668. static int iwl3945_add_sta_sync_callback(struct iwl_priv *priv,
  669. struct iwl_cmd *cmd, struct sk_buff *skb)
  670. {
  671. struct iwl_rx_packet *res = NULL;
  672. if (!skb) {
  673. IWL_ERR(priv, "Error: Response NULL in REPLY_ADD_STA.\n");
  674. return 1;
  675. }
  676. res = (struct iwl_rx_packet *)skb->data;
  677. if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
  678. IWL_ERR(priv, "Bad return from REPLY_ADD_STA (0x%08X)\n",
  679. res->hdr.flags);
  680. return 1;
  681. }
  682. switch (res->u.add_sta.status) {
  683. case ADD_STA_SUCCESS_MSK:
  684. break;
  685. default:
  686. break;
  687. }
  688. /* We didn't cache the SKB; let the caller free it */
  689. return 1;
  690. }
  691. int iwl3945_send_add_station(struct iwl_priv *priv,
  692. struct iwl3945_addsta_cmd *sta, u8 flags)
  693. {
  694. struct iwl_rx_packet *res = NULL;
  695. int rc = 0;
  696. struct iwl_host_cmd cmd = {
  697. .id = REPLY_ADD_STA,
  698. .len = sizeof(struct iwl3945_addsta_cmd),
  699. .meta.flags = flags,
  700. .data = sta,
  701. };
  702. if (flags & CMD_ASYNC)
  703. cmd.meta.u.callback = iwl3945_add_sta_sync_callback;
  704. else
  705. cmd.meta.flags |= CMD_WANT_SKB;
  706. rc = iwl_send_cmd(priv, &cmd);
  707. if (rc || (flags & CMD_ASYNC))
  708. return rc;
  709. res = (struct iwl_rx_packet *)cmd.meta.u.skb->data;
  710. if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
  711. IWL_ERR(priv, "Bad return from REPLY_ADD_STA (0x%08X)\n",
  712. res->hdr.flags);
  713. rc = -EIO;
  714. }
  715. if (rc == 0) {
  716. switch (res->u.add_sta.status) {
  717. case ADD_STA_SUCCESS_MSK:
  718. IWL_DEBUG_INFO("REPLY_ADD_STA PASSED\n");
  719. break;
  720. default:
  721. rc = -EIO;
  722. IWL_WARN(priv, "REPLY_ADD_STA failed\n");
  723. break;
  724. }
  725. }
  726. priv->alloc_rxb_skb--;
  727. dev_kfree_skb_any(cmd.meta.u.skb);
  728. return rc;
  729. }
  730. static int iwl3945_update_sta_key_info(struct iwl_priv *priv,
  731. struct ieee80211_key_conf *keyconf,
  732. u8 sta_id)
  733. {
  734. unsigned long flags;
  735. __le16 key_flags = 0;
  736. switch (keyconf->alg) {
  737. case ALG_CCMP:
  738. key_flags |= STA_KEY_FLG_CCMP;
  739. key_flags |= cpu_to_le16(
  740. keyconf->keyidx << STA_KEY_FLG_KEYID_POS);
  741. key_flags &= ~STA_KEY_FLG_INVALID;
  742. break;
  743. case ALG_TKIP:
  744. case ALG_WEP:
  745. default:
  746. return -EINVAL;
  747. }
  748. spin_lock_irqsave(&priv->sta_lock, flags);
  749. priv->stations_39[sta_id].keyinfo.alg = keyconf->alg;
  750. priv->stations_39[sta_id].keyinfo.keylen = keyconf->keylen;
  751. memcpy(priv->stations_39[sta_id].keyinfo.key, keyconf->key,
  752. keyconf->keylen);
  753. memcpy(priv->stations_39[sta_id].sta.key.key, keyconf->key,
  754. keyconf->keylen);
  755. priv->stations_39[sta_id].sta.key.key_flags = key_flags;
  756. priv->stations_39[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
  757. priv->stations_39[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
  758. spin_unlock_irqrestore(&priv->sta_lock, flags);
  759. IWL_DEBUG_INFO("hwcrypto: modify ucode station key info\n");
  760. iwl3945_send_add_station(priv, &priv->stations_39[sta_id].sta, 0);
  761. return 0;
  762. }
  763. static int iwl3945_clear_sta_key_info(struct iwl_priv *priv, u8 sta_id)
  764. {
  765. unsigned long flags;
  766. spin_lock_irqsave(&priv->sta_lock, flags);
  767. memset(&priv->stations_39[sta_id].keyinfo, 0, sizeof(struct iwl3945_hw_key));
  768. memset(&priv->stations_39[sta_id].sta.key, 0,
  769. sizeof(struct iwl4965_keyinfo));
  770. priv->stations_39[sta_id].sta.key.key_flags = STA_KEY_FLG_NO_ENC;
  771. priv->stations_39[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
  772. priv->stations_39[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
  773. spin_unlock_irqrestore(&priv->sta_lock, flags);
  774. IWL_DEBUG_INFO("hwcrypto: clear ucode station key info\n");
  775. iwl3945_send_add_station(priv, &priv->stations_39[sta_id].sta, 0);
  776. return 0;
  777. }
  778. static void iwl3945_clear_free_frames(struct iwl_priv *priv)
  779. {
  780. struct list_head *element;
  781. IWL_DEBUG_INFO("%d frames on pre-allocated heap on clear.\n",
  782. priv->frames_count);
  783. while (!list_empty(&priv->free_frames)) {
  784. element = priv->free_frames.next;
  785. list_del(element);
  786. kfree(list_entry(element, struct iwl3945_frame, list));
  787. priv->frames_count--;
  788. }
  789. if (priv->frames_count) {
  790. IWL_WARN(priv, "%d frames still in use. Did we lose one?\n",
  791. priv->frames_count);
  792. priv->frames_count = 0;
  793. }
  794. }
  795. static struct iwl3945_frame *iwl3945_get_free_frame(struct iwl_priv *priv)
  796. {
  797. struct iwl3945_frame *frame;
  798. struct list_head *element;
  799. if (list_empty(&priv->free_frames)) {
  800. frame = kzalloc(sizeof(*frame), GFP_KERNEL);
  801. if (!frame) {
  802. IWL_ERR(priv, "Could not allocate frame!\n");
  803. return NULL;
  804. }
  805. priv->frames_count++;
  806. return frame;
  807. }
  808. element = priv->free_frames.next;
  809. list_del(element);
  810. return list_entry(element, struct iwl3945_frame, list);
  811. }
  812. static void iwl3945_free_frame(struct iwl_priv *priv, struct iwl3945_frame *frame)
  813. {
  814. memset(frame, 0, sizeof(*frame));
  815. list_add(&frame->list, &priv->free_frames);
  816. }
  817. unsigned int iwl3945_fill_beacon_frame(struct iwl_priv *priv,
  818. struct ieee80211_hdr *hdr,
  819. int left)
  820. {
  821. if (!iwl3945_is_associated(priv) || !priv->ibss_beacon ||
  822. ((priv->iw_mode != NL80211_IFTYPE_ADHOC) &&
  823. (priv->iw_mode != NL80211_IFTYPE_AP)))
  824. return 0;
  825. if (priv->ibss_beacon->len > left)
  826. return 0;
  827. memcpy(hdr, priv->ibss_beacon->data, priv->ibss_beacon->len);
  828. return priv->ibss_beacon->len;
  829. }
  830. static u8 iwl3945_rate_get_lowest_plcp(struct iwl_priv *priv)
  831. {
  832. u8 i;
  833. int rate_mask;
  834. /* Set rate mask*/
  835. if (priv->staging39_rxon.flags & RXON_FLG_BAND_24G_MSK)
  836. rate_mask = priv->active_rate_basic & IWL_CCK_RATES_MASK;
  837. else
  838. rate_mask = priv->active_rate_basic & IWL_OFDM_RATES_MASK;
  839. for (i = IWL_RATE_1M_INDEX; i != IWL_RATE_INVALID;
  840. i = iwl3945_rates[i].next_ieee) {
  841. if (rate_mask & (1 << i))
  842. return iwl3945_rates[i].plcp;
  843. }
  844. /* No valid rate was found. Assign the lowest one */
  845. if (priv->staging39_rxon.flags & RXON_FLG_BAND_24G_MSK)
  846. return IWL_RATE_1M_PLCP;
  847. else
  848. return IWL_RATE_6M_PLCP;
  849. }
  850. static int iwl3945_send_beacon_cmd(struct iwl_priv *priv)
  851. {
  852. struct iwl3945_frame *frame;
  853. unsigned int frame_size;
  854. int rc;
  855. u8 rate;
  856. frame = iwl3945_get_free_frame(priv);
  857. if (!frame) {
  858. IWL_ERR(priv, "Could not obtain free frame buffer for beacon "
  859. "command.\n");
  860. return -ENOMEM;
  861. }
  862. rate = iwl3945_rate_get_lowest_plcp(priv);
  863. frame_size = iwl3945_hw_get_beacon_cmd(priv, frame, rate);
  864. rc = iwl_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size,
  865. &frame->u.cmd[0]);
  866. iwl3945_free_frame(priv, frame);
  867. return rc;
  868. }
  869. /******************************************************************************
  870. *
  871. * EEPROM related functions
  872. *
  873. ******************************************************************************/
  874. static void get_eeprom_mac(struct iwl_priv *priv, u8 *mac)
  875. {
  876. memcpy(mac, priv->eeprom39.mac_address, 6);
  877. }
  878. /*
  879. * Clear the OWNER_MSK, to establish driver (instead of uCode running on
  880. * embedded controller) as EEPROM reader; each read is a series of pulses
  881. * to/from the EEPROM chip, not a single event, so even reads could conflict
  882. * if they weren't arbitrated by some ownership mechanism. Here, the driver
  883. * simply claims ownership, which should be safe when this function is called
  884. * (i.e. before loading uCode!).
  885. */
  886. static inline int iwl3945_eeprom_acquire_semaphore(struct iwl_priv *priv)
  887. {
  888. _iwl_clear_bit(priv, CSR_EEPROM_GP, CSR_EEPROM_GP_IF_OWNER_MSK);
  889. return 0;
  890. }
  891. /**
  892. * iwl3945_eeprom_init - read EEPROM contents
  893. *
  894. * Load the EEPROM contents from adapter into priv->eeprom39
  895. *
  896. * NOTE: This routine uses the non-debug IO access functions.
  897. */
  898. int iwl3945_eeprom_init(struct iwl_priv *priv)
  899. {
  900. u16 *e = (u16 *)&priv->eeprom39;
  901. u32 gp = iwl_read32(priv, CSR_EEPROM_GP);
  902. int sz = sizeof(priv->eeprom39);
  903. int ret;
  904. u16 addr;
  905. /* The EEPROM structure has several padding buffers within it
  906. * and when adding new EEPROM maps is subject to programmer errors
  907. * which may be very difficult to identify without explicitly
  908. * checking the resulting size of the eeprom map. */
  909. BUILD_BUG_ON(sizeof(priv->eeprom39) != IWL_EEPROM_IMAGE_SIZE);
  910. if ((gp & CSR_EEPROM_GP_VALID_MSK) == CSR_EEPROM_GP_BAD_SIGNATURE) {
  911. IWL_ERR(priv, "EEPROM not found, EEPROM_GP=0x%08x\n", gp);
  912. return -ENOENT;
  913. }
  914. /* Make sure driver (instead of uCode) is allowed to read EEPROM */
  915. ret = iwl3945_eeprom_acquire_semaphore(priv);
  916. if (ret < 0) {
  917. IWL_ERR(priv, "Failed to acquire EEPROM semaphore.\n");
  918. return -ENOENT;
  919. }
  920. /* eeprom is an array of 16bit values */
  921. for (addr = 0; addr < sz; addr += sizeof(u16)) {
  922. u32 r;
  923. _iwl_write32(priv, CSR_EEPROM_REG,
  924. CSR_EEPROM_REG_MSK_ADDR & (addr << 1));
  925. _iwl_clear_bit(priv, CSR_EEPROM_REG, CSR_EEPROM_REG_BIT_CMD);
  926. ret = iwl_poll_direct_bit(priv, CSR_EEPROM_REG,
  927. CSR_EEPROM_REG_READ_VALID_MSK,
  928. IWL_EEPROM_ACCESS_TIMEOUT);
  929. if (ret < 0) {
  930. IWL_ERR(priv, "Time out reading EEPROM[%d]\n", addr);
  931. return ret;
  932. }
  933. r = _iwl_read_direct32(priv, CSR_EEPROM_REG);
  934. e[addr / 2] = le16_to_cpu((__force __le16)(r >> 16));
  935. }
  936. return 0;
  937. }
  938. static void iwl3945_unset_hw_params(struct iwl_priv *priv)
  939. {
  940. if (priv->shared_virt)
  941. pci_free_consistent(priv->pci_dev,
  942. sizeof(struct iwl3945_shared),
  943. priv->shared_virt,
  944. priv->shared_phys);
  945. }
  946. /*
  947. * QoS support
  948. */
  949. static int iwl3945_send_qos_params_command(struct iwl_priv *priv,
  950. struct iwl_qosparam_cmd *qos)
  951. {
  952. return iwl_send_cmd_pdu(priv, REPLY_QOS_PARAM,
  953. sizeof(struct iwl_qosparam_cmd), qos);
  954. }
  955. static void iwl3945_activate_qos(struct iwl_priv *priv, u8 force)
  956. {
  957. unsigned long flags;
  958. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  959. return;
  960. spin_lock_irqsave(&priv->lock, flags);
  961. priv->qos_data.def_qos_parm.qos_flags = 0;
  962. if (priv->qos_data.qos_cap.q_AP.queue_request &&
  963. !priv->qos_data.qos_cap.q_AP.txop_request)
  964. priv->qos_data.def_qos_parm.qos_flags |=
  965. QOS_PARAM_FLG_TXOP_TYPE_MSK;
  966. if (priv->qos_data.qos_active)
  967. priv->qos_data.def_qos_parm.qos_flags |=
  968. QOS_PARAM_FLG_UPDATE_EDCA_MSK;
  969. spin_unlock_irqrestore(&priv->lock, flags);
  970. if (force || iwl3945_is_associated(priv)) {
  971. IWL_DEBUG_QOS("send QoS cmd with QoS active %d \n",
  972. priv->qos_data.qos_active);
  973. iwl3945_send_qos_params_command(priv,
  974. &(priv->qos_data.def_qos_parm));
  975. }
  976. }
  977. /*
  978. * Power management (not Tx power!) functions
  979. */
  980. #define MSEC_TO_USEC 1024
  981. /* default power management (not Tx power) table values */
  982. /* for TIM 0-10 */
  983. static struct iwl_power_vec_entry range_0[IWL_POWER_MAX] = {
  984. {{NOSLP, SLP_TOUT(0), SLP_TOUT(0), SLP_VEC(0, 0, 0, 0, 0)}, 0},
  985. {{SLP, SLP_TOUT(200), SLP_TOUT(500), SLP_VEC(1, 2, 3, 4, 4)}, 0},
  986. {{SLP, SLP_TOUT(200), SLP_TOUT(300), SLP_VEC(2, 4, 6, 7, 7)}, 0},
  987. {{SLP, SLP_TOUT(50), SLP_TOUT(100), SLP_VEC(2, 6, 9, 9, 10)}, 0},
  988. {{SLP, SLP_TOUT(50), SLP_TOUT(25), SLP_VEC(2, 7, 9, 9, 10)}, 1},
  989. {{SLP, SLP_TOUT(25), SLP_TOUT(25), SLP_VEC(4, 7, 10, 10, 10)}, 1}
  990. };
  991. /* for TIM > 10 */
  992. static struct iwl_power_vec_entry range_1[IWL_POWER_MAX] = {
  993. {{NOSLP, SLP_TOUT(0), SLP_TOUT(0), SLP_VEC(0, 0, 0, 0, 0)}, 0},
  994. {{SLP, SLP_TOUT(200), SLP_TOUT(500), SLP_VEC(1, 2, 3, 4, 0xFF)}, 0},
  995. {{SLP, SLP_TOUT(200), SLP_TOUT(300), SLP_VEC(2, 4, 6, 7, 0xFF)}, 0},
  996. {{SLP, SLP_TOUT(50), SLP_TOUT(100), SLP_VEC(2, 6, 9, 9, 0xFF)}, 0},
  997. {{SLP, SLP_TOUT(50), SLP_TOUT(25), SLP_VEC(2, 7, 9, 9, 0xFF)}, 0},
  998. {{SLP, SLP_TOUT(25), SLP_TOUT(25), SLP_VEC(4, 7, 10, 10, 0xFF)}, 0}
  999. };
  1000. int iwl3945_power_init_handle(struct iwl_priv *priv)
  1001. {
  1002. int rc = 0, i;
  1003. struct iwl_power_mgr *pow_data;
  1004. int size = sizeof(struct iwl_power_vec_entry) * IWL_POWER_MAX;
  1005. u16 pci_pm;
  1006. IWL_DEBUG_POWER("Initialize power \n");
  1007. pow_data = &priv->power_data;
  1008. memset(pow_data, 0, sizeof(*pow_data));
  1009. pow_data->dtim_period = 1;
  1010. memcpy(&pow_data->pwr_range_0[0], &range_0[0], size);
  1011. memcpy(&pow_data->pwr_range_1[0], &range_1[0], size);
  1012. rc = pci_read_config_word(priv->pci_dev, PCI_LINK_CTRL, &pci_pm);
  1013. if (rc != 0)
  1014. return 0;
  1015. else {
  1016. struct iwl_powertable_cmd *cmd;
  1017. IWL_DEBUG_POWER("adjust power command flags\n");
  1018. for (i = 0; i < IWL_POWER_MAX; i++) {
  1019. cmd = &pow_data->pwr_range_0[i].cmd;
  1020. if (pci_pm & 0x1)
  1021. cmd->flags &= ~IWL_POWER_PCI_PM_MSK;
  1022. else
  1023. cmd->flags |= IWL_POWER_PCI_PM_MSK;
  1024. }
  1025. }
  1026. return rc;
  1027. }
  1028. static int iwl3945_update_power_cmd(struct iwl_priv *priv,
  1029. struct iwl_powertable_cmd *cmd, u32 mode)
  1030. {
  1031. struct iwl_power_mgr *pow_data;
  1032. struct iwl_power_vec_entry *range;
  1033. u32 max_sleep = 0;
  1034. int i;
  1035. u8 period = 0;
  1036. bool skip;
  1037. if (mode > IWL_POWER_INDEX_5) {
  1038. IWL_DEBUG_POWER("Error invalid power mode \n");
  1039. return -EINVAL;
  1040. }
  1041. pow_data = &priv->power_data;
  1042. if (pow_data->dtim_period < 10)
  1043. range = &pow_data->pwr_range_0[0];
  1044. else
  1045. range = &pow_data->pwr_range_1[1];
  1046. memcpy(cmd, &range[mode].cmd, sizeof(struct iwl3945_powertable_cmd));
  1047. if (period == 0) {
  1048. period = 1;
  1049. skip = false;
  1050. } else {
  1051. skip = !!range[mode].no_dtim;
  1052. }
  1053. if (skip) {
  1054. __le32 slp_itrvl = cmd->sleep_interval[IWL_POWER_VEC_SIZE - 1];
  1055. max_sleep = (le32_to_cpu(slp_itrvl) / period) * period;
  1056. cmd->flags |= IWL_POWER_SLEEP_OVER_DTIM_MSK;
  1057. } else {
  1058. max_sleep = period;
  1059. cmd->flags &= ~IWL_POWER_SLEEP_OVER_DTIM_MSK;
  1060. }
  1061. for (i = 0; i < IWL_POWER_VEC_SIZE; i++)
  1062. if (le32_to_cpu(cmd->sleep_interval[i]) > max_sleep)
  1063. cmd->sleep_interval[i] = cpu_to_le32(max_sleep);
  1064. IWL_DEBUG_POWER("Flags value = 0x%08X\n", cmd->flags);
  1065. IWL_DEBUG_POWER("Tx timeout = %u\n", le32_to_cpu(cmd->tx_data_timeout));
  1066. IWL_DEBUG_POWER("Rx timeout = %u\n", le32_to_cpu(cmd->rx_data_timeout));
  1067. IWL_DEBUG_POWER("Sleep interval vector = { %d , %d , %d , %d , %d }\n",
  1068. le32_to_cpu(cmd->sleep_interval[0]),
  1069. le32_to_cpu(cmd->sleep_interval[1]),
  1070. le32_to_cpu(cmd->sleep_interval[2]),
  1071. le32_to_cpu(cmd->sleep_interval[3]),
  1072. le32_to_cpu(cmd->sleep_interval[4]));
  1073. return 0;
  1074. }
  1075. static int iwl3945_send_power_mode(struct iwl_priv *priv, u32 mode)
  1076. {
  1077. u32 uninitialized_var(final_mode);
  1078. int rc;
  1079. struct iwl_powertable_cmd cmd;
  1080. /* If on battery, set to 3,
  1081. * if plugged into AC power, set to CAM ("continuously aware mode"),
  1082. * else user level */
  1083. switch (mode) {
  1084. case IWL39_POWER_BATTERY:
  1085. final_mode = IWL_POWER_INDEX_3;
  1086. break;
  1087. case IWL39_POWER_AC:
  1088. final_mode = IWL_POWER_MODE_CAM;
  1089. break;
  1090. default:
  1091. final_mode = mode;
  1092. break;
  1093. }
  1094. iwl3945_update_power_cmd(priv, &cmd, final_mode);
  1095. /* FIXME use get_hcmd_size 3945 command is 4 bytes shorter */
  1096. rc = iwl_send_cmd_pdu(priv, POWER_TABLE_CMD,
  1097. sizeof(struct iwl3945_powertable_cmd), &cmd);
  1098. if (final_mode == IWL_POWER_MODE_CAM)
  1099. clear_bit(STATUS_POWER_PMI, &priv->status);
  1100. else
  1101. set_bit(STATUS_POWER_PMI, &priv->status);
  1102. return rc;
  1103. }
  1104. #define MAX_UCODE_BEACON_INTERVAL 1024
  1105. #define INTEL_CONN_LISTEN_INTERVAL __constant_cpu_to_le16(0xA)
  1106. static __le16 iwl3945_adjust_beacon_interval(u16 beacon_val)
  1107. {
  1108. u16 new_val = 0;
  1109. u16 beacon_factor = 0;
  1110. beacon_factor =
  1111. (beacon_val + MAX_UCODE_BEACON_INTERVAL)
  1112. / MAX_UCODE_BEACON_INTERVAL;
  1113. new_val = beacon_val / beacon_factor;
  1114. return cpu_to_le16(new_val);
  1115. }
  1116. static void iwl3945_setup_rxon_timing(struct iwl_priv *priv)
  1117. {
  1118. u64 interval_tm_unit;
  1119. u64 tsf, result;
  1120. unsigned long flags;
  1121. struct ieee80211_conf *conf = NULL;
  1122. u16 beacon_int = 0;
  1123. conf = ieee80211_get_hw_conf(priv->hw);
  1124. spin_lock_irqsave(&priv->lock, flags);
  1125. priv->rxon_timing.timestamp = cpu_to_le64(priv->timestamp);
  1126. priv->rxon_timing.listen_interval = INTEL_CONN_LISTEN_INTERVAL;
  1127. tsf = priv->timestamp;
  1128. beacon_int = priv->beacon_int;
  1129. spin_unlock_irqrestore(&priv->lock, flags);
  1130. if (priv->iw_mode == NL80211_IFTYPE_STATION) {
  1131. if (beacon_int == 0) {
  1132. priv->rxon_timing.beacon_interval = cpu_to_le16(100);
  1133. priv->rxon_timing.beacon_init_val = cpu_to_le32(102400);
  1134. } else {
  1135. priv->rxon_timing.beacon_interval =
  1136. cpu_to_le16(beacon_int);
  1137. priv->rxon_timing.beacon_interval =
  1138. iwl3945_adjust_beacon_interval(
  1139. le16_to_cpu(priv->rxon_timing.beacon_interval));
  1140. }
  1141. priv->rxon_timing.atim_window = 0;
  1142. } else {
  1143. priv->rxon_timing.beacon_interval =
  1144. iwl3945_adjust_beacon_interval(conf->beacon_int);
  1145. /* TODO: we need to get atim_window from upper stack
  1146. * for now we set to 0 */
  1147. priv->rxon_timing.atim_window = 0;
  1148. }
  1149. interval_tm_unit =
  1150. (le16_to_cpu(priv->rxon_timing.beacon_interval) * 1024);
  1151. result = do_div(tsf, interval_tm_unit);
  1152. priv->rxon_timing.beacon_init_val =
  1153. cpu_to_le32((u32) ((u64) interval_tm_unit - result));
  1154. IWL_DEBUG_ASSOC
  1155. ("beacon interval %d beacon timer %d beacon tim %d\n",
  1156. le16_to_cpu(priv->rxon_timing.beacon_interval),
  1157. le32_to_cpu(priv->rxon_timing.beacon_init_val),
  1158. le16_to_cpu(priv->rxon_timing.atim_window));
  1159. }
  1160. static int iwl3945_scan_initiate(struct iwl_priv *priv)
  1161. {
  1162. if (!iwl_is_ready_rf(priv)) {
  1163. IWL_DEBUG_SCAN("Aborting scan due to not ready.\n");
  1164. return -EIO;
  1165. }
  1166. if (test_bit(STATUS_SCANNING, &priv->status)) {
  1167. IWL_DEBUG_SCAN("Scan already in progress.\n");
  1168. return -EAGAIN;
  1169. }
  1170. if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
  1171. IWL_DEBUG_SCAN("Scan request while abort pending. "
  1172. "Queuing.\n");
  1173. return -EAGAIN;
  1174. }
  1175. IWL_DEBUG_INFO("Starting scan...\n");
  1176. if (priv->cfg->sku & IWL_SKU_G)
  1177. priv->scan_bands |= BIT(IEEE80211_BAND_2GHZ);
  1178. if (priv->cfg->sku & IWL_SKU_A)
  1179. priv->scan_bands |= BIT(IEEE80211_BAND_5GHZ);
  1180. set_bit(STATUS_SCANNING, &priv->status);
  1181. priv->scan_start = jiffies;
  1182. priv->scan_pass_start = priv->scan_start;
  1183. queue_work(priv->workqueue, &priv->request_scan);
  1184. return 0;
  1185. }
  1186. static int iwl3945_set_rxon_hwcrypto(struct iwl_priv *priv, int hw_decrypt)
  1187. {
  1188. struct iwl3945_rxon_cmd *rxon = &priv->staging39_rxon;
  1189. if (hw_decrypt)
  1190. rxon->filter_flags &= ~RXON_FILTER_DIS_DECRYPT_MSK;
  1191. else
  1192. rxon->filter_flags |= RXON_FILTER_DIS_DECRYPT_MSK;
  1193. return 0;
  1194. }
  1195. static void iwl3945_set_flags_for_phymode(struct iwl_priv *priv,
  1196. enum ieee80211_band band)
  1197. {
  1198. if (band == IEEE80211_BAND_5GHZ) {
  1199. priv->staging39_rxon.flags &=
  1200. ~(RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK
  1201. | RXON_FLG_CCK_MSK);
  1202. priv->staging39_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
  1203. } else {
  1204. /* Copied from iwl3945_bg_post_associate() */
  1205. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
  1206. priv->staging39_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
  1207. else
  1208. priv->staging39_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  1209. if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
  1210. priv->staging39_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  1211. priv->staging39_rxon.flags |= RXON_FLG_BAND_24G_MSK;
  1212. priv->staging39_rxon.flags |= RXON_FLG_AUTO_DETECT_MSK;
  1213. priv->staging39_rxon.flags &= ~RXON_FLG_CCK_MSK;
  1214. }
  1215. }
  1216. /*
  1217. * initialize rxon structure with default values from eeprom
  1218. */
  1219. static void iwl3945_connection_init_rx_config(struct iwl_priv *priv,
  1220. int mode)
  1221. {
  1222. const struct iwl_channel_info *ch_info;
  1223. memset(&priv->staging39_rxon, 0, sizeof(priv->staging39_rxon));
  1224. switch (mode) {
  1225. case NL80211_IFTYPE_AP:
  1226. priv->staging39_rxon.dev_type = RXON_DEV_TYPE_AP;
  1227. break;
  1228. case NL80211_IFTYPE_STATION:
  1229. priv->staging39_rxon.dev_type = RXON_DEV_TYPE_ESS;
  1230. priv->staging39_rxon.filter_flags = RXON_FILTER_ACCEPT_GRP_MSK;
  1231. break;
  1232. case NL80211_IFTYPE_ADHOC:
  1233. priv->staging39_rxon.dev_type = RXON_DEV_TYPE_IBSS;
  1234. priv->staging39_rxon.flags = RXON_FLG_SHORT_PREAMBLE_MSK;
  1235. priv->staging39_rxon.filter_flags = RXON_FILTER_BCON_AWARE_MSK |
  1236. RXON_FILTER_ACCEPT_GRP_MSK;
  1237. break;
  1238. case NL80211_IFTYPE_MONITOR:
  1239. priv->staging39_rxon.dev_type = RXON_DEV_TYPE_SNIFFER;
  1240. priv->staging39_rxon.filter_flags = RXON_FILTER_PROMISC_MSK |
  1241. RXON_FILTER_CTL2HOST_MSK | RXON_FILTER_ACCEPT_GRP_MSK;
  1242. break;
  1243. default:
  1244. IWL_ERR(priv, "Unsupported interface type %d\n", mode);
  1245. break;
  1246. }
  1247. #if 0
  1248. /* TODO: Figure out when short_preamble would be set and cache from
  1249. * that */
  1250. if (!hw_to_local(priv->hw)->short_preamble)
  1251. priv->staging39_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
  1252. else
  1253. priv->staging39_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
  1254. #endif
  1255. ch_info = iwl3945_get_channel_info(priv, priv->band,
  1256. le16_to_cpu(priv->active39_rxon.channel));
  1257. if (!ch_info)
  1258. ch_info = &priv->channel_info[0];
  1259. /*
  1260. * in some case A channels are all non IBSS
  1261. * in this case force B/G channel
  1262. */
  1263. if ((mode == NL80211_IFTYPE_ADHOC) && !(is_channel_ibss(ch_info)))
  1264. ch_info = &priv->channel_info[0];
  1265. priv->staging39_rxon.channel = cpu_to_le16(ch_info->channel);
  1266. if (is_channel_a_band(ch_info))
  1267. priv->band = IEEE80211_BAND_5GHZ;
  1268. else
  1269. priv->band = IEEE80211_BAND_2GHZ;
  1270. iwl3945_set_flags_for_phymode(priv, priv->band);
  1271. priv->staging39_rxon.ofdm_basic_rates =
  1272. (IWL_OFDM_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
  1273. priv->staging39_rxon.cck_basic_rates =
  1274. (IWL_CCK_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF;
  1275. }
  1276. static int iwl3945_set_mode(struct iwl_priv *priv, int mode)
  1277. {
  1278. if (mode == NL80211_IFTYPE_ADHOC) {
  1279. const struct iwl_channel_info *ch_info;
  1280. ch_info = iwl3945_get_channel_info(priv,
  1281. priv->band,
  1282. le16_to_cpu(priv->staging39_rxon.channel));
  1283. if (!ch_info || !is_channel_ibss(ch_info)) {
  1284. IWL_ERR(priv, "channel %d not IBSS channel\n",
  1285. le16_to_cpu(priv->staging39_rxon.channel));
  1286. return -EINVAL;
  1287. }
  1288. }
  1289. iwl3945_connection_init_rx_config(priv, mode);
  1290. memcpy(priv->staging39_rxon.node_addr, priv->mac_addr, ETH_ALEN);
  1291. iwl3945_clear_stations_table(priv);
  1292. /* don't commit rxon if rf-kill is on*/
  1293. if (!iwl_is_ready_rf(priv))
  1294. return -EAGAIN;
  1295. cancel_delayed_work(&priv->scan_check);
  1296. if (iwl_scan_cancel_timeout(priv, 100)) {
  1297. IWL_WARN(priv, "Aborted scan still in progress after 100ms\n");
  1298. IWL_DEBUG_MAC80211("leaving - scan abort failed.\n");
  1299. return -EAGAIN;
  1300. }
  1301. iwl3945_commit_rxon(priv);
  1302. return 0;
  1303. }
  1304. static void iwl3945_build_tx_cmd_hwcrypto(struct iwl_priv *priv,
  1305. struct ieee80211_tx_info *info,
  1306. struct iwl_cmd *cmd,
  1307. struct sk_buff *skb_frag,
  1308. int last_frag)
  1309. {
  1310. struct iwl3945_tx_cmd *tx = (struct iwl3945_tx_cmd *)cmd->cmd.payload;
  1311. struct iwl3945_hw_key *keyinfo =
  1312. &priv->stations_39[info->control.hw_key->hw_key_idx].keyinfo;
  1313. switch (keyinfo->alg) {
  1314. case ALG_CCMP:
  1315. tx->sec_ctl = TX_CMD_SEC_CCM;
  1316. memcpy(tx->key, keyinfo->key, keyinfo->keylen);
  1317. IWL_DEBUG_TX("tx_cmd with AES hwcrypto\n");
  1318. break;
  1319. case ALG_TKIP:
  1320. #if 0
  1321. tx->sec_ctl = TX_CMD_SEC_TKIP;
  1322. if (last_frag)
  1323. memcpy(tx->tkip_mic.byte, skb_frag->tail - 8,
  1324. 8);
  1325. else
  1326. memset(tx->tkip_mic.byte, 0, 8);
  1327. #endif
  1328. break;
  1329. case ALG_WEP:
  1330. tx->sec_ctl = TX_CMD_SEC_WEP |
  1331. (info->control.hw_key->hw_key_idx & TX_CMD_SEC_MSK) << TX_CMD_SEC_SHIFT;
  1332. if (keyinfo->keylen == 13)
  1333. tx->sec_ctl |= TX_CMD_SEC_KEY128;
  1334. memcpy(&tx->key[3], keyinfo->key, keyinfo->keylen);
  1335. IWL_DEBUG_TX("Configuring packet for WEP encryption "
  1336. "with key %d\n", info->control.hw_key->hw_key_idx);
  1337. break;
  1338. default:
  1339. IWL_ERR(priv, "Unknown encode alg %d\n", keyinfo->alg);
  1340. break;
  1341. }
  1342. }
  1343. /*
  1344. * handle build REPLY_TX command notification.
  1345. */
  1346. static void iwl3945_build_tx_cmd_basic(struct iwl_priv *priv,
  1347. struct iwl_cmd *cmd,
  1348. struct ieee80211_tx_info *info,
  1349. struct ieee80211_hdr *hdr, u8 std_id)
  1350. {
  1351. struct iwl3945_tx_cmd *tx = (struct iwl3945_tx_cmd *)cmd->cmd.payload;
  1352. __le32 tx_flags = tx->tx_flags;
  1353. __le16 fc = hdr->frame_control;
  1354. u8 rc_flags = info->control.rates[0].flags;
  1355. tx->stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
  1356. if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) {
  1357. tx_flags |= TX_CMD_FLG_ACK_MSK;
  1358. if (ieee80211_is_mgmt(fc))
  1359. tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
  1360. if (ieee80211_is_probe_resp(fc) &&
  1361. !(le16_to_cpu(hdr->seq_ctrl) & 0xf))
  1362. tx_flags |= TX_CMD_FLG_TSF_MSK;
  1363. } else {
  1364. tx_flags &= (~TX_CMD_FLG_ACK_MSK);
  1365. tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
  1366. }
  1367. tx->sta_id = std_id;
  1368. if (ieee80211_has_morefrags(fc))
  1369. tx_flags |= TX_CMD_FLG_MORE_FRAG_MSK;
  1370. if (ieee80211_is_data_qos(fc)) {
  1371. u8 *qc = ieee80211_get_qos_ctl(hdr);
  1372. tx->tid_tspec = qc[0] & 0xf;
  1373. tx_flags &= ~TX_CMD_FLG_SEQ_CTL_MSK;
  1374. } else {
  1375. tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
  1376. }
  1377. if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) {
  1378. tx_flags |= TX_CMD_FLG_RTS_MSK;
  1379. tx_flags &= ~TX_CMD_FLG_CTS_MSK;
  1380. } else if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
  1381. tx_flags &= ~TX_CMD_FLG_RTS_MSK;
  1382. tx_flags |= TX_CMD_FLG_CTS_MSK;
  1383. }
  1384. if ((tx_flags & TX_CMD_FLG_RTS_MSK) || (tx_flags & TX_CMD_FLG_CTS_MSK))
  1385. tx_flags |= TX_CMD_FLG_FULL_TXOP_PROT_MSK;
  1386. tx_flags &= ~(TX_CMD_FLG_ANT_SEL_MSK);
  1387. if (ieee80211_is_mgmt(fc)) {
  1388. if (ieee80211_is_assoc_req(fc) || ieee80211_is_reassoc_req(fc))
  1389. tx->timeout.pm_frame_timeout = cpu_to_le16(3);
  1390. else
  1391. tx->timeout.pm_frame_timeout = cpu_to_le16(2);
  1392. } else {
  1393. tx->timeout.pm_frame_timeout = 0;
  1394. #ifdef CONFIG_IWL3945_LEDS
  1395. priv->rxtxpackets += le16_to_cpu(cmd->cmd.tx.len);
  1396. #endif
  1397. }
  1398. tx->driver_txop = 0;
  1399. tx->tx_flags = tx_flags;
  1400. tx->next_frame_len = 0;
  1401. }
  1402. /**
  1403. * iwl3945_get_sta_id - Find station's index within station table
  1404. */
  1405. static int iwl3945_get_sta_id(struct iwl_priv *priv, struct ieee80211_hdr *hdr)
  1406. {
  1407. int sta_id;
  1408. u16 fc = le16_to_cpu(hdr->frame_control);
  1409. /* If this frame is broadcast or management, use broadcast station id */
  1410. if (((fc & IEEE80211_FCTL_FTYPE) != IEEE80211_FTYPE_DATA) ||
  1411. is_multicast_ether_addr(hdr->addr1))
  1412. return priv->hw_params.bcast_sta_id;
  1413. switch (priv->iw_mode) {
  1414. /* If we are a client station in a BSS network, use the special
  1415. * AP station entry (that's the only station we communicate with) */
  1416. case NL80211_IFTYPE_STATION:
  1417. return IWL_AP_ID;
  1418. /* If we are an AP, then find the station, or use BCAST */
  1419. case NL80211_IFTYPE_AP:
  1420. sta_id = iwl3945_hw_find_station(priv, hdr->addr1);
  1421. if (sta_id != IWL_INVALID_STATION)
  1422. return sta_id;
  1423. return priv->hw_params.bcast_sta_id;
  1424. /* If this frame is going out to an IBSS network, find the station,
  1425. * or create a new station table entry */
  1426. case NL80211_IFTYPE_ADHOC: {
  1427. /* Create new station table entry */
  1428. sta_id = iwl3945_hw_find_station(priv, hdr->addr1);
  1429. if (sta_id != IWL_INVALID_STATION)
  1430. return sta_id;
  1431. sta_id = iwl3945_add_station(priv, hdr->addr1, 0, CMD_ASYNC);
  1432. if (sta_id != IWL_INVALID_STATION)
  1433. return sta_id;
  1434. IWL_DEBUG_DROP("Station %pM not in station map. "
  1435. "Defaulting to broadcast...\n",
  1436. hdr->addr1);
  1437. iwl_print_hex_dump(priv, IWL_DL_DROP, (u8 *) hdr, sizeof(*hdr));
  1438. return priv->hw_params.bcast_sta_id;
  1439. }
  1440. /* If we are in monitor mode, use BCAST. This is required for
  1441. * packet injection. */
  1442. case NL80211_IFTYPE_MONITOR:
  1443. return priv->hw_params.bcast_sta_id;
  1444. default:
  1445. IWL_WARN(priv, "Unknown mode of operation: %d\n",
  1446. priv->iw_mode);
  1447. return priv->hw_params.bcast_sta_id;
  1448. }
  1449. }
  1450. /*
  1451. * start REPLY_TX command process
  1452. */
  1453. static int iwl3945_tx_skb(struct iwl_priv *priv, struct sk_buff *skb)
  1454. {
  1455. struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
  1456. struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
  1457. struct iwl3945_tx_cmd *tx;
  1458. struct iwl_tx_queue *txq = NULL;
  1459. struct iwl_queue *q = NULL;
  1460. struct iwl_cmd *out_cmd = NULL;
  1461. dma_addr_t phys_addr;
  1462. dma_addr_t txcmd_phys;
  1463. int txq_id = skb_get_queue_mapping(skb);
  1464. u16 len, idx, len_org, hdr_len;
  1465. u8 id;
  1466. u8 unicast;
  1467. u8 sta_id;
  1468. u8 tid = 0;
  1469. u16 seq_number = 0;
  1470. __le16 fc;
  1471. u8 wait_write_ptr = 0;
  1472. u8 *qc = NULL;
  1473. unsigned long flags;
  1474. int rc;
  1475. spin_lock_irqsave(&priv->lock, flags);
  1476. if (iwl_is_rfkill(priv)) {
  1477. IWL_DEBUG_DROP("Dropping - RF KILL\n");
  1478. goto drop_unlock;
  1479. }
  1480. if ((ieee80211_get_tx_rate(priv->hw, info)->hw_value & 0xFF) == IWL_INVALID_RATE) {
  1481. IWL_ERR(priv, "ERROR: No TX rate available.\n");
  1482. goto drop_unlock;
  1483. }
  1484. unicast = !is_multicast_ether_addr(hdr->addr1);
  1485. id = 0;
  1486. fc = hdr->frame_control;
  1487. #ifdef CONFIG_IWL3945_DEBUG
  1488. if (ieee80211_is_auth(fc))
  1489. IWL_DEBUG_TX("Sending AUTH frame\n");
  1490. else if (ieee80211_is_assoc_req(fc))
  1491. IWL_DEBUG_TX("Sending ASSOC frame\n");
  1492. else if (ieee80211_is_reassoc_req(fc))
  1493. IWL_DEBUG_TX("Sending REASSOC frame\n");
  1494. #endif
  1495. /* drop all data frame if we are not associated */
  1496. if (ieee80211_is_data(fc) &&
  1497. (priv->iw_mode != NL80211_IFTYPE_MONITOR) && /* packet injection */
  1498. (!iwl3945_is_associated(priv) ||
  1499. ((priv->iw_mode == NL80211_IFTYPE_STATION) && !priv->assoc_id))) {
  1500. IWL_DEBUG_DROP("Dropping - !iwl3945_is_associated\n");
  1501. goto drop_unlock;
  1502. }
  1503. spin_unlock_irqrestore(&priv->lock, flags);
  1504. hdr_len = ieee80211_hdrlen(fc);
  1505. /* Find (or create) index into station table for destination station */
  1506. sta_id = iwl3945_get_sta_id(priv, hdr);
  1507. if (sta_id == IWL_INVALID_STATION) {
  1508. IWL_DEBUG_DROP("Dropping - INVALID STATION: %pM\n",
  1509. hdr->addr1);
  1510. goto drop;
  1511. }
  1512. IWL_DEBUG_RATE("station Id %d\n", sta_id);
  1513. if (ieee80211_is_data_qos(fc)) {
  1514. qc = ieee80211_get_qos_ctl(hdr);
  1515. tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK;
  1516. seq_number = priv->stations_39[sta_id].tid[tid].seq_number &
  1517. IEEE80211_SCTL_SEQ;
  1518. hdr->seq_ctrl = cpu_to_le16(seq_number) |
  1519. (hdr->seq_ctrl &
  1520. __constant_cpu_to_le16(IEEE80211_SCTL_FRAG));
  1521. seq_number += 0x10;
  1522. }
  1523. /* Descriptor for chosen Tx queue */
  1524. txq = &priv->txq[txq_id];
  1525. q = &txq->q;
  1526. spin_lock_irqsave(&priv->lock, flags);
  1527. idx = get_cmd_index(q, q->write_ptr, 0);
  1528. /* Set up driver data for this TFD */
  1529. memset(&(txq->txb[q->write_ptr]), 0, sizeof(struct iwl_tx_info));
  1530. txq->txb[q->write_ptr].skb[0] = skb;
  1531. /* Init first empty entry in queue's array of Tx/cmd buffers */
  1532. out_cmd = txq->cmd[idx];
  1533. tx = (struct iwl3945_tx_cmd *)out_cmd->cmd.payload;
  1534. memset(&out_cmd->hdr, 0, sizeof(out_cmd->hdr));
  1535. memset(tx, 0, sizeof(*tx));
  1536. /*
  1537. * Set up the Tx-command (not MAC!) header.
  1538. * Store the chosen Tx queue and TFD index within the sequence field;
  1539. * after Tx, uCode's Tx response will return this value so driver can
  1540. * locate the frame within the tx queue and do post-tx processing.
  1541. */
  1542. out_cmd->hdr.cmd = REPLY_TX;
  1543. out_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
  1544. INDEX_TO_SEQ(q->write_ptr)));
  1545. /* Copy MAC header from skb into command buffer */
  1546. memcpy(tx->hdr, hdr, hdr_len);
  1547. /*
  1548. * Use the first empty entry in this queue's command buffer array
  1549. * to contain the Tx command and MAC header concatenated together
  1550. * (payload data will be in another buffer).
  1551. * Size of this varies, due to varying MAC header length.
  1552. * If end is not dword aligned, we'll have 2 extra bytes at the end
  1553. * of the MAC header (device reads on dword boundaries).
  1554. * We'll tell device about this padding later.
  1555. */
  1556. len = sizeof(struct iwl3945_tx_cmd) +
  1557. sizeof(struct iwl_cmd_header) + hdr_len;
  1558. len_org = len;
  1559. len = (len + 3) & ~3;
  1560. if (len_org != len)
  1561. len_org = 1;
  1562. else
  1563. len_org = 0;
  1564. /* Physical address of this Tx command's header (not MAC header!),
  1565. * within command buffer array. */
  1566. txcmd_phys = pci_map_single(priv->pci_dev,
  1567. out_cmd, sizeof(struct iwl_cmd),
  1568. PCI_DMA_TODEVICE);
  1569. pci_unmap_addr_set(&out_cmd->meta, mapping, txcmd_phys);
  1570. pci_unmap_len_set(&out_cmd->meta, len, sizeof(struct iwl_cmd));
  1571. /* Add buffer containing Tx command and MAC(!) header to TFD's
  1572. * first entry */
  1573. txcmd_phys += offsetof(struct iwl_cmd, hdr);
  1574. /* Add buffer containing Tx command and MAC(!) header to TFD's
  1575. * first entry */
  1576. priv->cfg->ops->lib->txq_attach_buf_to_tfd(priv, txq,
  1577. txcmd_phys, len, 1, 0);
  1578. if (info->control.hw_key)
  1579. iwl3945_build_tx_cmd_hwcrypto(priv, info, out_cmd, skb, 0);
  1580. /* Set up TFD's 2nd entry to point directly to remainder of skb,
  1581. * if any (802.11 null frames have no payload). */
  1582. len = skb->len - hdr_len;
  1583. if (len) {
  1584. phys_addr = pci_map_single(priv->pci_dev, skb->data + hdr_len,
  1585. len, PCI_DMA_TODEVICE);
  1586. priv->cfg->ops->lib->txq_attach_buf_to_tfd(priv, txq,
  1587. phys_addr, len,
  1588. 0, U32_PAD(len));
  1589. }
  1590. /* Total # bytes to be transmitted */
  1591. len = (u16)skb->len;
  1592. tx->len = cpu_to_le16(len);
  1593. /* TODO need this for burst mode later on */
  1594. iwl3945_build_tx_cmd_basic(priv, out_cmd, info, hdr, sta_id);
  1595. /* set is_hcca to 0; it probably will never be implemented */
  1596. iwl3945_hw_build_tx_cmd_rate(priv, out_cmd, info, hdr, sta_id, 0);
  1597. tx->tx_flags &= ~TX_CMD_FLG_ANT_A_MSK;
  1598. tx->tx_flags &= ~TX_CMD_FLG_ANT_B_MSK;
  1599. if (!ieee80211_has_morefrags(hdr->frame_control)) {
  1600. txq->need_update = 1;
  1601. if (qc)
  1602. priv->stations_39[sta_id].tid[tid].seq_number = seq_number;
  1603. } else {
  1604. wait_write_ptr = 1;
  1605. txq->need_update = 0;
  1606. }
  1607. iwl_print_hex_dump(priv, IWL_DL_TX, tx, sizeof(*tx));
  1608. iwl_print_hex_dump(priv, IWL_DL_TX, (u8 *)tx->hdr,
  1609. ieee80211_hdrlen(fc));
  1610. /* Tell device the write index *just past* this latest filled TFD */
  1611. q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
  1612. rc = iwl_txq_update_write_ptr(priv, txq);
  1613. spin_unlock_irqrestore(&priv->lock, flags);
  1614. if (rc)
  1615. return rc;
  1616. if ((iwl_queue_space(q) < q->high_mark)
  1617. && priv->mac80211_registered) {
  1618. if (wait_write_ptr) {
  1619. spin_lock_irqsave(&priv->lock, flags);
  1620. txq->need_update = 1;
  1621. iwl_txq_update_write_ptr(priv, txq);
  1622. spin_unlock_irqrestore(&priv->lock, flags);
  1623. }
  1624. ieee80211_stop_queue(priv->hw, skb_get_queue_mapping(skb));
  1625. }
  1626. return 0;
  1627. drop_unlock:
  1628. spin_unlock_irqrestore(&priv->lock, flags);
  1629. drop:
  1630. return -1;
  1631. }
  1632. static void iwl3945_set_rate(struct iwl_priv *priv)
  1633. {
  1634. const struct ieee80211_supported_band *sband = NULL;
  1635. struct ieee80211_rate *rate;
  1636. int i;
  1637. sband = iwl_get_hw_mode(priv, priv->band);
  1638. if (!sband) {
  1639. IWL_ERR(priv, "Failed to set rate: unable to get hw mode\n");
  1640. return;
  1641. }
  1642. priv->active_rate = 0;
  1643. priv->active_rate_basic = 0;
  1644. IWL_DEBUG_RATE("Setting rates for %s GHz\n",
  1645. sband->band == IEEE80211_BAND_2GHZ ? "2.4" : "5");
  1646. for (i = 0; i < sband->n_bitrates; i++) {
  1647. rate = &sband->bitrates[i];
  1648. if ((rate->hw_value < IWL_RATE_COUNT) &&
  1649. !(rate->flags & IEEE80211_CHAN_DISABLED)) {
  1650. IWL_DEBUG_RATE("Adding rate index %d (plcp %d)\n",
  1651. rate->hw_value, iwl3945_rates[rate->hw_value].plcp);
  1652. priv->active_rate |= (1 << rate->hw_value);
  1653. }
  1654. }
  1655. IWL_DEBUG_RATE("Set active_rate = %0x, active_rate_basic = %0x\n",
  1656. priv->active_rate, priv->active_rate_basic);
  1657. /*
  1658. * If a basic rate is configured, then use it (adding IWL_RATE_1M_MASK)
  1659. * otherwise set it to the default of all CCK rates and 6, 12, 24 for
  1660. * OFDM
  1661. */
  1662. if (priv->active_rate_basic & IWL_CCK_BASIC_RATES_MASK)
  1663. priv->staging39_rxon.cck_basic_rates =
  1664. ((priv->active_rate_basic &
  1665. IWL_CCK_RATES_MASK) >> IWL_FIRST_CCK_RATE) & 0xF;
  1666. else
  1667. priv->staging39_rxon.cck_basic_rates =
  1668. (IWL_CCK_BASIC_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF;
  1669. if (priv->active_rate_basic & IWL_OFDM_BASIC_RATES_MASK)
  1670. priv->staging39_rxon.ofdm_basic_rates =
  1671. ((priv->active_rate_basic &
  1672. (IWL_OFDM_BASIC_RATES_MASK | IWL_RATE_6M_MASK)) >>
  1673. IWL_FIRST_OFDM_RATE) & 0xFF;
  1674. else
  1675. priv->staging39_rxon.ofdm_basic_rates =
  1676. (IWL_OFDM_BASIC_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
  1677. }
  1678. static void iwl3945_radio_kill_sw(struct iwl_priv *priv, int disable_radio)
  1679. {
  1680. unsigned long flags;
  1681. if (!!disable_radio == test_bit(STATUS_RF_KILL_SW, &priv->status))
  1682. return;
  1683. IWL_DEBUG_RF_KILL("Manual SW RF KILL set to: RADIO %s\n",
  1684. disable_radio ? "OFF" : "ON");
  1685. if (disable_radio) {
  1686. iwl_scan_cancel(priv);
  1687. /* FIXME: This is a workaround for AP */
  1688. if (priv->iw_mode != NL80211_IFTYPE_AP) {
  1689. spin_lock_irqsave(&priv->lock, flags);
  1690. iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
  1691. CSR_UCODE_SW_BIT_RFKILL);
  1692. spin_unlock_irqrestore(&priv->lock, flags);
  1693. iwl_send_card_state(priv, CARD_STATE_CMD_DISABLE, 0);
  1694. set_bit(STATUS_RF_KILL_SW, &priv->status);
  1695. }
  1696. return;
  1697. }
  1698. spin_lock_irqsave(&priv->lock, flags);
  1699. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  1700. clear_bit(STATUS_RF_KILL_SW, &priv->status);
  1701. spin_unlock_irqrestore(&priv->lock, flags);
  1702. /* wake up ucode */
  1703. msleep(10);
  1704. spin_lock_irqsave(&priv->lock, flags);
  1705. iwl_read32(priv, CSR_UCODE_DRV_GP1);
  1706. if (!iwl_grab_nic_access(priv))
  1707. iwl_release_nic_access(priv);
  1708. spin_unlock_irqrestore(&priv->lock, flags);
  1709. if (test_bit(STATUS_RF_KILL_HW, &priv->status)) {
  1710. IWL_DEBUG_RF_KILL("Can not turn radio back on - "
  1711. "disabled by HW switch\n");
  1712. return;
  1713. }
  1714. if (priv->is_open)
  1715. queue_work(priv->workqueue, &priv->restart);
  1716. return;
  1717. }
  1718. void iwl3945_set_decrypted_flag(struct iwl_priv *priv, struct sk_buff *skb,
  1719. u32 decrypt_res, struct ieee80211_rx_status *stats)
  1720. {
  1721. u16 fc =
  1722. le16_to_cpu(((struct ieee80211_hdr *)skb->data)->frame_control);
  1723. if (priv->active39_rxon.filter_flags & RXON_FILTER_DIS_DECRYPT_MSK)
  1724. return;
  1725. if (!(fc & IEEE80211_FCTL_PROTECTED))
  1726. return;
  1727. IWL_DEBUG_RX("decrypt_res:0x%x\n", decrypt_res);
  1728. switch (decrypt_res & RX_RES_STATUS_SEC_TYPE_MSK) {
  1729. case RX_RES_STATUS_SEC_TYPE_TKIP:
  1730. if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
  1731. RX_RES_STATUS_BAD_ICV_MIC)
  1732. stats->flag |= RX_FLAG_MMIC_ERROR;
  1733. case RX_RES_STATUS_SEC_TYPE_WEP:
  1734. case RX_RES_STATUS_SEC_TYPE_CCMP:
  1735. if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
  1736. RX_RES_STATUS_DECRYPT_OK) {
  1737. IWL_DEBUG_RX("hw decrypt successfully!!!\n");
  1738. stats->flag |= RX_FLAG_DECRYPTED;
  1739. }
  1740. break;
  1741. default:
  1742. break;
  1743. }
  1744. }
  1745. #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
  1746. #include "iwl-spectrum.h"
  1747. #define BEACON_TIME_MASK_LOW 0x00FFFFFF
  1748. #define BEACON_TIME_MASK_HIGH 0xFF000000
  1749. #define TIME_UNIT 1024
  1750. /*
  1751. * extended beacon time format
  1752. * time in usec will be changed into a 32-bit value in 8:24 format
  1753. * the high 1 byte is the beacon counts
  1754. * the lower 3 bytes is the time in usec within one beacon interval
  1755. */
  1756. static u32 iwl3945_usecs_to_beacons(u32 usec, u32 beacon_interval)
  1757. {
  1758. u32 quot;
  1759. u32 rem;
  1760. u32 interval = beacon_interval * 1024;
  1761. if (!interval || !usec)
  1762. return 0;
  1763. quot = (usec / interval) & (BEACON_TIME_MASK_HIGH >> 24);
  1764. rem = (usec % interval) & BEACON_TIME_MASK_LOW;
  1765. return (quot << 24) + rem;
  1766. }
  1767. /* base is usually what we get from ucode with each received frame,
  1768. * the same as HW timer counter counting down
  1769. */
  1770. static __le32 iwl3945_add_beacon_time(u32 base, u32 addon, u32 beacon_interval)
  1771. {
  1772. u32 base_low = base & BEACON_TIME_MASK_LOW;
  1773. u32 addon_low = addon & BEACON_TIME_MASK_LOW;
  1774. u32 interval = beacon_interval * TIME_UNIT;
  1775. u32 res = (base & BEACON_TIME_MASK_HIGH) +
  1776. (addon & BEACON_TIME_MASK_HIGH);
  1777. if (base_low > addon_low)
  1778. res += base_low - addon_low;
  1779. else if (base_low < addon_low) {
  1780. res += interval + base_low - addon_low;
  1781. res += (1 << 24);
  1782. } else
  1783. res += (1 << 24);
  1784. return cpu_to_le32(res);
  1785. }
  1786. static int iwl3945_get_measurement(struct iwl_priv *priv,
  1787. struct ieee80211_measurement_params *params,
  1788. u8 type)
  1789. {
  1790. struct iwl_spectrum_cmd spectrum;
  1791. struct iwl_rx_packet *res;
  1792. struct iwl_host_cmd cmd = {
  1793. .id = REPLY_SPECTRUM_MEASUREMENT_CMD,
  1794. .data = (void *)&spectrum,
  1795. .meta.flags = CMD_WANT_SKB,
  1796. };
  1797. u32 add_time = le64_to_cpu(params->start_time);
  1798. int rc;
  1799. int spectrum_resp_status;
  1800. int duration = le16_to_cpu(params->duration);
  1801. if (iwl3945_is_associated(priv))
  1802. add_time =
  1803. iwl3945_usecs_to_beacons(
  1804. le64_to_cpu(params->start_time) - priv->last_tsf,
  1805. le16_to_cpu(priv->rxon_timing.beacon_interval));
  1806. memset(&spectrum, 0, sizeof(spectrum));
  1807. spectrum.channel_count = cpu_to_le16(1);
  1808. spectrum.flags =
  1809. RXON_FLG_TSF2HOST_MSK | RXON_FLG_ANT_A_MSK | RXON_FLG_DIS_DIV_MSK;
  1810. spectrum.filter_flags = MEASUREMENT_FILTER_FLAG;
  1811. cmd.len = sizeof(spectrum);
  1812. spectrum.len = cpu_to_le16(cmd.len - sizeof(spectrum.len));
  1813. if (iwl3945_is_associated(priv))
  1814. spectrum.start_time =
  1815. iwl3945_add_beacon_time(priv->last_beacon_time,
  1816. add_time,
  1817. le16_to_cpu(priv->rxon_timing.beacon_interval));
  1818. else
  1819. spectrum.start_time = 0;
  1820. spectrum.channels[0].duration = cpu_to_le32(duration * TIME_UNIT);
  1821. spectrum.channels[0].channel = params->channel;
  1822. spectrum.channels[0].type = type;
  1823. if (priv->active39_rxon.flags & RXON_FLG_BAND_24G_MSK)
  1824. spectrum.flags |= RXON_FLG_BAND_24G_MSK |
  1825. RXON_FLG_AUTO_DETECT_MSK | RXON_FLG_TGG_PROTECT_MSK;
  1826. rc = iwl_send_cmd_sync(priv, &cmd);
  1827. if (rc)
  1828. return rc;
  1829. res = (struct iwl_rx_packet *)cmd.meta.u.skb->data;
  1830. if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
  1831. IWL_ERR(priv, "Bad return from REPLY_RX_ON_ASSOC command\n");
  1832. rc = -EIO;
  1833. }
  1834. spectrum_resp_status = le16_to_cpu(res->u.spectrum.status);
  1835. switch (spectrum_resp_status) {
  1836. case 0: /* Command will be handled */
  1837. if (res->u.spectrum.id != 0xff) {
  1838. IWL_DEBUG_INFO("Replaced existing measurement: %d\n",
  1839. res->u.spectrum.id);
  1840. priv->measurement_status &= ~MEASUREMENT_READY;
  1841. }
  1842. priv->measurement_status |= MEASUREMENT_ACTIVE;
  1843. rc = 0;
  1844. break;
  1845. case 1: /* Command will not be handled */
  1846. rc = -EAGAIN;
  1847. break;
  1848. }
  1849. dev_kfree_skb_any(cmd.meta.u.skb);
  1850. return rc;
  1851. }
  1852. #endif
  1853. static void iwl3945_rx_reply_alive(struct iwl_priv *priv,
  1854. struct iwl_rx_mem_buffer *rxb)
  1855. {
  1856. struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
  1857. struct iwl_alive_resp *palive;
  1858. struct delayed_work *pwork;
  1859. palive = &pkt->u.alive_frame;
  1860. IWL_DEBUG_INFO("Alive ucode status 0x%08X revision "
  1861. "0x%01X 0x%01X\n",
  1862. palive->is_valid, palive->ver_type,
  1863. palive->ver_subtype);
  1864. if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
  1865. IWL_DEBUG_INFO("Initialization Alive received.\n");
  1866. memcpy(&priv->card_alive_init, &pkt->u.alive_frame,
  1867. sizeof(struct iwl_alive_resp));
  1868. pwork = &priv->init_alive_start;
  1869. } else {
  1870. IWL_DEBUG_INFO("Runtime Alive received.\n");
  1871. memcpy(&priv->card_alive, &pkt->u.alive_frame,
  1872. sizeof(struct iwl_alive_resp));
  1873. pwork = &priv->alive_start;
  1874. iwl3945_disable_events(priv);
  1875. }
  1876. /* We delay the ALIVE response by 5ms to
  1877. * give the HW RF Kill time to activate... */
  1878. if (palive->is_valid == UCODE_VALID_OK)
  1879. queue_delayed_work(priv->workqueue, pwork,
  1880. msecs_to_jiffies(5));
  1881. else
  1882. IWL_WARN(priv, "uCode did not respond OK.\n");
  1883. }
  1884. static void iwl3945_rx_reply_add_sta(struct iwl_priv *priv,
  1885. struct iwl_rx_mem_buffer *rxb)
  1886. {
  1887. #ifdef CONFIG_IWLWIFI_DEBUG
  1888. struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
  1889. #endif
  1890. IWL_DEBUG_RX("Received REPLY_ADD_STA: 0x%02X\n", pkt->u.status);
  1891. return;
  1892. }
  1893. static void iwl3945_rx_reply_error(struct iwl_priv *priv,
  1894. struct iwl_rx_mem_buffer *rxb)
  1895. {
  1896. struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
  1897. IWL_ERR(priv, "Error Reply type 0x%08X cmd %s (0x%02X) "
  1898. "seq 0x%04X ser 0x%08X\n",
  1899. le32_to_cpu(pkt->u.err_resp.error_type),
  1900. get_cmd_string(pkt->u.err_resp.cmd_id),
  1901. pkt->u.err_resp.cmd_id,
  1902. le16_to_cpu(pkt->u.err_resp.bad_cmd_seq_num),
  1903. le32_to_cpu(pkt->u.err_resp.error_info));
  1904. }
  1905. #define TX_STATUS_ENTRY(x) case TX_STATUS_FAIL_ ## x: return #x
  1906. static void iwl3945_rx_csa(struct iwl_priv *priv, struct iwl_rx_mem_buffer *rxb)
  1907. {
  1908. struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
  1909. struct iwl3945_rxon_cmd *rxon = (void *)&priv->active39_rxon;
  1910. struct iwl_csa_notification *csa = &(pkt->u.csa_notif);
  1911. IWL_DEBUG_11H("CSA notif: channel %d, status %d\n",
  1912. le16_to_cpu(csa->channel), le32_to_cpu(csa->status));
  1913. rxon->channel = csa->channel;
  1914. priv->staging39_rxon.channel = csa->channel;
  1915. }
  1916. static void iwl3945_rx_spectrum_measure_notif(struct iwl_priv *priv,
  1917. struct iwl_rx_mem_buffer *rxb)
  1918. {
  1919. #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
  1920. struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
  1921. struct iwl_spectrum_notification *report = &(pkt->u.spectrum_notif);
  1922. if (!report->state) {
  1923. IWL_DEBUG(IWL_DL_11H | IWL_DL_INFO,
  1924. "Spectrum Measure Notification: Start\n");
  1925. return;
  1926. }
  1927. memcpy(&priv->measure_report, report, sizeof(*report));
  1928. priv->measurement_status |= MEASUREMENT_READY;
  1929. #endif
  1930. }
  1931. static void iwl3945_rx_pm_sleep_notif(struct iwl_priv *priv,
  1932. struct iwl_rx_mem_buffer *rxb)
  1933. {
  1934. #ifdef CONFIG_IWL3945_DEBUG
  1935. struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
  1936. struct iwl_sleep_notification *sleep = &(pkt->u.sleep_notif);
  1937. IWL_DEBUG_RX("sleep mode: %d, src: %d\n",
  1938. sleep->pm_sleep_mode, sleep->pm_wakeup_src);
  1939. #endif
  1940. }
  1941. static void iwl3945_rx_pm_debug_statistics_notif(struct iwl_priv *priv,
  1942. struct iwl_rx_mem_buffer *rxb)
  1943. {
  1944. struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
  1945. IWL_DEBUG_RADIO("Dumping %d bytes of unhandled "
  1946. "notification for %s:\n",
  1947. le32_to_cpu(pkt->len), get_cmd_string(pkt->hdr.cmd));
  1948. iwl_print_hex_dump(priv, IWL_DL_RADIO, pkt->u.raw,
  1949. le32_to_cpu(pkt->len));
  1950. }
  1951. static void iwl3945_bg_beacon_update(struct work_struct *work)
  1952. {
  1953. struct iwl_priv *priv =
  1954. container_of(work, struct iwl_priv, beacon_update);
  1955. struct sk_buff *beacon;
  1956. /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
  1957. beacon = ieee80211_beacon_get(priv->hw, priv->vif);
  1958. if (!beacon) {
  1959. IWL_ERR(priv, "update beacon failed\n");
  1960. return;
  1961. }
  1962. mutex_lock(&priv->mutex);
  1963. /* new beacon skb is allocated every time; dispose previous.*/
  1964. if (priv->ibss_beacon)
  1965. dev_kfree_skb(priv->ibss_beacon);
  1966. priv->ibss_beacon = beacon;
  1967. mutex_unlock(&priv->mutex);
  1968. iwl3945_send_beacon_cmd(priv);
  1969. }
  1970. static void iwl3945_rx_beacon_notif(struct iwl_priv *priv,
  1971. struct iwl_rx_mem_buffer *rxb)
  1972. {
  1973. #ifdef CONFIG_IWL3945_DEBUG
  1974. struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
  1975. struct iwl3945_beacon_notif *beacon = &(pkt->u.beacon_status);
  1976. u8 rate = beacon->beacon_notify_hdr.rate;
  1977. IWL_DEBUG_RX("beacon status %x retries %d iss %d "
  1978. "tsf %d %d rate %d\n",
  1979. le32_to_cpu(beacon->beacon_notify_hdr.status) & TX_STATUS_MSK,
  1980. beacon->beacon_notify_hdr.failure_frame,
  1981. le32_to_cpu(beacon->ibss_mgr_status),
  1982. le32_to_cpu(beacon->high_tsf),
  1983. le32_to_cpu(beacon->low_tsf), rate);
  1984. #endif
  1985. if ((priv->iw_mode == NL80211_IFTYPE_AP) &&
  1986. (!test_bit(STATUS_EXIT_PENDING, &priv->status)))
  1987. queue_work(priv->workqueue, &priv->beacon_update);
  1988. }
  1989. /* Service response to REPLY_SCAN_CMD (0x80) */
  1990. static void iwl3945_rx_reply_scan(struct iwl_priv *priv,
  1991. struct iwl_rx_mem_buffer *rxb)
  1992. {
  1993. #ifdef CONFIG_IWL3945_DEBUG
  1994. struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
  1995. struct iwl_scanreq_notification *notif =
  1996. (struct iwl_scanreq_notification *)pkt->u.raw;
  1997. IWL_DEBUG_RX("Scan request status = 0x%x\n", notif->status);
  1998. #endif
  1999. }
  2000. /* Service SCAN_START_NOTIFICATION (0x82) */
  2001. static void iwl3945_rx_scan_start_notif(struct iwl_priv *priv,
  2002. struct iwl_rx_mem_buffer *rxb)
  2003. {
  2004. struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
  2005. struct iwl_scanstart_notification *notif =
  2006. (struct iwl_scanstart_notification *)pkt->u.raw;
  2007. priv->scan_start_tsf = le32_to_cpu(notif->tsf_low);
  2008. IWL_DEBUG_SCAN("Scan start: "
  2009. "%d [802.11%s] "
  2010. "(TSF: 0x%08X:%08X) - %d (beacon timer %u)\n",
  2011. notif->channel,
  2012. notif->band ? "bg" : "a",
  2013. notif->tsf_high,
  2014. notif->tsf_low, notif->status, notif->beacon_timer);
  2015. }
  2016. /* Service SCAN_RESULTS_NOTIFICATION (0x83) */
  2017. static void iwl3945_rx_scan_results_notif(struct iwl_priv *priv,
  2018. struct iwl_rx_mem_buffer *rxb)
  2019. {
  2020. #ifdef CONFIG_IWLWIFI_DEBUG
  2021. struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
  2022. struct iwl_scanresults_notification *notif =
  2023. (struct iwl_scanresults_notification *)pkt->u.raw;
  2024. #endif
  2025. IWL_DEBUG_SCAN("Scan ch.res: "
  2026. "%d [802.11%s] "
  2027. "(TSF: 0x%08X:%08X) - %d "
  2028. "elapsed=%lu usec (%dms since last)\n",
  2029. notif->channel,
  2030. notif->band ? "bg" : "a",
  2031. le32_to_cpu(notif->tsf_high),
  2032. le32_to_cpu(notif->tsf_low),
  2033. le32_to_cpu(notif->statistics[0]),
  2034. le32_to_cpu(notif->tsf_low) - priv->scan_start_tsf,
  2035. jiffies_to_msecs(elapsed_jiffies
  2036. (priv->last_scan_jiffies, jiffies)));
  2037. priv->last_scan_jiffies = jiffies;
  2038. priv->next_scan_jiffies = 0;
  2039. }
  2040. /* Service SCAN_COMPLETE_NOTIFICATION (0x84) */
  2041. static void iwl3945_rx_scan_complete_notif(struct iwl_priv *priv,
  2042. struct iwl_rx_mem_buffer *rxb)
  2043. {
  2044. #ifdef CONFIG_IWLWIFI_DEBUG
  2045. struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
  2046. struct iwl_scancomplete_notification *scan_notif = (void *)pkt->u.raw;
  2047. #endif
  2048. IWL_DEBUG_SCAN("Scan complete: %d channels (TSF 0x%08X:%08X) - %d\n",
  2049. scan_notif->scanned_channels,
  2050. scan_notif->tsf_low,
  2051. scan_notif->tsf_high, scan_notif->status);
  2052. /* The HW is no longer scanning */
  2053. clear_bit(STATUS_SCAN_HW, &priv->status);
  2054. /* The scan completion notification came in, so kill that timer... */
  2055. cancel_delayed_work(&priv->scan_check);
  2056. IWL_DEBUG_INFO("Scan pass on %sGHz took %dms\n",
  2057. (priv->scan_bands & BIT(IEEE80211_BAND_2GHZ)) ?
  2058. "2.4" : "5.2",
  2059. jiffies_to_msecs(elapsed_jiffies
  2060. (priv->scan_pass_start, jiffies)));
  2061. /* Remove this scanned band from the list of pending
  2062. * bands to scan, band G precedes A in order of scanning
  2063. * as seen in iwl3945_bg_request_scan */
  2064. if (priv->scan_bands & BIT(IEEE80211_BAND_2GHZ))
  2065. priv->scan_bands &= ~BIT(IEEE80211_BAND_2GHZ);
  2066. else if (priv->scan_bands & BIT(IEEE80211_BAND_5GHZ))
  2067. priv->scan_bands &= ~BIT(IEEE80211_BAND_5GHZ);
  2068. /* If a request to abort was given, or the scan did not succeed
  2069. * then we reset the scan state machine and terminate,
  2070. * re-queuing another scan if one has been requested */
  2071. if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
  2072. IWL_DEBUG_INFO("Aborted scan completed.\n");
  2073. clear_bit(STATUS_SCAN_ABORTING, &priv->status);
  2074. } else {
  2075. /* If there are more bands on this scan pass reschedule */
  2076. if (priv->scan_bands > 0)
  2077. goto reschedule;
  2078. }
  2079. priv->last_scan_jiffies = jiffies;
  2080. priv->next_scan_jiffies = 0;
  2081. IWL_DEBUG_INFO("Setting scan to off\n");
  2082. clear_bit(STATUS_SCANNING, &priv->status);
  2083. IWL_DEBUG_INFO("Scan took %dms\n",
  2084. jiffies_to_msecs(elapsed_jiffies(priv->scan_start, jiffies)));
  2085. queue_work(priv->workqueue, &priv->scan_completed);
  2086. return;
  2087. reschedule:
  2088. priv->scan_pass_start = jiffies;
  2089. queue_work(priv->workqueue, &priv->request_scan);
  2090. }
  2091. /* Handle notification from uCode that card's power state is changing
  2092. * due to software, hardware, or critical temperature RFKILL */
  2093. static void iwl3945_rx_card_state_notif(struct iwl_priv *priv,
  2094. struct iwl_rx_mem_buffer *rxb)
  2095. {
  2096. struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
  2097. u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
  2098. unsigned long status = priv->status;
  2099. IWL_DEBUG_RF_KILL("Card state received: HW:%s SW:%s\n",
  2100. (flags & HW_CARD_DISABLED) ? "Kill" : "On",
  2101. (flags & SW_CARD_DISABLED) ? "Kill" : "On");
  2102. iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
  2103. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  2104. if (flags & HW_CARD_DISABLED)
  2105. set_bit(STATUS_RF_KILL_HW, &priv->status);
  2106. else
  2107. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  2108. if (flags & SW_CARD_DISABLED)
  2109. set_bit(STATUS_RF_KILL_SW, &priv->status);
  2110. else
  2111. clear_bit(STATUS_RF_KILL_SW, &priv->status);
  2112. iwl_scan_cancel(priv);
  2113. if ((test_bit(STATUS_RF_KILL_HW, &status) !=
  2114. test_bit(STATUS_RF_KILL_HW, &priv->status)) ||
  2115. (test_bit(STATUS_RF_KILL_SW, &status) !=
  2116. test_bit(STATUS_RF_KILL_SW, &priv->status)))
  2117. queue_work(priv->workqueue, &priv->rf_kill);
  2118. else
  2119. wake_up_interruptible(&priv->wait_command_queue);
  2120. }
  2121. /**
  2122. * iwl3945_setup_rx_handlers - Initialize Rx handler callbacks
  2123. *
  2124. * Setup the RX handlers for each of the reply types sent from the uCode
  2125. * to the host.
  2126. *
  2127. * This function chains into the hardware specific files for them to setup
  2128. * any hardware specific handlers as well.
  2129. */
  2130. static void iwl3945_setup_rx_handlers(struct iwl_priv *priv)
  2131. {
  2132. priv->rx_handlers[REPLY_ALIVE] = iwl3945_rx_reply_alive;
  2133. priv->rx_handlers[REPLY_ADD_STA] = iwl3945_rx_reply_add_sta;
  2134. priv->rx_handlers[REPLY_ERROR] = iwl3945_rx_reply_error;
  2135. priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl3945_rx_csa;
  2136. priv->rx_handlers[SPECTRUM_MEASURE_NOTIFICATION] =
  2137. iwl3945_rx_spectrum_measure_notif;
  2138. priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl3945_rx_pm_sleep_notif;
  2139. priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] =
  2140. iwl3945_rx_pm_debug_statistics_notif;
  2141. priv->rx_handlers[BEACON_NOTIFICATION] = iwl3945_rx_beacon_notif;
  2142. /*
  2143. * The same handler is used for both the REPLY to a discrete
  2144. * statistics request from the host as well as for the periodic
  2145. * statistics notifications (after received beacons) from the uCode.
  2146. */
  2147. priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl3945_hw_rx_statistics;
  2148. priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl3945_hw_rx_statistics;
  2149. priv->rx_handlers[REPLY_SCAN_CMD] = iwl3945_rx_reply_scan;
  2150. priv->rx_handlers[SCAN_START_NOTIFICATION] = iwl3945_rx_scan_start_notif;
  2151. priv->rx_handlers[SCAN_RESULTS_NOTIFICATION] =
  2152. iwl3945_rx_scan_results_notif;
  2153. priv->rx_handlers[SCAN_COMPLETE_NOTIFICATION] =
  2154. iwl3945_rx_scan_complete_notif;
  2155. priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl3945_rx_card_state_notif;
  2156. /* Set up hardware specific Rx handlers */
  2157. iwl3945_hw_rx_handler_setup(priv);
  2158. }
  2159. /**
  2160. * iwl3945_cmd_queue_reclaim - Reclaim CMD queue entries
  2161. * When FW advances 'R' index, all entries between old and new 'R' index
  2162. * need to be reclaimed.
  2163. */
  2164. static void iwl3945_cmd_queue_reclaim(struct iwl_priv *priv,
  2165. int txq_id, int index)
  2166. {
  2167. struct iwl_tx_queue *txq = &priv->txq[txq_id];
  2168. struct iwl_queue *q = &txq->q;
  2169. int nfreed = 0;
  2170. if ((index >= q->n_bd) || (iwl_queue_used(q, index) == 0)) {
  2171. IWL_ERR(priv, "Read index for DMA queue txq id (%d), index %d, "
  2172. "is out of range [0-%d] %d %d.\n", txq_id,
  2173. index, q->n_bd, q->write_ptr, q->read_ptr);
  2174. return;
  2175. }
  2176. for (index = iwl_queue_inc_wrap(index, q->n_bd); q->read_ptr != index;
  2177. q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
  2178. if (nfreed > 1) {
  2179. IWL_ERR(priv, "HCMD skipped: index (%d) %d %d\n", index,
  2180. q->write_ptr, q->read_ptr);
  2181. queue_work(priv->workqueue, &priv->restart);
  2182. break;
  2183. }
  2184. nfreed++;
  2185. }
  2186. }
  2187. /**
  2188. * iwl3945_tx_cmd_complete - Pull unused buffers off the queue and reclaim them
  2189. * @rxb: Rx buffer to reclaim
  2190. *
  2191. * If an Rx buffer has an async callback associated with it the callback
  2192. * will be executed. The attached skb (if present) will only be freed
  2193. * if the callback returns 1
  2194. */
  2195. static void iwl3945_tx_cmd_complete(struct iwl_priv *priv,
  2196. struct iwl_rx_mem_buffer *rxb)
  2197. {
  2198. struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
  2199. u16 sequence = le16_to_cpu(pkt->hdr.sequence);
  2200. int txq_id = SEQ_TO_QUEUE(sequence);
  2201. int index = SEQ_TO_INDEX(sequence);
  2202. int huge = !!(pkt->hdr.sequence & SEQ_HUGE_FRAME);
  2203. int cmd_index;
  2204. struct iwl_cmd *cmd;
  2205. if (WARN(txq_id != IWL_CMD_QUEUE_NUM,
  2206. "wrong command queue %d, sequence 0x%X readp=%d writep=%d\n",
  2207. txq_id, sequence,
  2208. priv->txq[IWL_CMD_QUEUE_NUM].q.read_ptr,
  2209. priv->txq[IWL_CMD_QUEUE_NUM].q.write_ptr)) {
  2210. iwl_print_hex_dump(priv, IWL_DL_INFO , rxb, 32);
  2211. return;
  2212. }
  2213. cmd_index = get_cmd_index(&priv->txq[IWL_CMD_QUEUE_NUM].q, index, huge);
  2214. cmd = priv->txq[IWL_CMD_QUEUE_NUM].cmd[cmd_index];
  2215. /* Input error checking is done when commands are added to queue. */
  2216. if (cmd->meta.flags & CMD_WANT_SKB) {
  2217. cmd->meta.source->u.skb = rxb->skb;
  2218. rxb->skb = NULL;
  2219. } else if (cmd->meta.u.callback &&
  2220. !cmd->meta.u.callback(priv, cmd, rxb->skb))
  2221. rxb->skb = NULL;
  2222. iwl3945_cmd_queue_reclaim(priv, txq_id, index);
  2223. if (!(cmd->meta.flags & CMD_ASYNC)) {
  2224. clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
  2225. wake_up_interruptible(&priv->wait_command_queue);
  2226. }
  2227. }
  2228. /************************** RX-FUNCTIONS ****************************/
  2229. /*
  2230. * Rx theory of operation
  2231. *
  2232. * The host allocates 32 DMA target addresses and passes the host address
  2233. * to the firmware at register IWL_RFDS_TABLE_LOWER + N * RFD_SIZE where N is
  2234. * 0 to 31
  2235. *
  2236. * Rx Queue Indexes
  2237. * The host/firmware share two index registers for managing the Rx buffers.
  2238. *
  2239. * The READ index maps to the first position that the firmware may be writing
  2240. * to -- the driver can read up to (but not including) this position and get
  2241. * good data.
  2242. * The READ index is managed by the firmware once the card is enabled.
  2243. *
  2244. * The WRITE index maps to the last position the driver has read from -- the
  2245. * position preceding WRITE is the last slot the firmware can place a packet.
  2246. *
  2247. * The queue is empty (no good data) if WRITE = READ - 1, and is full if
  2248. * WRITE = READ.
  2249. *
  2250. * During initialization, the host sets up the READ queue position to the first
  2251. * INDEX position, and WRITE to the last (READ - 1 wrapped)
  2252. *
  2253. * When the firmware places a packet in a buffer, it will advance the READ index
  2254. * and fire the RX interrupt. The driver can then query the READ index and
  2255. * process as many packets as possible, moving the WRITE index forward as it
  2256. * resets the Rx queue buffers with new memory.
  2257. *
  2258. * The management in the driver is as follows:
  2259. * + A list of pre-allocated SKBs is stored in iwl->rxq->rx_free. When
  2260. * iwl->rxq->free_count drops to or below RX_LOW_WATERMARK, work is scheduled
  2261. * to replenish the iwl->rxq->rx_free.
  2262. * + In iwl3945_rx_replenish (scheduled) if 'processed' != 'read' then the
  2263. * iwl->rxq is replenished and the READ INDEX is updated (updating the
  2264. * 'processed' and 'read' driver indexes as well)
  2265. * + A received packet is processed and handed to the kernel network stack,
  2266. * detached from the iwl->rxq. The driver 'processed' index is updated.
  2267. * + The Host/Firmware iwl->rxq is replenished at tasklet time from the rx_free
  2268. * list. If there are no allocated buffers in iwl->rxq->rx_free, the READ
  2269. * INDEX is not incremented and iwl->status(RX_STALLED) is set. If there
  2270. * were enough free buffers and RX_STALLED is set it is cleared.
  2271. *
  2272. *
  2273. * Driver sequence:
  2274. *
  2275. * iwl3945_rx_replenish() Replenishes rx_free list from rx_used, and calls
  2276. * iwl3945_rx_queue_restock
  2277. * iwl3945_rx_queue_restock() Moves available buffers from rx_free into Rx
  2278. * queue, updates firmware pointers, and updates
  2279. * the WRITE index. If insufficient rx_free buffers
  2280. * are available, schedules iwl3945_rx_replenish
  2281. *
  2282. * -- enable interrupts --
  2283. * ISR - iwl3945_rx() Detach iwl_rx_mem_buffers from pool up to the
  2284. * READ INDEX, detaching the SKB from the pool.
  2285. * Moves the packet buffer from queue to rx_used.
  2286. * Calls iwl3945_rx_queue_restock to refill any empty
  2287. * slots.
  2288. * ...
  2289. *
  2290. */
  2291. /**
  2292. * iwl3945_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
  2293. */
  2294. static inline __le32 iwl3945_dma_addr2rbd_ptr(struct iwl_priv *priv,
  2295. dma_addr_t dma_addr)
  2296. {
  2297. return cpu_to_le32((u32)dma_addr);
  2298. }
  2299. /**
  2300. * iwl3945_rx_queue_restock - refill RX queue from pre-allocated pool
  2301. *
  2302. * If there are slots in the RX queue that need to be restocked,
  2303. * and we have free pre-allocated buffers, fill the ranks as much
  2304. * as we can, pulling from rx_free.
  2305. *
  2306. * This moves the 'write' index forward to catch up with 'processed', and
  2307. * also updates the memory address in the firmware to reference the new
  2308. * target buffer.
  2309. */
  2310. static int iwl3945_rx_queue_restock(struct iwl_priv *priv)
  2311. {
  2312. struct iwl_rx_queue *rxq = &priv->rxq;
  2313. struct list_head *element;
  2314. struct iwl_rx_mem_buffer *rxb;
  2315. unsigned long flags;
  2316. int write, rc;
  2317. spin_lock_irqsave(&rxq->lock, flags);
  2318. write = rxq->write & ~0x7;
  2319. while ((iwl_rx_queue_space(rxq) > 0) && (rxq->free_count)) {
  2320. /* Get next free Rx buffer, remove from free list */
  2321. element = rxq->rx_free.next;
  2322. rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
  2323. list_del(element);
  2324. /* Point to Rx buffer via next RBD in circular buffer */
  2325. rxq->bd[rxq->write] = iwl3945_dma_addr2rbd_ptr(priv, rxb->real_dma_addr);
  2326. rxq->queue[rxq->write] = rxb;
  2327. rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
  2328. rxq->free_count--;
  2329. }
  2330. spin_unlock_irqrestore(&rxq->lock, flags);
  2331. /* If the pre-allocated buffer pool is dropping low, schedule to
  2332. * refill it */
  2333. if (rxq->free_count <= RX_LOW_WATERMARK)
  2334. queue_work(priv->workqueue, &priv->rx_replenish);
  2335. /* If we've added more space for the firmware to place data, tell it.
  2336. * Increment device's write pointer in multiples of 8. */
  2337. if ((write != (rxq->write & ~0x7))
  2338. || (abs(rxq->write - rxq->read) > 7)) {
  2339. spin_lock_irqsave(&rxq->lock, flags);
  2340. rxq->need_update = 1;
  2341. spin_unlock_irqrestore(&rxq->lock, flags);
  2342. rc = iwl_rx_queue_update_write_ptr(priv, rxq);
  2343. if (rc)
  2344. return rc;
  2345. }
  2346. return 0;
  2347. }
  2348. /**
  2349. * iwl3945_rx_replenish - Move all used packet from rx_used to rx_free
  2350. *
  2351. * When moving to rx_free an SKB is allocated for the slot.
  2352. *
  2353. * Also restock the Rx queue via iwl3945_rx_queue_restock.
  2354. * This is called as a scheduled work item (except for during initialization)
  2355. */
  2356. static void iwl3945_rx_allocate(struct iwl_priv *priv)
  2357. {
  2358. struct iwl_rx_queue *rxq = &priv->rxq;
  2359. struct list_head *element;
  2360. struct iwl_rx_mem_buffer *rxb;
  2361. unsigned long flags;
  2362. spin_lock_irqsave(&rxq->lock, flags);
  2363. while (!list_empty(&rxq->rx_used)) {
  2364. element = rxq->rx_used.next;
  2365. rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
  2366. /* Alloc a new receive buffer */
  2367. rxb->skb =
  2368. alloc_skb(priv->hw_params.rx_buf_size,
  2369. __GFP_NOWARN | GFP_ATOMIC);
  2370. if (!rxb->skb) {
  2371. if (net_ratelimit())
  2372. IWL_CRIT(priv, ": Can not allocate SKB buffers\n");
  2373. /* We don't reschedule replenish work here -- we will
  2374. * call the restock method and if it still needs
  2375. * more buffers it will schedule replenish */
  2376. break;
  2377. }
  2378. /* If radiotap head is required, reserve some headroom here.
  2379. * The physical head count is a variable rx_stats->phy_count.
  2380. * We reserve 4 bytes here. Plus these extra bytes, the
  2381. * headroom of the physical head should be enough for the
  2382. * radiotap head that iwl3945 supported. See iwl3945_rt.
  2383. */
  2384. skb_reserve(rxb->skb, 4);
  2385. priv->alloc_rxb_skb++;
  2386. list_del(element);
  2387. /* Get physical address of RB/SKB */
  2388. rxb->real_dma_addr = pci_map_single(priv->pci_dev,
  2389. rxb->skb->data,
  2390. priv->hw_params.rx_buf_size,
  2391. PCI_DMA_FROMDEVICE);
  2392. list_add_tail(&rxb->list, &rxq->rx_free);
  2393. rxq->free_count++;
  2394. }
  2395. spin_unlock_irqrestore(&rxq->lock, flags);
  2396. }
  2397. /*
  2398. * this should be called while priv->lock is locked
  2399. */
  2400. static void __iwl3945_rx_replenish(void *data)
  2401. {
  2402. struct iwl_priv *priv = data;
  2403. iwl3945_rx_allocate(priv);
  2404. iwl3945_rx_queue_restock(priv);
  2405. }
  2406. void iwl3945_rx_replenish(void *data)
  2407. {
  2408. struct iwl_priv *priv = data;
  2409. unsigned long flags;
  2410. iwl3945_rx_allocate(priv);
  2411. spin_lock_irqsave(&priv->lock, flags);
  2412. iwl3945_rx_queue_restock(priv);
  2413. spin_unlock_irqrestore(&priv->lock, flags);
  2414. }
  2415. /* Convert linear signal-to-noise ratio into dB */
  2416. static u8 ratio2dB[100] = {
  2417. /* 0 1 2 3 4 5 6 7 8 9 */
  2418. 0, 0, 6, 10, 12, 14, 16, 17, 18, 19, /* 00 - 09 */
  2419. 20, 21, 22, 22, 23, 23, 24, 25, 26, 26, /* 10 - 19 */
  2420. 26, 26, 26, 27, 27, 28, 28, 28, 29, 29, /* 20 - 29 */
  2421. 29, 30, 30, 30, 31, 31, 31, 31, 32, 32, /* 30 - 39 */
  2422. 32, 32, 32, 33, 33, 33, 33, 33, 34, 34, /* 40 - 49 */
  2423. 34, 34, 34, 34, 35, 35, 35, 35, 35, 35, /* 50 - 59 */
  2424. 36, 36, 36, 36, 36, 36, 36, 37, 37, 37, /* 60 - 69 */
  2425. 37, 37, 37, 37, 37, 38, 38, 38, 38, 38, /* 70 - 79 */
  2426. 38, 38, 38, 38, 38, 39, 39, 39, 39, 39, /* 80 - 89 */
  2427. 39, 39, 39, 39, 39, 40, 40, 40, 40, 40 /* 90 - 99 */
  2428. };
  2429. /* Calculates a relative dB value from a ratio of linear
  2430. * (i.e. not dB) signal levels.
  2431. * Conversion assumes that levels are voltages (20*log), not powers (10*log). */
  2432. int iwl3945_calc_db_from_ratio(int sig_ratio)
  2433. {
  2434. /* 1000:1 or higher just report as 60 dB */
  2435. if (sig_ratio >= 1000)
  2436. return 60;
  2437. /* 100:1 or higher, divide by 10 and use table,
  2438. * add 20 dB to make up for divide by 10 */
  2439. if (sig_ratio >= 100)
  2440. return 20 + (int)ratio2dB[sig_ratio/10];
  2441. /* We shouldn't see this */
  2442. if (sig_ratio < 1)
  2443. return 0;
  2444. /* Use table for ratios 1:1 - 99:1 */
  2445. return (int)ratio2dB[sig_ratio];
  2446. }
  2447. #define PERFECT_RSSI (-20) /* dBm */
  2448. #define WORST_RSSI (-95) /* dBm */
  2449. #define RSSI_RANGE (PERFECT_RSSI - WORST_RSSI)
  2450. /* Calculate an indication of rx signal quality (a percentage, not dBm!).
  2451. * See http://www.ces.clemson.edu/linux/signal_quality.shtml for info
  2452. * about formulas used below. */
  2453. int iwl3945_calc_sig_qual(int rssi_dbm, int noise_dbm)
  2454. {
  2455. int sig_qual;
  2456. int degradation = PERFECT_RSSI - rssi_dbm;
  2457. /* If we get a noise measurement, use signal-to-noise ratio (SNR)
  2458. * as indicator; formula is (signal dbm - noise dbm).
  2459. * SNR at or above 40 is a great signal (100%).
  2460. * Below that, scale to fit SNR of 0 - 40 dB within 0 - 100% indicator.
  2461. * Weakest usable signal is usually 10 - 15 dB SNR. */
  2462. if (noise_dbm) {
  2463. if (rssi_dbm - noise_dbm >= 40)
  2464. return 100;
  2465. else if (rssi_dbm < noise_dbm)
  2466. return 0;
  2467. sig_qual = ((rssi_dbm - noise_dbm) * 5) / 2;
  2468. /* Else use just the signal level.
  2469. * This formula is a least squares fit of data points collected and
  2470. * compared with a reference system that had a percentage (%) display
  2471. * for signal quality. */
  2472. } else
  2473. sig_qual = (100 * (RSSI_RANGE * RSSI_RANGE) - degradation *
  2474. (15 * RSSI_RANGE + 62 * degradation)) /
  2475. (RSSI_RANGE * RSSI_RANGE);
  2476. if (sig_qual > 100)
  2477. sig_qual = 100;
  2478. else if (sig_qual < 1)
  2479. sig_qual = 0;
  2480. return sig_qual;
  2481. }
  2482. /**
  2483. * iwl3945_rx_handle - Main entry function for receiving responses from uCode
  2484. *
  2485. * Uses the priv->rx_handlers callback function array to invoke
  2486. * the appropriate handlers, including command responses,
  2487. * frame-received notifications, and other notifications.
  2488. */
  2489. static void iwl3945_rx_handle(struct iwl_priv *priv)
  2490. {
  2491. struct iwl_rx_mem_buffer *rxb;
  2492. struct iwl_rx_packet *pkt;
  2493. struct iwl_rx_queue *rxq = &priv->rxq;
  2494. u32 r, i;
  2495. int reclaim;
  2496. unsigned long flags;
  2497. u8 fill_rx = 0;
  2498. u32 count = 8;
  2499. /* uCode's read index (stored in shared DRAM) indicates the last Rx
  2500. * buffer that the driver may process (last buffer filled by ucode). */
  2501. r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF;
  2502. i = rxq->read;
  2503. if (iwl_rx_queue_space(rxq) > (RX_QUEUE_SIZE / 2))
  2504. fill_rx = 1;
  2505. /* Rx interrupt, but nothing sent from uCode */
  2506. if (i == r)
  2507. IWL_DEBUG(IWL_DL_RX | IWL_DL_ISR, "r = %d, i = %d\n", r, i);
  2508. while (i != r) {
  2509. rxb = rxq->queue[i];
  2510. /* If an RXB doesn't have a Rx queue slot associated with it,
  2511. * then a bug has been introduced in the queue refilling
  2512. * routines -- catch it here */
  2513. BUG_ON(rxb == NULL);
  2514. rxq->queue[i] = NULL;
  2515. pci_dma_sync_single_for_cpu(priv->pci_dev, rxb->real_dma_addr,
  2516. priv->hw_params.rx_buf_size,
  2517. PCI_DMA_FROMDEVICE);
  2518. pkt = (struct iwl_rx_packet *)rxb->skb->data;
  2519. /* Reclaim a command buffer only if this packet is a response
  2520. * to a (driver-originated) command.
  2521. * If the packet (e.g. Rx frame) originated from uCode,
  2522. * there is no command buffer to reclaim.
  2523. * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
  2524. * but apparently a few don't get set; catch them here. */
  2525. reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
  2526. (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
  2527. (pkt->hdr.cmd != REPLY_TX);
  2528. /* Based on type of command response or notification,
  2529. * handle those that need handling via function in
  2530. * rx_handlers table. See iwl3945_setup_rx_handlers() */
  2531. if (priv->rx_handlers[pkt->hdr.cmd]) {
  2532. IWL_DEBUG(IWL_DL_HCMD | IWL_DL_RX | IWL_DL_ISR,
  2533. "r = %d, i = %d, %s, 0x%02x\n", r, i,
  2534. get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
  2535. priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
  2536. } else {
  2537. /* No handling needed */
  2538. IWL_DEBUG(IWL_DL_HCMD | IWL_DL_RX | IWL_DL_ISR,
  2539. "r %d i %d No handler needed for %s, 0x%02x\n",
  2540. r, i, get_cmd_string(pkt->hdr.cmd),
  2541. pkt->hdr.cmd);
  2542. }
  2543. if (reclaim) {
  2544. /* Invoke any callbacks, transfer the skb to caller, and
  2545. * fire off the (possibly) blocking iwl_send_cmd()
  2546. * as we reclaim the driver command queue */
  2547. if (rxb && rxb->skb)
  2548. iwl3945_tx_cmd_complete(priv, rxb);
  2549. else
  2550. IWL_WARN(priv, "Claim null rxb?\n");
  2551. }
  2552. /* For now we just don't re-use anything. We can tweak this
  2553. * later to try and re-use notification packets and SKBs that
  2554. * fail to Rx correctly */
  2555. if (rxb->skb != NULL) {
  2556. priv->alloc_rxb_skb--;
  2557. dev_kfree_skb_any(rxb->skb);
  2558. rxb->skb = NULL;
  2559. }
  2560. pci_unmap_single(priv->pci_dev, rxb->real_dma_addr,
  2561. priv->hw_params.rx_buf_size,
  2562. PCI_DMA_FROMDEVICE);
  2563. spin_lock_irqsave(&rxq->lock, flags);
  2564. list_add_tail(&rxb->list, &priv->rxq.rx_used);
  2565. spin_unlock_irqrestore(&rxq->lock, flags);
  2566. i = (i + 1) & RX_QUEUE_MASK;
  2567. /* If there are a lot of unused frames,
  2568. * restock the Rx queue so ucode won't assert. */
  2569. if (fill_rx) {
  2570. count++;
  2571. if (count >= 8) {
  2572. priv->rxq.read = i;
  2573. __iwl3945_rx_replenish(priv);
  2574. count = 0;
  2575. }
  2576. }
  2577. }
  2578. /* Backtrack one entry */
  2579. priv->rxq.read = i;
  2580. iwl3945_rx_queue_restock(priv);
  2581. }
  2582. #ifdef CONFIG_IWL3945_DEBUG
  2583. static void iwl3945_print_rx_config_cmd(struct iwl_priv *priv,
  2584. struct iwl3945_rxon_cmd *rxon)
  2585. {
  2586. IWL_DEBUG_RADIO("RX CONFIG:\n");
  2587. iwl_print_hex_dump(priv, IWL_DL_RADIO, (u8 *) rxon, sizeof(*rxon));
  2588. IWL_DEBUG_RADIO("u16 channel: 0x%x\n", le16_to_cpu(rxon->channel));
  2589. IWL_DEBUG_RADIO("u32 flags: 0x%08X\n", le32_to_cpu(rxon->flags));
  2590. IWL_DEBUG_RADIO("u32 filter_flags: 0x%08x\n",
  2591. le32_to_cpu(rxon->filter_flags));
  2592. IWL_DEBUG_RADIO("u8 dev_type: 0x%x\n", rxon->dev_type);
  2593. IWL_DEBUG_RADIO("u8 ofdm_basic_rates: 0x%02x\n",
  2594. rxon->ofdm_basic_rates);
  2595. IWL_DEBUG_RADIO("u8 cck_basic_rates: 0x%02x\n", rxon->cck_basic_rates);
  2596. IWL_DEBUG_RADIO("u8[6] node_addr: %pM\n", rxon->node_addr);
  2597. IWL_DEBUG_RADIO("u8[6] bssid_addr: %pM\n", rxon->bssid_addr);
  2598. IWL_DEBUG_RADIO("u16 assoc_id: 0x%x\n", le16_to_cpu(rxon->assoc_id));
  2599. }
  2600. #endif
  2601. static void iwl3945_enable_interrupts(struct iwl_priv *priv)
  2602. {
  2603. IWL_DEBUG_ISR("Enabling interrupts\n");
  2604. set_bit(STATUS_INT_ENABLED, &priv->status);
  2605. iwl_write32(priv, CSR_INT_MASK, CSR_INI_SET_MASK);
  2606. }
  2607. /* call this function to flush any scheduled tasklet */
  2608. static inline void iwl_synchronize_irq(struct iwl_priv *priv)
  2609. {
  2610. /* wait to make sure we flush pending tasklet*/
  2611. synchronize_irq(priv->pci_dev->irq);
  2612. tasklet_kill(&priv->irq_tasklet);
  2613. }
  2614. static inline void iwl3945_disable_interrupts(struct iwl_priv *priv)
  2615. {
  2616. clear_bit(STATUS_INT_ENABLED, &priv->status);
  2617. /* disable interrupts from uCode/NIC to host */
  2618. iwl_write32(priv, CSR_INT_MASK, 0x00000000);
  2619. /* acknowledge/clear/reset any interrupts still pending
  2620. * from uCode or flow handler (Rx/Tx DMA) */
  2621. iwl_write32(priv, CSR_INT, 0xffffffff);
  2622. iwl_write32(priv, CSR_FH_INT_STATUS, 0xffffffff);
  2623. IWL_DEBUG_ISR("Disabled interrupts\n");
  2624. }
  2625. static const char *desc_lookup(int i)
  2626. {
  2627. switch (i) {
  2628. case 1:
  2629. return "FAIL";
  2630. case 2:
  2631. return "BAD_PARAM";
  2632. case 3:
  2633. return "BAD_CHECKSUM";
  2634. case 4:
  2635. return "NMI_INTERRUPT";
  2636. case 5:
  2637. return "SYSASSERT";
  2638. case 6:
  2639. return "FATAL_ERROR";
  2640. }
  2641. return "UNKNOWN";
  2642. }
  2643. #define ERROR_START_OFFSET (1 * sizeof(u32))
  2644. #define ERROR_ELEM_SIZE (7 * sizeof(u32))
  2645. static void iwl3945_dump_nic_error_log(struct iwl_priv *priv)
  2646. {
  2647. u32 i;
  2648. u32 desc, time, count, base, data1;
  2649. u32 blink1, blink2, ilink1, ilink2;
  2650. int rc;
  2651. base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
  2652. if (!iwl3945_hw_valid_rtc_data_addr(base)) {
  2653. IWL_ERR(priv, "Not valid error log pointer 0x%08X\n", base);
  2654. return;
  2655. }
  2656. rc = iwl_grab_nic_access(priv);
  2657. if (rc) {
  2658. IWL_WARN(priv, "Can not read from adapter at this time.\n");
  2659. return;
  2660. }
  2661. count = iwl_read_targ_mem(priv, base);
  2662. if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
  2663. IWL_ERR(priv, "Start IWL Error Log Dump:\n");
  2664. IWL_ERR(priv, "Status: 0x%08lX, count: %d\n",
  2665. priv->status, count);
  2666. }
  2667. IWL_ERR(priv, "Desc Time asrtPC blink2 "
  2668. "ilink1 nmiPC Line\n");
  2669. for (i = ERROR_START_OFFSET;
  2670. i < (count * ERROR_ELEM_SIZE) + ERROR_START_OFFSET;
  2671. i += ERROR_ELEM_SIZE) {
  2672. desc = iwl_read_targ_mem(priv, base + i);
  2673. time =
  2674. iwl_read_targ_mem(priv, base + i + 1 * sizeof(u32));
  2675. blink1 =
  2676. iwl_read_targ_mem(priv, base + i + 2 * sizeof(u32));
  2677. blink2 =
  2678. iwl_read_targ_mem(priv, base + i + 3 * sizeof(u32));
  2679. ilink1 =
  2680. iwl_read_targ_mem(priv, base + i + 4 * sizeof(u32));
  2681. ilink2 =
  2682. iwl_read_targ_mem(priv, base + i + 5 * sizeof(u32));
  2683. data1 =
  2684. iwl_read_targ_mem(priv, base + i + 6 * sizeof(u32));
  2685. IWL_ERR(priv,
  2686. "%-13s (#%d) %010u 0x%05X 0x%05X 0x%05X 0x%05X %u\n\n",
  2687. desc_lookup(desc), desc, time, blink1, blink2,
  2688. ilink1, ilink2, data1);
  2689. }
  2690. iwl_release_nic_access(priv);
  2691. }
  2692. #define EVENT_START_OFFSET (6 * sizeof(u32))
  2693. /**
  2694. * iwl3945_print_event_log - Dump error event log to syslog
  2695. *
  2696. * NOTE: Must be called with iwl_grab_nic_access() already obtained!
  2697. */
  2698. static void iwl3945_print_event_log(struct iwl_priv *priv, u32 start_idx,
  2699. u32 num_events, u32 mode)
  2700. {
  2701. u32 i;
  2702. u32 base; /* SRAM byte address of event log header */
  2703. u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
  2704. u32 ptr; /* SRAM byte address of log data */
  2705. u32 ev, time, data; /* event log data */
  2706. if (num_events == 0)
  2707. return;
  2708. base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
  2709. if (mode == 0)
  2710. event_size = 2 * sizeof(u32);
  2711. else
  2712. event_size = 3 * sizeof(u32);
  2713. ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
  2714. /* "time" is actually "data" for mode 0 (no timestamp).
  2715. * place event id # at far right for easier visual parsing. */
  2716. for (i = 0; i < num_events; i++) {
  2717. ev = iwl_read_targ_mem(priv, ptr);
  2718. ptr += sizeof(u32);
  2719. time = iwl_read_targ_mem(priv, ptr);
  2720. ptr += sizeof(u32);
  2721. if (mode == 0) {
  2722. /* data, ev */
  2723. IWL_ERR(priv, "0x%08x\t%04u\n", time, ev);
  2724. } else {
  2725. data = iwl_read_targ_mem(priv, ptr);
  2726. ptr += sizeof(u32);
  2727. IWL_ERR(priv, "%010u\t0x%08x\t%04u\n", time, data, ev);
  2728. }
  2729. }
  2730. }
  2731. static void iwl3945_dump_nic_event_log(struct iwl_priv *priv)
  2732. {
  2733. int rc;
  2734. u32 base; /* SRAM byte address of event log header */
  2735. u32 capacity; /* event log capacity in # entries */
  2736. u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
  2737. u32 num_wraps; /* # times uCode wrapped to top of log */
  2738. u32 next_entry; /* index of next entry to be written by uCode */
  2739. u32 size; /* # entries that we'll print */
  2740. base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
  2741. if (!iwl3945_hw_valid_rtc_data_addr(base)) {
  2742. IWL_ERR(priv, "Invalid event log pointer 0x%08X\n", base);
  2743. return;
  2744. }
  2745. rc = iwl_grab_nic_access(priv);
  2746. if (rc) {
  2747. IWL_WARN(priv, "Can not read from adapter at this time.\n");
  2748. return;
  2749. }
  2750. /* event log header */
  2751. capacity = iwl_read_targ_mem(priv, base);
  2752. mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
  2753. num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
  2754. next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
  2755. size = num_wraps ? capacity : next_entry;
  2756. /* bail out if nothing in log */
  2757. if (size == 0) {
  2758. IWL_ERR(priv, "Start IWL Event Log Dump: nothing in log\n");
  2759. iwl_release_nic_access(priv);
  2760. return;
  2761. }
  2762. IWL_ERR(priv, "Start IWL Event Log Dump: display count %d, wraps %d\n",
  2763. size, num_wraps);
  2764. /* if uCode has wrapped back to top of log, start at the oldest entry,
  2765. * i.e the next one that uCode would fill. */
  2766. if (num_wraps)
  2767. iwl3945_print_event_log(priv, next_entry,
  2768. capacity - next_entry, mode);
  2769. /* (then/else) start at top of log */
  2770. iwl3945_print_event_log(priv, 0, next_entry, mode);
  2771. iwl_release_nic_access(priv);
  2772. }
  2773. /**
  2774. * iwl3945_irq_handle_error - called for HW or SW error interrupt from card
  2775. */
  2776. static void iwl3945_irq_handle_error(struct iwl_priv *priv)
  2777. {
  2778. /* Set the FW error flag -- cleared on iwl3945_down */
  2779. set_bit(STATUS_FW_ERROR, &priv->status);
  2780. /* Cancel currently queued command. */
  2781. clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
  2782. #ifdef CONFIG_IWL3945_DEBUG
  2783. if (priv->debug_level & IWL_DL_FW_ERRORS) {
  2784. iwl3945_dump_nic_error_log(priv);
  2785. iwl3945_dump_nic_event_log(priv);
  2786. iwl3945_print_rx_config_cmd(priv, &priv->staging39_rxon);
  2787. }
  2788. #endif
  2789. wake_up_interruptible(&priv->wait_command_queue);
  2790. /* Keep the restart process from trying to send host
  2791. * commands by clearing the INIT status bit */
  2792. clear_bit(STATUS_READY, &priv->status);
  2793. if (!test_bit(STATUS_EXIT_PENDING, &priv->status)) {
  2794. IWL_DEBUG(IWL_DL_INFO | IWL_DL_FW_ERRORS,
  2795. "Restarting adapter due to uCode error.\n");
  2796. if (iwl3945_is_associated(priv)) {
  2797. memcpy(&priv->recovery39_rxon, &priv->active39_rxon,
  2798. sizeof(priv->recovery39_rxon));
  2799. priv->error_recovering = 1;
  2800. }
  2801. queue_work(priv->workqueue, &priv->restart);
  2802. }
  2803. }
  2804. static void iwl3945_error_recovery(struct iwl_priv *priv)
  2805. {
  2806. unsigned long flags;
  2807. memcpy(&priv->staging39_rxon, &priv->recovery39_rxon,
  2808. sizeof(priv->staging39_rxon));
  2809. priv->staging39_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  2810. iwl3945_commit_rxon(priv);
  2811. iwl3945_add_station(priv, priv->bssid, 1, 0);
  2812. spin_lock_irqsave(&priv->lock, flags);
  2813. priv->assoc_id = le16_to_cpu(priv->staging39_rxon.assoc_id);
  2814. priv->error_recovering = 0;
  2815. spin_unlock_irqrestore(&priv->lock, flags);
  2816. }
  2817. static void iwl3945_irq_tasklet(struct iwl_priv *priv)
  2818. {
  2819. u32 inta, handled = 0;
  2820. u32 inta_fh;
  2821. unsigned long flags;
  2822. #ifdef CONFIG_IWL3945_DEBUG
  2823. u32 inta_mask;
  2824. #endif
  2825. spin_lock_irqsave(&priv->lock, flags);
  2826. /* Ack/clear/reset pending uCode interrupts.
  2827. * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
  2828. * and will clear only when CSR_FH_INT_STATUS gets cleared. */
  2829. inta = iwl_read32(priv, CSR_INT);
  2830. iwl_write32(priv, CSR_INT, inta);
  2831. /* Ack/clear/reset pending flow-handler (DMA) interrupts.
  2832. * Any new interrupts that happen after this, either while we're
  2833. * in this tasklet, or later, will show up in next ISR/tasklet. */
  2834. inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
  2835. iwl_write32(priv, CSR_FH_INT_STATUS, inta_fh);
  2836. #ifdef CONFIG_IWL3945_DEBUG
  2837. if (priv->debug_level & IWL_DL_ISR) {
  2838. /* just for debug */
  2839. inta_mask = iwl_read32(priv, CSR_INT_MASK);
  2840. IWL_DEBUG_ISR("inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
  2841. inta, inta_mask, inta_fh);
  2842. }
  2843. #endif
  2844. /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
  2845. * atomic, make sure that inta covers all the interrupts that
  2846. * we've discovered, even if FH interrupt came in just after
  2847. * reading CSR_INT. */
  2848. if (inta_fh & CSR39_FH_INT_RX_MASK)
  2849. inta |= CSR_INT_BIT_FH_RX;
  2850. if (inta_fh & CSR39_FH_INT_TX_MASK)
  2851. inta |= CSR_INT_BIT_FH_TX;
  2852. /* Now service all interrupt bits discovered above. */
  2853. if (inta & CSR_INT_BIT_HW_ERR) {
  2854. IWL_ERR(priv, "Microcode HW error detected. Restarting.\n");
  2855. /* Tell the device to stop sending interrupts */
  2856. iwl3945_disable_interrupts(priv);
  2857. iwl3945_irq_handle_error(priv);
  2858. handled |= CSR_INT_BIT_HW_ERR;
  2859. spin_unlock_irqrestore(&priv->lock, flags);
  2860. return;
  2861. }
  2862. #ifdef CONFIG_IWL3945_DEBUG
  2863. if (priv->debug_level & (IWL_DL_ISR)) {
  2864. /* NIC fires this, but we don't use it, redundant with WAKEUP */
  2865. if (inta & CSR_INT_BIT_SCD)
  2866. IWL_DEBUG_ISR("Scheduler finished to transmit "
  2867. "the frame/frames.\n");
  2868. /* Alive notification via Rx interrupt will do the real work */
  2869. if (inta & CSR_INT_BIT_ALIVE)
  2870. IWL_DEBUG_ISR("Alive interrupt\n");
  2871. }
  2872. #endif
  2873. /* Safely ignore these bits for debug checks below */
  2874. inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
  2875. /* Error detected by uCode */
  2876. if (inta & CSR_INT_BIT_SW_ERR) {
  2877. IWL_ERR(priv, "Microcode SW error detected. "
  2878. "Restarting 0x%X.\n", inta);
  2879. iwl3945_irq_handle_error(priv);
  2880. handled |= CSR_INT_BIT_SW_ERR;
  2881. }
  2882. /* uCode wakes up after power-down sleep */
  2883. if (inta & CSR_INT_BIT_WAKEUP) {
  2884. IWL_DEBUG_ISR("Wakeup interrupt\n");
  2885. iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
  2886. iwl_txq_update_write_ptr(priv, &priv->txq[0]);
  2887. iwl_txq_update_write_ptr(priv, &priv->txq[1]);
  2888. iwl_txq_update_write_ptr(priv, &priv->txq[2]);
  2889. iwl_txq_update_write_ptr(priv, &priv->txq[3]);
  2890. iwl_txq_update_write_ptr(priv, &priv->txq[4]);
  2891. iwl_txq_update_write_ptr(priv, &priv->txq[5]);
  2892. handled |= CSR_INT_BIT_WAKEUP;
  2893. }
  2894. /* All uCode command responses, including Tx command responses,
  2895. * Rx "responses" (frame-received notification), and other
  2896. * notifications from uCode come through here*/
  2897. if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
  2898. iwl3945_rx_handle(priv);
  2899. handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
  2900. }
  2901. if (inta & CSR_INT_BIT_FH_TX) {
  2902. IWL_DEBUG_ISR("Tx interrupt\n");
  2903. iwl_write32(priv, CSR_FH_INT_STATUS, (1 << 6));
  2904. if (!iwl_grab_nic_access(priv)) {
  2905. iwl_write_direct32(priv, FH39_TCSR_CREDIT
  2906. (FH39_SRVC_CHNL), 0x0);
  2907. iwl_release_nic_access(priv);
  2908. }
  2909. handled |= CSR_INT_BIT_FH_TX;
  2910. }
  2911. if (inta & ~handled)
  2912. IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
  2913. if (inta & ~CSR_INI_SET_MASK) {
  2914. IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
  2915. inta & ~CSR_INI_SET_MASK);
  2916. IWL_WARN(priv, " with FH_INT = 0x%08x\n", inta_fh);
  2917. }
  2918. /* Re-enable all interrupts */
  2919. /* only Re-enable if disabled by irq */
  2920. if (test_bit(STATUS_INT_ENABLED, &priv->status))
  2921. iwl3945_enable_interrupts(priv);
  2922. #ifdef CONFIG_IWL3945_DEBUG
  2923. if (priv->debug_level & (IWL_DL_ISR)) {
  2924. inta = iwl_read32(priv, CSR_INT);
  2925. inta_mask = iwl_read32(priv, CSR_INT_MASK);
  2926. inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
  2927. IWL_DEBUG_ISR("End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
  2928. "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
  2929. }
  2930. #endif
  2931. spin_unlock_irqrestore(&priv->lock, flags);
  2932. }
  2933. static irqreturn_t iwl3945_isr(int irq, void *data)
  2934. {
  2935. struct iwl_priv *priv = data;
  2936. u32 inta, inta_mask;
  2937. u32 inta_fh;
  2938. if (!priv)
  2939. return IRQ_NONE;
  2940. spin_lock(&priv->lock);
  2941. /* Disable (but don't clear!) interrupts here to avoid
  2942. * back-to-back ISRs and sporadic interrupts from our NIC.
  2943. * If we have something to service, the tasklet will re-enable ints.
  2944. * If we *don't* have something, we'll re-enable before leaving here. */
  2945. inta_mask = iwl_read32(priv, CSR_INT_MASK); /* just for debug */
  2946. iwl_write32(priv, CSR_INT_MASK, 0x00000000);
  2947. /* Discover which interrupts are active/pending */
  2948. inta = iwl_read32(priv, CSR_INT);
  2949. inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
  2950. /* Ignore interrupt if there's nothing in NIC to service.
  2951. * This may be due to IRQ shared with another device,
  2952. * or due to sporadic interrupts thrown from our NIC. */
  2953. if (!inta && !inta_fh) {
  2954. IWL_DEBUG_ISR("Ignore interrupt, inta == 0, inta_fh == 0\n");
  2955. goto none;
  2956. }
  2957. if ((inta == 0xFFFFFFFF) || ((inta & 0xFFFFFFF0) == 0xa5a5a5a0)) {
  2958. /* Hardware disappeared */
  2959. IWL_WARN(priv, "HARDWARE GONE?? INTA == 0x%08x\n", inta);
  2960. goto unplugged;
  2961. }
  2962. IWL_DEBUG_ISR("ISR inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
  2963. inta, inta_mask, inta_fh);
  2964. inta &= ~CSR_INT_BIT_SCD;
  2965. /* iwl3945_irq_tasklet() will service interrupts and re-enable them */
  2966. if (likely(inta || inta_fh))
  2967. tasklet_schedule(&priv->irq_tasklet);
  2968. unplugged:
  2969. spin_unlock(&priv->lock);
  2970. return IRQ_HANDLED;
  2971. none:
  2972. /* re-enable interrupts here since we don't have anything to service. */
  2973. /* only Re-enable if disabled by irq */
  2974. if (test_bit(STATUS_INT_ENABLED, &priv->status))
  2975. iwl3945_enable_interrupts(priv);
  2976. spin_unlock(&priv->lock);
  2977. return IRQ_NONE;
  2978. }
  2979. /************************** EEPROM BANDS ****************************
  2980. *
  2981. * The iwl3945_eeprom_band definitions below provide the mapping from the
  2982. * EEPROM contents to the specific channel number supported for each
  2983. * band.
  2984. *
  2985. * For example, iwl3945_priv->eeprom39.band_3_channels[4] from the band_3
  2986. * definition below maps to physical channel 42 in the 5.2GHz spectrum.
  2987. * The specific geography and calibration information for that channel
  2988. * is contained in the eeprom map itself.
  2989. *
  2990. * During init, we copy the eeprom information and channel map
  2991. * information into priv->channel_info_24/52 and priv->channel_map_24/52
  2992. *
  2993. * channel_map_24/52 provides the index in the channel_info array for a
  2994. * given channel. We have to have two separate maps as there is channel
  2995. * overlap with the 2.4GHz and 5.2GHz spectrum as seen in band_1 and
  2996. * band_2
  2997. *
  2998. * A value of 0xff stored in the channel_map indicates that the channel
  2999. * is not supported by the hardware at all.
  3000. *
  3001. * A value of 0xfe in the channel_map indicates that the channel is not
  3002. * valid for Tx with the current hardware. This means that
  3003. * while the system can tune and receive on a given channel, it may not
  3004. * be able to associate or transmit any frames on that
  3005. * channel. There is no corresponding channel information for that
  3006. * entry.
  3007. *
  3008. *********************************************************************/
  3009. /* 2.4 GHz */
  3010. static const u8 iwl3945_eeprom_band_1[14] = {
  3011. 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14
  3012. };
  3013. /* 5.2 GHz bands */
  3014. static const u8 iwl3945_eeprom_band_2[] = { /* 4915-5080MHz */
  3015. 183, 184, 185, 187, 188, 189, 192, 196, 7, 8, 11, 12, 16
  3016. };
  3017. static const u8 iwl3945_eeprom_band_3[] = { /* 5170-5320MHz */
  3018. 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64
  3019. };
  3020. static const u8 iwl3945_eeprom_band_4[] = { /* 5500-5700MHz */
  3021. 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140
  3022. };
  3023. static const u8 iwl3945_eeprom_band_5[] = { /* 5725-5825MHz */
  3024. 145, 149, 153, 157, 161, 165
  3025. };
  3026. static void iwl3945_init_band_reference(const struct iwl_priv *priv, int band,
  3027. int *eeprom_ch_count,
  3028. const struct iwl_eeprom_channel
  3029. **eeprom_ch_info,
  3030. const u8 **eeprom_ch_index)
  3031. {
  3032. switch (band) {
  3033. case 1: /* 2.4GHz band */
  3034. *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_1);
  3035. *eeprom_ch_info = priv->eeprom39.band_1_channels;
  3036. *eeprom_ch_index = iwl3945_eeprom_band_1;
  3037. break;
  3038. case 2: /* 4.9GHz band */
  3039. *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_2);
  3040. *eeprom_ch_info = priv->eeprom39.band_2_channels;
  3041. *eeprom_ch_index = iwl3945_eeprom_band_2;
  3042. break;
  3043. case 3: /* 5.2GHz band */
  3044. *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_3);
  3045. *eeprom_ch_info = priv->eeprom39.band_3_channels;
  3046. *eeprom_ch_index = iwl3945_eeprom_band_3;
  3047. break;
  3048. case 4: /* 5.5GHz band */
  3049. *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_4);
  3050. *eeprom_ch_info = priv->eeprom39.band_4_channels;
  3051. *eeprom_ch_index = iwl3945_eeprom_band_4;
  3052. break;
  3053. case 5: /* 5.7GHz band */
  3054. *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_5);
  3055. *eeprom_ch_info = priv->eeprom39.band_5_channels;
  3056. *eeprom_ch_index = iwl3945_eeprom_band_5;
  3057. break;
  3058. default:
  3059. BUG();
  3060. return;
  3061. }
  3062. }
  3063. /**
  3064. * iwl3945_get_channel_info - Find driver's private channel info
  3065. *
  3066. * Based on band and channel number.
  3067. */
  3068. const struct iwl_channel_info *
  3069. iwl3945_get_channel_info(const struct iwl_priv *priv,
  3070. enum ieee80211_band band, u16 channel)
  3071. {
  3072. int i;
  3073. switch (band) {
  3074. case IEEE80211_BAND_5GHZ:
  3075. for (i = 14; i < priv->channel_count; i++) {
  3076. if (priv->channel_info[i].channel == channel)
  3077. return &priv->channel_info[i];
  3078. }
  3079. break;
  3080. case IEEE80211_BAND_2GHZ:
  3081. if (channel >= 1 && channel <= 14)
  3082. return &priv->channel_info[channel - 1];
  3083. break;
  3084. case IEEE80211_NUM_BANDS:
  3085. WARN_ON(1);
  3086. }
  3087. return NULL;
  3088. }
  3089. #define CHECK_AND_PRINT(x) ((eeprom_ch_info[ch].flags & EEPROM_CHANNEL_##x) \
  3090. ? # x " " : "")
  3091. /**
  3092. * iwl3945_init_channel_map - Set up driver's info for all possible channels
  3093. */
  3094. static int iwl3945_init_channel_map(struct iwl_priv *priv)
  3095. {
  3096. int eeprom_ch_count = 0;
  3097. const u8 *eeprom_ch_index = NULL;
  3098. const struct iwl_eeprom_channel *eeprom_ch_info = NULL;
  3099. int band, ch;
  3100. struct iwl_channel_info *ch_info;
  3101. if (priv->channel_count) {
  3102. IWL_DEBUG_INFO("Channel map already initialized.\n");
  3103. return 0;
  3104. }
  3105. if (priv->eeprom39.version < 0x2f) {
  3106. IWL_WARN(priv, "Unsupported EEPROM version: 0x%04X\n",
  3107. priv->eeprom39.version);
  3108. return -EINVAL;
  3109. }
  3110. IWL_DEBUG_INFO("Initializing regulatory info from EEPROM\n");
  3111. priv->channel_count =
  3112. ARRAY_SIZE(iwl3945_eeprom_band_1) +
  3113. ARRAY_SIZE(iwl3945_eeprom_band_2) +
  3114. ARRAY_SIZE(iwl3945_eeprom_band_3) +
  3115. ARRAY_SIZE(iwl3945_eeprom_band_4) +
  3116. ARRAY_SIZE(iwl3945_eeprom_band_5);
  3117. IWL_DEBUG_INFO("Parsing data for %d channels.\n", priv->channel_count);
  3118. priv->channel_info = kzalloc(sizeof(struct iwl_channel_info) *
  3119. priv->channel_count, GFP_KERNEL);
  3120. if (!priv->channel_info) {
  3121. IWL_ERR(priv, "Could not allocate channel_info\n");
  3122. priv->channel_count = 0;
  3123. return -ENOMEM;
  3124. }
  3125. ch_info = priv->channel_info;
  3126. /* Loop through the 5 EEPROM bands adding them in order to the
  3127. * channel map we maintain (that contains additional information than
  3128. * what just in the EEPROM) */
  3129. for (band = 1; band <= 5; band++) {
  3130. iwl3945_init_band_reference(priv, band, &eeprom_ch_count,
  3131. &eeprom_ch_info, &eeprom_ch_index);
  3132. /* Loop through each band adding each of the channels */
  3133. for (ch = 0; ch < eeprom_ch_count; ch++) {
  3134. ch_info->channel = eeprom_ch_index[ch];
  3135. ch_info->band = (band == 1) ? IEEE80211_BAND_2GHZ :
  3136. IEEE80211_BAND_5GHZ;
  3137. /* permanently store EEPROM's channel regulatory flags
  3138. * and max power in channel info database. */
  3139. ch_info->eeprom = eeprom_ch_info[ch];
  3140. /* Copy the run-time flags so they are there even on
  3141. * invalid channels */
  3142. ch_info->flags = eeprom_ch_info[ch].flags;
  3143. if (!(is_channel_valid(ch_info))) {
  3144. IWL_DEBUG_INFO("Ch. %d Flags %x [%sGHz] - "
  3145. "No traffic\n",
  3146. ch_info->channel,
  3147. ch_info->flags,
  3148. is_channel_a_band(ch_info) ?
  3149. "5.2" : "2.4");
  3150. ch_info++;
  3151. continue;
  3152. }
  3153. /* Initialize regulatory-based run-time data */
  3154. ch_info->max_power_avg = ch_info->curr_txpow =
  3155. eeprom_ch_info[ch].max_power_avg;
  3156. ch_info->scan_power = eeprom_ch_info[ch].max_power_avg;
  3157. ch_info->min_power = 0;
  3158. IWL_DEBUG_INFO("Ch. %d [%sGHz] %s%s%s%s%s%s(0x%02x"
  3159. " %ddBm): Ad-Hoc %ssupported\n",
  3160. ch_info->channel,
  3161. is_channel_a_band(ch_info) ?
  3162. "5.2" : "2.4",
  3163. CHECK_AND_PRINT(VALID),
  3164. CHECK_AND_PRINT(IBSS),
  3165. CHECK_AND_PRINT(ACTIVE),
  3166. CHECK_AND_PRINT(RADAR),
  3167. CHECK_AND_PRINT(WIDE),
  3168. CHECK_AND_PRINT(DFS),
  3169. eeprom_ch_info[ch].flags,
  3170. eeprom_ch_info[ch].max_power_avg,
  3171. ((eeprom_ch_info[ch].
  3172. flags & EEPROM_CHANNEL_IBSS)
  3173. && !(eeprom_ch_info[ch].
  3174. flags & EEPROM_CHANNEL_RADAR))
  3175. ? "" : "not ");
  3176. /* Set the tx_power_user_lmt to the highest power
  3177. * supported by any channel */
  3178. if (eeprom_ch_info[ch].max_power_avg >
  3179. priv->tx_power_user_lmt)
  3180. priv->tx_power_user_lmt =
  3181. eeprom_ch_info[ch].max_power_avg;
  3182. ch_info++;
  3183. }
  3184. }
  3185. /* Set up txpower settings in driver for all channels */
  3186. if (iwl3945_txpower_set_from_eeprom(priv))
  3187. return -EIO;
  3188. return 0;
  3189. }
  3190. /*
  3191. * iwl3945_free_channel_map - undo allocations in iwl3945_init_channel_map
  3192. */
  3193. static void iwl3945_free_channel_map(struct iwl_priv *priv)
  3194. {
  3195. kfree(priv->channel_info);
  3196. priv->channel_count = 0;
  3197. }
  3198. static int iwl3945_get_channels_for_scan(struct iwl_priv *priv,
  3199. enum ieee80211_band band,
  3200. u8 is_active, u8 n_probes,
  3201. struct iwl3945_scan_channel *scan_ch)
  3202. {
  3203. const struct ieee80211_channel *channels = NULL;
  3204. const struct ieee80211_supported_band *sband;
  3205. const struct iwl_channel_info *ch_info;
  3206. u16 passive_dwell = 0;
  3207. u16 active_dwell = 0;
  3208. int added, i;
  3209. sband = iwl_get_hw_mode(priv, band);
  3210. if (!sband)
  3211. return 0;
  3212. channels = sband->channels;
  3213. active_dwell = iwl_get_active_dwell_time(priv, band, n_probes);
  3214. passive_dwell = iwl_get_passive_dwell_time(priv, band);
  3215. if (passive_dwell <= active_dwell)
  3216. passive_dwell = active_dwell + 1;
  3217. for (i = 0, added = 0; i < sband->n_channels; i++) {
  3218. if (channels[i].flags & IEEE80211_CHAN_DISABLED)
  3219. continue;
  3220. scan_ch->channel = channels[i].hw_value;
  3221. ch_info = iwl3945_get_channel_info(priv, band, scan_ch->channel);
  3222. if (!is_channel_valid(ch_info)) {
  3223. IWL_DEBUG_SCAN("Channel %d is INVALID for this band.\n",
  3224. scan_ch->channel);
  3225. continue;
  3226. }
  3227. scan_ch->active_dwell = cpu_to_le16(active_dwell);
  3228. scan_ch->passive_dwell = cpu_to_le16(passive_dwell);
  3229. /* If passive , set up for auto-switch
  3230. * and use long active_dwell time.
  3231. */
  3232. if (!is_active || is_channel_passive(ch_info) ||
  3233. (channels[i].flags & IEEE80211_CHAN_PASSIVE_SCAN)) {
  3234. scan_ch->type = 0; /* passive */
  3235. if (IWL_UCODE_API(priv->ucode_ver) == 1)
  3236. scan_ch->active_dwell = cpu_to_le16(passive_dwell - 1);
  3237. } else {
  3238. scan_ch->type = 1; /* active */
  3239. }
  3240. /* Set direct probe bits. These may be used both for active
  3241. * scan channels (probes gets sent right away),
  3242. * or for passive channels (probes get se sent only after
  3243. * hearing clear Rx packet).*/
  3244. if (IWL_UCODE_API(priv->ucode_ver) >= 2) {
  3245. if (n_probes)
  3246. scan_ch->type |= IWL_SCAN_PROBE_MASK(n_probes);
  3247. } else {
  3248. /* uCode v1 does not allow setting direct probe bits on
  3249. * passive channel. */
  3250. if ((scan_ch->type & 1) && n_probes)
  3251. scan_ch->type |= IWL_SCAN_PROBE_MASK(n_probes);
  3252. }
  3253. /* Set txpower levels to defaults */
  3254. scan_ch->tpc.dsp_atten = 110;
  3255. /* scan_pwr_info->tpc.dsp_atten; */
  3256. /*scan_pwr_info->tpc.tx_gain; */
  3257. if (band == IEEE80211_BAND_5GHZ)
  3258. scan_ch->tpc.tx_gain = ((1 << 5) | (3 << 3)) | 3;
  3259. else {
  3260. scan_ch->tpc.tx_gain = ((1 << 5) | (5 << 3));
  3261. /* NOTE: if we were doing 6Mb OFDM for scans we'd use
  3262. * power level:
  3263. * scan_ch->tpc.tx_gain = ((1 << 5) | (2 << 3)) | 3;
  3264. */
  3265. }
  3266. IWL_DEBUG_SCAN("Scanning %d [%s %d]\n",
  3267. scan_ch->channel,
  3268. (scan_ch->type & 1) ? "ACTIVE" : "PASSIVE",
  3269. (scan_ch->type & 1) ?
  3270. active_dwell : passive_dwell);
  3271. scan_ch++;
  3272. added++;
  3273. }
  3274. IWL_DEBUG_SCAN("total channels to scan %d \n", added);
  3275. return added;
  3276. }
  3277. static void iwl3945_init_hw_rates(struct iwl_priv *priv,
  3278. struct ieee80211_rate *rates)
  3279. {
  3280. int i;
  3281. for (i = 0; i < IWL_RATE_COUNT; i++) {
  3282. rates[i].bitrate = iwl3945_rates[i].ieee * 5;
  3283. rates[i].hw_value = i; /* Rate scaling will work on indexes */
  3284. rates[i].hw_value_short = i;
  3285. rates[i].flags = 0;
  3286. if ((i > IWL39_LAST_OFDM_RATE) || (i < IWL_FIRST_OFDM_RATE)) {
  3287. /*
  3288. * If CCK != 1M then set short preamble rate flag.
  3289. */
  3290. rates[i].flags |= (iwl3945_rates[i].plcp == 10) ?
  3291. 0 : IEEE80211_RATE_SHORT_PREAMBLE;
  3292. }
  3293. }
  3294. }
  3295. /**
  3296. * iwl3945_init_geos - Initialize mac80211's geo/channel info based from eeprom
  3297. */
  3298. static int iwl3945_init_geos(struct iwl_priv *priv)
  3299. {
  3300. struct iwl_channel_info *ch;
  3301. struct ieee80211_supported_band *sband;
  3302. struct ieee80211_channel *channels;
  3303. struct ieee80211_channel *geo_ch;
  3304. struct ieee80211_rate *rates;
  3305. int i = 0;
  3306. if (priv->bands[IEEE80211_BAND_2GHZ].n_bitrates ||
  3307. priv->bands[IEEE80211_BAND_5GHZ].n_bitrates) {
  3308. IWL_DEBUG_INFO("Geography modes already initialized.\n");
  3309. set_bit(STATUS_GEO_CONFIGURED, &priv->status);
  3310. return 0;
  3311. }
  3312. channels = kzalloc(sizeof(struct ieee80211_channel) *
  3313. priv->channel_count, GFP_KERNEL);
  3314. if (!channels)
  3315. return -ENOMEM;
  3316. rates = kzalloc((sizeof(struct ieee80211_rate) * (IWL_RATE_COUNT + 1)),
  3317. GFP_KERNEL);
  3318. if (!rates) {
  3319. kfree(channels);
  3320. return -ENOMEM;
  3321. }
  3322. /* 5.2GHz channels start after the 2.4GHz channels */
  3323. sband = &priv->bands[IEEE80211_BAND_5GHZ];
  3324. sband->channels = &channels[ARRAY_SIZE(iwl3945_eeprom_band_1)];
  3325. /* just OFDM */
  3326. sband->bitrates = &rates[IWL_FIRST_OFDM_RATE];
  3327. sband->n_bitrates = IWL_RATE_COUNT - IWL_FIRST_OFDM_RATE;
  3328. sband = &priv->bands[IEEE80211_BAND_2GHZ];
  3329. sband->channels = channels;
  3330. /* OFDM & CCK */
  3331. sband->bitrates = rates;
  3332. sband->n_bitrates = IWL_RATE_COUNT;
  3333. priv->ieee_channels = channels;
  3334. priv->ieee_rates = rates;
  3335. iwl3945_init_hw_rates(priv, rates);
  3336. for (i = 0; i < priv->channel_count; i++) {
  3337. ch = &priv->channel_info[i];
  3338. /* FIXME: might be removed if scan is OK*/
  3339. if (!is_channel_valid(ch))
  3340. continue;
  3341. if (is_channel_a_band(ch))
  3342. sband = &priv->bands[IEEE80211_BAND_5GHZ];
  3343. else
  3344. sband = &priv->bands[IEEE80211_BAND_2GHZ];
  3345. geo_ch = &sband->channels[sband->n_channels++];
  3346. geo_ch->center_freq = ieee80211_channel_to_frequency(ch->channel);
  3347. geo_ch->max_power = ch->max_power_avg;
  3348. geo_ch->max_antenna_gain = 0xff;
  3349. geo_ch->hw_value = ch->channel;
  3350. if (is_channel_valid(ch)) {
  3351. if (!(ch->flags & EEPROM_CHANNEL_IBSS))
  3352. geo_ch->flags |= IEEE80211_CHAN_NO_IBSS;
  3353. if (!(ch->flags & EEPROM_CHANNEL_ACTIVE))
  3354. geo_ch->flags |= IEEE80211_CHAN_PASSIVE_SCAN;
  3355. if (ch->flags & EEPROM_CHANNEL_RADAR)
  3356. geo_ch->flags |= IEEE80211_CHAN_RADAR;
  3357. if (ch->max_power_avg > priv->tx_power_channel_lmt)
  3358. priv->tx_power_channel_lmt =
  3359. ch->max_power_avg;
  3360. } else {
  3361. geo_ch->flags |= IEEE80211_CHAN_DISABLED;
  3362. }
  3363. /* Save flags for reg domain usage */
  3364. geo_ch->orig_flags = geo_ch->flags;
  3365. IWL_DEBUG_INFO("Channel %d Freq=%d[%sGHz] %s flag=0%X\n",
  3366. ch->channel, geo_ch->center_freq,
  3367. is_channel_a_band(ch) ? "5.2" : "2.4",
  3368. geo_ch->flags & IEEE80211_CHAN_DISABLED ?
  3369. "restricted" : "valid",
  3370. geo_ch->flags);
  3371. }
  3372. if ((priv->bands[IEEE80211_BAND_5GHZ].n_channels == 0) &&
  3373. priv->cfg->sku & IWL_SKU_A) {
  3374. IWL_INFO(priv, "Incorrectly detected BG card as ABG. "
  3375. "Please send your PCI ID 0x%04X:0x%04X to maintainer.\n",
  3376. priv->pci_dev->device, priv->pci_dev->subsystem_device);
  3377. priv->cfg->sku &= ~IWL_SKU_A;
  3378. }
  3379. IWL_INFO(priv, "Tunable channels: %d 802.11bg, %d 802.11a channels\n",
  3380. priv->bands[IEEE80211_BAND_2GHZ].n_channels,
  3381. priv->bands[IEEE80211_BAND_5GHZ].n_channels);
  3382. if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
  3383. priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
  3384. &priv->bands[IEEE80211_BAND_2GHZ];
  3385. if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
  3386. priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
  3387. &priv->bands[IEEE80211_BAND_5GHZ];
  3388. set_bit(STATUS_GEO_CONFIGURED, &priv->status);
  3389. return 0;
  3390. }
  3391. /*
  3392. * iwl3945_free_geos - undo allocations in iwl3945_init_geos
  3393. */
  3394. static void iwl3945_free_geos(struct iwl_priv *priv)
  3395. {
  3396. kfree(priv->ieee_channels);
  3397. kfree(priv->ieee_rates);
  3398. clear_bit(STATUS_GEO_CONFIGURED, &priv->status);
  3399. }
  3400. /******************************************************************************
  3401. *
  3402. * uCode download functions
  3403. *
  3404. ******************************************************************************/
  3405. static void iwl3945_dealloc_ucode_pci(struct iwl_priv *priv)
  3406. {
  3407. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code);
  3408. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data);
  3409. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
  3410. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init);
  3411. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data);
  3412. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot);
  3413. }
  3414. /**
  3415. * iwl3945_verify_inst_full - verify runtime uCode image in card vs. host,
  3416. * looking at all data.
  3417. */
  3418. static int iwl3945_verify_inst_full(struct iwl_priv *priv, __le32 *image, u32 len)
  3419. {
  3420. u32 val;
  3421. u32 save_len = len;
  3422. int rc = 0;
  3423. u32 errcnt;
  3424. IWL_DEBUG_INFO("ucode inst image size is %u\n", len);
  3425. rc = iwl_grab_nic_access(priv);
  3426. if (rc)
  3427. return rc;
  3428. iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR,
  3429. IWL39_RTC_INST_LOWER_BOUND);
  3430. errcnt = 0;
  3431. for (; len > 0; len -= sizeof(u32), image++) {
  3432. /* read data comes through single port, auto-incr addr */
  3433. /* NOTE: Use the debugless read so we don't flood kernel log
  3434. * if IWL_DL_IO is set */
  3435. val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  3436. if (val != le32_to_cpu(*image)) {
  3437. IWL_ERR(priv, "uCode INST section is invalid at "
  3438. "offset 0x%x, is 0x%x, s/b 0x%x\n",
  3439. save_len - len, val, le32_to_cpu(*image));
  3440. rc = -EIO;
  3441. errcnt++;
  3442. if (errcnt >= 20)
  3443. break;
  3444. }
  3445. }
  3446. iwl_release_nic_access(priv);
  3447. if (!errcnt)
  3448. IWL_DEBUG_INFO("ucode image in INSTRUCTION memory is good\n");
  3449. return rc;
  3450. }
  3451. /**
  3452. * iwl3945_verify_inst_sparse - verify runtime uCode image in card vs. host,
  3453. * using sample data 100 bytes apart. If these sample points are good,
  3454. * it's a pretty good bet that everything between them is good, too.
  3455. */
  3456. static int iwl3945_verify_inst_sparse(struct iwl_priv *priv, __le32 *image, u32 len)
  3457. {
  3458. u32 val;
  3459. int rc = 0;
  3460. u32 errcnt = 0;
  3461. u32 i;
  3462. IWL_DEBUG_INFO("ucode inst image size is %u\n", len);
  3463. rc = iwl_grab_nic_access(priv);
  3464. if (rc)
  3465. return rc;
  3466. for (i = 0; i < len; i += 100, image += 100/sizeof(u32)) {
  3467. /* read data comes through single port, auto-incr addr */
  3468. /* NOTE: Use the debugless read so we don't flood kernel log
  3469. * if IWL_DL_IO is set */
  3470. iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR,
  3471. i + IWL39_RTC_INST_LOWER_BOUND);
  3472. val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  3473. if (val != le32_to_cpu(*image)) {
  3474. #if 0 /* Enable this if you want to see details */
  3475. IWL_ERR(priv, "uCode INST section is invalid at "
  3476. "offset 0x%x, is 0x%x, s/b 0x%x\n",
  3477. i, val, *image);
  3478. #endif
  3479. rc = -EIO;
  3480. errcnt++;
  3481. if (errcnt >= 3)
  3482. break;
  3483. }
  3484. }
  3485. iwl_release_nic_access(priv);
  3486. return rc;
  3487. }
  3488. /**
  3489. * iwl3945_verify_ucode - determine which instruction image is in SRAM,
  3490. * and verify its contents
  3491. */
  3492. static int iwl3945_verify_ucode(struct iwl_priv *priv)
  3493. {
  3494. __le32 *image;
  3495. u32 len;
  3496. int rc = 0;
  3497. /* Try bootstrap */
  3498. image = (__le32 *)priv->ucode_boot.v_addr;
  3499. len = priv->ucode_boot.len;
  3500. rc = iwl3945_verify_inst_sparse(priv, image, len);
  3501. if (rc == 0) {
  3502. IWL_DEBUG_INFO("Bootstrap uCode is good in inst SRAM\n");
  3503. return 0;
  3504. }
  3505. /* Try initialize */
  3506. image = (__le32 *)priv->ucode_init.v_addr;
  3507. len = priv->ucode_init.len;
  3508. rc = iwl3945_verify_inst_sparse(priv, image, len);
  3509. if (rc == 0) {
  3510. IWL_DEBUG_INFO("Initialize uCode is good in inst SRAM\n");
  3511. return 0;
  3512. }
  3513. /* Try runtime/protocol */
  3514. image = (__le32 *)priv->ucode_code.v_addr;
  3515. len = priv->ucode_code.len;
  3516. rc = iwl3945_verify_inst_sparse(priv, image, len);
  3517. if (rc == 0) {
  3518. IWL_DEBUG_INFO("Runtime uCode is good in inst SRAM\n");
  3519. return 0;
  3520. }
  3521. IWL_ERR(priv, "NO VALID UCODE IMAGE IN INSTRUCTION SRAM!!\n");
  3522. /* Since nothing seems to match, show first several data entries in
  3523. * instruction SRAM, so maybe visual inspection will give a clue.
  3524. * Selection of bootstrap image (vs. other images) is arbitrary. */
  3525. image = (__le32 *)priv->ucode_boot.v_addr;
  3526. len = priv->ucode_boot.len;
  3527. rc = iwl3945_verify_inst_full(priv, image, len);
  3528. return rc;
  3529. }
  3530. static void iwl3945_nic_start(struct iwl_priv *priv)
  3531. {
  3532. /* Remove all resets to allow NIC to operate */
  3533. iwl_write32(priv, CSR_RESET, 0);
  3534. }
  3535. /**
  3536. * iwl3945_read_ucode - Read uCode images from disk file.
  3537. *
  3538. * Copy into buffers for card to fetch via bus-mastering
  3539. */
  3540. static int iwl3945_read_ucode(struct iwl_priv *priv)
  3541. {
  3542. struct iwl_ucode *ucode;
  3543. int ret = -EINVAL, index;
  3544. const struct firmware *ucode_raw;
  3545. /* firmware file name contains uCode/driver compatibility version */
  3546. const char *name_pre = priv->cfg->fw_name_pre;
  3547. const unsigned int api_max = priv->cfg->ucode_api_max;
  3548. const unsigned int api_min = priv->cfg->ucode_api_min;
  3549. char buf[25];
  3550. u8 *src;
  3551. size_t len;
  3552. u32 api_ver, inst_size, data_size, init_size, init_data_size, boot_size;
  3553. /* Ask kernel firmware_class module to get the boot firmware off disk.
  3554. * request_firmware() is synchronous, file is in memory on return. */
  3555. for (index = api_max; index >= api_min; index--) {
  3556. sprintf(buf, "%s%u%s", name_pre, index, ".ucode");
  3557. ret = request_firmware(&ucode_raw, buf, &priv->pci_dev->dev);
  3558. if (ret < 0) {
  3559. IWL_ERR(priv, "%s firmware file req failed: %d\n",
  3560. buf, ret);
  3561. if (ret == -ENOENT)
  3562. continue;
  3563. else
  3564. goto error;
  3565. } else {
  3566. if (index < api_max)
  3567. IWL_ERR(priv, "Loaded firmware %s, "
  3568. "which is deprecated. "
  3569. " Please use API v%u instead.\n",
  3570. buf, api_max);
  3571. IWL_DEBUG_INFO("Got firmware '%s' file (%zd bytes) from disk\n",
  3572. buf, ucode_raw->size);
  3573. break;
  3574. }
  3575. }
  3576. if (ret < 0)
  3577. goto error;
  3578. /* Make sure that we got at least our header! */
  3579. if (ucode_raw->size < sizeof(*ucode)) {
  3580. IWL_ERR(priv, "File size way too small!\n");
  3581. ret = -EINVAL;
  3582. goto err_release;
  3583. }
  3584. /* Data from ucode file: header followed by uCode images */
  3585. ucode = (void *)ucode_raw->data;
  3586. priv->ucode_ver = le32_to_cpu(ucode->ver);
  3587. api_ver = IWL_UCODE_API(priv->ucode_ver);
  3588. inst_size = le32_to_cpu(ucode->inst_size);
  3589. data_size = le32_to_cpu(ucode->data_size);
  3590. init_size = le32_to_cpu(ucode->init_size);
  3591. init_data_size = le32_to_cpu(ucode->init_data_size);
  3592. boot_size = le32_to_cpu(ucode->boot_size);
  3593. /* api_ver should match the api version forming part of the
  3594. * firmware filename ... but we don't check for that and only rely
  3595. * on the API version read from firware header from here on forward */
  3596. if (api_ver < api_min || api_ver > api_max) {
  3597. IWL_ERR(priv, "Driver unable to support your firmware API. "
  3598. "Driver supports v%u, firmware is v%u.\n",
  3599. api_max, api_ver);
  3600. priv->ucode_ver = 0;
  3601. ret = -EINVAL;
  3602. goto err_release;
  3603. }
  3604. if (api_ver != api_max)
  3605. IWL_ERR(priv, "Firmware has old API version. Expected %u, "
  3606. "got %u. New firmware can be obtained "
  3607. "from http://www.intellinuxwireless.org.\n",
  3608. api_max, api_ver);
  3609. IWL_INFO(priv, "loaded firmware version %u.%u.%u.%u\n",
  3610. IWL_UCODE_MAJOR(priv->ucode_ver),
  3611. IWL_UCODE_MINOR(priv->ucode_ver),
  3612. IWL_UCODE_API(priv->ucode_ver),
  3613. IWL_UCODE_SERIAL(priv->ucode_ver));
  3614. IWL_DEBUG_INFO("f/w package hdr ucode version raw = 0x%x\n",
  3615. priv->ucode_ver);
  3616. IWL_DEBUG_INFO("f/w package hdr runtime inst size = %u\n", inst_size);
  3617. IWL_DEBUG_INFO("f/w package hdr runtime data size = %u\n", data_size);
  3618. IWL_DEBUG_INFO("f/w package hdr init inst size = %u\n", init_size);
  3619. IWL_DEBUG_INFO("f/w package hdr init data size = %u\n", init_data_size);
  3620. IWL_DEBUG_INFO("f/w package hdr boot inst size = %u\n", boot_size);
  3621. /* Verify size of file vs. image size info in file's header */
  3622. if (ucode_raw->size < sizeof(*ucode) +
  3623. inst_size + data_size + init_size +
  3624. init_data_size + boot_size) {
  3625. IWL_DEBUG_INFO("uCode file size %d too small\n",
  3626. (int)ucode_raw->size);
  3627. ret = -EINVAL;
  3628. goto err_release;
  3629. }
  3630. /* Verify that uCode images will fit in card's SRAM */
  3631. if (inst_size > IWL39_MAX_INST_SIZE) {
  3632. IWL_DEBUG_INFO("uCode instr len %d too large to fit in\n",
  3633. inst_size);
  3634. ret = -EINVAL;
  3635. goto err_release;
  3636. }
  3637. if (data_size > IWL39_MAX_DATA_SIZE) {
  3638. IWL_DEBUG_INFO("uCode data len %d too large to fit in\n",
  3639. data_size);
  3640. ret = -EINVAL;
  3641. goto err_release;
  3642. }
  3643. if (init_size > IWL39_MAX_INST_SIZE) {
  3644. IWL_DEBUG_INFO("uCode init instr len %d too large to fit in\n",
  3645. init_size);
  3646. ret = -EINVAL;
  3647. goto err_release;
  3648. }
  3649. if (init_data_size > IWL39_MAX_DATA_SIZE) {
  3650. IWL_DEBUG_INFO("uCode init data len %d too large to fit in\n",
  3651. init_data_size);
  3652. ret = -EINVAL;
  3653. goto err_release;
  3654. }
  3655. if (boot_size > IWL39_MAX_BSM_SIZE) {
  3656. IWL_DEBUG_INFO("uCode boot instr len %d too large to fit in\n",
  3657. boot_size);
  3658. ret = -EINVAL;
  3659. goto err_release;
  3660. }
  3661. /* Allocate ucode buffers for card's bus-master loading ... */
  3662. /* Runtime instructions and 2 copies of data:
  3663. * 1) unmodified from disk
  3664. * 2) backup cache for save/restore during power-downs */
  3665. priv->ucode_code.len = inst_size;
  3666. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code);
  3667. priv->ucode_data.len = data_size;
  3668. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data);
  3669. priv->ucode_data_backup.len = data_size;
  3670. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
  3671. if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr ||
  3672. !priv->ucode_data_backup.v_addr)
  3673. goto err_pci_alloc;
  3674. /* Initialization instructions and data */
  3675. if (init_size && init_data_size) {
  3676. priv->ucode_init.len = init_size;
  3677. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init);
  3678. priv->ucode_init_data.len = init_data_size;
  3679. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data);
  3680. if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr)
  3681. goto err_pci_alloc;
  3682. }
  3683. /* Bootstrap (instructions only, no data) */
  3684. if (boot_size) {
  3685. priv->ucode_boot.len = boot_size;
  3686. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot);
  3687. if (!priv->ucode_boot.v_addr)
  3688. goto err_pci_alloc;
  3689. }
  3690. /* Copy images into buffers for card's bus-master reads ... */
  3691. /* Runtime instructions (first block of data in file) */
  3692. src = &ucode->data[0];
  3693. len = priv->ucode_code.len;
  3694. IWL_DEBUG_INFO("Copying (but not loading) uCode instr len %Zd\n", len);
  3695. memcpy(priv->ucode_code.v_addr, src, len);
  3696. IWL_DEBUG_INFO("uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
  3697. priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr);
  3698. /* Runtime data (2nd block)
  3699. * NOTE: Copy into backup buffer will be done in iwl3945_up() */
  3700. src = &ucode->data[inst_size];
  3701. len = priv->ucode_data.len;
  3702. IWL_DEBUG_INFO("Copying (but not loading) uCode data len %Zd\n", len);
  3703. memcpy(priv->ucode_data.v_addr, src, len);
  3704. memcpy(priv->ucode_data_backup.v_addr, src, len);
  3705. /* Initialization instructions (3rd block) */
  3706. if (init_size) {
  3707. src = &ucode->data[inst_size + data_size];
  3708. len = priv->ucode_init.len;
  3709. IWL_DEBUG_INFO("Copying (but not loading) init instr len %Zd\n",
  3710. len);
  3711. memcpy(priv->ucode_init.v_addr, src, len);
  3712. }
  3713. /* Initialization data (4th block) */
  3714. if (init_data_size) {
  3715. src = &ucode->data[inst_size + data_size + init_size];
  3716. len = priv->ucode_init_data.len;
  3717. IWL_DEBUG_INFO("Copying (but not loading) init data len %d\n",
  3718. (int)len);
  3719. memcpy(priv->ucode_init_data.v_addr, src, len);
  3720. }
  3721. /* Bootstrap instructions (5th block) */
  3722. src = &ucode->data[inst_size + data_size + init_size + init_data_size];
  3723. len = priv->ucode_boot.len;
  3724. IWL_DEBUG_INFO("Copying (but not loading) boot instr len %d\n",
  3725. (int)len);
  3726. memcpy(priv->ucode_boot.v_addr, src, len);
  3727. /* We have our copies now, allow OS release its copies */
  3728. release_firmware(ucode_raw);
  3729. return 0;
  3730. err_pci_alloc:
  3731. IWL_ERR(priv, "failed to allocate pci memory\n");
  3732. ret = -ENOMEM;
  3733. iwl3945_dealloc_ucode_pci(priv);
  3734. err_release:
  3735. release_firmware(ucode_raw);
  3736. error:
  3737. return ret;
  3738. }
  3739. /**
  3740. * iwl3945_set_ucode_ptrs - Set uCode address location
  3741. *
  3742. * Tell initialization uCode where to find runtime uCode.
  3743. *
  3744. * BSM registers initially contain pointers to initialization uCode.
  3745. * We need to replace them to load runtime uCode inst and data,
  3746. * and to save runtime data when powering down.
  3747. */
  3748. static int iwl3945_set_ucode_ptrs(struct iwl_priv *priv)
  3749. {
  3750. dma_addr_t pinst;
  3751. dma_addr_t pdata;
  3752. int rc = 0;
  3753. unsigned long flags;
  3754. /* bits 31:0 for 3945 */
  3755. pinst = priv->ucode_code.p_addr;
  3756. pdata = priv->ucode_data_backup.p_addr;
  3757. spin_lock_irqsave(&priv->lock, flags);
  3758. rc = iwl_grab_nic_access(priv);
  3759. if (rc) {
  3760. spin_unlock_irqrestore(&priv->lock, flags);
  3761. return rc;
  3762. }
  3763. /* Tell bootstrap uCode where to find image to load */
  3764. iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
  3765. iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
  3766. iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG,
  3767. priv->ucode_data.len);
  3768. /* Inst byte count must be last to set up, bit 31 signals uCode
  3769. * that all new ptr/size info is in place */
  3770. iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG,
  3771. priv->ucode_code.len | BSM_DRAM_INST_LOAD);
  3772. iwl_release_nic_access(priv);
  3773. spin_unlock_irqrestore(&priv->lock, flags);
  3774. IWL_DEBUG_INFO("Runtime uCode pointers are set.\n");
  3775. return rc;
  3776. }
  3777. /**
  3778. * iwl3945_init_alive_start - Called after REPLY_ALIVE notification received
  3779. *
  3780. * Called after REPLY_ALIVE notification received from "initialize" uCode.
  3781. *
  3782. * Tell "initialize" uCode to go ahead and load the runtime uCode.
  3783. */
  3784. static void iwl3945_init_alive_start(struct iwl_priv *priv)
  3785. {
  3786. /* Check alive response for "valid" sign from uCode */
  3787. if (priv->card_alive_init.is_valid != UCODE_VALID_OK) {
  3788. /* We had an error bringing up the hardware, so take it
  3789. * all the way back down so we can try again */
  3790. IWL_DEBUG_INFO("Initialize Alive failed.\n");
  3791. goto restart;
  3792. }
  3793. /* Bootstrap uCode has loaded initialize uCode ... verify inst image.
  3794. * This is a paranoid check, because we would not have gotten the
  3795. * "initialize" alive if code weren't properly loaded. */
  3796. if (iwl3945_verify_ucode(priv)) {
  3797. /* Runtime instruction load was bad;
  3798. * take it all the way back down so we can try again */
  3799. IWL_DEBUG_INFO("Bad \"initialize\" uCode load.\n");
  3800. goto restart;
  3801. }
  3802. /* Send pointers to protocol/runtime uCode image ... init code will
  3803. * load and launch runtime uCode, which will send us another "Alive"
  3804. * notification. */
  3805. IWL_DEBUG_INFO("Initialization Alive received.\n");
  3806. if (iwl3945_set_ucode_ptrs(priv)) {
  3807. /* Runtime instruction load won't happen;
  3808. * take it all the way back down so we can try again */
  3809. IWL_DEBUG_INFO("Couldn't set up uCode pointers.\n");
  3810. goto restart;
  3811. }
  3812. return;
  3813. restart:
  3814. queue_work(priv->workqueue, &priv->restart);
  3815. }
  3816. /* temporary */
  3817. static int iwl3945_mac_beacon_update(struct ieee80211_hw *hw,
  3818. struct sk_buff *skb);
  3819. /**
  3820. * iwl3945_alive_start - called after REPLY_ALIVE notification received
  3821. * from protocol/runtime uCode (initialization uCode's
  3822. * Alive gets handled by iwl3945_init_alive_start()).
  3823. */
  3824. static void iwl3945_alive_start(struct iwl_priv *priv)
  3825. {
  3826. int rc = 0;
  3827. int thermal_spin = 0;
  3828. u32 rfkill;
  3829. IWL_DEBUG_INFO("Runtime Alive received.\n");
  3830. if (priv->card_alive.is_valid != UCODE_VALID_OK) {
  3831. /* We had an error bringing up the hardware, so take it
  3832. * all the way back down so we can try again */
  3833. IWL_DEBUG_INFO("Alive failed.\n");
  3834. goto restart;
  3835. }
  3836. /* Initialize uCode has loaded Runtime uCode ... verify inst image.
  3837. * This is a paranoid check, because we would not have gotten the
  3838. * "runtime" alive if code weren't properly loaded. */
  3839. if (iwl3945_verify_ucode(priv)) {
  3840. /* Runtime instruction load was bad;
  3841. * take it all the way back down so we can try again */
  3842. IWL_DEBUG_INFO("Bad runtime uCode load.\n");
  3843. goto restart;
  3844. }
  3845. iwl3945_clear_stations_table(priv);
  3846. rc = iwl_grab_nic_access(priv);
  3847. if (rc) {
  3848. IWL_WARN(priv, "Can not read RFKILL status from adapter\n");
  3849. return;
  3850. }
  3851. rfkill = iwl_read_prph(priv, APMG_RFKILL_REG);
  3852. IWL_DEBUG_INFO("RFKILL status: 0x%x\n", rfkill);
  3853. iwl_release_nic_access(priv);
  3854. if (rfkill & 0x1) {
  3855. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  3856. /* if RFKILL is not on, then wait for thermal
  3857. * sensor in adapter to kick in */
  3858. while (iwl3945_hw_get_temperature(priv) == 0) {
  3859. thermal_spin++;
  3860. udelay(10);
  3861. }
  3862. if (thermal_spin)
  3863. IWL_DEBUG_INFO("Thermal calibration took %dus\n",
  3864. thermal_spin * 10);
  3865. } else
  3866. set_bit(STATUS_RF_KILL_HW, &priv->status);
  3867. /* After the ALIVE response, we can send commands to 3945 uCode */
  3868. set_bit(STATUS_ALIVE, &priv->status);
  3869. /* Clear out the uCode error bit if it is set */
  3870. clear_bit(STATUS_FW_ERROR, &priv->status);
  3871. if (iwl_is_rfkill(priv))
  3872. return;
  3873. ieee80211_wake_queues(priv->hw);
  3874. priv->active_rate = priv->rates_mask;
  3875. priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK;
  3876. iwl3945_send_power_mode(priv, IWL_POWER_LEVEL(priv->power_mode));
  3877. if (iwl3945_is_associated(priv)) {
  3878. struct iwl3945_rxon_cmd *active_rxon =
  3879. (struct iwl3945_rxon_cmd *)(&priv->active39_rxon);
  3880. memcpy(&priv->staging39_rxon, &priv->active39_rxon,
  3881. sizeof(priv->staging39_rxon));
  3882. active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  3883. } else {
  3884. /* Initialize our rx_config data */
  3885. iwl3945_connection_init_rx_config(priv, priv->iw_mode);
  3886. memcpy(priv->staging39_rxon.node_addr, priv->mac_addr, ETH_ALEN);
  3887. }
  3888. /* Configure Bluetooth device coexistence support */
  3889. iwl3945_send_bt_config(priv);
  3890. /* Configure the adapter for unassociated operation */
  3891. iwl3945_commit_rxon(priv);
  3892. iwl3945_reg_txpower_periodic(priv);
  3893. iwl3945_led_register(priv);
  3894. IWL_DEBUG_INFO("ALIVE processing complete.\n");
  3895. set_bit(STATUS_READY, &priv->status);
  3896. wake_up_interruptible(&priv->wait_command_queue);
  3897. if (priv->error_recovering)
  3898. iwl3945_error_recovery(priv);
  3899. /* reassociate for ADHOC mode */
  3900. if (priv->vif && (priv->iw_mode == NL80211_IFTYPE_ADHOC)) {
  3901. struct sk_buff *beacon = ieee80211_beacon_get(priv->hw,
  3902. priv->vif);
  3903. if (beacon)
  3904. iwl3945_mac_beacon_update(priv->hw, beacon);
  3905. }
  3906. return;
  3907. restart:
  3908. queue_work(priv->workqueue, &priv->restart);
  3909. }
  3910. static void iwl3945_cancel_deferred_work(struct iwl_priv *priv);
  3911. static void __iwl3945_down(struct iwl_priv *priv)
  3912. {
  3913. unsigned long flags;
  3914. int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status);
  3915. struct ieee80211_conf *conf = NULL;
  3916. IWL_DEBUG_INFO(DRV_NAME " is going down\n");
  3917. conf = ieee80211_get_hw_conf(priv->hw);
  3918. if (!exit_pending)
  3919. set_bit(STATUS_EXIT_PENDING, &priv->status);
  3920. iwl3945_led_unregister(priv);
  3921. iwl3945_clear_stations_table(priv);
  3922. /* Unblock any waiting calls */
  3923. wake_up_interruptible_all(&priv->wait_command_queue);
  3924. /* Wipe out the EXIT_PENDING status bit if we are not actually
  3925. * exiting the module */
  3926. if (!exit_pending)
  3927. clear_bit(STATUS_EXIT_PENDING, &priv->status);
  3928. /* stop and reset the on-board processor */
  3929. iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
  3930. /* tell the device to stop sending interrupts */
  3931. spin_lock_irqsave(&priv->lock, flags);
  3932. iwl3945_disable_interrupts(priv);
  3933. spin_unlock_irqrestore(&priv->lock, flags);
  3934. iwl_synchronize_irq(priv);
  3935. if (priv->mac80211_registered)
  3936. ieee80211_stop_queues(priv->hw);
  3937. /* If we have not previously called iwl3945_init() then
  3938. * clear all bits but the RF Kill and SUSPEND bits and return */
  3939. if (!iwl_is_init(priv)) {
  3940. priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) <<
  3941. STATUS_RF_KILL_HW |
  3942. test_bit(STATUS_RF_KILL_SW, &priv->status) <<
  3943. STATUS_RF_KILL_SW |
  3944. test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
  3945. STATUS_GEO_CONFIGURED |
  3946. test_bit(STATUS_IN_SUSPEND, &priv->status) <<
  3947. STATUS_IN_SUSPEND |
  3948. test_bit(STATUS_EXIT_PENDING, &priv->status) <<
  3949. STATUS_EXIT_PENDING;
  3950. goto exit;
  3951. }
  3952. /* ...otherwise clear out all the status bits but the RF Kill and
  3953. * SUSPEND bits and continue taking the NIC down. */
  3954. priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
  3955. STATUS_RF_KILL_HW |
  3956. test_bit(STATUS_RF_KILL_SW, &priv->status) <<
  3957. STATUS_RF_KILL_SW |
  3958. test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
  3959. STATUS_GEO_CONFIGURED |
  3960. test_bit(STATUS_IN_SUSPEND, &priv->status) <<
  3961. STATUS_IN_SUSPEND |
  3962. test_bit(STATUS_FW_ERROR, &priv->status) <<
  3963. STATUS_FW_ERROR |
  3964. test_bit(STATUS_EXIT_PENDING, &priv->status) <<
  3965. STATUS_EXIT_PENDING;
  3966. priv->cfg->ops->lib->apm_ops.reset(priv);
  3967. spin_lock_irqsave(&priv->lock, flags);
  3968. iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
  3969. spin_unlock_irqrestore(&priv->lock, flags);
  3970. iwl3945_hw_txq_ctx_stop(priv);
  3971. iwl3945_hw_rxq_stop(priv);
  3972. spin_lock_irqsave(&priv->lock, flags);
  3973. if (!iwl_grab_nic_access(priv)) {
  3974. iwl_write_prph(priv, APMG_CLK_DIS_REG,
  3975. APMG_CLK_VAL_DMA_CLK_RQT);
  3976. iwl_release_nic_access(priv);
  3977. }
  3978. spin_unlock_irqrestore(&priv->lock, flags);
  3979. udelay(5);
  3980. if (exit_pending || test_bit(STATUS_IN_SUSPEND, &priv->status))
  3981. priv->cfg->ops->lib->apm_ops.stop(priv);
  3982. else
  3983. priv->cfg->ops->lib->apm_ops.reset(priv);
  3984. exit:
  3985. memset(&priv->card_alive, 0, sizeof(struct iwl_alive_resp));
  3986. if (priv->ibss_beacon)
  3987. dev_kfree_skb(priv->ibss_beacon);
  3988. priv->ibss_beacon = NULL;
  3989. /* clear out any free frames */
  3990. iwl3945_clear_free_frames(priv);
  3991. }
  3992. static void iwl3945_down(struct iwl_priv *priv)
  3993. {
  3994. mutex_lock(&priv->mutex);
  3995. __iwl3945_down(priv);
  3996. mutex_unlock(&priv->mutex);
  3997. iwl3945_cancel_deferred_work(priv);
  3998. }
  3999. #define MAX_HW_RESTARTS 5
  4000. static int __iwl3945_up(struct iwl_priv *priv)
  4001. {
  4002. int rc, i;
  4003. if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
  4004. IWL_WARN(priv, "Exit pending; will not bring the NIC up\n");
  4005. return -EIO;
  4006. }
  4007. if (test_bit(STATUS_RF_KILL_SW, &priv->status)) {
  4008. IWL_WARN(priv, "Radio disabled by SW RF kill (module "
  4009. "parameter)\n");
  4010. return -ENODEV;
  4011. }
  4012. if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) {
  4013. IWL_ERR(priv, "ucode not available for device bring up\n");
  4014. return -EIO;
  4015. }
  4016. /* If platform's RF_KILL switch is NOT set to KILL */
  4017. if (iwl_read32(priv, CSR_GP_CNTRL) &
  4018. CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
  4019. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  4020. else {
  4021. set_bit(STATUS_RF_KILL_HW, &priv->status);
  4022. if (!test_bit(STATUS_IN_SUSPEND, &priv->status)) {
  4023. IWL_WARN(priv, "Radio disabled by HW RF Kill switch\n");
  4024. return -ENODEV;
  4025. }
  4026. }
  4027. iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
  4028. rc = iwl3945_hw_nic_init(priv);
  4029. if (rc) {
  4030. IWL_ERR(priv, "Unable to int nic\n");
  4031. return rc;
  4032. }
  4033. /* make sure rfkill handshake bits are cleared */
  4034. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  4035. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
  4036. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  4037. /* clear (again), then enable host interrupts */
  4038. iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
  4039. iwl3945_enable_interrupts(priv);
  4040. /* really make sure rfkill handshake bits are cleared */
  4041. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  4042. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  4043. /* Copy original ucode data image from disk into backup cache.
  4044. * This will be used to initialize the on-board processor's
  4045. * data SRAM for a clean start when the runtime program first loads. */
  4046. memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr,
  4047. priv->ucode_data.len);
  4048. /* We return success when we resume from suspend and rf_kill is on. */
  4049. if (test_bit(STATUS_RF_KILL_HW, &priv->status))
  4050. return 0;
  4051. for (i = 0; i < MAX_HW_RESTARTS; i++) {
  4052. iwl3945_clear_stations_table(priv);
  4053. /* load bootstrap state machine,
  4054. * load bootstrap program into processor's memory,
  4055. * prepare to load the "initialize" uCode */
  4056. priv->cfg->ops->lib->load_ucode(priv);
  4057. if (rc) {
  4058. IWL_ERR(priv,
  4059. "Unable to set up bootstrap uCode: %d\n", rc);
  4060. continue;
  4061. }
  4062. /* start card; "initialize" will load runtime ucode */
  4063. iwl3945_nic_start(priv);
  4064. IWL_DEBUG_INFO(DRV_NAME " is coming up\n");
  4065. return 0;
  4066. }
  4067. set_bit(STATUS_EXIT_PENDING, &priv->status);
  4068. __iwl3945_down(priv);
  4069. clear_bit(STATUS_EXIT_PENDING, &priv->status);
  4070. /* tried to restart and config the device for as long as our
  4071. * patience could withstand */
  4072. IWL_ERR(priv, "Unable to initialize device after %d attempts.\n", i);
  4073. return -EIO;
  4074. }
  4075. /*****************************************************************************
  4076. *
  4077. * Workqueue callbacks
  4078. *
  4079. *****************************************************************************/
  4080. static void iwl3945_bg_init_alive_start(struct work_struct *data)
  4081. {
  4082. struct iwl_priv *priv =
  4083. container_of(data, struct iwl_priv, init_alive_start.work);
  4084. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  4085. return;
  4086. mutex_lock(&priv->mutex);
  4087. iwl3945_init_alive_start(priv);
  4088. mutex_unlock(&priv->mutex);
  4089. }
  4090. static void iwl3945_bg_alive_start(struct work_struct *data)
  4091. {
  4092. struct iwl_priv *priv =
  4093. container_of(data, struct iwl_priv, alive_start.work);
  4094. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  4095. return;
  4096. mutex_lock(&priv->mutex);
  4097. iwl3945_alive_start(priv);
  4098. mutex_unlock(&priv->mutex);
  4099. }
  4100. static void iwl3945_rfkill_poll(struct work_struct *data)
  4101. {
  4102. struct iwl_priv *priv =
  4103. container_of(data, struct iwl_priv, rfkill_poll.work);
  4104. unsigned long status = priv->status;
  4105. if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
  4106. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  4107. else
  4108. set_bit(STATUS_RF_KILL_HW, &priv->status);
  4109. if (test_bit(STATUS_RF_KILL_HW, &status) != test_bit(STATUS_RF_KILL_HW, &priv->status))
  4110. queue_work(priv->workqueue, &priv->rf_kill);
  4111. queue_delayed_work(priv->workqueue, &priv->rfkill_poll,
  4112. round_jiffies_relative(2 * HZ));
  4113. }
  4114. #define IWL_SCAN_CHECK_WATCHDOG (7 * HZ)
  4115. static void iwl3945_bg_request_scan(struct work_struct *data)
  4116. {
  4117. struct iwl_priv *priv =
  4118. container_of(data, struct iwl_priv, request_scan);
  4119. struct iwl_host_cmd cmd = {
  4120. .id = REPLY_SCAN_CMD,
  4121. .len = sizeof(struct iwl3945_scan_cmd),
  4122. .meta.flags = CMD_SIZE_HUGE,
  4123. };
  4124. int rc = 0;
  4125. struct iwl3945_scan_cmd *scan;
  4126. struct ieee80211_conf *conf = NULL;
  4127. u8 n_probes = 2;
  4128. enum ieee80211_band band;
  4129. DECLARE_SSID_BUF(ssid);
  4130. conf = ieee80211_get_hw_conf(priv->hw);
  4131. mutex_lock(&priv->mutex);
  4132. if (!iwl_is_ready(priv)) {
  4133. IWL_WARN(priv, "request scan called when driver not ready.\n");
  4134. goto done;
  4135. }
  4136. /* Make sure the scan wasn't canceled before this queued work
  4137. * was given the chance to run... */
  4138. if (!test_bit(STATUS_SCANNING, &priv->status))
  4139. goto done;
  4140. /* This should never be called or scheduled if there is currently
  4141. * a scan active in the hardware. */
  4142. if (test_bit(STATUS_SCAN_HW, &priv->status)) {
  4143. IWL_DEBUG_INFO("Multiple concurrent scan requests in parallel. "
  4144. "Ignoring second request.\n");
  4145. rc = -EIO;
  4146. goto done;
  4147. }
  4148. if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
  4149. IWL_DEBUG_SCAN("Aborting scan due to device shutdown\n");
  4150. goto done;
  4151. }
  4152. if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
  4153. IWL_DEBUG_HC("Scan request while abort pending. Queuing.\n");
  4154. goto done;
  4155. }
  4156. if (iwl_is_rfkill(priv)) {
  4157. IWL_DEBUG_HC("Aborting scan due to RF Kill activation\n");
  4158. goto done;
  4159. }
  4160. if (!test_bit(STATUS_READY, &priv->status)) {
  4161. IWL_DEBUG_HC("Scan request while uninitialized. Queuing.\n");
  4162. goto done;
  4163. }
  4164. if (!priv->scan_bands) {
  4165. IWL_DEBUG_HC("Aborting scan due to no requested bands\n");
  4166. goto done;
  4167. }
  4168. if (!priv->scan) {
  4169. priv->scan = kmalloc(sizeof(struct iwl3945_scan_cmd) +
  4170. IWL_MAX_SCAN_SIZE, GFP_KERNEL);
  4171. if (!priv->scan) {
  4172. rc = -ENOMEM;
  4173. goto done;
  4174. }
  4175. }
  4176. scan = priv->scan;
  4177. memset(scan, 0, sizeof(struct iwl3945_scan_cmd) + IWL_MAX_SCAN_SIZE);
  4178. scan->quiet_plcp_th = IWL_PLCP_QUIET_THRESH;
  4179. scan->quiet_time = IWL_ACTIVE_QUIET_TIME;
  4180. if (iwl3945_is_associated(priv)) {
  4181. u16 interval = 0;
  4182. u32 extra;
  4183. u32 suspend_time = 100;
  4184. u32 scan_suspend_time = 100;
  4185. unsigned long flags;
  4186. IWL_DEBUG_INFO("Scanning while associated...\n");
  4187. spin_lock_irqsave(&priv->lock, flags);
  4188. interval = priv->beacon_int;
  4189. spin_unlock_irqrestore(&priv->lock, flags);
  4190. scan->suspend_time = 0;
  4191. scan->max_out_time = cpu_to_le32(200 * 1024);
  4192. if (!interval)
  4193. interval = suspend_time;
  4194. /*
  4195. * suspend time format:
  4196. * 0-19: beacon interval in usec (time before exec.)
  4197. * 20-23: 0
  4198. * 24-31: number of beacons (suspend between channels)
  4199. */
  4200. extra = (suspend_time / interval) << 24;
  4201. scan_suspend_time = 0xFF0FFFFF &
  4202. (extra | ((suspend_time % interval) * 1024));
  4203. scan->suspend_time = cpu_to_le32(scan_suspend_time);
  4204. IWL_DEBUG_SCAN("suspend_time 0x%X beacon interval %d\n",
  4205. scan_suspend_time, interval);
  4206. }
  4207. /* We should add the ability for user to lock to PASSIVE ONLY */
  4208. if (priv->one_direct_scan) {
  4209. IWL_DEBUG_SCAN
  4210. ("Kicking off one direct scan for '%s'\n",
  4211. print_ssid(ssid, priv->direct_ssid,
  4212. priv->direct_ssid_len));
  4213. scan->direct_scan[0].id = WLAN_EID_SSID;
  4214. scan->direct_scan[0].len = priv->direct_ssid_len;
  4215. memcpy(scan->direct_scan[0].ssid,
  4216. priv->direct_ssid, priv->direct_ssid_len);
  4217. n_probes++;
  4218. } else
  4219. IWL_DEBUG_SCAN("Kicking off one indirect scan.\n");
  4220. /* We don't build a direct scan probe request; the uCode will do
  4221. * that based on the direct_mask added to each channel entry */
  4222. scan->tx_cmd.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK;
  4223. scan->tx_cmd.sta_id = priv->hw_params.bcast_sta_id;
  4224. scan->tx_cmd.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
  4225. /* flags + rate selection */
  4226. if (priv->scan_bands & BIT(IEEE80211_BAND_2GHZ)) {
  4227. scan->flags = RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK;
  4228. scan->tx_cmd.rate = IWL_RATE_1M_PLCP;
  4229. scan->good_CRC_th = 0;
  4230. band = IEEE80211_BAND_2GHZ;
  4231. } else if (priv->scan_bands & BIT(IEEE80211_BAND_5GHZ)) {
  4232. scan->tx_cmd.rate = IWL_RATE_6M_PLCP;
  4233. scan->good_CRC_th = IWL_GOOD_CRC_TH;
  4234. band = IEEE80211_BAND_5GHZ;
  4235. } else {
  4236. IWL_WARN(priv, "Invalid scan band count\n");
  4237. goto done;
  4238. }
  4239. scan->tx_cmd.len = cpu_to_le16(
  4240. iwl_fill_probe_req(priv, band,
  4241. (struct ieee80211_mgmt *)scan->data,
  4242. IWL_MAX_SCAN_SIZE - sizeof(*scan)));
  4243. /* select Rx antennas */
  4244. scan->flags |= iwl3945_get_antenna_flags(priv);
  4245. if (priv->iw_mode == NL80211_IFTYPE_MONITOR)
  4246. scan->filter_flags = RXON_FILTER_PROMISC_MSK;
  4247. scan->channel_count =
  4248. iwl3945_get_channels_for_scan(priv, band, 1, /* active */
  4249. n_probes,
  4250. (void *)&scan->data[le16_to_cpu(scan->tx_cmd.len)]);
  4251. if (scan->channel_count == 0) {
  4252. IWL_DEBUG_SCAN("channel count %d\n", scan->channel_count);
  4253. goto done;
  4254. }
  4255. cmd.len += le16_to_cpu(scan->tx_cmd.len) +
  4256. scan->channel_count * sizeof(struct iwl3945_scan_channel);
  4257. cmd.data = scan;
  4258. scan->len = cpu_to_le16(cmd.len);
  4259. set_bit(STATUS_SCAN_HW, &priv->status);
  4260. rc = iwl_send_cmd_sync(priv, &cmd);
  4261. if (rc)
  4262. goto done;
  4263. queue_delayed_work(priv->workqueue, &priv->scan_check,
  4264. IWL_SCAN_CHECK_WATCHDOG);
  4265. mutex_unlock(&priv->mutex);
  4266. return;
  4267. done:
  4268. /* can not perform scan make sure we clear scanning
  4269. * bits from status so next scan request can be performed.
  4270. * if we dont clear scanning status bit here all next scan
  4271. * will fail
  4272. */
  4273. clear_bit(STATUS_SCAN_HW, &priv->status);
  4274. clear_bit(STATUS_SCANNING, &priv->status);
  4275. /* inform mac80211 scan aborted */
  4276. queue_work(priv->workqueue, &priv->scan_completed);
  4277. mutex_unlock(&priv->mutex);
  4278. }
  4279. static void iwl3945_bg_up(struct work_struct *data)
  4280. {
  4281. struct iwl_priv *priv = container_of(data, struct iwl_priv, up);
  4282. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  4283. return;
  4284. mutex_lock(&priv->mutex);
  4285. __iwl3945_up(priv);
  4286. mutex_unlock(&priv->mutex);
  4287. iwl_rfkill_set_hw_state(priv);
  4288. }
  4289. static void iwl3945_bg_restart(struct work_struct *data)
  4290. {
  4291. struct iwl_priv *priv = container_of(data, struct iwl_priv, restart);
  4292. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  4293. return;
  4294. iwl3945_down(priv);
  4295. queue_work(priv->workqueue, &priv->up);
  4296. }
  4297. static void iwl3945_bg_rx_replenish(struct work_struct *data)
  4298. {
  4299. struct iwl_priv *priv =
  4300. container_of(data, struct iwl_priv, rx_replenish);
  4301. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  4302. return;
  4303. mutex_lock(&priv->mutex);
  4304. iwl3945_rx_replenish(priv);
  4305. mutex_unlock(&priv->mutex);
  4306. }
  4307. #define IWL_DELAY_NEXT_SCAN (HZ*2)
  4308. static void iwl3945_post_associate(struct iwl_priv *priv)
  4309. {
  4310. int rc = 0;
  4311. struct ieee80211_conf *conf = NULL;
  4312. if (priv->iw_mode == NL80211_IFTYPE_AP) {
  4313. IWL_ERR(priv, "%s Should not be called in AP mode\n", __func__);
  4314. return;
  4315. }
  4316. IWL_DEBUG_ASSOC("Associated as %d to: %pM\n",
  4317. priv->assoc_id, priv->active39_rxon.bssid_addr);
  4318. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  4319. return;
  4320. if (!priv->vif || !priv->is_open)
  4321. return;
  4322. iwl_scan_cancel_timeout(priv, 200);
  4323. conf = ieee80211_get_hw_conf(priv->hw);
  4324. priv->staging39_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  4325. iwl3945_commit_rxon(priv);
  4326. memset(&priv->rxon_timing, 0, sizeof(struct iwl_rxon_time_cmd));
  4327. iwl3945_setup_rxon_timing(priv);
  4328. rc = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING,
  4329. sizeof(priv->rxon_timing), &priv->rxon_timing);
  4330. if (rc)
  4331. IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
  4332. "Attempting to continue.\n");
  4333. priv->staging39_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
  4334. priv->staging39_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
  4335. IWL_DEBUG_ASSOC("assoc id %d beacon interval %d\n",
  4336. priv->assoc_id, priv->beacon_int);
  4337. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
  4338. priv->staging39_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
  4339. else
  4340. priv->staging39_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
  4341. if (priv->staging39_rxon.flags & RXON_FLG_BAND_24G_MSK) {
  4342. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
  4343. priv->staging39_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
  4344. else
  4345. priv->staging39_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  4346. if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
  4347. priv->staging39_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  4348. }
  4349. iwl3945_commit_rxon(priv);
  4350. switch (priv->iw_mode) {
  4351. case NL80211_IFTYPE_STATION:
  4352. iwl3945_rate_scale_init(priv->hw, IWL_AP_ID);
  4353. break;
  4354. case NL80211_IFTYPE_ADHOC:
  4355. priv->assoc_id = 1;
  4356. iwl3945_add_station(priv, priv->bssid, 0, 0);
  4357. iwl3945_sync_sta(priv, IWL_STA_ID,
  4358. (priv->band == IEEE80211_BAND_5GHZ) ?
  4359. IWL_RATE_6M_PLCP : IWL_RATE_1M_PLCP,
  4360. CMD_ASYNC);
  4361. iwl3945_rate_scale_init(priv->hw, IWL_STA_ID);
  4362. iwl3945_send_beacon_cmd(priv);
  4363. break;
  4364. default:
  4365. IWL_ERR(priv, "%s Should not be called in %d mode\n",
  4366. __func__, priv->iw_mode);
  4367. break;
  4368. }
  4369. iwl3945_activate_qos(priv, 0);
  4370. /* we have just associated, don't start scan too early */
  4371. priv->next_scan_jiffies = jiffies + IWL_DELAY_NEXT_SCAN;
  4372. }
  4373. static int iwl3945_mac_config(struct ieee80211_hw *hw, u32 changed);
  4374. /*****************************************************************************
  4375. *
  4376. * mac80211 entry point functions
  4377. *
  4378. *****************************************************************************/
  4379. #define UCODE_READY_TIMEOUT (2 * HZ)
  4380. static int iwl3945_mac_start(struct ieee80211_hw *hw)
  4381. {
  4382. struct iwl_priv *priv = hw->priv;
  4383. int ret;
  4384. IWL_DEBUG_MAC80211("enter\n");
  4385. /* we should be verifying the device is ready to be opened */
  4386. mutex_lock(&priv->mutex);
  4387. memset(&priv->staging39_rxon, 0, sizeof(struct iwl3945_rxon_cmd));
  4388. /* fetch ucode file from disk, alloc and copy to bus-master buffers ...
  4389. * ucode filename and max sizes are card-specific. */
  4390. if (!priv->ucode_code.len) {
  4391. ret = iwl3945_read_ucode(priv);
  4392. if (ret) {
  4393. IWL_ERR(priv, "Could not read microcode: %d\n", ret);
  4394. mutex_unlock(&priv->mutex);
  4395. goto out_release_irq;
  4396. }
  4397. }
  4398. ret = __iwl3945_up(priv);
  4399. mutex_unlock(&priv->mutex);
  4400. iwl_rfkill_set_hw_state(priv);
  4401. if (ret)
  4402. goto out_release_irq;
  4403. IWL_DEBUG_INFO("Start UP work.\n");
  4404. if (test_bit(STATUS_IN_SUSPEND, &priv->status))
  4405. return 0;
  4406. /* Wait for START_ALIVE from ucode. Otherwise callbacks from
  4407. * mac80211 will not be run successfully. */
  4408. ret = wait_event_interruptible_timeout(priv->wait_command_queue,
  4409. test_bit(STATUS_READY, &priv->status),
  4410. UCODE_READY_TIMEOUT);
  4411. if (!ret) {
  4412. if (!test_bit(STATUS_READY, &priv->status)) {
  4413. IWL_ERR(priv,
  4414. "Wait for START_ALIVE timeout after %dms.\n",
  4415. jiffies_to_msecs(UCODE_READY_TIMEOUT));
  4416. ret = -ETIMEDOUT;
  4417. goto out_release_irq;
  4418. }
  4419. }
  4420. /* ucode is running and will send rfkill notifications,
  4421. * no need to poll the killswitch state anymore */
  4422. cancel_delayed_work(&priv->rfkill_poll);
  4423. priv->is_open = 1;
  4424. IWL_DEBUG_MAC80211("leave\n");
  4425. return 0;
  4426. out_release_irq:
  4427. priv->is_open = 0;
  4428. IWL_DEBUG_MAC80211("leave - failed\n");
  4429. return ret;
  4430. }
  4431. static void iwl3945_mac_stop(struct ieee80211_hw *hw)
  4432. {
  4433. struct iwl_priv *priv = hw->priv;
  4434. IWL_DEBUG_MAC80211("enter\n");
  4435. if (!priv->is_open) {
  4436. IWL_DEBUG_MAC80211("leave - skip\n");
  4437. return;
  4438. }
  4439. priv->is_open = 0;
  4440. if (iwl_is_ready_rf(priv)) {
  4441. /* stop mac, cancel any scan request and clear
  4442. * RXON_FILTER_ASSOC_MSK BIT
  4443. */
  4444. mutex_lock(&priv->mutex);
  4445. iwl_scan_cancel_timeout(priv, 100);
  4446. mutex_unlock(&priv->mutex);
  4447. }
  4448. iwl3945_down(priv);
  4449. flush_workqueue(priv->workqueue);
  4450. /* start polling the killswitch state again */
  4451. queue_delayed_work(priv->workqueue, &priv->rfkill_poll,
  4452. round_jiffies_relative(2 * HZ));
  4453. IWL_DEBUG_MAC80211("leave\n");
  4454. }
  4455. static int iwl3945_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
  4456. {
  4457. struct iwl_priv *priv = hw->priv;
  4458. IWL_DEBUG_MAC80211("enter\n");
  4459. IWL_DEBUG_TX("dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
  4460. ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
  4461. if (iwl3945_tx_skb(priv, skb))
  4462. dev_kfree_skb_any(skb);
  4463. IWL_DEBUG_MAC80211("leave\n");
  4464. return NETDEV_TX_OK;
  4465. }
  4466. static int iwl3945_mac_add_interface(struct ieee80211_hw *hw,
  4467. struct ieee80211_if_init_conf *conf)
  4468. {
  4469. struct iwl_priv *priv = hw->priv;
  4470. unsigned long flags;
  4471. IWL_DEBUG_MAC80211("enter: type %d\n", conf->type);
  4472. if (priv->vif) {
  4473. IWL_DEBUG_MAC80211("leave - vif != NULL\n");
  4474. return -EOPNOTSUPP;
  4475. }
  4476. spin_lock_irqsave(&priv->lock, flags);
  4477. priv->vif = conf->vif;
  4478. priv->iw_mode = conf->type;
  4479. spin_unlock_irqrestore(&priv->lock, flags);
  4480. mutex_lock(&priv->mutex);
  4481. if (conf->mac_addr) {
  4482. IWL_DEBUG_MAC80211("Set: %pM\n", conf->mac_addr);
  4483. memcpy(priv->mac_addr, conf->mac_addr, ETH_ALEN);
  4484. }
  4485. if (iwl_is_ready(priv))
  4486. iwl3945_set_mode(priv, conf->type);
  4487. mutex_unlock(&priv->mutex);
  4488. IWL_DEBUG_MAC80211("leave\n");
  4489. return 0;
  4490. }
  4491. /**
  4492. * iwl3945_mac_config - mac80211 config callback
  4493. *
  4494. * We ignore conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME since it seems to
  4495. * be set inappropriately and the driver currently sets the hardware up to
  4496. * use it whenever needed.
  4497. */
  4498. static int iwl3945_mac_config(struct ieee80211_hw *hw, u32 changed)
  4499. {
  4500. struct iwl_priv *priv = hw->priv;
  4501. const struct iwl_channel_info *ch_info;
  4502. struct ieee80211_conf *conf = &hw->conf;
  4503. unsigned long flags;
  4504. int ret = 0;
  4505. mutex_lock(&priv->mutex);
  4506. IWL_DEBUG_MAC80211("enter to channel %d\n", conf->channel->hw_value);
  4507. if (!iwl_is_ready(priv)) {
  4508. IWL_DEBUG_MAC80211("leave - not ready\n");
  4509. ret = -EIO;
  4510. goto out;
  4511. }
  4512. if (unlikely(!iwl3945_mod_params.disable_hw_scan &&
  4513. test_bit(STATUS_SCANNING, &priv->status))) {
  4514. IWL_DEBUG_MAC80211("leave - scanning\n");
  4515. set_bit(STATUS_CONF_PENDING, &priv->status);
  4516. mutex_unlock(&priv->mutex);
  4517. return 0;
  4518. }
  4519. spin_lock_irqsave(&priv->lock, flags);
  4520. ch_info = iwl3945_get_channel_info(priv, conf->channel->band,
  4521. conf->channel->hw_value);
  4522. if (!is_channel_valid(ch_info)) {
  4523. IWL_DEBUG_SCAN("Channel %d [%d] is INVALID for this band.\n",
  4524. conf->channel->hw_value, conf->channel->band);
  4525. IWL_DEBUG_MAC80211("leave - invalid channel\n");
  4526. spin_unlock_irqrestore(&priv->lock, flags);
  4527. ret = -EINVAL;
  4528. goto out;
  4529. }
  4530. iwl3945_set_rxon_channel(priv, conf->channel->band, conf->channel->hw_value);
  4531. iwl3945_set_flags_for_phymode(priv, conf->channel->band);
  4532. /* The list of supported rates and rate mask can be different
  4533. * for each phymode; since the phymode may have changed, reset
  4534. * the rate mask to what mac80211 lists */
  4535. iwl3945_set_rate(priv);
  4536. spin_unlock_irqrestore(&priv->lock, flags);
  4537. #ifdef IEEE80211_CONF_CHANNEL_SWITCH
  4538. if (conf->flags & IEEE80211_CONF_CHANNEL_SWITCH) {
  4539. iwl3945_hw_channel_switch(priv, conf->channel);
  4540. goto out;
  4541. }
  4542. #endif
  4543. iwl3945_radio_kill_sw(priv, !conf->radio_enabled);
  4544. if (!conf->radio_enabled) {
  4545. IWL_DEBUG_MAC80211("leave - radio disabled\n");
  4546. goto out;
  4547. }
  4548. if (iwl_is_rfkill(priv)) {
  4549. IWL_DEBUG_MAC80211("leave - RF kill\n");
  4550. ret = -EIO;
  4551. goto out;
  4552. }
  4553. iwl3945_set_rate(priv);
  4554. if (memcmp(&priv->active39_rxon,
  4555. &priv->staging39_rxon, sizeof(priv->staging39_rxon)))
  4556. iwl3945_commit_rxon(priv);
  4557. else
  4558. IWL_DEBUG_INFO("No re-sending same RXON configuration.\n");
  4559. IWL_DEBUG_MAC80211("leave\n");
  4560. out:
  4561. clear_bit(STATUS_CONF_PENDING, &priv->status);
  4562. mutex_unlock(&priv->mutex);
  4563. return ret;
  4564. }
  4565. static void iwl3945_config_ap(struct iwl_priv *priv)
  4566. {
  4567. int rc = 0;
  4568. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  4569. return;
  4570. /* The following should be done only at AP bring up */
  4571. if (!(iwl3945_is_associated(priv))) {
  4572. /* RXON - unassoc (to set timing command) */
  4573. priv->staging39_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  4574. iwl3945_commit_rxon(priv);
  4575. /* RXON Timing */
  4576. memset(&priv->rxon_timing, 0, sizeof(struct iwl_rxon_time_cmd));
  4577. iwl3945_setup_rxon_timing(priv);
  4578. rc = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING,
  4579. sizeof(priv->rxon_timing),
  4580. &priv->rxon_timing);
  4581. if (rc)
  4582. IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
  4583. "Attempting to continue.\n");
  4584. /* FIXME: what should be the assoc_id for AP? */
  4585. priv->staging39_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
  4586. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
  4587. priv->staging39_rxon.flags |=
  4588. RXON_FLG_SHORT_PREAMBLE_MSK;
  4589. else
  4590. priv->staging39_rxon.flags &=
  4591. ~RXON_FLG_SHORT_PREAMBLE_MSK;
  4592. if (priv->staging39_rxon.flags & RXON_FLG_BAND_24G_MSK) {
  4593. if (priv->assoc_capability &
  4594. WLAN_CAPABILITY_SHORT_SLOT_TIME)
  4595. priv->staging39_rxon.flags |=
  4596. RXON_FLG_SHORT_SLOT_MSK;
  4597. else
  4598. priv->staging39_rxon.flags &=
  4599. ~RXON_FLG_SHORT_SLOT_MSK;
  4600. if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
  4601. priv->staging39_rxon.flags &=
  4602. ~RXON_FLG_SHORT_SLOT_MSK;
  4603. }
  4604. /* restore RXON assoc */
  4605. priv->staging39_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
  4606. iwl3945_commit_rxon(priv);
  4607. iwl3945_add_station(priv, iwl_bcast_addr, 0, 0);
  4608. }
  4609. iwl3945_send_beacon_cmd(priv);
  4610. /* FIXME - we need to add code here to detect a totally new
  4611. * configuration, reset the AP, unassoc, rxon timing, assoc,
  4612. * clear sta table, add BCAST sta... */
  4613. }
  4614. static int iwl3945_mac_config_interface(struct ieee80211_hw *hw,
  4615. struct ieee80211_vif *vif,
  4616. struct ieee80211_if_conf *conf)
  4617. {
  4618. struct iwl_priv *priv = hw->priv;
  4619. int rc;
  4620. if (conf == NULL)
  4621. return -EIO;
  4622. if (priv->vif != vif) {
  4623. IWL_DEBUG_MAC80211("leave - priv->vif != vif\n");
  4624. return 0;
  4625. }
  4626. /* handle this temporarily here */
  4627. if (priv->iw_mode == NL80211_IFTYPE_ADHOC &&
  4628. conf->changed & IEEE80211_IFCC_BEACON) {
  4629. struct sk_buff *beacon = ieee80211_beacon_get(hw, vif);
  4630. if (!beacon)
  4631. return -ENOMEM;
  4632. mutex_lock(&priv->mutex);
  4633. rc = iwl3945_mac_beacon_update(hw, beacon);
  4634. mutex_unlock(&priv->mutex);
  4635. if (rc)
  4636. return rc;
  4637. }
  4638. if (!iwl_is_alive(priv))
  4639. return -EAGAIN;
  4640. mutex_lock(&priv->mutex);
  4641. if (conf->bssid)
  4642. IWL_DEBUG_MAC80211("bssid: %pM\n", conf->bssid);
  4643. /*
  4644. * very dubious code was here; the probe filtering flag is never set:
  4645. *
  4646. if (unlikely(test_bit(STATUS_SCANNING, &priv->status)) &&
  4647. !(priv->hw->flags & IEEE80211_HW_NO_PROBE_FILTERING)) {
  4648. */
  4649. if (priv->iw_mode == NL80211_IFTYPE_AP) {
  4650. if (!conf->bssid) {
  4651. conf->bssid = priv->mac_addr;
  4652. memcpy(priv->bssid, priv->mac_addr, ETH_ALEN);
  4653. IWL_DEBUG_MAC80211("bssid was set to: %pM\n",
  4654. conf->bssid);
  4655. }
  4656. if (priv->ibss_beacon)
  4657. dev_kfree_skb(priv->ibss_beacon);
  4658. priv->ibss_beacon = ieee80211_beacon_get(hw, vif);
  4659. }
  4660. if (iwl_is_rfkill(priv))
  4661. goto done;
  4662. if (conf->bssid && !is_zero_ether_addr(conf->bssid) &&
  4663. !is_multicast_ether_addr(conf->bssid)) {
  4664. /* If there is currently a HW scan going on in the background
  4665. * then we need to cancel it else the RXON below will fail. */
  4666. if (iwl_scan_cancel_timeout(priv, 100)) {
  4667. IWL_WARN(priv, "Aborted scan still in progress "
  4668. "after 100ms\n");
  4669. IWL_DEBUG_MAC80211("leaving - scan abort failed.\n");
  4670. mutex_unlock(&priv->mutex);
  4671. return -EAGAIN;
  4672. }
  4673. memcpy(priv->staging39_rxon.bssid_addr, conf->bssid, ETH_ALEN);
  4674. /* TODO: Audit driver for usage of these members and see
  4675. * if mac80211 deprecates them (priv->bssid looks like it
  4676. * shouldn't be there, but I haven't scanned the IBSS code
  4677. * to verify) - jpk */
  4678. memcpy(priv->bssid, conf->bssid, ETH_ALEN);
  4679. if (priv->iw_mode == NL80211_IFTYPE_AP)
  4680. iwl3945_config_ap(priv);
  4681. else {
  4682. rc = iwl3945_commit_rxon(priv);
  4683. if ((priv->iw_mode == NL80211_IFTYPE_STATION) && rc)
  4684. iwl3945_add_station(priv,
  4685. priv->active39_rxon.bssid_addr, 1, 0);
  4686. }
  4687. } else {
  4688. iwl_scan_cancel_timeout(priv, 100);
  4689. priv->staging39_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  4690. iwl3945_commit_rxon(priv);
  4691. }
  4692. done:
  4693. IWL_DEBUG_MAC80211("leave\n");
  4694. mutex_unlock(&priv->mutex);
  4695. return 0;
  4696. }
  4697. static void iwl3945_configure_filter(struct ieee80211_hw *hw,
  4698. unsigned int changed_flags,
  4699. unsigned int *total_flags,
  4700. int mc_count, struct dev_addr_list *mc_list)
  4701. {
  4702. struct iwl_priv *priv = hw->priv;
  4703. __le32 *filter_flags = &priv->staging39_rxon.filter_flags;
  4704. IWL_DEBUG_MAC80211("Enter: changed: 0x%x, total: 0x%x\n",
  4705. changed_flags, *total_flags);
  4706. if (changed_flags & (FIF_OTHER_BSS | FIF_PROMISC_IN_BSS)) {
  4707. if (*total_flags & (FIF_OTHER_BSS | FIF_PROMISC_IN_BSS))
  4708. *filter_flags |= RXON_FILTER_PROMISC_MSK;
  4709. else
  4710. *filter_flags &= ~RXON_FILTER_PROMISC_MSK;
  4711. }
  4712. if (changed_flags & FIF_ALLMULTI) {
  4713. if (*total_flags & FIF_ALLMULTI)
  4714. *filter_flags |= RXON_FILTER_ACCEPT_GRP_MSK;
  4715. else
  4716. *filter_flags &= ~RXON_FILTER_ACCEPT_GRP_MSK;
  4717. }
  4718. if (changed_flags & FIF_CONTROL) {
  4719. if (*total_flags & FIF_CONTROL)
  4720. *filter_flags |= RXON_FILTER_CTL2HOST_MSK;
  4721. else
  4722. *filter_flags &= ~RXON_FILTER_CTL2HOST_MSK;
  4723. }
  4724. if (changed_flags & FIF_BCN_PRBRESP_PROMISC) {
  4725. if (*total_flags & FIF_BCN_PRBRESP_PROMISC)
  4726. *filter_flags |= RXON_FILTER_BCON_AWARE_MSK;
  4727. else
  4728. *filter_flags &= ~RXON_FILTER_BCON_AWARE_MSK;
  4729. }
  4730. /* We avoid iwl_commit_rxon here to commit the new filter flags
  4731. * since mac80211 will call ieee80211_hw_config immediately.
  4732. * (mc_list is not supported at this time). Otherwise, we need to
  4733. * queue a background iwl_commit_rxon work.
  4734. */
  4735. *total_flags &= FIF_OTHER_BSS | FIF_ALLMULTI | FIF_PROMISC_IN_BSS |
  4736. FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL;
  4737. }
  4738. static void iwl3945_mac_remove_interface(struct ieee80211_hw *hw,
  4739. struct ieee80211_if_init_conf *conf)
  4740. {
  4741. struct iwl_priv *priv = hw->priv;
  4742. IWL_DEBUG_MAC80211("enter\n");
  4743. mutex_lock(&priv->mutex);
  4744. if (iwl_is_ready_rf(priv)) {
  4745. iwl_scan_cancel_timeout(priv, 100);
  4746. priv->staging39_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  4747. iwl3945_commit_rxon(priv);
  4748. }
  4749. if (priv->vif == conf->vif) {
  4750. priv->vif = NULL;
  4751. memset(priv->bssid, 0, ETH_ALEN);
  4752. }
  4753. mutex_unlock(&priv->mutex);
  4754. IWL_DEBUG_MAC80211("leave\n");
  4755. }
  4756. #define IWL_DELAY_NEXT_SCAN_AFTER_ASSOC (HZ*6)
  4757. static void iwl3945_bss_info_changed(struct ieee80211_hw *hw,
  4758. struct ieee80211_vif *vif,
  4759. struct ieee80211_bss_conf *bss_conf,
  4760. u32 changes)
  4761. {
  4762. struct iwl_priv *priv = hw->priv;
  4763. IWL_DEBUG_MAC80211("changes = 0x%X\n", changes);
  4764. if (changes & BSS_CHANGED_ERP_PREAMBLE) {
  4765. IWL_DEBUG_MAC80211("ERP_PREAMBLE %d\n",
  4766. bss_conf->use_short_preamble);
  4767. if (bss_conf->use_short_preamble)
  4768. priv->staging39_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
  4769. else
  4770. priv->staging39_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
  4771. }
  4772. if (changes & BSS_CHANGED_ERP_CTS_PROT) {
  4773. IWL_DEBUG_MAC80211("ERP_CTS %d\n", bss_conf->use_cts_prot);
  4774. if (bss_conf->use_cts_prot && (priv->band != IEEE80211_BAND_5GHZ))
  4775. priv->staging39_rxon.flags |= RXON_FLG_TGG_PROTECT_MSK;
  4776. else
  4777. priv->staging39_rxon.flags &= ~RXON_FLG_TGG_PROTECT_MSK;
  4778. }
  4779. if (changes & BSS_CHANGED_ASSOC) {
  4780. IWL_DEBUG_MAC80211("ASSOC %d\n", bss_conf->assoc);
  4781. /* This should never happen as this function should
  4782. * never be called from interrupt context. */
  4783. if (WARN_ON_ONCE(in_interrupt()))
  4784. return;
  4785. if (bss_conf->assoc) {
  4786. priv->assoc_id = bss_conf->aid;
  4787. priv->beacon_int = bss_conf->beacon_int;
  4788. priv->timestamp = bss_conf->timestamp;
  4789. priv->assoc_capability = bss_conf->assoc_capability;
  4790. priv->power_data.dtim_period = bss_conf->dtim_period;
  4791. priv->next_scan_jiffies = jiffies +
  4792. IWL_DELAY_NEXT_SCAN_AFTER_ASSOC;
  4793. mutex_lock(&priv->mutex);
  4794. iwl3945_post_associate(priv);
  4795. mutex_unlock(&priv->mutex);
  4796. } else {
  4797. priv->assoc_id = 0;
  4798. IWL_DEBUG_MAC80211("DISASSOC %d\n", bss_conf->assoc);
  4799. }
  4800. } else if (changes && iwl3945_is_associated(priv) && priv->assoc_id) {
  4801. IWL_DEBUG_MAC80211("Associated Changes %d\n", changes);
  4802. iwl3945_send_rxon_assoc(priv);
  4803. }
  4804. }
  4805. static int iwl3945_mac_hw_scan(struct ieee80211_hw *hw, u8 *ssid, size_t len)
  4806. {
  4807. int rc = 0;
  4808. unsigned long flags;
  4809. struct iwl_priv *priv = hw->priv;
  4810. DECLARE_SSID_BUF(ssid_buf);
  4811. IWL_DEBUG_MAC80211("enter\n");
  4812. mutex_lock(&priv->mutex);
  4813. spin_lock_irqsave(&priv->lock, flags);
  4814. if (!iwl_is_ready_rf(priv)) {
  4815. rc = -EIO;
  4816. IWL_DEBUG_MAC80211("leave - not ready or exit pending\n");
  4817. goto out_unlock;
  4818. }
  4819. /* we don't schedule scan within next_scan_jiffies period */
  4820. if (priv->next_scan_jiffies &&
  4821. time_after(priv->next_scan_jiffies, jiffies)) {
  4822. rc = -EAGAIN;
  4823. goto out_unlock;
  4824. }
  4825. /* if we just finished scan ask for delay for a broadcast scan */
  4826. if ((len == 0) && priv->last_scan_jiffies &&
  4827. time_after(priv->last_scan_jiffies + IWL_DELAY_NEXT_SCAN,
  4828. jiffies)) {
  4829. rc = -EAGAIN;
  4830. goto out_unlock;
  4831. }
  4832. if (len) {
  4833. IWL_DEBUG_SCAN("direct scan for %s [%d]\n ",
  4834. print_ssid(ssid_buf, ssid, len), (int)len);
  4835. priv->one_direct_scan = 1;
  4836. priv->direct_ssid_len = (u8)
  4837. min((u8) len, (u8) IW_ESSID_MAX_SIZE);
  4838. memcpy(priv->direct_ssid, ssid, priv->direct_ssid_len);
  4839. } else
  4840. priv->one_direct_scan = 0;
  4841. rc = iwl3945_scan_initiate(priv);
  4842. IWL_DEBUG_MAC80211("leave\n");
  4843. out_unlock:
  4844. spin_unlock_irqrestore(&priv->lock, flags);
  4845. mutex_unlock(&priv->mutex);
  4846. return rc;
  4847. }
  4848. static int iwl3945_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
  4849. struct ieee80211_vif *vif,
  4850. struct ieee80211_sta *sta,
  4851. struct ieee80211_key_conf *key)
  4852. {
  4853. struct iwl_priv *priv = hw->priv;
  4854. const u8 *addr;
  4855. int ret;
  4856. u8 sta_id;
  4857. IWL_DEBUG_MAC80211("enter\n");
  4858. if (iwl3945_mod_params.sw_crypto) {
  4859. IWL_DEBUG_MAC80211("leave - hwcrypto disabled\n");
  4860. return -EOPNOTSUPP;
  4861. }
  4862. addr = sta ? sta->addr : iwl_bcast_addr;
  4863. sta_id = iwl3945_hw_find_station(priv, addr);
  4864. if (sta_id == IWL_INVALID_STATION) {
  4865. IWL_DEBUG_MAC80211("leave - %pM not in station map.\n",
  4866. addr);
  4867. return -EINVAL;
  4868. }
  4869. mutex_lock(&priv->mutex);
  4870. iwl_scan_cancel_timeout(priv, 100);
  4871. switch (cmd) {
  4872. case SET_KEY:
  4873. ret = iwl3945_update_sta_key_info(priv, key, sta_id);
  4874. if (!ret) {
  4875. iwl3945_set_rxon_hwcrypto(priv, 1);
  4876. iwl3945_commit_rxon(priv);
  4877. key->hw_key_idx = sta_id;
  4878. IWL_DEBUG_MAC80211("set_key success, using hwcrypto\n");
  4879. key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
  4880. }
  4881. break;
  4882. case DISABLE_KEY:
  4883. ret = iwl3945_clear_sta_key_info(priv, sta_id);
  4884. if (!ret) {
  4885. iwl3945_set_rxon_hwcrypto(priv, 0);
  4886. iwl3945_commit_rxon(priv);
  4887. IWL_DEBUG_MAC80211("disable hwcrypto key\n");
  4888. }
  4889. break;
  4890. default:
  4891. ret = -EINVAL;
  4892. }
  4893. IWL_DEBUG_MAC80211("leave\n");
  4894. mutex_unlock(&priv->mutex);
  4895. return ret;
  4896. }
  4897. static int iwl3945_mac_conf_tx(struct ieee80211_hw *hw, u16 queue,
  4898. const struct ieee80211_tx_queue_params *params)
  4899. {
  4900. struct iwl_priv *priv = hw->priv;
  4901. unsigned long flags;
  4902. int q;
  4903. IWL_DEBUG_MAC80211("enter\n");
  4904. if (!iwl_is_ready_rf(priv)) {
  4905. IWL_DEBUG_MAC80211("leave - RF not ready\n");
  4906. return -EIO;
  4907. }
  4908. if (queue >= AC_NUM) {
  4909. IWL_DEBUG_MAC80211("leave - queue >= AC_NUM %d\n", queue);
  4910. return 0;
  4911. }
  4912. q = AC_NUM - 1 - queue;
  4913. spin_lock_irqsave(&priv->lock, flags);
  4914. priv->qos_data.def_qos_parm.ac[q].cw_min = cpu_to_le16(params->cw_min);
  4915. priv->qos_data.def_qos_parm.ac[q].cw_max = cpu_to_le16(params->cw_max);
  4916. priv->qos_data.def_qos_parm.ac[q].aifsn = params->aifs;
  4917. priv->qos_data.def_qos_parm.ac[q].edca_txop =
  4918. cpu_to_le16((params->txop * 32));
  4919. priv->qos_data.def_qos_parm.ac[q].reserved1 = 0;
  4920. priv->qos_data.qos_active = 1;
  4921. spin_unlock_irqrestore(&priv->lock, flags);
  4922. mutex_lock(&priv->mutex);
  4923. if (priv->iw_mode == NL80211_IFTYPE_AP)
  4924. iwl3945_activate_qos(priv, 1);
  4925. else if (priv->assoc_id && iwl3945_is_associated(priv))
  4926. iwl3945_activate_qos(priv, 0);
  4927. mutex_unlock(&priv->mutex);
  4928. IWL_DEBUG_MAC80211("leave\n");
  4929. return 0;
  4930. }
  4931. static int iwl3945_mac_get_tx_stats(struct ieee80211_hw *hw,
  4932. struct ieee80211_tx_queue_stats *stats)
  4933. {
  4934. struct iwl_priv *priv = hw->priv;
  4935. int i, avail;
  4936. struct iwl_tx_queue *txq;
  4937. struct iwl_queue *q;
  4938. unsigned long flags;
  4939. IWL_DEBUG_MAC80211("enter\n");
  4940. if (!iwl_is_ready_rf(priv)) {
  4941. IWL_DEBUG_MAC80211("leave - RF not ready\n");
  4942. return -EIO;
  4943. }
  4944. spin_lock_irqsave(&priv->lock, flags);
  4945. for (i = 0; i < AC_NUM; i++) {
  4946. txq = &priv->txq[i];
  4947. q = &txq->q;
  4948. avail = iwl_queue_space(q);
  4949. stats[i].len = q->n_window - avail;
  4950. stats[i].limit = q->n_window - q->high_mark;
  4951. stats[i].count = q->n_window;
  4952. }
  4953. spin_unlock_irqrestore(&priv->lock, flags);
  4954. IWL_DEBUG_MAC80211("leave\n");
  4955. return 0;
  4956. }
  4957. static void iwl3945_mac_reset_tsf(struct ieee80211_hw *hw)
  4958. {
  4959. struct iwl_priv *priv = hw->priv;
  4960. unsigned long flags;
  4961. mutex_lock(&priv->mutex);
  4962. IWL_DEBUG_MAC80211("enter\n");
  4963. iwl_reset_qos(priv);
  4964. spin_lock_irqsave(&priv->lock, flags);
  4965. priv->assoc_id = 0;
  4966. priv->assoc_capability = 0;
  4967. /* new association get rid of ibss beacon skb */
  4968. if (priv->ibss_beacon)
  4969. dev_kfree_skb(priv->ibss_beacon);
  4970. priv->ibss_beacon = NULL;
  4971. priv->beacon_int = priv->hw->conf.beacon_int;
  4972. priv->timestamp = 0;
  4973. if ((priv->iw_mode == NL80211_IFTYPE_STATION))
  4974. priv->beacon_int = 0;
  4975. spin_unlock_irqrestore(&priv->lock, flags);
  4976. if (!iwl_is_ready_rf(priv)) {
  4977. IWL_DEBUG_MAC80211("leave - not ready\n");
  4978. mutex_unlock(&priv->mutex);
  4979. return;
  4980. }
  4981. /* we are restarting association process
  4982. * clear RXON_FILTER_ASSOC_MSK bit
  4983. */
  4984. if (priv->iw_mode != NL80211_IFTYPE_AP) {
  4985. iwl_scan_cancel_timeout(priv, 100);
  4986. priv->staging39_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  4987. iwl3945_commit_rxon(priv);
  4988. }
  4989. /* Per mac80211.h: This is only used in IBSS mode... */
  4990. if (priv->iw_mode != NL80211_IFTYPE_ADHOC) {
  4991. IWL_DEBUG_MAC80211("leave - not in IBSS\n");
  4992. mutex_unlock(&priv->mutex);
  4993. return;
  4994. }
  4995. iwl3945_set_rate(priv);
  4996. mutex_unlock(&priv->mutex);
  4997. IWL_DEBUG_MAC80211("leave\n");
  4998. }
  4999. static int iwl3945_mac_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb)
  5000. {
  5001. struct iwl_priv *priv = hw->priv;
  5002. unsigned long flags;
  5003. IWL_DEBUG_MAC80211("enter\n");
  5004. if (!iwl_is_ready_rf(priv)) {
  5005. IWL_DEBUG_MAC80211("leave - RF not ready\n");
  5006. return -EIO;
  5007. }
  5008. if (priv->iw_mode != NL80211_IFTYPE_ADHOC) {
  5009. IWL_DEBUG_MAC80211("leave - not IBSS\n");
  5010. return -EIO;
  5011. }
  5012. spin_lock_irqsave(&priv->lock, flags);
  5013. if (priv->ibss_beacon)
  5014. dev_kfree_skb(priv->ibss_beacon);
  5015. priv->ibss_beacon = skb;
  5016. priv->assoc_id = 0;
  5017. IWL_DEBUG_MAC80211("leave\n");
  5018. spin_unlock_irqrestore(&priv->lock, flags);
  5019. iwl_reset_qos(priv);
  5020. iwl3945_post_associate(priv);
  5021. return 0;
  5022. }
  5023. /*****************************************************************************
  5024. *
  5025. * sysfs attributes
  5026. *
  5027. *****************************************************************************/
  5028. #ifdef CONFIG_IWL3945_DEBUG
  5029. /*
  5030. * The following adds a new attribute to the sysfs representation
  5031. * of this device driver (i.e. a new file in /sys/bus/pci/drivers/iwl/)
  5032. * used for controlling the debug level.
  5033. *
  5034. * See the level definitions in iwl for details.
  5035. */
  5036. static ssize_t show_debug_level(struct device *d,
  5037. struct device_attribute *attr, char *buf)
  5038. {
  5039. struct iwl_priv *priv = d->driver_data;
  5040. return sprintf(buf, "0x%08X\n", priv->debug_level);
  5041. }
  5042. static ssize_t store_debug_level(struct device *d,
  5043. struct device_attribute *attr,
  5044. const char *buf, size_t count)
  5045. {
  5046. struct iwl_priv *priv = d->driver_data;
  5047. unsigned long val;
  5048. int ret;
  5049. ret = strict_strtoul(buf, 0, &val);
  5050. if (ret)
  5051. IWL_INFO(priv, "%s is not in hex or decimal form.\n", buf);
  5052. else
  5053. priv->debug_level = val;
  5054. return strnlen(buf, count);
  5055. }
  5056. static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO,
  5057. show_debug_level, store_debug_level);
  5058. #endif /* CONFIG_IWL3945_DEBUG */
  5059. static ssize_t show_temperature(struct device *d,
  5060. struct device_attribute *attr, char *buf)
  5061. {
  5062. struct iwl_priv *priv = (struct iwl_priv *)d->driver_data;
  5063. if (!iwl_is_alive(priv))
  5064. return -EAGAIN;
  5065. return sprintf(buf, "%d\n", iwl3945_hw_get_temperature(priv));
  5066. }
  5067. static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
  5068. static ssize_t show_tx_power(struct device *d,
  5069. struct device_attribute *attr, char *buf)
  5070. {
  5071. struct iwl_priv *priv = (struct iwl_priv *)d->driver_data;
  5072. return sprintf(buf, "%d\n", priv->tx_power_user_lmt);
  5073. }
  5074. static ssize_t store_tx_power(struct device *d,
  5075. struct device_attribute *attr,
  5076. const char *buf, size_t count)
  5077. {
  5078. struct iwl_priv *priv = (struct iwl_priv *)d->driver_data;
  5079. char *p = (char *)buf;
  5080. u32 val;
  5081. val = simple_strtoul(p, &p, 10);
  5082. if (p == buf)
  5083. IWL_INFO(priv, ": %s is not in decimal form.\n", buf);
  5084. else
  5085. iwl3945_hw_reg_set_txpower(priv, val);
  5086. return count;
  5087. }
  5088. static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
  5089. static ssize_t show_flags(struct device *d,
  5090. struct device_attribute *attr, char *buf)
  5091. {
  5092. struct iwl_priv *priv = (struct iwl_priv *)d->driver_data;
  5093. return sprintf(buf, "0x%04X\n", priv->active39_rxon.flags);
  5094. }
  5095. static ssize_t store_flags(struct device *d,
  5096. struct device_attribute *attr,
  5097. const char *buf, size_t count)
  5098. {
  5099. struct iwl_priv *priv = (struct iwl_priv *)d->driver_data;
  5100. u32 flags = simple_strtoul(buf, NULL, 0);
  5101. mutex_lock(&priv->mutex);
  5102. if (le32_to_cpu(priv->staging39_rxon.flags) != flags) {
  5103. /* Cancel any currently running scans... */
  5104. if (iwl_scan_cancel_timeout(priv, 100))
  5105. IWL_WARN(priv, "Could not cancel scan.\n");
  5106. else {
  5107. IWL_DEBUG_INFO("Committing rxon.flags = 0x%04X\n",
  5108. flags);
  5109. priv->staging39_rxon.flags = cpu_to_le32(flags);
  5110. iwl3945_commit_rxon(priv);
  5111. }
  5112. }
  5113. mutex_unlock(&priv->mutex);
  5114. return count;
  5115. }
  5116. static DEVICE_ATTR(flags, S_IWUSR | S_IRUGO, show_flags, store_flags);
  5117. static ssize_t show_filter_flags(struct device *d,
  5118. struct device_attribute *attr, char *buf)
  5119. {
  5120. struct iwl_priv *priv = (struct iwl_priv *)d->driver_data;
  5121. return sprintf(buf, "0x%04X\n",
  5122. le32_to_cpu(priv->active39_rxon.filter_flags));
  5123. }
  5124. static ssize_t store_filter_flags(struct device *d,
  5125. struct device_attribute *attr,
  5126. const char *buf, size_t count)
  5127. {
  5128. struct iwl_priv *priv = (struct iwl_priv *)d->driver_data;
  5129. u32 filter_flags = simple_strtoul(buf, NULL, 0);
  5130. mutex_lock(&priv->mutex);
  5131. if (le32_to_cpu(priv->staging39_rxon.filter_flags) != filter_flags) {
  5132. /* Cancel any currently running scans... */
  5133. if (iwl_scan_cancel_timeout(priv, 100))
  5134. IWL_WARN(priv, "Could not cancel scan.\n");
  5135. else {
  5136. IWL_DEBUG_INFO("Committing rxon.filter_flags = "
  5137. "0x%04X\n", filter_flags);
  5138. priv->staging39_rxon.filter_flags =
  5139. cpu_to_le32(filter_flags);
  5140. iwl3945_commit_rxon(priv);
  5141. }
  5142. }
  5143. mutex_unlock(&priv->mutex);
  5144. return count;
  5145. }
  5146. static DEVICE_ATTR(filter_flags, S_IWUSR | S_IRUGO, show_filter_flags,
  5147. store_filter_flags);
  5148. #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
  5149. static ssize_t show_measurement(struct device *d,
  5150. struct device_attribute *attr, char *buf)
  5151. {
  5152. struct iwl_priv *priv = dev_get_drvdata(d);
  5153. struct iwl_spectrum_notification measure_report;
  5154. u32 size = sizeof(measure_report), len = 0, ofs = 0;
  5155. u8 *data = (u8 *)&measure_report;
  5156. unsigned long flags;
  5157. spin_lock_irqsave(&priv->lock, flags);
  5158. if (!(priv->measurement_status & MEASUREMENT_READY)) {
  5159. spin_unlock_irqrestore(&priv->lock, flags);
  5160. return 0;
  5161. }
  5162. memcpy(&measure_report, &priv->measure_report, size);
  5163. priv->measurement_status = 0;
  5164. spin_unlock_irqrestore(&priv->lock, flags);
  5165. while (size && (PAGE_SIZE - len)) {
  5166. hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
  5167. PAGE_SIZE - len, 1);
  5168. len = strlen(buf);
  5169. if (PAGE_SIZE - len)
  5170. buf[len++] = '\n';
  5171. ofs += 16;
  5172. size -= min(size, 16U);
  5173. }
  5174. return len;
  5175. }
  5176. static ssize_t store_measurement(struct device *d,
  5177. struct device_attribute *attr,
  5178. const char *buf, size_t count)
  5179. {
  5180. struct iwl_priv *priv = dev_get_drvdata(d);
  5181. struct ieee80211_measurement_params params = {
  5182. .channel = le16_to_cpu(priv->active39_rxon.channel),
  5183. .start_time = cpu_to_le64(priv->last_tsf),
  5184. .duration = cpu_to_le16(1),
  5185. };
  5186. u8 type = IWL_MEASURE_BASIC;
  5187. u8 buffer[32];
  5188. u8 channel;
  5189. if (count) {
  5190. char *p = buffer;
  5191. strncpy(buffer, buf, min(sizeof(buffer), count));
  5192. channel = simple_strtoul(p, NULL, 0);
  5193. if (channel)
  5194. params.channel = channel;
  5195. p = buffer;
  5196. while (*p && *p != ' ')
  5197. p++;
  5198. if (*p)
  5199. type = simple_strtoul(p + 1, NULL, 0);
  5200. }
  5201. IWL_DEBUG_INFO("Invoking measurement of type %d on "
  5202. "channel %d (for '%s')\n", type, params.channel, buf);
  5203. iwl3945_get_measurement(priv, &params, type);
  5204. return count;
  5205. }
  5206. static DEVICE_ATTR(measurement, S_IRUSR | S_IWUSR,
  5207. show_measurement, store_measurement);
  5208. #endif /* CONFIG_IWL3945_SPECTRUM_MEASUREMENT */
  5209. static ssize_t store_retry_rate(struct device *d,
  5210. struct device_attribute *attr,
  5211. const char *buf, size_t count)
  5212. {
  5213. struct iwl_priv *priv = dev_get_drvdata(d);
  5214. priv->retry_rate = simple_strtoul(buf, NULL, 0);
  5215. if (priv->retry_rate <= 0)
  5216. priv->retry_rate = 1;
  5217. return count;
  5218. }
  5219. static ssize_t show_retry_rate(struct device *d,
  5220. struct device_attribute *attr, char *buf)
  5221. {
  5222. struct iwl_priv *priv = dev_get_drvdata(d);
  5223. return sprintf(buf, "%d", priv->retry_rate);
  5224. }
  5225. static DEVICE_ATTR(retry_rate, S_IWUSR | S_IRUSR, show_retry_rate,
  5226. store_retry_rate);
  5227. static ssize_t store_power_level(struct device *d,
  5228. struct device_attribute *attr,
  5229. const char *buf, size_t count)
  5230. {
  5231. struct iwl_priv *priv = dev_get_drvdata(d);
  5232. int rc;
  5233. int mode;
  5234. mode = simple_strtoul(buf, NULL, 0);
  5235. mutex_lock(&priv->mutex);
  5236. if (!iwl_is_ready(priv)) {
  5237. rc = -EAGAIN;
  5238. goto out;
  5239. }
  5240. if ((mode < 1) || (mode > IWL39_POWER_LIMIT) ||
  5241. (mode == IWL39_POWER_AC))
  5242. mode = IWL39_POWER_AC;
  5243. else
  5244. mode |= IWL_POWER_ENABLED;
  5245. if (mode != priv->power_mode) {
  5246. rc = iwl3945_send_power_mode(priv, IWL_POWER_LEVEL(mode));
  5247. if (rc) {
  5248. IWL_DEBUG_MAC80211("failed setting power mode.\n");
  5249. goto out;
  5250. }
  5251. priv->power_mode = mode;
  5252. }
  5253. rc = count;
  5254. out:
  5255. mutex_unlock(&priv->mutex);
  5256. return rc;
  5257. }
  5258. #define MAX_WX_STRING 80
  5259. /* Values are in microsecond */
  5260. static const s32 timeout_duration[] = {
  5261. 350000,
  5262. 250000,
  5263. 75000,
  5264. 37000,
  5265. 25000,
  5266. };
  5267. static const s32 period_duration[] = {
  5268. 400000,
  5269. 700000,
  5270. 1000000,
  5271. 1000000,
  5272. 1000000
  5273. };
  5274. static ssize_t show_power_level(struct device *d,
  5275. struct device_attribute *attr, char *buf)
  5276. {
  5277. struct iwl_priv *priv = dev_get_drvdata(d);
  5278. int level = IWL_POWER_LEVEL(priv->power_mode);
  5279. char *p = buf;
  5280. p += sprintf(p, "%d ", level);
  5281. switch (level) {
  5282. case IWL_POWER_MODE_CAM:
  5283. case IWL39_POWER_AC:
  5284. p += sprintf(p, "(AC)");
  5285. break;
  5286. case IWL39_POWER_BATTERY:
  5287. p += sprintf(p, "(BATTERY)");
  5288. break;
  5289. default:
  5290. p += sprintf(p,
  5291. "(Timeout %dms, Period %dms)",
  5292. timeout_duration[level - 1] / 1000,
  5293. period_duration[level - 1] / 1000);
  5294. }
  5295. if (!(priv->power_mode & IWL_POWER_ENABLED))
  5296. p += sprintf(p, " OFF\n");
  5297. else
  5298. p += sprintf(p, " \n");
  5299. return p - buf + 1;
  5300. }
  5301. static DEVICE_ATTR(power_level, S_IWUSR | S_IRUSR, show_power_level,
  5302. store_power_level);
  5303. static ssize_t show_channels(struct device *d,
  5304. struct device_attribute *attr, char *buf)
  5305. {
  5306. /* all this shit doesn't belong into sysfs anyway */
  5307. return 0;
  5308. }
  5309. static DEVICE_ATTR(channels, S_IRUSR, show_channels, NULL);
  5310. static ssize_t show_statistics(struct device *d,
  5311. struct device_attribute *attr, char *buf)
  5312. {
  5313. struct iwl_priv *priv = dev_get_drvdata(d);
  5314. u32 size = sizeof(struct iwl3945_notif_statistics);
  5315. u32 len = 0, ofs = 0;
  5316. u8 *data = (u8 *)&priv->statistics_39;
  5317. int rc = 0;
  5318. if (!iwl_is_alive(priv))
  5319. return -EAGAIN;
  5320. mutex_lock(&priv->mutex);
  5321. rc = iwl3945_send_statistics_request(priv);
  5322. mutex_unlock(&priv->mutex);
  5323. if (rc) {
  5324. len = sprintf(buf,
  5325. "Error sending statistics request: 0x%08X\n", rc);
  5326. return len;
  5327. }
  5328. while (size && (PAGE_SIZE - len)) {
  5329. hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
  5330. PAGE_SIZE - len, 1);
  5331. len = strlen(buf);
  5332. if (PAGE_SIZE - len)
  5333. buf[len++] = '\n';
  5334. ofs += 16;
  5335. size -= min(size, 16U);
  5336. }
  5337. return len;
  5338. }
  5339. static DEVICE_ATTR(statistics, S_IRUGO, show_statistics, NULL);
  5340. static ssize_t show_antenna(struct device *d,
  5341. struct device_attribute *attr, char *buf)
  5342. {
  5343. struct iwl_priv *priv = dev_get_drvdata(d);
  5344. if (!iwl_is_alive(priv))
  5345. return -EAGAIN;
  5346. return sprintf(buf, "%d\n", priv->antenna);
  5347. }
  5348. static ssize_t store_antenna(struct device *d,
  5349. struct device_attribute *attr,
  5350. const char *buf, size_t count)
  5351. {
  5352. int ant;
  5353. struct iwl_priv *priv = dev_get_drvdata(d);
  5354. if (count == 0)
  5355. return 0;
  5356. if (sscanf(buf, "%1i", &ant) != 1) {
  5357. IWL_DEBUG_INFO("not in hex or decimal form.\n");
  5358. return count;
  5359. }
  5360. if ((ant >= 0) && (ant <= 2)) {
  5361. IWL_DEBUG_INFO("Setting antenna select to %d.\n", ant);
  5362. priv->antenna = (enum iwl3945_antenna)ant;
  5363. } else
  5364. IWL_DEBUG_INFO("Bad antenna select value %d.\n", ant);
  5365. return count;
  5366. }
  5367. static DEVICE_ATTR(antenna, S_IWUSR | S_IRUGO, show_antenna, store_antenna);
  5368. static ssize_t show_status(struct device *d,
  5369. struct device_attribute *attr, char *buf)
  5370. {
  5371. struct iwl_priv *priv = (struct iwl_priv *)d->driver_data;
  5372. if (!iwl_is_alive(priv))
  5373. return -EAGAIN;
  5374. return sprintf(buf, "0x%08x\n", (int)priv->status);
  5375. }
  5376. static DEVICE_ATTR(status, S_IRUGO, show_status, NULL);
  5377. static ssize_t dump_error_log(struct device *d,
  5378. struct device_attribute *attr,
  5379. const char *buf, size_t count)
  5380. {
  5381. char *p = (char *)buf;
  5382. if (p[0] == '1')
  5383. iwl3945_dump_nic_error_log((struct iwl_priv *)d->driver_data);
  5384. return strnlen(buf, count);
  5385. }
  5386. static DEVICE_ATTR(dump_errors, S_IWUSR, NULL, dump_error_log);
  5387. static ssize_t dump_event_log(struct device *d,
  5388. struct device_attribute *attr,
  5389. const char *buf, size_t count)
  5390. {
  5391. char *p = (char *)buf;
  5392. if (p[0] == '1')
  5393. iwl3945_dump_nic_event_log((struct iwl_priv *)d->driver_data);
  5394. return strnlen(buf, count);
  5395. }
  5396. static DEVICE_ATTR(dump_events, S_IWUSR, NULL, dump_event_log);
  5397. /*****************************************************************************
  5398. *
  5399. * driver setup and tear down
  5400. *
  5401. *****************************************************************************/
  5402. static void iwl3945_setup_deferred_work(struct iwl_priv *priv)
  5403. {
  5404. priv->workqueue = create_workqueue(DRV_NAME);
  5405. init_waitqueue_head(&priv->wait_command_queue);
  5406. INIT_WORK(&priv->up, iwl3945_bg_up);
  5407. INIT_WORK(&priv->restart, iwl3945_bg_restart);
  5408. INIT_WORK(&priv->rx_replenish, iwl3945_bg_rx_replenish);
  5409. INIT_WORK(&priv->rf_kill, iwl_bg_rf_kill);
  5410. INIT_WORK(&priv->beacon_update, iwl3945_bg_beacon_update);
  5411. INIT_DELAYED_WORK(&priv->init_alive_start, iwl3945_bg_init_alive_start);
  5412. INIT_DELAYED_WORK(&priv->alive_start, iwl3945_bg_alive_start);
  5413. INIT_DELAYED_WORK(&priv->rfkill_poll, iwl3945_rfkill_poll);
  5414. INIT_WORK(&priv->scan_completed, iwl_bg_scan_completed);
  5415. INIT_WORK(&priv->request_scan, iwl3945_bg_request_scan);
  5416. INIT_WORK(&priv->abort_scan, iwl_bg_abort_scan);
  5417. INIT_DELAYED_WORK(&priv->scan_check, iwl_bg_scan_check);
  5418. iwl3945_hw_setup_deferred_work(priv);
  5419. tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
  5420. iwl3945_irq_tasklet, (unsigned long)priv);
  5421. }
  5422. static void iwl3945_cancel_deferred_work(struct iwl_priv *priv)
  5423. {
  5424. iwl3945_hw_cancel_deferred_work(priv);
  5425. cancel_delayed_work_sync(&priv->init_alive_start);
  5426. cancel_delayed_work(&priv->scan_check);
  5427. cancel_delayed_work(&priv->alive_start);
  5428. cancel_work_sync(&priv->beacon_update);
  5429. }
  5430. static struct attribute *iwl3945_sysfs_entries[] = {
  5431. &dev_attr_antenna.attr,
  5432. &dev_attr_channels.attr,
  5433. &dev_attr_dump_errors.attr,
  5434. &dev_attr_dump_events.attr,
  5435. &dev_attr_flags.attr,
  5436. &dev_attr_filter_flags.attr,
  5437. #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
  5438. &dev_attr_measurement.attr,
  5439. #endif
  5440. &dev_attr_power_level.attr,
  5441. &dev_attr_retry_rate.attr,
  5442. &dev_attr_statistics.attr,
  5443. &dev_attr_status.attr,
  5444. &dev_attr_temperature.attr,
  5445. &dev_attr_tx_power.attr,
  5446. #ifdef CONFIG_IWL3945_DEBUG
  5447. &dev_attr_debug_level.attr,
  5448. #endif
  5449. NULL
  5450. };
  5451. static struct attribute_group iwl3945_attribute_group = {
  5452. .name = NULL, /* put in device directory */
  5453. .attrs = iwl3945_sysfs_entries,
  5454. };
  5455. static struct ieee80211_ops iwl3945_hw_ops = {
  5456. .tx = iwl3945_mac_tx,
  5457. .start = iwl3945_mac_start,
  5458. .stop = iwl3945_mac_stop,
  5459. .add_interface = iwl3945_mac_add_interface,
  5460. .remove_interface = iwl3945_mac_remove_interface,
  5461. .config = iwl3945_mac_config,
  5462. .config_interface = iwl3945_mac_config_interface,
  5463. .configure_filter = iwl3945_configure_filter,
  5464. .set_key = iwl3945_mac_set_key,
  5465. .get_tx_stats = iwl3945_mac_get_tx_stats,
  5466. .conf_tx = iwl3945_mac_conf_tx,
  5467. .reset_tsf = iwl3945_mac_reset_tsf,
  5468. .bss_info_changed = iwl3945_bss_info_changed,
  5469. .hw_scan = iwl3945_mac_hw_scan
  5470. };
  5471. static int iwl3945_init_drv(struct iwl_priv *priv)
  5472. {
  5473. int ret;
  5474. priv->retry_rate = 1;
  5475. priv->ibss_beacon = NULL;
  5476. spin_lock_init(&priv->lock);
  5477. spin_lock_init(&priv->power_data.lock);
  5478. spin_lock_init(&priv->sta_lock);
  5479. spin_lock_init(&priv->hcmd_lock);
  5480. INIT_LIST_HEAD(&priv->free_frames);
  5481. mutex_init(&priv->mutex);
  5482. /* Clear the driver's (not device's) station table */
  5483. iwl3945_clear_stations_table(priv);
  5484. priv->data_retry_limit = -1;
  5485. priv->ieee_channels = NULL;
  5486. priv->ieee_rates = NULL;
  5487. priv->band = IEEE80211_BAND_2GHZ;
  5488. priv->iw_mode = NL80211_IFTYPE_STATION;
  5489. iwl_reset_qos(priv);
  5490. priv->qos_data.qos_active = 0;
  5491. priv->qos_data.qos_cap.val = 0;
  5492. priv->rates_mask = IWL_RATES_MASK;
  5493. /* If power management is turned on, default to AC mode */
  5494. priv->power_mode = IWL39_POWER_AC;
  5495. priv->tx_power_user_lmt = IWL_DEFAULT_TX_POWER;
  5496. ret = iwl3945_init_channel_map(priv);
  5497. if (ret) {
  5498. IWL_ERR(priv, "initializing regulatory failed: %d\n", ret);
  5499. goto err;
  5500. }
  5501. ret = iwl3945_init_geos(priv);
  5502. if (ret) {
  5503. IWL_ERR(priv, "initializing geos failed: %d\n", ret);
  5504. goto err_free_channel_map;
  5505. }
  5506. return 0;
  5507. err_free_channel_map:
  5508. iwl3945_free_channel_map(priv);
  5509. err:
  5510. return ret;
  5511. }
  5512. static int iwl3945_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
  5513. {
  5514. int err = 0;
  5515. struct iwl_priv *priv;
  5516. struct ieee80211_hw *hw;
  5517. struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data);
  5518. unsigned long flags;
  5519. /***********************
  5520. * 1. Allocating HW data
  5521. * ********************/
  5522. /* mac80211 allocates memory for this device instance, including
  5523. * space for this driver's private structure */
  5524. hw = iwl_alloc_all(cfg, &iwl3945_hw_ops);
  5525. if (hw == NULL) {
  5526. printk(KERN_ERR DRV_NAME "Can not allocate network device\n");
  5527. err = -ENOMEM;
  5528. goto out;
  5529. }
  5530. priv = hw->priv;
  5531. SET_IEEE80211_DEV(hw, &pdev->dev);
  5532. if ((iwl3945_mod_params.num_of_queues > IWL39_MAX_NUM_QUEUES) ||
  5533. (iwl3945_mod_params.num_of_queues < IWL_MIN_NUM_QUEUES)) {
  5534. IWL_ERR(priv,
  5535. "invalid queues_num, should be between %d and %d\n",
  5536. IWL_MIN_NUM_QUEUES, IWL39_MAX_NUM_QUEUES);
  5537. err = -EINVAL;
  5538. goto out;
  5539. }
  5540. /*
  5541. * Disabling hardware scan means that mac80211 will perform scans
  5542. * "the hard way", rather than using device's scan.
  5543. */
  5544. if (iwl3945_mod_params.disable_hw_scan) {
  5545. IWL_DEBUG_INFO("Disabling hw_scan\n");
  5546. iwl3945_hw_ops.hw_scan = NULL;
  5547. }
  5548. IWL_DEBUG_INFO("*** LOAD DRIVER ***\n");
  5549. priv->cfg = cfg;
  5550. priv->pci_dev = pdev;
  5551. #ifdef CONFIG_IWL3945_DEBUG
  5552. priv->debug_level = iwl3945_mod_params.debug;
  5553. atomic_set(&priv->restrict_refcnt, 0);
  5554. #endif
  5555. hw->rate_control_algorithm = "iwl-3945-rs";
  5556. hw->sta_data_size = sizeof(struct iwl3945_sta_priv);
  5557. /* Select antenna (may be helpful if only one antenna is connected) */
  5558. priv->antenna = (enum iwl3945_antenna)iwl3945_mod_params.antenna;
  5559. /* Tell mac80211 our characteristics */
  5560. hw->flags = IEEE80211_HW_SIGNAL_DBM |
  5561. IEEE80211_HW_NOISE_DBM;
  5562. hw->wiphy->interface_modes =
  5563. BIT(NL80211_IFTYPE_STATION) |
  5564. BIT(NL80211_IFTYPE_ADHOC);
  5565. hw->wiphy->custom_regulatory = true;
  5566. /* 4 EDCA QOS priorities */
  5567. hw->queues = 4;
  5568. /***************************
  5569. * 2. Initializing PCI bus
  5570. * *************************/
  5571. if (pci_enable_device(pdev)) {
  5572. err = -ENODEV;
  5573. goto out_ieee80211_free_hw;
  5574. }
  5575. pci_set_master(pdev);
  5576. err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
  5577. if (!err)
  5578. err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
  5579. if (err) {
  5580. IWL_WARN(priv, "No suitable DMA available.\n");
  5581. goto out_pci_disable_device;
  5582. }
  5583. pci_set_drvdata(pdev, priv);
  5584. err = pci_request_regions(pdev, DRV_NAME);
  5585. if (err)
  5586. goto out_pci_disable_device;
  5587. /***********************
  5588. * 3. Read REV Register
  5589. * ********************/
  5590. priv->hw_base = pci_iomap(pdev, 0, 0);
  5591. if (!priv->hw_base) {
  5592. err = -ENODEV;
  5593. goto out_pci_release_regions;
  5594. }
  5595. IWL_DEBUG_INFO("pci_resource_len = 0x%08llx\n",
  5596. (unsigned long long) pci_resource_len(pdev, 0));
  5597. IWL_DEBUG_INFO("pci_resource_base = %p\n", priv->hw_base);
  5598. /* We disable the RETRY_TIMEOUT register (0x41) to keep
  5599. * PCI Tx retries from interfering with C3 CPU state */
  5600. pci_write_config_byte(pdev, 0x41, 0x00);
  5601. /* amp init */
  5602. err = priv->cfg->ops->lib->apm_ops.init(priv);
  5603. if (err < 0) {
  5604. IWL_DEBUG_INFO("Failed to init APMG\n");
  5605. goto out_iounmap;
  5606. }
  5607. /***********************
  5608. * 4. Read EEPROM
  5609. * ********************/
  5610. /* Read the EEPROM */
  5611. err = iwl3945_eeprom_init(priv);
  5612. if (err) {
  5613. IWL_ERR(priv, "Unable to init EEPROM\n");
  5614. goto out_remove_sysfs;
  5615. }
  5616. /* MAC Address location in EEPROM same for 3945/4965 */
  5617. get_eeprom_mac(priv, priv->mac_addr);
  5618. IWL_DEBUG_INFO("MAC address: %pM\n", priv->mac_addr);
  5619. SET_IEEE80211_PERM_ADDR(priv->hw, priv->mac_addr);
  5620. /***********************
  5621. * 5. Setup HW Constants
  5622. * ********************/
  5623. /* Device-specific setup */
  5624. if (iwl3945_hw_set_hw_params(priv)) {
  5625. IWL_ERR(priv, "failed to set hw settings\n");
  5626. goto out_iounmap;
  5627. }
  5628. /***********************
  5629. * 6. Setup priv
  5630. * ********************/
  5631. err = iwl3945_init_drv(priv);
  5632. if (err) {
  5633. IWL_ERR(priv, "initializing driver failed\n");
  5634. goto out_free_geos;
  5635. }
  5636. IWL_INFO(priv, "Detected Intel Wireless WiFi Link %s\n",
  5637. priv->cfg->name);
  5638. /***********************************
  5639. * 7. Initialize Module Parameters
  5640. * **********************************/
  5641. /* Initialize module parameter values here */
  5642. /* Disable radio (SW RF KILL) via parameter when loading driver */
  5643. if (iwl3945_mod_params.disable) {
  5644. set_bit(STATUS_RF_KILL_SW, &priv->status);
  5645. IWL_DEBUG_INFO("Radio disabled.\n");
  5646. }
  5647. /***********************
  5648. * 8. Setup Services
  5649. * ********************/
  5650. spin_lock_irqsave(&priv->lock, flags);
  5651. iwl3945_disable_interrupts(priv);
  5652. spin_unlock_irqrestore(&priv->lock, flags);
  5653. pci_enable_msi(priv->pci_dev);
  5654. err = request_irq(priv->pci_dev->irq, iwl3945_isr, IRQF_SHARED,
  5655. DRV_NAME, priv);
  5656. if (err) {
  5657. IWL_ERR(priv, "Error allocating IRQ %d\n", priv->pci_dev->irq);
  5658. goto out_disable_msi;
  5659. }
  5660. err = sysfs_create_group(&pdev->dev.kobj, &iwl3945_attribute_group);
  5661. if (err) {
  5662. IWL_ERR(priv, "failed to create sysfs device attributes\n");
  5663. goto out_release_irq;
  5664. }
  5665. iwl3945_set_rxon_channel(priv, IEEE80211_BAND_2GHZ, 6);
  5666. iwl3945_setup_deferred_work(priv);
  5667. iwl3945_setup_rx_handlers(priv);
  5668. /*********************************
  5669. * 9. Setup and Register mac80211
  5670. * *******************************/
  5671. err = ieee80211_register_hw(priv->hw);
  5672. if (err) {
  5673. IWL_ERR(priv, "Failed to register network device: %d\n", err);
  5674. goto out_remove_sysfs;
  5675. }
  5676. priv->hw->conf.beacon_int = 100;
  5677. priv->mac80211_registered = 1;
  5678. err = iwl_rfkill_init(priv);
  5679. if (err)
  5680. IWL_ERR(priv, "Unable to initialize RFKILL system. "
  5681. "Ignoring error: %d\n", err);
  5682. /* Start monitoring the killswitch */
  5683. queue_delayed_work(priv->workqueue, &priv->rfkill_poll,
  5684. 2 * HZ);
  5685. return 0;
  5686. out_remove_sysfs:
  5687. sysfs_remove_group(&pdev->dev.kobj, &iwl3945_attribute_group);
  5688. out_free_geos:
  5689. iwl3945_free_geos(priv);
  5690. out_release_irq:
  5691. free_irq(priv->pci_dev->irq, priv);
  5692. destroy_workqueue(priv->workqueue);
  5693. priv->workqueue = NULL;
  5694. iwl3945_unset_hw_params(priv);
  5695. out_disable_msi:
  5696. pci_disable_msi(priv->pci_dev);
  5697. out_iounmap:
  5698. pci_iounmap(pdev, priv->hw_base);
  5699. out_pci_release_regions:
  5700. pci_release_regions(pdev);
  5701. out_pci_disable_device:
  5702. pci_disable_device(pdev);
  5703. pci_set_drvdata(pdev, NULL);
  5704. out_ieee80211_free_hw:
  5705. ieee80211_free_hw(priv->hw);
  5706. out:
  5707. return err;
  5708. }
  5709. static void __devexit iwl3945_pci_remove(struct pci_dev *pdev)
  5710. {
  5711. struct iwl_priv *priv = pci_get_drvdata(pdev);
  5712. unsigned long flags;
  5713. if (!priv)
  5714. return;
  5715. IWL_DEBUG_INFO("*** UNLOAD DRIVER ***\n");
  5716. set_bit(STATUS_EXIT_PENDING, &priv->status);
  5717. if (priv->mac80211_registered) {
  5718. ieee80211_unregister_hw(priv->hw);
  5719. priv->mac80211_registered = 0;
  5720. } else {
  5721. iwl3945_down(priv);
  5722. }
  5723. /* make sure we flush any pending irq or
  5724. * tasklet for the driver
  5725. */
  5726. spin_lock_irqsave(&priv->lock, flags);
  5727. iwl3945_disable_interrupts(priv);
  5728. spin_unlock_irqrestore(&priv->lock, flags);
  5729. iwl_synchronize_irq(priv);
  5730. sysfs_remove_group(&pdev->dev.kobj, &iwl3945_attribute_group);
  5731. iwl_rfkill_unregister(priv);
  5732. cancel_delayed_work(&priv->rfkill_poll);
  5733. iwl3945_dealloc_ucode_pci(priv);
  5734. if (priv->rxq.bd)
  5735. iwl_rx_queue_free(priv, &priv->rxq);
  5736. iwl3945_hw_txq_ctx_free(priv);
  5737. iwl3945_unset_hw_params(priv);
  5738. iwl3945_clear_stations_table(priv);
  5739. /*netif_stop_queue(dev); */
  5740. flush_workqueue(priv->workqueue);
  5741. /* ieee80211_unregister_hw calls iwl3945_mac_stop, which flushes
  5742. * priv->workqueue... so we can't take down the workqueue
  5743. * until now... */
  5744. destroy_workqueue(priv->workqueue);
  5745. priv->workqueue = NULL;
  5746. free_irq(pdev->irq, priv);
  5747. pci_disable_msi(pdev);
  5748. pci_iounmap(pdev, priv->hw_base);
  5749. pci_release_regions(pdev);
  5750. pci_disable_device(pdev);
  5751. pci_set_drvdata(pdev, NULL);
  5752. iwl3945_free_channel_map(priv);
  5753. iwl3945_free_geos(priv);
  5754. kfree(priv->scan);
  5755. if (priv->ibss_beacon)
  5756. dev_kfree_skb(priv->ibss_beacon);
  5757. ieee80211_free_hw(priv->hw);
  5758. }
  5759. #ifdef CONFIG_PM
  5760. static int iwl3945_pci_suspend(struct pci_dev *pdev, pm_message_t state)
  5761. {
  5762. struct iwl_priv *priv = pci_get_drvdata(pdev);
  5763. if (priv->is_open) {
  5764. set_bit(STATUS_IN_SUSPEND, &priv->status);
  5765. iwl3945_mac_stop(priv->hw);
  5766. priv->is_open = 1;
  5767. }
  5768. pci_save_state(pdev);
  5769. pci_disable_device(pdev);
  5770. pci_set_power_state(pdev, PCI_D3hot);
  5771. return 0;
  5772. }
  5773. static int iwl3945_pci_resume(struct pci_dev *pdev)
  5774. {
  5775. struct iwl_priv *priv = pci_get_drvdata(pdev);
  5776. pci_set_power_state(pdev, PCI_D0);
  5777. pci_enable_device(pdev);
  5778. pci_restore_state(pdev);
  5779. if (priv->is_open)
  5780. iwl3945_mac_start(priv->hw);
  5781. clear_bit(STATUS_IN_SUSPEND, &priv->status);
  5782. return 0;
  5783. }
  5784. #endif /* CONFIG_PM */
  5785. /*****************************************************************************
  5786. *
  5787. * driver and module entry point
  5788. *
  5789. *****************************************************************************/
  5790. static struct pci_driver iwl3945_driver = {
  5791. .name = DRV_NAME,
  5792. .id_table = iwl3945_hw_card_ids,
  5793. .probe = iwl3945_pci_probe,
  5794. .remove = __devexit_p(iwl3945_pci_remove),
  5795. #ifdef CONFIG_PM
  5796. .suspend = iwl3945_pci_suspend,
  5797. .resume = iwl3945_pci_resume,
  5798. #endif
  5799. };
  5800. static int __init iwl3945_init(void)
  5801. {
  5802. int ret;
  5803. printk(KERN_INFO DRV_NAME ": " DRV_DESCRIPTION ", " DRV_VERSION "\n");
  5804. printk(KERN_INFO DRV_NAME ": " DRV_COPYRIGHT "\n");
  5805. ret = iwl3945_rate_control_register();
  5806. if (ret) {
  5807. printk(KERN_ERR DRV_NAME
  5808. "Unable to register rate control algorithm: %d\n", ret);
  5809. return ret;
  5810. }
  5811. ret = pci_register_driver(&iwl3945_driver);
  5812. if (ret) {
  5813. printk(KERN_ERR DRV_NAME "Unable to initialize PCI module\n");
  5814. goto error_register;
  5815. }
  5816. return ret;
  5817. error_register:
  5818. iwl3945_rate_control_unregister();
  5819. return ret;
  5820. }
  5821. static void __exit iwl3945_exit(void)
  5822. {
  5823. pci_unregister_driver(&iwl3945_driver);
  5824. iwl3945_rate_control_unregister();
  5825. }
  5826. MODULE_FIRMWARE(IWL3945_MODULE_FIRMWARE(IWL3945_UCODE_API_MAX));
  5827. module_param_named(antenna, iwl3945_mod_params.antenna, int, 0444);
  5828. MODULE_PARM_DESC(antenna, "select antenna (1=Main, 2=Aux, default 0 [both])");
  5829. module_param_named(disable, iwl3945_mod_params.disable, int, 0444);
  5830. MODULE_PARM_DESC(disable, "manually disable the radio (default 0 [radio on])");
  5831. module_param_named(swcrypto, iwl3945_mod_params.sw_crypto, int, 0444);
  5832. MODULE_PARM_DESC(swcrypto,
  5833. "using software crypto (default 1 [software])\n");
  5834. module_param_named(debug, iwl3945_mod_params.debug, uint, 0444);
  5835. MODULE_PARM_DESC(debug, "debug output mask");
  5836. module_param_named(disable_hw_scan, iwl3945_mod_params.disable_hw_scan, int, 0444);
  5837. MODULE_PARM_DESC(disable_hw_scan, "disable hardware scanning (default 0)");
  5838. module_param_named(queues_num, iwl3945_mod_params.num_of_queues, int, 0444);
  5839. MODULE_PARM_DESC(queues_num, "number of hw queues.");
  5840. module_exit(iwl3945_exit);
  5841. module_init(iwl3945_init);