dev.c 4.8 KB

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  1. /*
  2. * Tegra host1x driver
  3. *
  4. * Copyright (c) 2010-2013, NVIDIA Corporation.
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms and conditions of the GNU General Public License,
  8. * version 2, as published by the Free Software Foundation.
  9. *
  10. * This program is distributed in the hope it will be useful, but WITHOUT
  11. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  13. * more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program. If not, see <http://www.gnu.org/licenses/>.
  17. */
  18. #include <linux/module.h>
  19. #include <linux/list.h>
  20. #include <linux/slab.h>
  21. #include <linux/of.h>
  22. #include <linux/of_device.h>
  23. #include <linux/clk.h>
  24. #include <linux/io.h>
  25. #define CREATE_TRACE_POINTS
  26. #include <trace/events/host1x.h>
  27. #include "bus.h"
  28. #include "dev.h"
  29. #include "intr.h"
  30. #include "channel.h"
  31. #include "debug.h"
  32. #include "hw/host1x01.h"
  33. void host1x_sync_writel(struct host1x *host1x, u32 v, u32 r)
  34. {
  35. void __iomem *sync_regs = host1x->regs + host1x->info->sync_offset;
  36. writel(v, sync_regs + r);
  37. }
  38. u32 host1x_sync_readl(struct host1x *host1x, u32 r)
  39. {
  40. void __iomem *sync_regs = host1x->regs + host1x->info->sync_offset;
  41. return readl(sync_regs + r);
  42. }
  43. void host1x_ch_writel(struct host1x_channel *ch, u32 v, u32 r)
  44. {
  45. writel(v, ch->regs + r);
  46. }
  47. u32 host1x_ch_readl(struct host1x_channel *ch, u32 r)
  48. {
  49. return readl(ch->regs + r);
  50. }
  51. static const struct host1x_info host1x01_info = {
  52. .nb_channels = 8,
  53. .nb_pts = 32,
  54. .nb_mlocks = 16,
  55. .nb_bases = 8,
  56. .init = host1x01_init,
  57. .sync_offset = 0x3000,
  58. };
  59. static struct of_device_id host1x_of_match[] = {
  60. { .compatible = "nvidia,tegra30-host1x", .data = &host1x01_info, },
  61. { .compatible = "nvidia,tegra20-host1x", .data = &host1x01_info, },
  62. { },
  63. };
  64. MODULE_DEVICE_TABLE(of, host1x_of_match);
  65. static int host1x_probe(struct platform_device *pdev)
  66. {
  67. const struct of_device_id *id;
  68. struct host1x *host;
  69. struct resource *regs;
  70. int syncpt_irq;
  71. int err;
  72. id = of_match_device(host1x_of_match, &pdev->dev);
  73. if (!id)
  74. return -EINVAL;
  75. regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  76. if (!regs) {
  77. dev_err(&pdev->dev, "failed to get registers\n");
  78. return -ENXIO;
  79. }
  80. syncpt_irq = platform_get_irq(pdev, 0);
  81. if (syncpt_irq < 0) {
  82. dev_err(&pdev->dev, "failed to get IRQ\n");
  83. return -ENXIO;
  84. }
  85. host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL);
  86. if (!host)
  87. return -ENOMEM;
  88. mutex_init(&host->devices_lock);
  89. INIT_LIST_HEAD(&host->devices);
  90. INIT_LIST_HEAD(&host->list);
  91. host->dev = &pdev->dev;
  92. host->info = id->data;
  93. /* set common host1x device data */
  94. platform_set_drvdata(pdev, host);
  95. host->regs = devm_ioremap_resource(&pdev->dev, regs);
  96. if (IS_ERR(host->regs))
  97. return PTR_ERR(host->regs);
  98. if (host->info->init) {
  99. err = host->info->init(host);
  100. if (err)
  101. return err;
  102. }
  103. host->clk = devm_clk_get(&pdev->dev, NULL);
  104. if (IS_ERR(host->clk)) {
  105. dev_err(&pdev->dev, "failed to get clock\n");
  106. err = PTR_ERR(host->clk);
  107. return err;
  108. }
  109. err = host1x_channel_list_init(host);
  110. if (err) {
  111. dev_err(&pdev->dev, "failed to initialize channel list\n");
  112. return err;
  113. }
  114. err = clk_prepare_enable(host->clk);
  115. if (err < 0) {
  116. dev_err(&pdev->dev, "failed to enable clock\n");
  117. return err;
  118. }
  119. err = host1x_syncpt_init(host);
  120. if (err) {
  121. dev_err(&pdev->dev, "failed to initialize syncpts\n");
  122. return err;
  123. }
  124. err = host1x_intr_init(host, syncpt_irq);
  125. if (err) {
  126. dev_err(&pdev->dev, "failed to initialize interrupts\n");
  127. goto fail_deinit_syncpt;
  128. }
  129. host1x_debug_init(host);
  130. err = host1x_register(host);
  131. if (err < 0)
  132. goto fail_deinit_intr;
  133. return 0;
  134. fail_deinit_intr:
  135. host1x_intr_deinit(host);
  136. fail_deinit_syncpt:
  137. host1x_syncpt_deinit(host);
  138. return err;
  139. }
  140. static int host1x_remove(struct platform_device *pdev)
  141. {
  142. struct host1x *host = platform_get_drvdata(pdev);
  143. host1x_unregister(host);
  144. host1x_intr_deinit(host);
  145. host1x_syncpt_deinit(host);
  146. clk_disable_unprepare(host->clk);
  147. return 0;
  148. }
  149. static struct platform_driver tegra_host1x_driver = {
  150. .driver = {
  151. .name = "tegra-host1x",
  152. .of_match_table = host1x_of_match,
  153. },
  154. .probe = host1x_probe,
  155. .remove = host1x_remove,
  156. };
  157. static int __init tegra_host1x_init(void)
  158. {
  159. int err;
  160. err = host1x_bus_init();
  161. if (err < 0)
  162. return err;
  163. err = platform_driver_register(&tegra_host1x_driver);
  164. if (err < 0) {
  165. host1x_bus_exit();
  166. return err;
  167. }
  168. return 0;
  169. }
  170. module_init(tegra_host1x_init);
  171. static void __exit tegra_host1x_exit(void)
  172. {
  173. platform_driver_unregister(&tegra_host1x_driver);
  174. host1x_bus_exit();
  175. }
  176. module_exit(tegra_host1x_exit);
  177. MODULE_AUTHOR("Thierry Reding <thierry.reding@avionic-design.de>");
  178. MODULE_AUTHOR("Terje Bergstrom <tbergstrom@nvidia.com>");
  179. MODULE_DESCRIPTION("Host1x driver for Tegra products");
  180. MODULE_LICENSE("GPL");