bfa_hw_ct.c 3.4 KB

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  1. /*
  2. * Copyright (c) 2005-2010 Brocade Communications Systems, Inc.
  3. * All rights reserved
  4. * www.brocade.com
  5. *
  6. * Linux driver for Brocade Fibre Channel Host Bus Adapter.
  7. *
  8. * This program is free software; you can redistribute it and/or modify it
  9. * under the terms of the GNU General Public License (GPL) Version 2 as
  10. * published by the Free Software Foundation
  11. *
  12. * This program is distributed in the hope that it will be useful, but
  13. * WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  15. * General Public License for more details.
  16. */
  17. #include "bfad_drv.h"
  18. #include "bfa_modules.h"
  19. #include "bfi_reg.h"
  20. BFA_TRC_FILE(HAL, IOCFC_CT);
  21. /*
  22. * Dummy interrupt handler for handling spurious interrupt during chip-reinit.
  23. */
  24. static void
  25. bfa_hwct_msix_dummy(struct bfa_s *bfa, int vec)
  26. {
  27. }
  28. void
  29. bfa_hwct_reginit(struct bfa_s *bfa)
  30. {
  31. struct bfa_iocfc_regs_s *bfa_regs = &bfa->iocfc.bfa_regs;
  32. void __iomem *kva = bfa_ioc_bar0(&bfa->ioc);
  33. int fn = bfa_ioc_pcifn(&bfa->ioc);
  34. if (fn == 0) {
  35. bfa_regs->intr_status = (kva + HOSTFN0_INT_STATUS);
  36. bfa_regs->intr_mask = (kva + HOSTFN0_INT_MSK);
  37. } else {
  38. bfa_regs->intr_status = (kva + HOSTFN1_INT_STATUS);
  39. bfa_regs->intr_mask = (kva + HOSTFN1_INT_MSK);
  40. }
  41. }
  42. void
  43. bfa_hwct2_reginit(struct bfa_s *bfa)
  44. {
  45. struct bfa_iocfc_regs_s *bfa_regs = &bfa->iocfc.bfa_regs;
  46. void __iomem *kva = bfa_ioc_bar0(&bfa->ioc);
  47. bfa_regs->intr_status = (kva + CT2_HOSTFN_INT_STATUS);
  48. bfa_regs->intr_mask = (kva + CT2_HOSTFN_INTR_MASK);
  49. }
  50. void
  51. bfa_hwct_reqq_ack(struct bfa_s *bfa, int reqq)
  52. {
  53. u32 r32;
  54. r32 = readl(bfa->iocfc.bfa_regs.cpe_q_ctrl[reqq]);
  55. writel(r32, bfa->iocfc.bfa_regs.cpe_q_ctrl[reqq]);
  56. }
  57. void
  58. bfa_hwct_rspq_ack(struct bfa_s *bfa, int rspq)
  59. {
  60. u32 r32;
  61. r32 = readl(bfa->iocfc.bfa_regs.rme_q_ctrl[rspq]);
  62. writel(r32, bfa->iocfc.bfa_regs.rme_q_ctrl[rspq]);
  63. }
  64. void
  65. bfa_hwct_msix_getvecs(struct bfa_s *bfa, u32 *msix_vecs_bmap,
  66. u32 *num_vecs, u32 *max_vec_bit)
  67. {
  68. *msix_vecs_bmap = (1 << BFI_MSIX_CT_MAX) - 1;
  69. *max_vec_bit = (1 << (BFI_MSIX_CT_MAX - 1));
  70. *num_vecs = BFI_MSIX_CT_MAX;
  71. }
  72. /*
  73. * Setup MSI-X vector for catapult
  74. */
  75. void
  76. bfa_hwct_msix_init(struct bfa_s *bfa, int nvecs)
  77. {
  78. WARN_ON((nvecs != 1) && (nvecs != BFI_MSIX_CT_MAX));
  79. bfa_trc(bfa, nvecs);
  80. bfa->msix.nvecs = nvecs;
  81. bfa_hwct_msix_uninstall(bfa);
  82. }
  83. void
  84. bfa_hwct_msix_ctrl_install(struct bfa_s *bfa)
  85. {
  86. if (bfa->msix.nvecs == 0)
  87. return;
  88. if (bfa->msix.nvecs == 1)
  89. bfa->msix.handler[BFI_MSIX_LPU_ERR_CT] = bfa_msix_all;
  90. else
  91. bfa->msix.handler[BFI_MSIX_LPU_ERR_CT] = bfa_msix_lpu_err;
  92. }
  93. void
  94. bfa_hwct_msix_queue_install(struct bfa_s *bfa)
  95. {
  96. int i;
  97. if (bfa->msix.nvecs == 0)
  98. return;
  99. if (bfa->msix.nvecs == 1) {
  100. for (i = BFI_MSIX_CPE_QMIN_CT; i < BFI_MSIX_CT_MAX; i++)
  101. bfa->msix.handler[i] = bfa_msix_all;
  102. return;
  103. }
  104. for (i = BFI_MSIX_CPE_QMIN_CT; i <= BFI_MSIX_CPE_QMAX_CT; i++)
  105. bfa->msix.handler[i] = bfa_msix_reqq;
  106. for (i = BFI_MSIX_RME_QMIN_CT; i <= BFI_MSIX_RME_QMAX_CT; i++)
  107. bfa->msix.handler[i] = bfa_msix_rspq;
  108. }
  109. void
  110. bfa_hwct_msix_uninstall(struct bfa_s *bfa)
  111. {
  112. int i;
  113. for (i = 0; i < BFI_MSIX_CT_MAX; i++)
  114. bfa->msix.handler[i] = bfa_hwct_msix_dummy;
  115. }
  116. /*
  117. * Enable MSI-X vectors
  118. */
  119. void
  120. bfa_hwct_isr_mode_set(struct bfa_s *bfa, bfa_boolean_t msix)
  121. {
  122. bfa_trc(bfa, 0);
  123. bfa_ioc_isr_mode_set(&bfa->ioc, msix);
  124. }
  125. void
  126. bfa_hwct_msix_get_rme_range(struct bfa_s *bfa, u32 *start, u32 *end)
  127. {
  128. *start = BFI_MSIX_RME_QMIN_CT;
  129. *end = BFI_MSIX_RME_QMAX_CT;
  130. }