pm-sh7372.c 6.4 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282
  1. /*
  2. * sh7372 Power management support
  3. *
  4. * Copyright (C) 2011 Magnus Damm
  5. *
  6. * This file is subject to the terms and conditions of the GNU General Public
  7. * License. See the file "COPYING" in the main directory of this archive
  8. * for more details.
  9. */
  10. #include <linux/pm.h>
  11. #include <linux/suspend.h>
  12. #include <linux/cpuidle.h>
  13. #include <linux/module.h>
  14. #include <linux/list.h>
  15. #include <linux/err.h>
  16. #include <linux/slab.h>
  17. #include <linux/pm_runtime.h>
  18. #include <linux/platform_device.h>
  19. #include <linux/delay.h>
  20. #include <asm/system.h>
  21. #include <asm/io.h>
  22. #include <asm/tlbflush.h>
  23. #include <mach/common.h>
  24. #include <mach/sh7372.h>
  25. #define SMFRAM 0xe6a70000
  26. #define SYSTBCR 0xe6150024
  27. #define SBAR 0xe6180020
  28. #define APARMBAREA 0xe6f10020
  29. #define SPDCR 0xe6180008
  30. #define SWUCR 0xe6180014
  31. #define PSTR 0xe6180080
  32. #define PSTR_RETRIES 100
  33. #define PSTR_DELAY_US 10
  34. #ifdef CONFIG_PM
  35. static int pd_power_down(struct generic_pm_domain *genpd)
  36. {
  37. struct sh7372_pm_domain *sh7372_pd = to_sh7372_pd(genpd);
  38. unsigned int mask = 1 << sh7372_pd->bit_shift;
  39. if (__raw_readl(PSTR) & mask) {
  40. unsigned int retry_count;
  41. __raw_writel(mask, SPDCR);
  42. for (retry_count = PSTR_RETRIES; retry_count; retry_count--) {
  43. if (!(__raw_readl(SPDCR) & mask))
  44. break;
  45. cpu_relax();
  46. }
  47. }
  48. pr_debug("sh7372 power domain down 0x%08x -> PSTR = 0x%08x\n",
  49. mask, __raw_readl(PSTR));
  50. return 0;
  51. }
  52. static int pd_power_up(struct generic_pm_domain *genpd)
  53. {
  54. struct sh7372_pm_domain *sh7372_pd = to_sh7372_pd(genpd);
  55. unsigned int mask = 1 << sh7372_pd->bit_shift;
  56. unsigned int retry_count;
  57. int ret = 0;
  58. if (__raw_readl(PSTR) & mask)
  59. goto out;
  60. __raw_writel(mask, SWUCR);
  61. for (retry_count = 2 * PSTR_RETRIES; retry_count; retry_count--) {
  62. if (!(__raw_readl(SWUCR) & mask))
  63. goto out;
  64. if (retry_count > PSTR_RETRIES)
  65. udelay(PSTR_DELAY_US);
  66. else
  67. cpu_relax();
  68. }
  69. if (__raw_readl(SWUCR) & mask)
  70. ret = -EIO;
  71. out:
  72. pr_debug("sh7372 power domain up 0x%08x -> PSTR = 0x%08x\n",
  73. mask, __raw_readl(PSTR));
  74. return ret;
  75. }
  76. static int pd_power_up_a3rv(struct generic_pm_domain *genpd)
  77. {
  78. int ret = pd_power_up(genpd);
  79. /* force A4LC on after A3RV has been requested on */
  80. pm_genpd_poweron(&sh7372_a4lc.genpd);
  81. return ret;
  82. }
  83. static int pd_power_down_a3rv(struct generic_pm_domain *genpd)
  84. {
  85. int ret = pd_power_down(genpd);
  86. /* try to power down A4LC after A3RV is requested off */
  87. pm_genpd_poweron(&sh7372_a4lc.genpd);
  88. queue_work(pm_wq, &sh7372_a4lc.genpd.power_off_work);
  89. return ret;
  90. }
  91. static int pd_power_down_a4lc(struct generic_pm_domain *genpd)
  92. {
  93. /* only power down A4LC if A3RV is off */
  94. if (!(__raw_readl(PSTR) & (1 << sh7372_a3rv.bit_shift)))
  95. return pd_power_down(genpd);
  96. return 0;
  97. }
  98. static bool pd_active_wakeup(struct device *dev)
  99. {
  100. return true;
  101. }
  102. static void sh7372_late_pm_domain_off(void)
  103. {
  104. /* request power down of unused pm domains */
  105. queue_work(pm_wq, &sh7372_a4lc.genpd.power_off_work);
  106. queue_work(pm_wq, &sh7372_a4mp.genpd.power_off_work);
  107. queue_work(pm_wq, &sh7372_d4.genpd.power_off_work);
  108. queue_work(pm_wq, &sh7372_a3rv.genpd.power_off_work);
  109. queue_work(pm_wq, &sh7372_a3ri.genpd.power_off_work);
  110. queue_work(pm_wq, &sh7372_a3sg.genpd.power_off_work);
  111. }
  112. void sh7372_init_pm_domain(struct sh7372_pm_domain *sh7372_pd)
  113. {
  114. struct generic_pm_domain *genpd = &sh7372_pd->genpd;
  115. pm_genpd_init(genpd, NULL, false);
  116. genpd->stop_device = pm_clk_suspend;
  117. genpd->start_device = pm_clk_resume;
  118. genpd->active_wakeup = pd_active_wakeup;
  119. if (sh7372_pd == &sh7372_a4lc) {
  120. genpd->power_off = pd_power_down_a4lc;
  121. genpd->power_on = pd_power_up;
  122. } else if (sh7372_pd == &sh7372_a3rv) {
  123. genpd->power_off = pd_power_down_a3rv;
  124. genpd->power_on = pd_power_up_a3rv;
  125. } else {
  126. genpd->power_off = pd_power_down;
  127. genpd->power_on = pd_power_up;
  128. }
  129. genpd->power_on(&sh7372_pd->genpd);
  130. shmobile_runtime_pm_late_init = sh7372_late_pm_domain_off;
  131. }
  132. void sh7372_add_device_to_domain(struct sh7372_pm_domain *sh7372_pd,
  133. struct platform_device *pdev)
  134. {
  135. struct device *dev = &pdev->dev;
  136. if (!dev->power.subsys_data) {
  137. pm_clk_init(dev);
  138. pm_clk_add(dev, NULL);
  139. }
  140. pm_genpd_add_device(&sh7372_pd->genpd, dev);
  141. }
  142. struct sh7372_pm_domain sh7372_a4lc = {
  143. .bit_shift = 1,
  144. };
  145. struct sh7372_pm_domain sh7372_a4mp = {
  146. .bit_shift = 2,
  147. };
  148. struct sh7372_pm_domain sh7372_d4 = {
  149. .bit_shift = 3,
  150. };
  151. struct sh7372_pm_domain sh7372_a3rv = {
  152. .bit_shift = 6,
  153. };
  154. struct sh7372_pm_domain sh7372_a3ri = {
  155. .bit_shift = 8,
  156. };
  157. struct sh7372_pm_domain sh7372_a3sg = {
  158. .bit_shift = 13,
  159. };
  160. #endif /* CONFIG_PM */
  161. static void sh7372_enter_core_standby(void)
  162. {
  163. void __iomem *smfram = (void __iomem *)SMFRAM;
  164. __raw_writel(0, APARMBAREA); /* translate 4k */
  165. __raw_writel(__pa(sh7372_cpu_resume), SBAR); /* set reset vector */
  166. __raw_writel(0x10, SYSTBCR); /* enable core standby */
  167. __raw_writel(0, smfram + 0x3c); /* clear page table address */
  168. sh7372_cpu_suspend();
  169. cpu_init();
  170. /* if page table address is non-NULL then we have been powered down */
  171. if (__raw_readl(smfram + 0x3c)) {
  172. __raw_writel(__raw_readl(smfram + 0x40),
  173. __va(__raw_readl(smfram + 0x3c)));
  174. flush_tlb_all();
  175. set_cr(__raw_readl(smfram + 0x38));
  176. }
  177. __raw_writel(0, SYSTBCR); /* disable core standby */
  178. __raw_writel(0, SBAR); /* disable reset vector translation */
  179. }
  180. #ifdef CONFIG_CPU_IDLE
  181. static void sh7372_cpuidle_setup(struct cpuidle_device *dev)
  182. {
  183. struct cpuidle_state *state;
  184. int i = dev->state_count;
  185. state = &dev->states[i];
  186. snprintf(state->name, CPUIDLE_NAME_LEN, "C2");
  187. strncpy(state->desc, "Core Standby Mode", CPUIDLE_DESC_LEN);
  188. state->exit_latency = 10;
  189. state->target_residency = 20 + 10;
  190. state->power_usage = 1; /* perhaps not */
  191. state->flags = 0;
  192. state->flags |= CPUIDLE_FLAG_TIME_VALID;
  193. shmobile_cpuidle_modes[i] = sh7372_enter_core_standby;
  194. dev->state_count = i + 1;
  195. }
  196. static void sh7372_cpuidle_init(void)
  197. {
  198. shmobile_cpuidle_setup = sh7372_cpuidle_setup;
  199. }
  200. #else
  201. static void sh7372_cpuidle_init(void) {}
  202. #endif
  203. #ifdef CONFIG_SUSPEND
  204. static int sh7372_enter_suspend(suspend_state_t suspend_state)
  205. {
  206. sh7372_enter_core_standby();
  207. return 0;
  208. }
  209. static void sh7372_suspend_init(void)
  210. {
  211. shmobile_suspend_ops.enter = sh7372_enter_suspend;
  212. }
  213. #else
  214. static void sh7372_suspend_init(void) {}
  215. #endif
  216. #define DBGREG1 0xe6100020
  217. #define DBGREG9 0xe6100040
  218. void __init sh7372_pm_init(void)
  219. {
  220. /* enable DBG hardware block to kick SYSC */
  221. __raw_writel(0x0000a500, DBGREG9);
  222. __raw_writel(0x0000a501, DBGREG9);
  223. __raw_writel(0x00000000, DBGREG1);
  224. sh7372_suspend_init();
  225. sh7372_cpuidle_init();
  226. }