bh.c 14 KB

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  1. /*
  2. * Device handling thread implementation for mac80211 ST-Ericsson CW1200 drivers
  3. *
  4. * Copyright (c) 2010, ST-Ericsson
  5. * Author: Dmitry Tarnyagin <dmitry.tarnyagin@lockless.no>
  6. *
  7. * Based on:
  8. * ST-Ericsson UMAC CW1200 driver, which is
  9. * Copyright (c) 2010, ST-Ericsson
  10. * Author: Ajitpal Singh <ajitpal.singh@stericsson.com>
  11. *
  12. * This program is free software; you can redistribute it and/or modify
  13. * it under the terms of the GNU General Public License version 2 as
  14. * published by the Free Software Foundation.
  15. */
  16. #include <linux/module.h>
  17. #include <net/mac80211.h>
  18. #include <linux/kthread.h>
  19. #include <linux/timer.h>
  20. #include "cw1200.h"
  21. #include "bh.h"
  22. #include "hwio.h"
  23. #include "wsm.h"
  24. #include "sbus.h"
  25. #include "debug.h"
  26. #include "fwio.h"
  27. static int cw1200_bh(void *arg);
  28. #define DOWNLOAD_BLOCK_SIZE_WR (0x1000 - 4)
  29. /* an SPI message cannot be bigger than (2"12-1)*2 bytes
  30. * "*2" to cvt to bytes */
  31. #define MAX_SZ_RD_WR_BUFFERS (DOWNLOAD_BLOCK_SIZE_WR*2)
  32. #define PIGGYBACK_CTRL_REG (2)
  33. #define EFFECTIVE_BUF_SIZE (MAX_SZ_RD_WR_BUFFERS - PIGGYBACK_CTRL_REG)
  34. /* Suspend state privates */
  35. enum cw1200_bh_pm_state {
  36. CW1200_BH_RESUMED = 0,
  37. CW1200_BH_SUSPEND,
  38. CW1200_BH_SUSPENDED,
  39. CW1200_BH_RESUME,
  40. };
  41. typedef int (*cw1200_wsm_handler)(struct cw1200_common *priv,
  42. u8 *data, size_t size);
  43. static void cw1200_bh_work(struct work_struct *work)
  44. {
  45. struct cw1200_common *priv =
  46. container_of(work, struct cw1200_common, bh_work);
  47. cw1200_bh(priv);
  48. }
  49. int cw1200_register_bh(struct cw1200_common *priv)
  50. {
  51. int err = 0;
  52. /* Realtime workqueue */
  53. priv->bh_workqueue = alloc_workqueue("cw1200_bh",
  54. WQ_MEM_RECLAIM | WQ_HIGHPRI
  55. | WQ_CPU_INTENSIVE, 1);
  56. if (!priv->bh_workqueue)
  57. return -ENOMEM;
  58. INIT_WORK(&priv->bh_work, cw1200_bh_work);
  59. pr_debug("[BH] register.\n");
  60. atomic_set(&priv->bh_rx, 0);
  61. atomic_set(&priv->bh_tx, 0);
  62. atomic_set(&priv->bh_term, 0);
  63. atomic_set(&priv->bh_suspend, CW1200_BH_RESUMED);
  64. priv->bh_error = 0;
  65. priv->hw_bufs_used = 0;
  66. priv->buf_id_tx = 0;
  67. priv->buf_id_rx = 0;
  68. init_waitqueue_head(&priv->bh_wq);
  69. init_waitqueue_head(&priv->bh_evt_wq);
  70. err = !queue_work(priv->bh_workqueue, &priv->bh_work);
  71. WARN_ON(err);
  72. return err;
  73. }
  74. void cw1200_unregister_bh(struct cw1200_common *priv)
  75. {
  76. atomic_add(1, &priv->bh_term);
  77. wake_up(&priv->bh_wq);
  78. flush_workqueue(priv->bh_workqueue);
  79. destroy_workqueue(priv->bh_workqueue);
  80. priv->bh_workqueue = NULL;
  81. pr_debug("[BH] unregistered.\n");
  82. }
  83. void cw1200_irq_handler(struct cw1200_common *priv)
  84. {
  85. pr_debug("[BH] irq.\n");
  86. /* Disable Interrupts! */
  87. /* NOTE: sbus_ops->lock already held */
  88. __cw1200_irq_enable(priv, 0);
  89. if (/* WARN_ON */(priv->bh_error))
  90. return;
  91. if (atomic_add_return(1, &priv->bh_rx) == 1)
  92. wake_up(&priv->bh_wq);
  93. }
  94. EXPORT_SYMBOL_GPL(cw1200_irq_handler);
  95. void cw1200_bh_wakeup(struct cw1200_common *priv)
  96. {
  97. pr_debug("[BH] wakeup.\n");
  98. if (priv->bh_error) {
  99. pr_err("[BH] wakeup failed (BH error)\n");
  100. return;
  101. }
  102. if (atomic_add_return(1, &priv->bh_tx) == 1)
  103. wake_up(&priv->bh_wq);
  104. }
  105. int cw1200_bh_suspend(struct cw1200_common *priv)
  106. {
  107. pr_debug("[BH] suspend.\n");
  108. if (priv->bh_error) {
  109. wiphy_warn(priv->hw->wiphy, "BH error -- can't suspend\n");
  110. return -EINVAL;
  111. }
  112. atomic_set(&priv->bh_suspend, CW1200_BH_SUSPEND);
  113. wake_up(&priv->bh_wq);
  114. return wait_event_timeout(priv->bh_evt_wq, priv->bh_error ||
  115. (CW1200_BH_SUSPENDED == atomic_read(&priv->bh_suspend)),
  116. 1 * HZ) ? 0 : -ETIMEDOUT;
  117. }
  118. int cw1200_bh_resume(struct cw1200_common *priv)
  119. {
  120. pr_debug("[BH] resume.\n");
  121. if (priv->bh_error) {
  122. wiphy_warn(priv->hw->wiphy, "BH error -- can't resume\n");
  123. return -EINVAL;
  124. }
  125. atomic_set(&priv->bh_suspend, CW1200_BH_RESUME);
  126. wake_up(&priv->bh_wq);
  127. return wait_event_timeout(priv->bh_evt_wq, priv->bh_error ||
  128. (CW1200_BH_RESUMED == atomic_read(&priv->bh_suspend)),
  129. 1 * HZ) ? 0 : -ETIMEDOUT;
  130. }
  131. static inline void wsm_alloc_tx_buffer(struct cw1200_common *priv)
  132. {
  133. ++priv->hw_bufs_used;
  134. }
  135. int wsm_release_tx_buffer(struct cw1200_common *priv, int count)
  136. {
  137. int ret = 0;
  138. int hw_bufs_used = priv->hw_bufs_used;
  139. priv->hw_bufs_used -= count;
  140. if (WARN_ON(priv->hw_bufs_used < 0))
  141. ret = -1;
  142. else if (hw_bufs_used >= priv->wsm_caps.input_buffers)
  143. ret = 1;
  144. if (!priv->hw_bufs_used)
  145. wake_up(&priv->bh_evt_wq);
  146. return ret;
  147. }
  148. static int cw1200_bh_read_ctrl_reg(struct cw1200_common *priv,
  149. u16 *ctrl_reg)
  150. {
  151. int ret;
  152. ret = cw1200_reg_read_16(priv,
  153. ST90TDS_CONTROL_REG_ID, ctrl_reg);
  154. if (ret) {
  155. ret = cw1200_reg_read_16(priv,
  156. ST90TDS_CONTROL_REG_ID, ctrl_reg);
  157. if (ret)
  158. pr_err("[BH] Failed to read control register.\n");
  159. }
  160. return ret;
  161. }
  162. static int cw1200_device_wakeup(struct cw1200_common *priv)
  163. {
  164. u16 ctrl_reg;
  165. int ret;
  166. pr_debug("[BH] Device wakeup.\n");
  167. /* First, set the dpll register */
  168. ret = cw1200_reg_write_32(priv, ST90TDS_TSET_GEN_R_W_REG_ID,
  169. cw1200_dpll_from_clk(priv->hw_refclk));
  170. if (WARN_ON(ret))
  171. return ret;
  172. /* To force the device to be always-on, the host sets WLAN_UP to 1 */
  173. ret = cw1200_reg_write_16(priv, ST90TDS_CONTROL_REG_ID,
  174. ST90TDS_CONT_WUP_BIT);
  175. if (WARN_ON(ret))
  176. return ret;
  177. ret = cw1200_bh_read_ctrl_reg(priv, &ctrl_reg);
  178. if (WARN_ON(ret))
  179. return ret;
  180. /* If the device returns WLAN_RDY as 1, the device is active and will
  181. * remain active. */
  182. if (ctrl_reg & ST90TDS_CONT_RDY_BIT) {
  183. pr_debug("[BH] Device awake.\n");
  184. return 1;
  185. }
  186. return 0;
  187. }
  188. /* Must be called from BH thraed. */
  189. void cw1200_enable_powersave(struct cw1200_common *priv,
  190. bool enable)
  191. {
  192. pr_debug("[BH] Powerave is %s.\n",
  193. enable ? "enabled" : "disabled");
  194. priv->powersave_enabled = enable;
  195. }
  196. static int cw1200_bh_rx_helper(struct cw1200_common *priv,
  197. uint16_t *ctrl_reg,
  198. int *tx)
  199. {
  200. size_t read_len = 0;
  201. struct sk_buff *skb_rx = NULL;
  202. struct wsm_hdr *wsm;
  203. size_t wsm_len;
  204. u16 wsm_id;
  205. u8 wsm_seq;
  206. int rx_resync = 1;
  207. size_t alloc_len;
  208. u8 *data;
  209. read_len = (*ctrl_reg & ST90TDS_CONT_NEXT_LEN_MASK) * 2;
  210. if (!read_len)
  211. return 0; /* No more work */
  212. if (WARN_ON((read_len < sizeof(struct wsm_hdr)) ||
  213. (read_len > EFFECTIVE_BUF_SIZE))) {
  214. pr_debug("Invalid read len: %zu (%04x)",
  215. read_len, *ctrl_reg);
  216. goto err;
  217. }
  218. /* Add SIZE of PIGGYBACK reg (CONTROL Reg)
  219. * to the NEXT Message length + 2 Bytes for SKB */
  220. read_len = read_len + 2;
  221. alloc_len = priv->sbus_ops->align_size(
  222. priv->sbus_priv, read_len);
  223. /* Check if not exceeding CW1200 capabilities */
  224. if (WARN_ON_ONCE(alloc_len > EFFECTIVE_BUF_SIZE)) {
  225. pr_debug("Read aligned len: %zu\n",
  226. alloc_len);
  227. }
  228. skb_rx = dev_alloc_skb(alloc_len);
  229. if (WARN_ON(!skb_rx))
  230. goto err;
  231. skb_trim(skb_rx, 0);
  232. skb_put(skb_rx, read_len);
  233. data = skb_rx->data;
  234. if (WARN_ON(!data))
  235. goto err;
  236. if (WARN_ON(cw1200_data_read(priv, data, alloc_len))) {
  237. pr_err("rx blew up, len %zu\n", alloc_len);
  238. goto err;
  239. }
  240. /* Piggyback */
  241. *ctrl_reg = __le16_to_cpu(
  242. ((__le16 *)data)[alloc_len / 2 - 1]);
  243. wsm = (struct wsm_hdr *)data;
  244. wsm_len = __le16_to_cpu(wsm->len);
  245. if (WARN_ON(wsm_len > read_len))
  246. goto err;
  247. if (priv->wsm_enable_wsm_dumps)
  248. print_hex_dump_bytes("<-- ",
  249. DUMP_PREFIX_NONE,
  250. data, wsm_len);
  251. wsm_id = __le16_to_cpu(wsm->id) & 0xFFF;
  252. wsm_seq = (__le16_to_cpu(wsm->id) >> 13) & 7;
  253. skb_trim(skb_rx, wsm_len);
  254. if (wsm_id == 0x0800) {
  255. wsm_handle_exception(priv,
  256. &data[sizeof(*wsm)],
  257. wsm_len - sizeof(*wsm));
  258. goto err;
  259. } else if (!rx_resync) {
  260. if (WARN_ON(wsm_seq != priv->wsm_rx_seq))
  261. goto err;
  262. }
  263. priv->wsm_rx_seq = (wsm_seq + 1) & 7;
  264. rx_resync = 0;
  265. if (wsm_id & 0x0400) {
  266. int rc = wsm_release_tx_buffer(priv, 1);
  267. if (WARN_ON(rc < 0))
  268. return rc;
  269. else if (rc > 0)
  270. *tx = 1;
  271. }
  272. /* cw1200_wsm_rx takes care on SKB livetime */
  273. if (WARN_ON(wsm_handle_rx(priv, wsm_id, wsm, &skb_rx)))
  274. goto err;
  275. if (skb_rx) {
  276. dev_kfree_skb(skb_rx);
  277. skb_rx = NULL;
  278. }
  279. return 0;
  280. err:
  281. if (skb_rx) {
  282. dev_kfree_skb(skb_rx);
  283. skb_rx = NULL;
  284. }
  285. return -1;
  286. }
  287. static int cw1200_bh_tx_helper(struct cw1200_common *priv,
  288. int *pending_tx,
  289. int *tx_burst)
  290. {
  291. size_t tx_len;
  292. u8 *data;
  293. int ret;
  294. struct wsm_hdr *wsm;
  295. if (priv->device_can_sleep) {
  296. ret = cw1200_device_wakeup(priv);
  297. if (WARN_ON(ret < 0)) { /* Error in wakeup */
  298. *pending_tx = 1;
  299. return 0;
  300. } else if (ret) { /* Woke up */
  301. priv->device_can_sleep = false;
  302. } else { /* Did not awake */
  303. *pending_tx = 1;
  304. return 0;
  305. }
  306. }
  307. wsm_alloc_tx_buffer(priv);
  308. ret = wsm_get_tx(priv, &data, &tx_len, tx_burst);
  309. if (ret <= 0) {
  310. wsm_release_tx_buffer(priv, 1);
  311. if (WARN_ON(ret < 0))
  312. return ret; /* Error */
  313. return 0; /* No work */
  314. }
  315. wsm = (struct wsm_hdr *)data;
  316. BUG_ON(tx_len < sizeof(*wsm));
  317. BUG_ON(__le16_to_cpu(wsm->len) != tx_len);
  318. atomic_add(1, &priv->bh_tx);
  319. tx_len = priv->sbus_ops->align_size(
  320. priv->sbus_priv, tx_len);
  321. /* Check if not exceeding CW1200 capabilities */
  322. if (WARN_ON_ONCE(tx_len > EFFECTIVE_BUF_SIZE))
  323. pr_debug("Write aligned len: %zu\n", tx_len);
  324. wsm->id &= __cpu_to_le16(0xffff ^ WSM_TX_SEQ(WSM_TX_SEQ_MAX));
  325. wsm->id |= __cpu_to_le16(WSM_TX_SEQ(priv->wsm_tx_seq));
  326. if (WARN_ON(cw1200_data_write(priv, data, tx_len))) {
  327. pr_err("tx blew up, len %zu\n", tx_len);
  328. wsm_release_tx_buffer(priv, 1);
  329. return -1; /* Error */
  330. }
  331. if (priv->wsm_enable_wsm_dumps)
  332. print_hex_dump_bytes("--> ",
  333. DUMP_PREFIX_NONE,
  334. data,
  335. __le16_to_cpu(wsm->len));
  336. wsm_txed(priv, data);
  337. priv->wsm_tx_seq = (priv->wsm_tx_seq + 1) & WSM_TX_SEQ_MAX;
  338. if (*tx_burst > 1) {
  339. cw1200_debug_tx_burst(priv);
  340. return 1; /* Work remains */
  341. }
  342. return 0;
  343. }
  344. static int cw1200_bh(void *arg)
  345. {
  346. struct cw1200_common *priv = arg;
  347. int rx, tx, term, suspend;
  348. u16 ctrl_reg = 0;
  349. int tx_allowed;
  350. int pending_tx = 0;
  351. int tx_burst;
  352. long status;
  353. u32 dummy;
  354. int ret;
  355. for (;;) {
  356. if (!priv->hw_bufs_used &&
  357. priv->powersave_enabled &&
  358. !priv->device_can_sleep &&
  359. !atomic_read(&priv->recent_scan)) {
  360. status = 1 * HZ;
  361. pr_debug("[BH] Device wakedown. No data.\n");
  362. cw1200_reg_write_16(priv, ST90TDS_CONTROL_REG_ID, 0);
  363. priv->device_can_sleep = true;
  364. } else if (priv->hw_bufs_used) {
  365. /* Interrupt loss detection */
  366. status = 1 * HZ;
  367. } else {
  368. status = MAX_SCHEDULE_TIMEOUT;
  369. }
  370. /* Dummy Read for SDIO retry mechanism*/
  371. if ((priv->hw_type != -1) &&
  372. (atomic_read(&priv->bh_rx) == 0) &&
  373. (atomic_read(&priv->bh_tx) == 0))
  374. cw1200_reg_read(priv, ST90TDS_CONFIG_REG_ID,
  375. &dummy, sizeof(dummy));
  376. pr_debug("[BH] waiting ...\n");
  377. status = wait_event_interruptible_timeout(priv->bh_wq, ({
  378. rx = atomic_xchg(&priv->bh_rx, 0);
  379. tx = atomic_xchg(&priv->bh_tx, 0);
  380. term = atomic_xchg(&priv->bh_term, 0);
  381. suspend = pending_tx ?
  382. 0 : atomic_read(&priv->bh_suspend);
  383. (rx || tx || term || suspend || priv->bh_error);
  384. }), status);
  385. pr_debug("[BH] - rx: %d, tx: %d, term: %d, suspend: %d, status: %ld\n",
  386. rx, tx, term, suspend, status);
  387. /* Did an error occur? */
  388. if ((status < 0 && status != -ERESTARTSYS) ||
  389. term || priv->bh_error) {
  390. break;
  391. }
  392. if (!status) { /* wait_event timed out */
  393. unsigned long timestamp = jiffies;
  394. long timeout;
  395. int pending = 0;
  396. int i;
  397. /* Check to see if we have any outstanding frames */
  398. if (priv->hw_bufs_used && (!rx || !tx)) {
  399. wiphy_warn(priv->hw->wiphy,
  400. "Missed interrupt? (%d frames outstanding)\n",
  401. priv->hw_bufs_used);
  402. rx = 1;
  403. /* Get a timestamp of "oldest" frame */
  404. for (i = 0; i < 4; ++i)
  405. pending += cw1200_queue_get_xmit_timestamp(
  406. &priv->tx_queue[i],
  407. &timestamp,
  408. priv->pending_frame_id);
  409. /* Check if frame transmission is timed out.
  410. * Add an extra second with respect to possible
  411. * interrupt loss.
  412. */
  413. timeout = timestamp +
  414. WSM_CMD_LAST_CHANCE_TIMEOUT +
  415. 1 * HZ -
  416. jiffies;
  417. /* And terminate BH thread if the frame is "stuck" */
  418. if (pending && timeout < 0) {
  419. wiphy_warn(priv->hw->wiphy,
  420. "Timeout waiting for TX confirm (%d/%d pending, %ld vs %lu).\n",
  421. priv->hw_bufs_used, pending,
  422. timestamp, jiffies);
  423. break;
  424. }
  425. } else if (!priv->device_can_sleep &&
  426. !atomic_read(&priv->recent_scan)) {
  427. pr_debug("[BH] Device wakedown. Timeout.\n");
  428. cw1200_reg_write_16(priv,
  429. ST90TDS_CONTROL_REG_ID, 0);
  430. priv->device_can_sleep = true;
  431. }
  432. goto done;
  433. } else if (suspend) {
  434. pr_debug("[BH] Device suspend.\n");
  435. if (priv->powersave_enabled) {
  436. pr_debug("[BH] Device wakedown. Suspend.\n");
  437. cw1200_reg_write_16(priv,
  438. ST90TDS_CONTROL_REG_ID, 0);
  439. priv->device_can_sleep = true;
  440. }
  441. atomic_set(&priv->bh_suspend, CW1200_BH_SUSPENDED);
  442. wake_up(&priv->bh_evt_wq);
  443. status = wait_event_interruptible(priv->bh_wq,
  444. CW1200_BH_RESUME == atomic_read(&priv->bh_suspend));
  445. if (status < 0) {
  446. wiphy_err(priv->hw->wiphy,
  447. "Failed to wait for resume: %ld.\n",
  448. status);
  449. break;
  450. }
  451. pr_debug("[BH] Device resume.\n");
  452. atomic_set(&priv->bh_suspend, CW1200_BH_RESUMED);
  453. wake_up(&priv->bh_evt_wq);
  454. atomic_add(1, &priv->bh_rx);
  455. goto done;
  456. }
  457. rx:
  458. tx += pending_tx;
  459. pending_tx = 0;
  460. if (cw1200_bh_read_ctrl_reg(priv, &ctrl_reg))
  461. break;
  462. /* Don't bother trying to rx unless we have data to read */
  463. if (ctrl_reg & ST90TDS_CONT_NEXT_LEN_MASK) {
  464. ret = cw1200_bh_rx_helper(priv, &ctrl_reg, &tx);
  465. if (ret < 0)
  466. break;
  467. /* Double up here if there's more data.. */
  468. if (ctrl_reg & ST90TDS_CONT_NEXT_LEN_MASK) {
  469. ret = cw1200_bh_rx_helper(priv, &ctrl_reg, &tx);
  470. if (ret < 0)
  471. break;
  472. }
  473. }
  474. tx:
  475. if (tx) {
  476. tx = 0;
  477. BUG_ON(priv->hw_bufs_used > priv->wsm_caps.input_buffers);
  478. tx_burst = priv->wsm_caps.input_buffers - priv->hw_bufs_used;
  479. tx_allowed = tx_burst > 0;
  480. if (!tx_allowed) {
  481. /* Buffers full. Ensure we process tx
  482. * after we handle rx..
  483. */
  484. pending_tx = tx;
  485. goto done_rx;
  486. }
  487. ret = cw1200_bh_tx_helper(priv, &pending_tx, &tx_burst);
  488. if (ret < 0)
  489. break;
  490. if (ret > 0) /* More to transmit */
  491. tx = ret;
  492. /* Re-read ctrl reg */
  493. if (cw1200_bh_read_ctrl_reg(priv, &ctrl_reg))
  494. break;
  495. }
  496. done_rx:
  497. if (priv->bh_error)
  498. break;
  499. if (ctrl_reg & ST90TDS_CONT_NEXT_LEN_MASK)
  500. goto rx;
  501. if (tx)
  502. goto tx;
  503. done:
  504. /* Re-enable device interrupts */
  505. priv->sbus_ops->lock(priv->sbus_priv);
  506. __cw1200_irq_enable(priv, 1);
  507. priv->sbus_ops->unlock(priv->sbus_priv);
  508. }
  509. /* Explicitly disable device interrupts */
  510. priv->sbus_ops->lock(priv->sbus_priv);
  511. __cw1200_irq_enable(priv, 0);
  512. priv->sbus_ops->unlock(priv->sbus_priv);
  513. if (!term) {
  514. pr_err("[BH] Fatal error, exiting.\n");
  515. priv->bh_error = 1;
  516. /* TODO: schedule_work(recovery) */
  517. }
  518. return 0;
  519. }