rts5249.c 8.0 KB

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  1. /* Driver for Realtek PCI-Express card reader
  2. *
  3. * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms of the GNU General Public License as published by the
  7. * Free Software Foundation; either version 2, or (at your option) any
  8. * later version.
  9. *
  10. * This program is distributed in the hope that it will be useful, but
  11. * WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  13. * General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License along
  16. * with this program; if not, see <http://www.gnu.org/licenses/>.
  17. *
  18. * Author:
  19. * Wei WANG <wei_wang@realsil.com.cn>
  20. * No. 128, West Shenhu Road, Suzhou Industry Park, Suzhou, China
  21. */
  22. #include <linux/module.h>
  23. #include <linux/delay.h>
  24. #include <linux/mfd/rtsx_pci.h>
  25. #include "rtsx_pcr.h"
  26. static u8 rts5249_get_ic_version(struct rtsx_pcr *pcr)
  27. {
  28. u8 val;
  29. rtsx_pci_read_register(pcr, DUMMY_REG_RESET_0, &val);
  30. return val & 0x0F;
  31. }
  32. static void rts5249_fill_driving(struct rtsx_pcr *pcr, u8 voltage)
  33. {
  34. u8 driving_3v3[4][3] = {
  35. {0x11, 0x11, 0x11},
  36. {0x55, 0x55, 0x5C},
  37. {0x99, 0x99, 0x92},
  38. {0x99, 0x99, 0x92},
  39. };
  40. u8 driving_1v8[4][3] = {
  41. {0x3C, 0x3C, 0x3C},
  42. {0xB3, 0xB3, 0xB3},
  43. {0xFE, 0xFE, 0xFE},
  44. {0xC4, 0xC4, 0xC4},
  45. };
  46. u8 (*driving)[3], drive_sel;
  47. if (voltage == OUTPUT_3V3) {
  48. driving = driving_3v3;
  49. drive_sel = pcr->sd30_drive_sel_3v3;
  50. } else {
  51. driving = driving_1v8;
  52. drive_sel = pcr->sd30_drive_sel_1v8;
  53. }
  54. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_CLK_DRIVE_SEL,
  55. 0xFF, driving[drive_sel][0]);
  56. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_CMD_DRIVE_SEL,
  57. 0xFF, driving[drive_sel][1]);
  58. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_DAT_DRIVE_SEL,
  59. 0xFF, driving[drive_sel][2]);
  60. }
  61. static void rts5249_fetch_vendor_settings(struct rtsx_pcr *pcr)
  62. {
  63. u32 reg;
  64. rtsx_pci_read_config_dword(pcr, PCR_SETTING_REG1, &reg);
  65. dev_dbg(&(pcr->pci->dev), "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG1, reg);
  66. if (!rtsx_vendor_setting_valid(reg))
  67. return;
  68. pcr->aspm_en = rtsx_reg_to_aspm(reg);
  69. pcr->sd30_drive_sel_1v8 = rtsx_reg_to_sd30_drive_sel_1v8(reg);
  70. pcr->card_drive_sel &= 0x3F;
  71. pcr->card_drive_sel |= rtsx_reg_to_card_drive_sel(reg);
  72. rtsx_pci_read_config_dword(pcr, PCR_SETTING_REG2, &reg);
  73. dev_dbg(&(pcr->pci->dev), "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG2, reg);
  74. pcr->sd30_drive_sel_3v3 = rtsx_reg_to_sd30_drive_sel_3v3(reg);
  75. if (rtsx_reg_check_reverse_socket(reg))
  76. pcr->flags |= PCR_REVERSE_SOCKET;
  77. }
  78. static int rts5249_extra_init_hw(struct rtsx_pcr *pcr)
  79. {
  80. rtsx_pci_init_cmd(pcr);
  81. /* Configure GPIO as output */
  82. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, GPIO_CTL, 0x02, 0x02);
  83. /* Switch LDO3318 source from DV33 to card_3v3 */
  84. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_PWR_SEL, 0x03, 0x00);
  85. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_PWR_SEL, 0x03, 0x01);
  86. /* LED shine disabled, set initial shine cycle period */
  87. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, OLT_LED_CTL, 0x0F, 0x02);
  88. /* Configure driving */
  89. rts5249_fill_driving(pcr, OUTPUT_3V3);
  90. if (pcr->flags & PCR_REVERSE_SOCKET)
  91. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
  92. AUTOLOAD_CFG_BASE + 3, 0xB0, 0xB0);
  93. else
  94. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
  95. AUTOLOAD_CFG_BASE + 3, 0xB0, 0x80);
  96. return rtsx_pci_send_cmd(pcr, 100);
  97. }
  98. static int rts5249_optimize_phy(struct rtsx_pcr *pcr)
  99. {
  100. int err;
  101. err = rtsx_pci_write_phy_register(pcr, PHY_REG_REV, 0xFE46);
  102. if (err < 0)
  103. return err;
  104. msleep(1);
  105. return rtsx_pci_write_phy_register(pcr, PHY_BPCR, 0x05C0);
  106. }
  107. static int rts5249_turn_on_led(struct rtsx_pcr *pcr)
  108. {
  109. return rtsx_pci_write_register(pcr, GPIO_CTL, 0x02, 0x02);
  110. }
  111. static int rts5249_turn_off_led(struct rtsx_pcr *pcr)
  112. {
  113. return rtsx_pci_write_register(pcr, GPIO_CTL, 0x02, 0x00);
  114. }
  115. static int rts5249_enable_auto_blink(struct rtsx_pcr *pcr)
  116. {
  117. return rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x08, 0x08);
  118. }
  119. static int rts5249_disable_auto_blink(struct rtsx_pcr *pcr)
  120. {
  121. return rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x08, 0x00);
  122. }
  123. static int rts5249_card_power_on(struct rtsx_pcr *pcr, int card)
  124. {
  125. int err;
  126. rtsx_pci_init_cmd(pcr);
  127. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
  128. SD_POWER_MASK, SD_VCC_PARTIAL_POWER_ON);
  129. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
  130. LDO3318_PWR_MASK, 0x02);
  131. err = rtsx_pci_send_cmd(pcr, 100);
  132. if (err < 0)
  133. return err;
  134. msleep(5);
  135. rtsx_pci_init_cmd(pcr);
  136. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
  137. SD_POWER_MASK, SD_VCC_POWER_ON);
  138. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
  139. LDO3318_PWR_MASK, 0x06);
  140. err = rtsx_pci_send_cmd(pcr, 100);
  141. if (err < 0)
  142. return err;
  143. return 0;
  144. }
  145. static int rts5249_card_power_off(struct rtsx_pcr *pcr, int card)
  146. {
  147. rtsx_pci_init_cmd(pcr);
  148. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
  149. SD_POWER_MASK, SD_POWER_OFF);
  150. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
  151. LDO3318_PWR_MASK, 0x00);
  152. return rtsx_pci_send_cmd(pcr, 100);
  153. }
  154. static int rts5249_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
  155. {
  156. int err;
  157. if (voltage == OUTPUT_3V3) {
  158. err = rtsx_pci_write_phy_register(pcr, PHY_TUNE, 0x4FC0 | 0x24);
  159. if (err < 0)
  160. return err;
  161. } else if (voltage == OUTPUT_1V8) {
  162. err = rtsx_pci_write_phy_register(pcr, PHY_BACR, 0x3C02);
  163. if (err < 0)
  164. return err;
  165. err = rtsx_pci_write_phy_register(pcr, PHY_TUNE, 0x4C40 | 0x24);
  166. if (err < 0)
  167. return err;
  168. } else {
  169. return -EINVAL;
  170. }
  171. /* set pad drive */
  172. rtsx_pci_init_cmd(pcr);
  173. rts5249_fill_driving(pcr, voltage);
  174. return rtsx_pci_send_cmd(pcr, 100);
  175. }
  176. static const struct pcr_ops rts5249_pcr_ops = {
  177. .fetch_vendor_settings = rts5249_fetch_vendor_settings,
  178. .extra_init_hw = rts5249_extra_init_hw,
  179. .optimize_phy = rts5249_optimize_phy,
  180. .turn_on_led = rts5249_turn_on_led,
  181. .turn_off_led = rts5249_turn_off_led,
  182. .enable_auto_blink = rts5249_enable_auto_blink,
  183. .disable_auto_blink = rts5249_disable_auto_blink,
  184. .card_power_on = rts5249_card_power_on,
  185. .card_power_off = rts5249_card_power_off,
  186. .switch_output_voltage = rts5249_switch_output_voltage,
  187. };
  188. /* SD Pull Control Enable:
  189. * SD_DAT[3:0] ==> pull up
  190. * SD_CD ==> pull up
  191. * SD_WP ==> pull up
  192. * SD_CMD ==> pull up
  193. * SD_CLK ==> pull down
  194. */
  195. static const u32 rts5249_sd_pull_ctl_enable_tbl[] = {
  196. RTSX_REG_PAIR(CARD_PULL_CTL1, 0x66),
  197. RTSX_REG_PAIR(CARD_PULL_CTL2, 0xAA),
  198. RTSX_REG_PAIR(CARD_PULL_CTL3, 0xE9),
  199. RTSX_REG_PAIR(CARD_PULL_CTL4, 0xAA),
  200. 0,
  201. };
  202. /* SD Pull Control Disable:
  203. * SD_DAT[3:0] ==> pull down
  204. * SD_CD ==> pull up
  205. * SD_WP ==> pull down
  206. * SD_CMD ==> pull down
  207. * SD_CLK ==> pull down
  208. */
  209. static const u32 rts5249_sd_pull_ctl_disable_tbl[] = {
  210. RTSX_REG_PAIR(CARD_PULL_CTL1, 0x66),
  211. RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55),
  212. RTSX_REG_PAIR(CARD_PULL_CTL3, 0xD5),
  213. RTSX_REG_PAIR(CARD_PULL_CTL4, 0x55),
  214. 0,
  215. };
  216. /* MS Pull Control Enable:
  217. * MS CD ==> pull up
  218. * others ==> pull down
  219. */
  220. static const u32 rts5249_ms_pull_ctl_enable_tbl[] = {
  221. RTSX_REG_PAIR(CARD_PULL_CTL4, 0x55),
  222. RTSX_REG_PAIR(CARD_PULL_CTL5, 0x55),
  223. RTSX_REG_PAIR(CARD_PULL_CTL6, 0x15),
  224. 0,
  225. };
  226. /* MS Pull Control Disable:
  227. * MS CD ==> pull up
  228. * others ==> pull down
  229. */
  230. static const u32 rts5249_ms_pull_ctl_disable_tbl[] = {
  231. RTSX_REG_PAIR(CARD_PULL_CTL4, 0x55),
  232. RTSX_REG_PAIR(CARD_PULL_CTL5, 0x55),
  233. RTSX_REG_PAIR(CARD_PULL_CTL6, 0x15),
  234. 0,
  235. };
  236. void rts5249_init_params(struct rtsx_pcr *pcr)
  237. {
  238. pcr->extra_caps = EXTRA_CAPS_SD_SDR50 | EXTRA_CAPS_SD_SDR104;
  239. pcr->num_slots = 2;
  240. pcr->ops = &rts5249_pcr_ops;
  241. pcr->flags = 0;
  242. pcr->card_drive_sel = RTSX_CARD_DRIVE_DEFAULT;
  243. pcr->sd30_drive_sel_1v8 = CFG_DRIVER_TYPE_C;
  244. pcr->sd30_drive_sel_3v3 = CFG_DRIVER_TYPE_B;
  245. pcr->aspm_en = ASPM_L1_EN;
  246. pcr->ic_version = rts5249_get_ic_version(pcr);
  247. pcr->sd_pull_ctl_enable_tbl = rts5249_sd_pull_ctl_enable_tbl;
  248. pcr->sd_pull_ctl_disable_tbl = rts5249_sd_pull_ctl_disable_tbl;
  249. pcr->ms_pull_ctl_enable_tbl = rts5249_ms_pull_ctl_enable_tbl;
  250. pcr->ms_pull_ctl_disable_tbl = rts5249_ms_pull_ctl_disable_tbl;
  251. }