rts5227.c 8.0 KB

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  1. /* Driver for Realtek PCI-Express card reader
  2. *
  3. * Copyright(c) 2009 Realtek Semiconductor Corp. All rights reserved.
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms of the GNU General Public License as published by the
  7. * Free Software Foundation; either version 2, or (at your option) any
  8. * later version.
  9. *
  10. * This program is distributed in the hope that it will be useful, but
  11. * WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  13. * General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License along
  16. * with this program; if not, see <http://www.gnu.org/licenses/>.
  17. *
  18. * Author:
  19. * Wei WANG <wei_wang@realsil.com.cn>
  20. * No. 450, Shenhu Road, Suzhou Industry Park, Suzhou, China
  21. *
  22. * Roger Tseng <rogerable@realtek.com>
  23. * No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan
  24. */
  25. #include <linux/module.h>
  26. #include <linux/delay.h>
  27. #include <linux/mfd/rtsx_pci.h>
  28. #include "rtsx_pcr.h"
  29. static void rts5227_fill_driving(struct rtsx_pcr *pcr, u8 voltage)
  30. {
  31. u8 driving_3v3[4][3] = {
  32. {0x13, 0x13, 0x13},
  33. {0x96, 0x96, 0x96},
  34. {0x7F, 0x7F, 0x7F},
  35. {0x96, 0x96, 0x96},
  36. };
  37. u8 driving_1v8[4][3] = {
  38. {0x99, 0x99, 0x99},
  39. {0xAA, 0xAA, 0xAA},
  40. {0xFE, 0xFE, 0xFE},
  41. {0xB3, 0xB3, 0xB3},
  42. };
  43. u8 (*driving)[3], drive_sel;
  44. if (voltage == OUTPUT_3V3) {
  45. driving = driving_3v3;
  46. drive_sel = pcr->sd30_drive_sel_3v3;
  47. } else {
  48. driving = driving_1v8;
  49. drive_sel = pcr->sd30_drive_sel_1v8;
  50. }
  51. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_CLK_DRIVE_SEL,
  52. 0xFF, driving[drive_sel][0]);
  53. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_CMD_DRIVE_SEL,
  54. 0xFF, driving[drive_sel][1]);
  55. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_DAT_DRIVE_SEL,
  56. 0xFF, driving[drive_sel][2]);
  57. }
  58. static void rts5227_fetch_vendor_settings(struct rtsx_pcr *pcr)
  59. {
  60. u32 reg;
  61. rtsx_pci_read_config_dword(pcr, PCR_SETTING_REG1, &reg);
  62. dev_dbg(&(pcr->pci->dev), "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG1, reg);
  63. if (!rtsx_vendor_setting_valid(reg))
  64. return;
  65. pcr->aspm_en = rtsx_reg_to_aspm(reg);
  66. pcr->sd30_drive_sel_1v8 = rtsx_reg_to_sd30_drive_sel_1v8(reg);
  67. pcr->card_drive_sel &= 0x3F;
  68. pcr->card_drive_sel |= rtsx_reg_to_card_drive_sel(reg);
  69. rtsx_pci_read_config_dword(pcr, PCR_SETTING_REG2, &reg);
  70. dev_dbg(&(pcr->pci->dev), "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG2, reg);
  71. pcr->sd30_drive_sel_3v3 = rtsx_reg_to_sd30_drive_sel_3v3(reg);
  72. if (rtsx_reg_check_reverse_socket(reg))
  73. pcr->flags |= PCR_REVERSE_SOCKET;
  74. }
  75. static int rts5227_extra_init_hw(struct rtsx_pcr *pcr)
  76. {
  77. u16 cap;
  78. rtsx_pci_init_cmd(pcr);
  79. /* Configure GPIO as output */
  80. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, GPIO_CTL, 0x02, 0x02);
  81. /* Switch LDO3318 source from DV33 to card_3v3 */
  82. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_PWR_SEL, 0x03, 0x00);
  83. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_PWR_SEL, 0x03, 0x01);
  84. /* LED shine disabled, set initial shine cycle period */
  85. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, OLT_LED_CTL, 0x0F, 0x02);
  86. /* Configure LTR */
  87. pcie_capability_read_word(pcr->pci, PCI_EXP_DEVCTL2, &cap);
  88. if (cap & PCI_EXP_LTR_EN)
  89. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LTR_CTL, 0xFF, 0xA3);
  90. /* Configure OBFF */
  91. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, OBFF_CFG, 0x03, 0x03);
  92. /* Configure driving */
  93. rts5227_fill_driving(pcr, OUTPUT_3V3);
  94. /* Configure force_clock_req */
  95. if (pcr->flags & PCR_REVERSE_SOCKET)
  96. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
  97. AUTOLOAD_CFG_BASE + 3, 0xB8, 0xB8);
  98. else
  99. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
  100. AUTOLOAD_CFG_BASE + 3, 0xB8, 0x88);
  101. return rtsx_pci_send_cmd(pcr, 100);
  102. }
  103. static int rts5227_optimize_phy(struct rtsx_pcr *pcr)
  104. {
  105. /* Optimize RX sensitivity */
  106. return rtsx_pci_write_phy_register(pcr, 0x00, 0xBA42);
  107. }
  108. static int rts5227_turn_on_led(struct rtsx_pcr *pcr)
  109. {
  110. return rtsx_pci_write_register(pcr, GPIO_CTL, 0x02, 0x02);
  111. }
  112. static int rts5227_turn_off_led(struct rtsx_pcr *pcr)
  113. {
  114. return rtsx_pci_write_register(pcr, GPIO_CTL, 0x02, 0x00);
  115. }
  116. static int rts5227_enable_auto_blink(struct rtsx_pcr *pcr)
  117. {
  118. return rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x08, 0x08);
  119. }
  120. static int rts5227_disable_auto_blink(struct rtsx_pcr *pcr)
  121. {
  122. return rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x08, 0x00);
  123. }
  124. static int rts5227_card_power_on(struct rtsx_pcr *pcr, int card)
  125. {
  126. int err;
  127. rtsx_pci_init_cmd(pcr);
  128. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
  129. SD_POWER_MASK, SD_PARTIAL_POWER_ON);
  130. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
  131. LDO3318_PWR_MASK, 0x02);
  132. err = rtsx_pci_send_cmd(pcr, 100);
  133. if (err < 0)
  134. return err;
  135. /* To avoid too large in-rush current */
  136. udelay(150);
  137. rtsx_pci_init_cmd(pcr);
  138. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
  139. SD_POWER_MASK, SD_POWER_ON);
  140. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
  141. LDO3318_PWR_MASK, 0x06);
  142. err = rtsx_pci_send_cmd(pcr, 100);
  143. if (err < 0)
  144. return err;
  145. return 0;
  146. }
  147. static int rts5227_card_power_off(struct rtsx_pcr *pcr, int card)
  148. {
  149. rtsx_pci_init_cmd(pcr);
  150. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
  151. SD_POWER_MASK | PMOS_STRG_MASK,
  152. SD_POWER_OFF | PMOS_STRG_400mA);
  153. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
  154. LDO3318_PWR_MASK, 0X00);
  155. return rtsx_pci_send_cmd(pcr, 100);
  156. }
  157. static int rts5227_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
  158. {
  159. int err;
  160. if (voltage == OUTPUT_3V3) {
  161. err = rtsx_pci_write_phy_register(pcr, 0x08, 0x4FC0 | 0x24);
  162. if (err < 0)
  163. return err;
  164. } else if (voltage == OUTPUT_1V8) {
  165. err = rtsx_pci_write_phy_register(pcr, 0x11, 0x3C02);
  166. if (err < 0)
  167. return err;
  168. err = rtsx_pci_write_phy_register(pcr, 0x08, 0x4C80 | 0x24);
  169. if (err < 0)
  170. return err;
  171. } else {
  172. return -EINVAL;
  173. }
  174. /* set pad drive */
  175. rtsx_pci_init_cmd(pcr);
  176. rts5227_fill_driving(pcr, voltage);
  177. return rtsx_pci_send_cmd(pcr, 100);
  178. }
  179. static const struct pcr_ops rts5227_pcr_ops = {
  180. .fetch_vendor_settings = rts5227_fetch_vendor_settings,
  181. .extra_init_hw = rts5227_extra_init_hw,
  182. .optimize_phy = rts5227_optimize_phy,
  183. .turn_on_led = rts5227_turn_on_led,
  184. .turn_off_led = rts5227_turn_off_led,
  185. .enable_auto_blink = rts5227_enable_auto_blink,
  186. .disable_auto_blink = rts5227_disable_auto_blink,
  187. .card_power_on = rts5227_card_power_on,
  188. .card_power_off = rts5227_card_power_off,
  189. .switch_output_voltage = rts5227_switch_output_voltage,
  190. .cd_deglitch = NULL,
  191. .conv_clk_and_div_n = NULL,
  192. };
  193. /* SD Pull Control Enable:
  194. * SD_DAT[3:0] ==> pull up
  195. * SD_CD ==> pull up
  196. * SD_WP ==> pull up
  197. * SD_CMD ==> pull up
  198. * SD_CLK ==> pull down
  199. */
  200. static const u32 rts5227_sd_pull_ctl_enable_tbl[] = {
  201. RTSX_REG_PAIR(CARD_PULL_CTL2, 0xAA),
  202. RTSX_REG_PAIR(CARD_PULL_CTL3, 0xE9),
  203. 0,
  204. };
  205. /* SD Pull Control Disable:
  206. * SD_DAT[3:0] ==> pull down
  207. * SD_CD ==> pull up
  208. * SD_WP ==> pull down
  209. * SD_CMD ==> pull down
  210. * SD_CLK ==> pull down
  211. */
  212. static const u32 rts5227_sd_pull_ctl_disable_tbl[] = {
  213. RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55),
  214. RTSX_REG_PAIR(CARD_PULL_CTL3, 0xD5),
  215. 0,
  216. };
  217. /* MS Pull Control Enable:
  218. * MS CD ==> pull up
  219. * others ==> pull down
  220. */
  221. static const u32 rts5227_ms_pull_ctl_enable_tbl[] = {
  222. RTSX_REG_PAIR(CARD_PULL_CTL5, 0x55),
  223. RTSX_REG_PAIR(CARD_PULL_CTL6, 0x15),
  224. 0,
  225. };
  226. /* MS Pull Control Disable:
  227. * MS CD ==> pull up
  228. * others ==> pull down
  229. */
  230. static const u32 rts5227_ms_pull_ctl_disable_tbl[] = {
  231. RTSX_REG_PAIR(CARD_PULL_CTL5, 0x55),
  232. RTSX_REG_PAIR(CARD_PULL_CTL6, 0x15),
  233. 0,
  234. };
  235. void rts5227_init_params(struct rtsx_pcr *pcr)
  236. {
  237. pcr->extra_caps = EXTRA_CAPS_SD_SDR50 | EXTRA_CAPS_SD_SDR104;
  238. pcr->num_slots = 2;
  239. pcr->ops = &rts5227_pcr_ops;
  240. pcr->flags = 0;
  241. pcr->card_drive_sel = RTSX_CARD_DRIVE_DEFAULT;
  242. pcr->sd30_drive_sel_1v8 = CFG_DRIVER_TYPE_B;
  243. pcr->sd30_drive_sel_3v3 = CFG_DRIVER_TYPE_B;
  244. pcr->aspm_en = ASPM_L1_EN;
  245. pcr->sd_pull_ctl_enable_tbl = rts5227_sd_pull_ctl_enable_tbl;
  246. pcr->sd_pull_ctl_disable_tbl = rts5227_sd_pull_ctl_disable_tbl;
  247. pcr->ms_pull_ctl_enable_tbl = rts5227_ms_pull_ctl_enable_tbl;
  248. pcr->ms_pull_ctl_disable_tbl = rts5227_ms_pull_ctl_disable_tbl;
  249. }