atl1c_main.c 77 KB

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  1. /*
  2. * Copyright(c) 2008 - 2009 Atheros Corporation. All rights reserved.
  3. *
  4. * Derived from Intel e1000 driver
  5. * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
  6. *
  7. * This program is free software; you can redistribute it and/or modify it
  8. * under the terms of the GNU General Public License as published by the Free
  9. * Software Foundation; either version 2 of the License, or (at your option)
  10. * any later version.
  11. *
  12. * This program is distributed in the hope that it will be useful, but WITHOUT
  13. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  15. * more details.
  16. *
  17. * You should have received a copy of the GNU General Public License along with
  18. * this program; if not, write to the Free Software Foundation, Inc., 59
  19. * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  20. */
  21. #include "atl1c.h"
  22. #define ATL1C_DRV_VERSION "1.0.1.0-NAPI"
  23. char atl1c_driver_name[] = "atl1c";
  24. char atl1c_driver_version[] = ATL1C_DRV_VERSION;
  25. #define PCI_DEVICE_ID_ATTANSIC_L2C 0x1062
  26. #define PCI_DEVICE_ID_ATTANSIC_L1C 0x1063
  27. #define PCI_DEVICE_ID_ATHEROS_L2C_B 0x2060 /* AR8152 v1.1 Fast 10/100 */
  28. #define PCI_DEVICE_ID_ATHEROS_L2C_B2 0x2062 /* AR8152 v2.0 Fast 10/100 */
  29. #define PCI_DEVICE_ID_ATHEROS_L1D 0x1073 /* AR8151 v1.0 Gigabit 1000 */
  30. #define PCI_DEVICE_ID_ATHEROS_L1D_2_0 0x1083 /* AR8151 v2.0 Gigabit 1000 */
  31. #define L2CB_V10 0xc0
  32. #define L2CB_V11 0xc1
  33. /*
  34. * atl1c_pci_tbl - PCI Device ID Table
  35. *
  36. * Wildcard entries (PCI_ANY_ID) should come last
  37. * Last entry must be all 0s
  38. *
  39. * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
  40. * Class, Class Mask, private data (not used) }
  41. */
  42. static DEFINE_PCI_DEVICE_TABLE(atl1c_pci_tbl) = {
  43. {PCI_DEVICE(PCI_VENDOR_ID_ATTANSIC, PCI_DEVICE_ID_ATTANSIC_L1C)},
  44. {PCI_DEVICE(PCI_VENDOR_ID_ATTANSIC, PCI_DEVICE_ID_ATTANSIC_L2C)},
  45. {PCI_DEVICE(PCI_VENDOR_ID_ATTANSIC, PCI_DEVICE_ID_ATHEROS_L2C_B)},
  46. {PCI_DEVICE(PCI_VENDOR_ID_ATTANSIC, PCI_DEVICE_ID_ATHEROS_L2C_B2)},
  47. {PCI_DEVICE(PCI_VENDOR_ID_ATTANSIC, PCI_DEVICE_ID_ATHEROS_L1D)},
  48. {PCI_DEVICE(PCI_VENDOR_ID_ATTANSIC, PCI_DEVICE_ID_ATHEROS_L1D_2_0)},
  49. /* required last entry */
  50. { 0 }
  51. };
  52. MODULE_DEVICE_TABLE(pci, atl1c_pci_tbl);
  53. MODULE_AUTHOR("Jie Yang");
  54. MODULE_AUTHOR("Qualcomm Atheros Inc., <nic-devel@qualcomm.com>");
  55. MODULE_DESCRIPTION("Qualcom Atheros 100/1000M Ethernet Network Driver");
  56. MODULE_LICENSE("GPL");
  57. MODULE_VERSION(ATL1C_DRV_VERSION);
  58. static int atl1c_stop_mac(struct atl1c_hw *hw);
  59. static void atl1c_enable_rx_ctrl(struct atl1c_hw *hw);
  60. static void atl1c_enable_tx_ctrl(struct atl1c_hw *hw);
  61. static void atl1c_disable_l0s_l1(struct atl1c_hw *hw);
  62. static void atl1c_set_aspm(struct atl1c_hw *hw, u16 link_speed);
  63. static void atl1c_setup_mac_ctrl(struct atl1c_adapter *adapter);
  64. static void atl1c_clean_rx_irq(struct atl1c_adapter *adapter,
  65. int *work_done, int work_to_do);
  66. static int atl1c_up(struct atl1c_adapter *adapter);
  67. static void atl1c_down(struct atl1c_adapter *adapter);
  68. static const u16 atl1c_pay_load_size[] = {
  69. 128, 256, 512, 1024, 2048, 4096,
  70. };
  71. static const u32 atl1c_default_msg = NETIF_MSG_DRV | NETIF_MSG_PROBE |
  72. NETIF_MSG_LINK | NETIF_MSG_TIMER | NETIF_MSG_IFDOWN | NETIF_MSG_IFUP;
  73. static void atl1c_pcie_patch(struct atl1c_hw *hw)
  74. {
  75. u32 mst_data, data;
  76. /* pclk sel could switch to 25M */
  77. AT_READ_REG(hw, REG_MASTER_CTRL, &mst_data);
  78. mst_data &= ~MASTER_CTRL_CLK_SEL_DIS;
  79. AT_WRITE_REG(hw, REG_MASTER_CTRL, mst_data);
  80. /* WoL/PCIE related settings */
  81. if (hw->nic_type == athr_l1c || hw->nic_type == athr_l2c) {
  82. AT_READ_REG(hw, REG_PCIE_PHYMISC, &data);
  83. data |= PCIE_PHYMISC_FORCE_RCV_DET;
  84. AT_WRITE_REG(hw, REG_PCIE_PHYMISC, data);
  85. } else { /* new dev set bit5 of MASTER */
  86. if (!(mst_data & MASTER_CTRL_WAKEN_25M))
  87. AT_WRITE_REG(hw, REG_MASTER_CTRL,
  88. mst_data | MASTER_CTRL_WAKEN_25M);
  89. }
  90. /* aspm/PCIE setting only for l2cb 1.0 */
  91. if (hw->nic_type == athr_l2c_b && hw->revision_id == L2CB_V10) {
  92. AT_READ_REG(hw, REG_PCIE_PHYMISC2, &data);
  93. data = FIELD_SETX(data, PCIE_PHYMISC2_CDR_BW,
  94. L2CB1_PCIE_PHYMISC2_CDR_BW);
  95. data = FIELD_SETX(data, PCIE_PHYMISC2_L0S_TH,
  96. L2CB1_PCIE_PHYMISC2_L0S_TH);
  97. AT_WRITE_REG(hw, REG_PCIE_PHYMISC2, data);
  98. /* extend L1 sync timer */
  99. AT_READ_REG(hw, REG_LINK_CTRL, &data);
  100. data |= LINK_CTRL_EXT_SYNC;
  101. AT_WRITE_REG(hw, REG_LINK_CTRL, data);
  102. }
  103. /* l2cb 1.x & l1d 1.x */
  104. if (hw->nic_type == athr_l2c_b || hw->nic_type == athr_l1d) {
  105. AT_READ_REG(hw, REG_PM_CTRL, &data);
  106. data |= PM_CTRL_L0S_BUFSRX_EN;
  107. AT_WRITE_REG(hw, REG_PM_CTRL, data);
  108. /* clear vendor msg */
  109. AT_READ_REG(hw, REG_DMA_DBG, &data);
  110. AT_WRITE_REG(hw, REG_DMA_DBG, data & ~DMA_DBG_VENDOR_MSG);
  111. }
  112. }
  113. /* FIXME: no need any more ? */
  114. /*
  115. * atl1c_init_pcie - init PCIE module
  116. */
  117. static void atl1c_reset_pcie(struct atl1c_hw *hw, u32 flag)
  118. {
  119. u32 data;
  120. u32 pci_cmd;
  121. struct pci_dev *pdev = hw->adapter->pdev;
  122. int pos;
  123. AT_READ_REG(hw, PCI_COMMAND, &pci_cmd);
  124. pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
  125. pci_cmd |= (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
  126. PCI_COMMAND_IO);
  127. AT_WRITE_REG(hw, PCI_COMMAND, pci_cmd);
  128. /*
  129. * Clear any PowerSaveing Settings
  130. */
  131. pci_enable_wake(pdev, PCI_D3hot, 0);
  132. pci_enable_wake(pdev, PCI_D3cold, 0);
  133. /*
  134. * Mask some pcie error bits
  135. */
  136. pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR);
  137. pci_read_config_dword(pdev, pos + PCI_ERR_UNCOR_SEVER, &data);
  138. data &= ~(PCI_ERR_UNC_DLP | PCI_ERR_UNC_FCP);
  139. pci_write_config_dword(pdev, pos + PCI_ERR_UNCOR_SEVER, data);
  140. /* clear error status */
  141. pci_write_config_word(pdev, pci_pcie_cap(pdev) + PCI_EXP_DEVSTA,
  142. PCI_EXP_DEVSTA_NFED |
  143. PCI_EXP_DEVSTA_FED |
  144. PCI_EXP_DEVSTA_CED |
  145. PCI_EXP_DEVSTA_URD);
  146. AT_READ_REG(hw, REG_LTSSM_ID_CTRL, &data);
  147. data &= ~LTSSM_ID_EN_WRO;
  148. AT_WRITE_REG(hw, REG_LTSSM_ID_CTRL, data);
  149. atl1c_pcie_patch(hw);
  150. if (flag & ATL1C_PCIE_L0S_L1_DISABLE)
  151. atl1c_disable_l0s_l1(hw);
  152. msleep(5);
  153. }
  154. /*
  155. * atl1c_irq_enable - Enable default interrupt generation settings
  156. * @adapter: board private structure
  157. */
  158. static inline void atl1c_irq_enable(struct atl1c_adapter *adapter)
  159. {
  160. if (likely(atomic_dec_and_test(&adapter->irq_sem))) {
  161. AT_WRITE_REG(&adapter->hw, REG_ISR, 0x7FFFFFFF);
  162. AT_WRITE_REG(&adapter->hw, REG_IMR, adapter->hw.intr_mask);
  163. AT_WRITE_FLUSH(&adapter->hw);
  164. }
  165. }
  166. /*
  167. * atl1c_irq_disable - Mask off interrupt generation on the NIC
  168. * @adapter: board private structure
  169. */
  170. static inline void atl1c_irq_disable(struct atl1c_adapter *adapter)
  171. {
  172. atomic_inc(&adapter->irq_sem);
  173. AT_WRITE_REG(&adapter->hw, REG_IMR, 0);
  174. AT_WRITE_REG(&adapter->hw, REG_ISR, ISR_DIS_INT);
  175. AT_WRITE_FLUSH(&adapter->hw);
  176. synchronize_irq(adapter->pdev->irq);
  177. }
  178. /*
  179. * atl1c_irq_reset - reset interrupt confiure on the NIC
  180. * @adapter: board private structure
  181. */
  182. static inline void atl1c_irq_reset(struct atl1c_adapter *adapter)
  183. {
  184. atomic_set(&adapter->irq_sem, 1);
  185. atl1c_irq_enable(adapter);
  186. }
  187. /*
  188. * atl1c_wait_until_idle - wait up to AT_HW_MAX_IDLE_DELAY reads
  189. * of the idle status register until the device is actually idle
  190. */
  191. static u32 atl1c_wait_until_idle(struct atl1c_hw *hw, u32 modu_ctrl)
  192. {
  193. int timeout;
  194. u32 data;
  195. for (timeout = 0; timeout < AT_HW_MAX_IDLE_DELAY; timeout++) {
  196. AT_READ_REG(hw, REG_IDLE_STATUS, &data);
  197. if ((data & modu_ctrl) == 0)
  198. return 0;
  199. msleep(1);
  200. }
  201. return data;
  202. }
  203. /*
  204. * atl1c_phy_config - Timer Call-back
  205. * @data: pointer to netdev cast into an unsigned long
  206. */
  207. static void atl1c_phy_config(unsigned long data)
  208. {
  209. struct atl1c_adapter *adapter = (struct atl1c_adapter *) data;
  210. struct atl1c_hw *hw = &adapter->hw;
  211. unsigned long flags;
  212. spin_lock_irqsave(&adapter->mdio_lock, flags);
  213. atl1c_restart_autoneg(hw);
  214. spin_unlock_irqrestore(&adapter->mdio_lock, flags);
  215. }
  216. void atl1c_reinit_locked(struct atl1c_adapter *adapter)
  217. {
  218. WARN_ON(in_interrupt());
  219. atl1c_down(adapter);
  220. atl1c_up(adapter);
  221. clear_bit(__AT_RESETTING, &adapter->flags);
  222. }
  223. static void atl1c_check_link_status(struct atl1c_adapter *adapter)
  224. {
  225. struct atl1c_hw *hw = &adapter->hw;
  226. struct net_device *netdev = adapter->netdev;
  227. struct pci_dev *pdev = adapter->pdev;
  228. int err;
  229. unsigned long flags;
  230. u16 speed, duplex, phy_data;
  231. spin_lock_irqsave(&adapter->mdio_lock, flags);
  232. /* MII_BMSR must read twise */
  233. atl1c_read_phy_reg(hw, MII_BMSR, &phy_data);
  234. atl1c_read_phy_reg(hw, MII_BMSR, &phy_data);
  235. spin_unlock_irqrestore(&adapter->mdio_lock, flags);
  236. if ((phy_data & BMSR_LSTATUS) == 0) {
  237. /* link down */
  238. hw->hibernate = true;
  239. if (atl1c_stop_mac(hw) != 0)
  240. if (netif_msg_hw(adapter))
  241. dev_warn(&pdev->dev, "stop mac failed\n");
  242. atl1c_set_aspm(hw, SPEED_0);
  243. netif_carrier_off(netdev);
  244. netif_stop_queue(netdev);
  245. atl1c_phy_reset(hw);
  246. atl1c_phy_init(&adapter->hw);
  247. } else {
  248. /* Link Up */
  249. hw->hibernate = false;
  250. spin_lock_irqsave(&adapter->mdio_lock, flags);
  251. err = atl1c_get_speed_and_duplex(hw, &speed, &duplex);
  252. spin_unlock_irqrestore(&adapter->mdio_lock, flags);
  253. if (unlikely(err))
  254. return;
  255. /* link result is our setting */
  256. if (adapter->link_speed != speed ||
  257. adapter->link_duplex != duplex) {
  258. adapter->link_speed = speed;
  259. adapter->link_duplex = duplex;
  260. atl1c_set_aspm(hw, speed);
  261. atl1c_enable_tx_ctrl(hw);
  262. atl1c_enable_rx_ctrl(hw);
  263. atl1c_setup_mac_ctrl(adapter);
  264. if (netif_msg_link(adapter))
  265. dev_info(&pdev->dev,
  266. "%s: %s NIC Link is Up<%d Mbps %s>\n",
  267. atl1c_driver_name, netdev->name,
  268. adapter->link_speed,
  269. adapter->link_duplex == FULL_DUPLEX ?
  270. "Full Duplex" : "Half Duplex");
  271. }
  272. if (!netif_carrier_ok(netdev))
  273. netif_carrier_on(netdev);
  274. }
  275. }
  276. static void atl1c_link_chg_event(struct atl1c_adapter *adapter)
  277. {
  278. struct net_device *netdev = adapter->netdev;
  279. struct pci_dev *pdev = adapter->pdev;
  280. u16 phy_data;
  281. u16 link_up;
  282. spin_lock(&adapter->mdio_lock);
  283. atl1c_read_phy_reg(&adapter->hw, MII_BMSR, &phy_data);
  284. atl1c_read_phy_reg(&adapter->hw, MII_BMSR, &phy_data);
  285. spin_unlock(&adapter->mdio_lock);
  286. link_up = phy_data & BMSR_LSTATUS;
  287. /* notify upper layer link down ASAP */
  288. if (!link_up) {
  289. if (netif_carrier_ok(netdev)) {
  290. /* old link state: Up */
  291. netif_carrier_off(netdev);
  292. if (netif_msg_link(adapter))
  293. dev_info(&pdev->dev,
  294. "%s: %s NIC Link is Down\n",
  295. atl1c_driver_name, netdev->name);
  296. adapter->link_speed = SPEED_0;
  297. }
  298. }
  299. set_bit(ATL1C_WORK_EVENT_LINK_CHANGE, &adapter->work_event);
  300. schedule_work(&adapter->common_task);
  301. }
  302. static void atl1c_common_task(struct work_struct *work)
  303. {
  304. struct atl1c_adapter *adapter;
  305. struct net_device *netdev;
  306. adapter = container_of(work, struct atl1c_adapter, common_task);
  307. netdev = adapter->netdev;
  308. if (test_and_clear_bit(ATL1C_WORK_EVENT_RESET, &adapter->work_event)) {
  309. netif_device_detach(netdev);
  310. atl1c_down(adapter);
  311. atl1c_up(adapter);
  312. netif_device_attach(netdev);
  313. }
  314. if (test_and_clear_bit(ATL1C_WORK_EVENT_LINK_CHANGE,
  315. &adapter->work_event))
  316. atl1c_check_link_status(adapter);
  317. }
  318. static void atl1c_del_timer(struct atl1c_adapter *adapter)
  319. {
  320. del_timer_sync(&adapter->phy_config_timer);
  321. }
  322. /*
  323. * atl1c_tx_timeout - Respond to a Tx Hang
  324. * @netdev: network interface device structure
  325. */
  326. static void atl1c_tx_timeout(struct net_device *netdev)
  327. {
  328. struct atl1c_adapter *adapter = netdev_priv(netdev);
  329. /* Do the reset outside of interrupt context */
  330. set_bit(ATL1C_WORK_EVENT_RESET, &adapter->work_event);
  331. schedule_work(&adapter->common_task);
  332. }
  333. /*
  334. * atl1c_set_multi - Multicast and Promiscuous mode set
  335. * @netdev: network interface device structure
  336. *
  337. * The set_multi entry point is called whenever the multicast address
  338. * list or the network interface flags are updated. This routine is
  339. * responsible for configuring the hardware for proper multicast,
  340. * promiscuous mode, and all-multi behavior.
  341. */
  342. static void atl1c_set_multi(struct net_device *netdev)
  343. {
  344. struct atl1c_adapter *adapter = netdev_priv(netdev);
  345. struct atl1c_hw *hw = &adapter->hw;
  346. struct netdev_hw_addr *ha;
  347. u32 mac_ctrl_data;
  348. u32 hash_value;
  349. /* Check for Promiscuous and All Multicast modes */
  350. AT_READ_REG(hw, REG_MAC_CTRL, &mac_ctrl_data);
  351. if (netdev->flags & IFF_PROMISC) {
  352. mac_ctrl_data |= MAC_CTRL_PROMIS_EN;
  353. } else if (netdev->flags & IFF_ALLMULTI) {
  354. mac_ctrl_data |= MAC_CTRL_MC_ALL_EN;
  355. mac_ctrl_data &= ~MAC_CTRL_PROMIS_EN;
  356. } else {
  357. mac_ctrl_data &= ~(MAC_CTRL_PROMIS_EN | MAC_CTRL_MC_ALL_EN);
  358. }
  359. AT_WRITE_REG(hw, REG_MAC_CTRL, mac_ctrl_data);
  360. /* clear the old settings from the multicast hash table */
  361. AT_WRITE_REG(hw, REG_RX_HASH_TABLE, 0);
  362. AT_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, 1, 0);
  363. /* comoute mc addresses' hash value ,and put it into hash table */
  364. netdev_for_each_mc_addr(ha, netdev) {
  365. hash_value = atl1c_hash_mc_addr(hw, ha->addr);
  366. atl1c_hash_set(hw, hash_value);
  367. }
  368. }
  369. static void __atl1c_vlan_mode(netdev_features_t features, u32 *mac_ctrl_data)
  370. {
  371. if (features & NETIF_F_HW_VLAN_RX) {
  372. /* enable VLAN tag insert/strip */
  373. *mac_ctrl_data |= MAC_CTRL_RMV_VLAN;
  374. } else {
  375. /* disable VLAN tag insert/strip */
  376. *mac_ctrl_data &= ~MAC_CTRL_RMV_VLAN;
  377. }
  378. }
  379. static void atl1c_vlan_mode(struct net_device *netdev,
  380. netdev_features_t features)
  381. {
  382. struct atl1c_adapter *adapter = netdev_priv(netdev);
  383. struct pci_dev *pdev = adapter->pdev;
  384. u32 mac_ctrl_data = 0;
  385. if (netif_msg_pktdata(adapter))
  386. dev_dbg(&pdev->dev, "atl1c_vlan_mode\n");
  387. atl1c_irq_disable(adapter);
  388. AT_READ_REG(&adapter->hw, REG_MAC_CTRL, &mac_ctrl_data);
  389. __atl1c_vlan_mode(features, &mac_ctrl_data);
  390. AT_WRITE_REG(&adapter->hw, REG_MAC_CTRL, mac_ctrl_data);
  391. atl1c_irq_enable(adapter);
  392. }
  393. static void atl1c_restore_vlan(struct atl1c_adapter *adapter)
  394. {
  395. struct pci_dev *pdev = adapter->pdev;
  396. if (netif_msg_pktdata(adapter))
  397. dev_dbg(&pdev->dev, "atl1c_restore_vlan\n");
  398. atl1c_vlan_mode(adapter->netdev, adapter->netdev->features);
  399. }
  400. /*
  401. * atl1c_set_mac - Change the Ethernet Address of the NIC
  402. * @netdev: network interface device structure
  403. * @p: pointer to an address structure
  404. *
  405. * Returns 0 on success, negative on failure
  406. */
  407. static int atl1c_set_mac_addr(struct net_device *netdev, void *p)
  408. {
  409. struct atl1c_adapter *adapter = netdev_priv(netdev);
  410. struct sockaddr *addr = p;
  411. if (!is_valid_ether_addr(addr->sa_data))
  412. return -EADDRNOTAVAIL;
  413. if (netif_running(netdev))
  414. return -EBUSY;
  415. memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
  416. memcpy(adapter->hw.mac_addr, addr->sa_data, netdev->addr_len);
  417. netdev->addr_assign_type &= ~NET_ADDR_RANDOM;
  418. atl1c_hw_set_mac_addr(&adapter->hw);
  419. return 0;
  420. }
  421. static void atl1c_set_rxbufsize(struct atl1c_adapter *adapter,
  422. struct net_device *dev)
  423. {
  424. int mtu = dev->mtu;
  425. adapter->rx_buffer_len = mtu > AT_RX_BUF_SIZE ?
  426. roundup(mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN, 8) : AT_RX_BUF_SIZE;
  427. }
  428. static netdev_features_t atl1c_fix_features(struct net_device *netdev,
  429. netdev_features_t features)
  430. {
  431. /*
  432. * Since there is no support for separate rx/tx vlan accel
  433. * enable/disable make sure tx flag is always in same state as rx.
  434. */
  435. if (features & NETIF_F_HW_VLAN_RX)
  436. features |= NETIF_F_HW_VLAN_TX;
  437. else
  438. features &= ~NETIF_F_HW_VLAN_TX;
  439. if (netdev->mtu > MAX_TSO_FRAME_SIZE)
  440. features &= ~(NETIF_F_TSO | NETIF_F_TSO6);
  441. return features;
  442. }
  443. static int atl1c_set_features(struct net_device *netdev,
  444. netdev_features_t features)
  445. {
  446. netdev_features_t changed = netdev->features ^ features;
  447. if (changed & NETIF_F_HW_VLAN_RX)
  448. atl1c_vlan_mode(netdev, features);
  449. return 0;
  450. }
  451. /*
  452. * atl1c_change_mtu - Change the Maximum Transfer Unit
  453. * @netdev: network interface device structure
  454. * @new_mtu: new value for maximum frame size
  455. *
  456. * Returns 0 on success, negative on failure
  457. */
  458. static int atl1c_change_mtu(struct net_device *netdev, int new_mtu)
  459. {
  460. struct atl1c_adapter *adapter = netdev_priv(netdev);
  461. struct atl1c_hw *hw = &adapter->hw;
  462. int old_mtu = netdev->mtu;
  463. int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
  464. /* Fast Ethernet controller doesn't support jumbo packet */
  465. if (((hw->nic_type == athr_l2c ||
  466. hw->nic_type == athr_l2c_b ||
  467. hw->nic_type == athr_l2c_b2) && new_mtu > ETH_DATA_LEN) ||
  468. max_frame < ETH_ZLEN + ETH_FCS_LEN ||
  469. max_frame > MAX_JUMBO_FRAME_SIZE) {
  470. if (netif_msg_link(adapter))
  471. dev_warn(&adapter->pdev->dev, "invalid MTU setting\n");
  472. return -EINVAL;
  473. }
  474. /* set MTU */
  475. if (old_mtu != new_mtu && netif_running(netdev)) {
  476. while (test_and_set_bit(__AT_RESETTING, &adapter->flags))
  477. msleep(1);
  478. netdev->mtu = new_mtu;
  479. adapter->hw.max_frame_size = new_mtu;
  480. atl1c_set_rxbufsize(adapter, netdev);
  481. atl1c_down(adapter);
  482. netdev_update_features(netdev);
  483. atl1c_up(adapter);
  484. clear_bit(__AT_RESETTING, &adapter->flags);
  485. if (adapter->hw.ctrl_flags & ATL1C_FPGA_VERSION) {
  486. u32 phy_data;
  487. AT_READ_REG(&adapter->hw, 0x1414, &phy_data);
  488. phy_data |= 0x10000000;
  489. AT_WRITE_REG(&adapter->hw, 0x1414, phy_data);
  490. }
  491. }
  492. return 0;
  493. }
  494. /*
  495. * caller should hold mdio_lock
  496. */
  497. static int atl1c_mdio_read(struct net_device *netdev, int phy_id, int reg_num)
  498. {
  499. struct atl1c_adapter *adapter = netdev_priv(netdev);
  500. u16 result;
  501. atl1c_read_phy_reg(&adapter->hw, reg_num, &result);
  502. return result;
  503. }
  504. static void atl1c_mdio_write(struct net_device *netdev, int phy_id,
  505. int reg_num, int val)
  506. {
  507. struct atl1c_adapter *adapter = netdev_priv(netdev);
  508. atl1c_write_phy_reg(&adapter->hw, reg_num, val);
  509. }
  510. /*
  511. * atl1c_mii_ioctl -
  512. * @netdev:
  513. * @ifreq:
  514. * @cmd:
  515. */
  516. static int atl1c_mii_ioctl(struct net_device *netdev,
  517. struct ifreq *ifr, int cmd)
  518. {
  519. struct atl1c_adapter *adapter = netdev_priv(netdev);
  520. struct pci_dev *pdev = adapter->pdev;
  521. struct mii_ioctl_data *data = if_mii(ifr);
  522. unsigned long flags;
  523. int retval = 0;
  524. if (!netif_running(netdev))
  525. return -EINVAL;
  526. spin_lock_irqsave(&adapter->mdio_lock, flags);
  527. switch (cmd) {
  528. case SIOCGMIIPHY:
  529. data->phy_id = 0;
  530. break;
  531. case SIOCGMIIREG:
  532. if (atl1c_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
  533. &data->val_out)) {
  534. retval = -EIO;
  535. goto out;
  536. }
  537. break;
  538. case SIOCSMIIREG:
  539. if (data->reg_num & ~(0x1F)) {
  540. retval = -EFAULT;
  541. goto out;
  542. }
  543. dev_dbg(&pdev->dev, "<atl1c_mii_ioctl> write %x %x",
  544. data->reg_num, data->val_in);
  545. if (atl1c_write_phy_reg(&adapter->hw,
  546. data->reg_num, data->val_in)) {
  547. retval = -EIO;
  548. goto out;
  549. }
  550. break;
  551. default:
  552. retval = -EOPNOTSUPP;
  553. break;
  554. }
  555. out:
  556. spin_unlock_irqrestore(&adapter->mdio_lock, flags);
  557. return retval;
  558. }
  559. /*
  560. * atl1c_ioctl -
  561. * @netdev:
  562. * @ifreq:
  563. * @cmd:
  564. */
  565. static int atl1c_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
  566. {
  567. switch (cmd) {
  568. case SIOCGMIIPHY:
  569. case SIOCGMIIREG:
  570. case SIOCSMIIREG:
  571. return atl1c_mii_ioctl(netdev, ifr, cmd);
  572. default:
  573. return -EOPNOTSUPP;
  574. }
  575. }
  576. /*
  577. * atl1c_alloc_queues - Allocate memory for all rings
  578. * @adapter: board private structure to initialize
  579. *
  580. */
  581. static int __devinit atl1c_alloc_queues(struct atl1c_adapter *adapter)
  582. {
  583. return 0;
  584. }
  585. static void atl1c_set_mac_type(struct atl1c_hw *hw)
  586. {
  587. switch (hw->device_id) {
  588. case PCI_DEVICE_ID_ATTANSIC_L2C:
  589. hw->nic_type = athr_l2c;
  590. break;
  591. case PCI_DEVICE_ID_ATTANSIC_L1C:
  592. hw->nic_type = athr_l1c;
  593. break;
  594. case PCI_DEVICE_ID_ATHEROS_L2C_B:
  595. hw->nic_type = athr_l2c_b;
  596. break;
  597. case PCI_DEVICE_ID_ATHEROS_L2C_B2:
  598. hw->nic_type = athr_l2c_b2;
  599. break;
  600. case PCI_DEVICE_ID_ATHEROS_L1D:
  601. hw->nic_type = athr_l1d;
  602. break;
  603. case PCI_DEVICE_ID_ATHEROS_L1D_2_0:
  604. hw->nic_type = athr_l1d_2;
  605. break;
  606. default:
  607. break;
  608. }
  609. }
  610. static int atl1c_setup_mac_funcs(struct atl1c_hw *hw)
  611. {
  612. u32 link_ctrl_data;
  613. atl1c_set_mac_type(hw);
  614. AT_READ_REG(hw, REG_LINK_CTRL, &link_ctrl_data);
  615. hw->ctrl_flags = ATL1C_INTR_MODRT_ENABLE |
  616. ATL1C_TXQ_MODE_ENHANCE;
  617. hw->ctrl_flags |= ATL1C_ASPM_L0S_SUPPORT |
  618. ATL1C_ASPM_L1_SUPPORT;
  619. hw->ctrl_flags |= ATL1C_ASPM_CTRL_MON;
  620. if (hw->nic_type == athr_l1c ||
  621. hw->nic_type == athr_l1d ||
  622. hw->nic_type == athr_l1d_2)
  623. hw->link_cap_flags |= ATL1C_LINK_CAP_1000M;
  624. return 0;
  625. }
  626. /*
  627. * atl1c_sw_init - Initialize general software structures (struct atl1c_adapter)
  628. * @adapter: board private structure to initialize
  629. *
  630. * atl1c_sw_init initializes the Adapter private data structure.
  631. * Fields are initialized based on PCI device information and
  632. * OS network device settings (MTU size).
  633. */
  634. static int __devinit atl1c_sw_init(struct atl1c_adapter *adapter)
  635. {
  636. struct atl1c_hw *hw = &adapter->hw;
  637. struct pci_dev *pdev = adapter->pdev;
  638. u32 revision;
  639. adapter->wol = 0;
  640. device_set_wakeup_enable(&pdev->dev, false);
  641. adapter->link_speed = SPEED_0;
  642. adapter->link_duplex = FULL_DUPLEX;
  643. adapter->tpd_ring[0].count = 1024;
  644. adapter->rfd_ring.count = 512;
  645. hw->vendor_id = pdev->vendor;
  646. hw->device_id = pdev->device;
  647. hw->subsystem_vendor_id = pdev->subsystem_vendor;
  648. hw->subsystem_id = pdev->subsystem_device;
  649. AT_READ_REG(hw, PCI_CLASS_REVISION, &revision);
  650. hw->revision_id = revision & 0xFF;
  651. /* before link up, we assume hibernate is true */
  652. hw->hibernate = true;
  653. hw->media_type = MEDIA_TYPE_AUTO_SENSOR;
  654. if (atl1c_setup_mac_funcs(hw) != 0) {
  655. dev_err(&pdev->dev, "set mac function pointers failed\n");
  656. return -1;
  657. }
  658. hw->intr_mask = IMR_NORMAL_MASK;
  659. hw->phy_configured = false;
  660. hw->preamble_len = 7;
  661. hw->max_frame_size = adapter->netdev->mtu;
  662. hw->autoneg_advertised = ADVERTISED_Autoneg;
  663. hw->indirect_tab = 0xE4E4E4E4;
  664. hw->base_cpu = 0;
  665. hw->ict = 50000; /* 100ms */
  666. hw->smb_timer = 200000; /* 400ms */
  667. hw->rx_imt = 200;
  668. hw->tx_imt = 1000;
  669. hw->tpd_burst = 5;
  670. hw->rfd_burst = 8;
  671. hw->dma_order = atl1c_dma_ord_out;
  672. hw->dmar_block = atl1c_dma_req_1024;
  673. if (atl1c_alloc_queues(adapter)) {
  674. dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
  675. return -ENOMEM;
  676. }
  677. /* TODO */
  678. atl1c_set_rxbufsize(adapter, adapter->netdev);
  679. atomic_set(&adapter->irq_sem, 1);
  680. spin_lock_init(&adapter->mdio_lock);
  681. spin_lock_init(&adapter->tx_lock);
  682. set_bit(__AT_DOWN, &adapter->flags);
  683. return 0;
  684. }
  685. static inline void atl1c_clean_buffer(struct pci_dev *pdev,
  686. struct atl1c_buffer *buffer_info, int in_irq)
  687. {
  688. u16 pci_driection;
  689. if (buffer_info->flags & ATL1C_BUFFER_FREE)
  690. return;
  691. if (buffer_info->dma) {
  692. if (buffer_info->flags & ATL1C_PCIMAP_FROMDEVICE)
  693. pci_driection = PCI_DMA_FROMDEVICE;
  694. else
  695. pci_driection = PCI_DMA_TODEVICE;
  696. if (buffer_info->flags & ATL1C_PCIMAP_SINGLE)
  697. pci_unmap_single(pdev, buffer_info->dma,
  698. buffer_info->length, pci_driection);
  699. else if (buffer_info->flags & ATL1C_PCIMAP_PAGE)
  700. pci_unmap_page(pdev, buffer_info->dma,
  701. buffer_info->length, pci_driection);
  702. }
  703. if (buffer_info->skb) {
  704. if (in_irq)
  705. dev_kfree_skb_irq(buffer_info->skb);
  706. else
  707. dev_kfree_skb(buffer_info->skb);
  708. }
  709. buffer_info->dma = 0;
  710. buffer_info->skb = NULL;
  711. ATL1C_SET_BUFFER_STATE(buffer_info, ATL1C_BUFFER_FREE);
  712. }
  713. /*
  714. * atl1c_clean_tx_ring - Free Tx-skb
  715. * @adapter: board private structure
  716. */
  717. static void atl1c_clean_tx_ring(struct atl1c_adapter *adapter,
  718. enum atl1c_trans_queue type)
  719. {
  720. struct atl1c_tpd_ring *tpd_ring = &adapter->tpd_ring[type];
  721. struct atl1c_buffer *buffer_info;
  722. struct pci_dev *pdev = adapter->pdev;
  723. u16 index, ring_count;
  724. ring_count = tpd_ring->count;
  725. for (index = 0; index < ring_count; index++) {
  726. buffer_info = &tpd_ring->buffer_info[index];
  727. atl1c_clean_buffer(pdev, buffer_info, 0);
  728. }
  729. /* Zero out Tx-buffers */
  730. memset(tpd_ring->desc, 0, sizeof(struct atl1c_tpd_desc) *
  731. ring_count);
  732. atomic_set(&tpd_ring->next_to_clean, 0);
  733. tpd_ring->next_to_use = 0;
  734. }
  735. /*
  736. * atl1c_clean_rx_ring - Free rx-reservation skbs
  737. * @adapter: board private structure
  738. */
  739. static void atl1c_clean_rx_ring(struct atl1c_adapter *adapter)
  740. {
  741. struct atl1c_rfd_ring *rfd_ring = &adapter->rfd_ring;
  742. struct atl1c_rrd_ring *rrd_ring = &adapter->rrd_ring;
  743. struct atl1c_buffer *buffer_info;
  744. struct pci_dev *pdev = adapter->pdev;
  745. int j;
  746. for (j = 0; j < rfd_ring->count; j++) {
  747. buffer_info = &rfd_ring->buffer_info[j];
  748. atl1c_clean_buffer(pdev, buffer_info, 0);
  749. }
  750. /* zero out the descriptor ring */
  751. memset(rfd_ring->desc, 0, rfd_ring->size);
  752. rfd_ring->next_to_clean = 0;
  753. rfd_ring->next_to_use = 0;
  754. rrd_ring->next_to_use = 0;
  755. rrd_ring->next_to_clean = 0;
  756. }
  757. /*
  758. * Read / Write Ptr Initialize:
  759. */
  760. static void atl1c_init_ring_ptrs(struct atl1c_adapter *adapter)
  761. {
  762. struct atl1c_tpd_ring *tpd_ring = adapter->tpd_ring;
  763. struct atl1c_rfd_ring *rfd_ring = &adapter->rfd_ring;
  764. struct atl1c_rrd_ring *rrd_ring = &adapter->rrd_ring;
  765. struct atl1c_buffer *buffer_info;
  766. int i, j;
  767. for (i = 0; i < AT_MAX_TRANSMIT_QUEUE; i++) {
  768. tpd_ring[i].next_to_use = 0;
  769. atomic_set(&tpd_ring[i].next_to_clean, 0);
  770. buffer_info = tpd_ring[i].buffer_info;
  771. for (j = 0; j < tpd_ring->count; j++)
  772. ATL1C_SET_BUFFER_STATE(&buffer_info[i],
  773. ATL1C_BUFFER_FREE);
  774. }
  775. rfd_ring->next_to_use = 0;
  776. rfd_ring->next_to_clean = 0;
  777. rrd_ring->next_to_use = 0;
  778. rrd_ring->next_to_clean = 0;
  779. for (j = 0; j < rfd_ring->count; j++) {
  780. buffer_info = &rfd_ring->buffer_info[j];
  781. ATL1C_SET_BUFFER_STATE(buffer_info, ATL1C_BUFFER_FREE);
  782. }
  783. }
  784. /*
  785. * atl1c_free_ring_resources - Free Tx / RX descriptor Resources
  786. * @adapter: board private structure
  787. *
  788. * Free all transmit software resources
  789. */
  790. static void atl1c_free_ring_resources(struct atl1c_adapter *adapter)
  791. {
  792. struct pci_dev *pdev = adapter->pdev;
  793. pci_free_consistent(pdev, adapter->ring_header.size,
  794. adapter->ring_header.desc,
  795. adapter->ring_header.dma);
  796. adapter->ring_header.desc = NULL;
  797. /* Note: just free tdp_ring.buffer_info,
  798. * it contain rfd_ring.buffer_info, do not double free */
  799. if (adapter->tpd_ring[0].buffer_info) {
  800. kfree(adapter->tpd_ring[0].buffer_info);
  801. adapter->tpd_ring[0].buffer_info = NULL;
  802. }
  803. }
  804. /*
  805. * atl1c_setup_mem_resources - allocate Tx / RX descriptor resources
  806. * @adapter: board private structure
  807. *
  808. * Return 0 on success, negative on failure
  809. */
  810. static int atl1c_setup_ring_resources(struct atl1c_adapter *adapter)
  811. {
  812. struct pci_dev *pdev = adapter->pdev;
  813. struct atl1c_tpd_ring *tpd_ring = adapter->tpd_ring;
  814. struct atl1c_rfd_ring *rfd_ring = &adapter->rfd_ring;
  815. struct atl1c_rrd_ring *rrd_ring = &adapter->rrd_ring;
  816. struct atl1c_ring_header *ring_header = &adapter->ring_header;
  817. int size;
  818. int i;
  819. int count = 0;
  820. int rx_desc_count = 0;
  821. u32 offset = 0;
  822. rrd_ring->count = rfd_ring->count;
  823. for (i = 1; i < AT_MAX_TRANSMIT_QUEUE; i++)
  824. tpd_ring[i].count = tpd_ring[0].count;
  825. /* 2 tpd queue, one high priority queue,
  826. * another normal priority queue */
  827. size = sizeof(struct atl1c_buffer) * (tpd_ring->count * 2 +
  828. rfd_ring->count);
  829. tpd_ring->buffer_info = kzalloc(size, GFP_KERNEL);
  830. if (unlikely(!tpd_ring->buffer_info)) {
  831. dev_err(&pdev->dev, "kzalloc failed, size = %d\n",
  832. size);
  833. goto err_nomem;
  834. }
  835. for (i = 0; i < AT_MAX_TRANSMIT_QUEUE; i++) {
  836. tpd_ring[i].buffer_info =
  837. (struct atl1c_buffer *) (tpd_ring->buffer_info + count);
  838. count += tpd_ring[i].count;
  839. }
  840. rfd_ring->buffer_info =
  841. (struct atl1c_buffer *) (tpd_ring->buffer_info + count);
  842. count += rfd_ring->count;
  843. rx_desc_count += rfd_ring->count;
  844. /*
  845. * real ring DMA buffer
  846. * each ring/block may need up to 8 bytes for alignment, hence the
  847. * additional bytes tacked onto the end.
  848. */
  849. ring_header->size = size =
  850. sizeof(struct atl1c_tpd_desc) * tpd_ring->count * 2 +
  851. sizeof(struct atl1c_rx_free_desc) * rx_desc_count +
  852. sizeof(struct atl1c_recv_ret_status) * rx_desc_count +
  853. 8 * 4;
  854. ring_header->desc = pci_alloc_consistent(pdev, ring_header->size,
  855. &ring_header->dma);
  856. if (unlikely(!ring_header->desc)) {
  857. dev_err(&pdev->dev, "pci_alloc_consistend failed\n");
  858. goto err_nomem;
  859. }
  860. memset(ring_header->desc, 0, ring_header->size);
  861. /* init TPD ring */
  862. tpd_ring[0].dma = roundup(ring_header->dma, 8);
  863. offset = tpd_ring[0].dma - ring_header->dma;
  864. for (i = 0; i < AT_MAX_TRANSMIT_QUEUE; i++) {
  865. tpd_ring[i].dma = ring_header->dma + offset;
  866. tpd_ring[i].desc = (u8 *) ring_header->desc + offset;
  867. tpd_ring[i].size =
  868. sizeof(struct atl1c_tpd_desc) * tpd_ring[i].count;
  869. offset += roundup(tpd_ring[i].size, 8);
  870. }
  871. /* init RFD ring */
  872. rfd_ring->dma = ring_header->dma + offset;
  873. rfd_ring->desc = (u8 *) ring_header->desc + offset;
  874. rfd_ring->size = sizeof(struct atl1c_rx_free_desc) * rfd_ring->count;
  875. offset += roundup(rfd_ring->size, 8);
  876. /* init RRD ring */
  877. rrd_ring->dma = ring_header->dma + offset;
  878. rrd_ring->desc = (u8 *) ring_header->desc + offset;
  879. rrd_ring->size = sizeof(struct atl1c_recv_ret_status) *
  880. rrd_ring->count;
  881. offset += roundup(rrd_ring->size, 8);
  882. return 0;
  883. err_nomem:
  884. kfree(tpd_ring->buffer_info);
  885. return -ENOMEM;
  886. }
  887. static void atl1c_configure_des_ring(struct atl1c_adapter *adapter)
  888. {
  889. struct atl1c_hw *hw = &adapter->hw;
  890. struct atl1c_rfd_ring *rfd_ring = &adapter->rfd_ring;
  891. struct atl1c_rrd_ring *rrd_ring = &adapter->rrd_ring;
  892. struct atl1c_tpd_ring *tpd_ring = (struct atl1c_tpd_ring *)
  893. adapter->tpd_ring;
  894. /* TPD */
  895. AT_WRITE_REG(hw, REG_TX_BASE_ADDR_HI,
  896. (u32)((tpd_ring[atl1c_trans_normal].dma &
  897. AT_DMA_HI_ADDR_MASK) >> 32));
  898. /* just enable normal priority TX queue */
  899. AT_WRITE_REG(hw, REG_TPD_PRI0_ADDR_LO,
  900. (u32)(tpd_ring[atl1c_trans_normal].dma &
  901. AT_DMA_LO_ADDR_MASK));
  902. AT_WRITE_REG(hw, REG_TPD_PRI1_ADDR_LO,
  903. (u32)(tpd_ring[atl1c_trans_high].dma &
  904. AT_DMA_LO_ADDR_MASK));
  905. AT_WRITE_REG(hw, REG_TPD_RING_SIZE,
  906. (u32)(tpd_ring[0].count & TPD_RING_SIZE_MASK));
  907. /* RFD */
  908. AT_WRITE_REG(hw, REG_RX_BASE_ADDR_HI,
  909. (u32)((rfd_ring->dma & AT_DMA_HI_ADDR_MASK) >> 32));
  910. AT_WRITE_REG(hw, REG_RFD0_HEAD_ADDR_LO,
  911. (u32)(rfd_ring->dma & AT_DMA_LO_ADDR_MASK));
  912. AT_WRITE_REG(hw, REG_RFD_RING_SIZE,
  913. rfd_ring->count & RFD_RING_SIZE_MASK);
  914. AT_WRITE_REG(hw, REG_RX_BUF_SIZE,
  915. adapter->rx_buffer_len & RX_BUF_SIZE_MASK);
  916. /* RRD */
  917. AT_WRITE_REG(hw, REG_RRD0_HEAD_ADDR_LO,
  918. (u32)(rrd_ring->dma & AT_DMA_LO_ADDR_MASK));
  919. AT_WRITE_REG(hw, REG_RRD_RING_SIZE,
  920. (rrd_ring->count & RRD_RING_SIZE_MASK));
  921. if (hw->nic_type == athr_l2c_b) {
  922. AT_WRITE_REG(hw, REG_SRAM_RXF_LEN, 0x02a0L);
  923. AT_WRITE_REG(hw, REG_SRAM_TXF_LEN, 0x0100L);
  924. AT_WRITE_REG(hw, REG_SRAM_RXF_ADDR, 0x029f0000L);
  925. AT_WRITE_REG(hw, REG_SRAM_RFD0_INFO, 0x02bf02a0L);
  926. AT_WRITE_REG(hw, REG_SRAM_TXF_ADDR, 0x03bf02c0L);
  927. AT_WRITE_REG(hw, REG_SRAM_TRD_ADDR, 0x03df03c0L);
  928. AT_WRITE_REG(hw, REG_TXF_WATER_MARK, 0); /* TX watermark, to enter l1 state.*/
  929. AT_WRITE_REG(hw, REG_RXD_DMA_CTRL, 0); /* RXD threshold.*/
  930. }
  931. /* Load all of base address above */
  932. AT_WRITE_REG(hw, REG_LOAD_PTR, 1);
  933. }
  934. static void atl1c_configure_tx(struct atl1c_adapter *adapter)
  935. {
  936. struct atl1c_hw *hw = &adapter->hw;
  937. int max_pay_load;
  938. u16 tx_offload_thresh;
  939. u32 txq_ctrl_data;
  940. tx_offload_thresh = MAX_TSO_FRAME_SIZE;
  941. AT_WRITE_REG(hw, REG_TX_TSO_OFFLOAD_THRESH,
  942. (tx_offload_thresh >> 3) & TX_TSO_OFFLOAD_THRESH_MASK);
  943. max_pay_load = pcie_get_readrq(adapter->pdev) >> 8;
  944. hw->dmar_block = min_t(u32, max_pay_load, hw->dmar_block);
  945. /*
  946. * if BIOS had changed the dam-read-max-length to an invalid value,
  947. * restore it to default value
  948. */
  949. if (hw->dmar_block < DEVICE_CTRL_MAXRRS_MIN) {
  950. pcie_set_readrq(adapter->pdev, 128 << DEVICE_CTRL_MAXRRS_MIN);
  951. hw->dmar_block = DEVICE_CTRL_MAXRRS_MIN;
  952. }
  953. txq_ctrl_data =
  954. hw->nic_type == athr_l2c_b || hw->nic_type == athr_l2c_b2 ?
  955. L2CB_TXQ_CFGV : L1C_TXQ_CFGV;
  956. AT_WRITE_REG(hw, REG_TXQ_CTRL, txq_ctrl_data);
  957. }
  958. static void atl1c_configure_rx(struct atl1c_adapter *adapter)
  959. {
  960. struct atl1c_hw *hw = &adapter->hw;
  961. u32 rxq_ctrl_data;
  962. rxq_ctrl_data = (hw->rfd_burst & RXQ_RFD_BURST_NUM_MASK) <<
  963. RXQ_RFD_BURST_NUM_SHIFT;
  964. if (hw->ctrl_flags & ATL1C_RX_IPV6_CHKSUM)
  965. rxq_ctrl_data |= IPV6_CHKSUM_CTRL_EN;
  966. /* aspm for gigabit */
  967. if (hw->nic_type != athr_l1d_2 && (hw->device_id & 1) != 0)
  968. rxq_ctrl_data = FIELD_SETX(rxq_ctrl_data, ASPM_THRUPUT_LIMIT,
  969. ASPM_THRUPUT_LIMIT_100M);
  970. AT_WRITE_REG(hw, REG_RXQ_CTRL, rxq_ctrl_data);
  971. }
  972. static void atl1c_configure_dma(struct atl1c_adapter *adapter)
  973. {
  974. struct atl1c_hw *hw = &adapter->hw;
  975. u32 dma_ctrl_data;
  976. dma_ctrl_data = FIELDX(DMA_CTRL_RORDER_MODE, DMA_CTRL_RORDER_MODE_OUT) |
  977. DMA_CTRL_RREQ_PRI_DATA |
  978. FIELDX(DMA_CTRL_RREQ_BLEN, hw->dmar_block) |
  979. FIELDX(DMA_CTRL_WDLY_CNT, DMA_CTRL_WDLY_CNT_DEF) |
  980. FIELDX(DMA_CTRL_RDLY_CNT, DMA_CTRL_RDLY_CNT_DEF);
  981. AT_WRITE_REG(hw, REG_DMA_CTRL, dma_ctrl_data);
  982. }
  983. /*
  984. * Stop the mac, transmit and receive units
  985. * hw - Struct containing variables accessed by shared code
  986. * return : 0 or idle status (if error)
  987. */
  988. static int atl1c_stop_mac(struct atl1c_hw *hw)
  989. {
  990. u32 data;
  991. AT_READ_REG(hw, REG_RXQ_CTRL, &data);
  992. data &= ~RXQ_CTRL_EN;
  993. AT_WRITE_REG(hw, REG_RXQ_CTRL, data);
  994. AT_READ_REG(hw, REG_TXQ_CTRL, &data);
  995. data &= ~TXQ_CTRL_EN;
  996. AT_WRITE_REG(hw, REG_TXQ_CTRL, data);
  997. atl1c_wait_until_idle(hw, IDLE_STATUS_RXQ_BUSY | IDLE_STATUS_TXQ_BUSY);
  998. AT_READ_REG(hw, REG_MAC_CTRL, &data);
  999. data &= ~(MAC_CTRL_TX_EN | MAC_CTRL_RX_EN);
  1000. AT_WRITE_REG(hw, REG_MAC_CTRL, data);
  1001. return (int)atl1c_wait_until_idle(hw,
  1002. IDLE_STATUS_TXMAC_BUSY | IDLE_STATUS_RXMAC_BUSY);
  1003. }
  1004. static void atl1c_enable_rx_ctrl(struct atl1c_hw *hw)
  1005. {
  1006. u32 data;
  1007. AT_READ_REG(hw, REG_RXQ_CTRL, &data);
  1008. data |= RXQ_CTRL_EN;
  1009. AT_WRITE_REG(hw, REG_RXQ_CTRL, data);
  1010. }
  1011. static void atl1c_enable_tx_ctrl(struct atl1c_hw *hw)
  1012. {
  1013. u32 data;
  1014. AT_READ_REG(hw, REG_TXQ_CTRL, &data);
  1015. data |= TXQ_CTRL_EN;
  1016. AT_WRITE_REG(hw, REG_TXQ_CTRL, data);
  1017. }
  1018. /*
  1019. * Reset the transmit and receive units; mask and clear all interrupts.
  1020. * hw - Struct containing variables accessed by shared code
  1021. * return : 0 or idle status (if error)
  1022. */
  1023. static int atl1c_reset_mac(struct atl1c_hw *hw)
  1024. {
  1025. struct atl1c_adapter *adapter = (struct atl1c_adapter *)hw->adapter;
  1026. struct pci_dev *pdev = adapter->pdev;
  1027. u32 ctrl_data = 0;
  1028. AT_WRITE_REG(hw, REG_IMR, 0);
  1029. AT_WRITE_REG(hw, REG_ISR, ISR_DIS_INT);
  1030. atl1c_stop_mac(hw);
  1031. /*
  1032. * Issue Soft Reset to the MAC. This will reset the chip's
  1033. * transmit, receive, DMA. It will not effect
  1034. * the current PCI configuration. The global reset bit is self-
  1035. * clearing, and should clear within a microsecond.
  1036. */
  1037. AT_READ_REG(hw, REG_MASTER_CTRL, &ctrl_data);
  1038. ctrl_data |= MASTER_CTRL_OOB_DIS;
  1039. AT_WRITE_REG(hw, REG_MASTER_CTRL, ctrl_data | MASTER_CTRL_SOFT_RST);
  1040. AT_WRITE_FLUSH(hw);
  1041. msleep(10);
  1042. /* Wait at least 10ms for All module to be Idle */
  1043. if (atl1c_wait_until_idle(hw, IDLE_STATUS_MASK)) {
  1044. dev_err(&pdev->dev,
  1045. "MAC state machine can't be idle since"
  1046. " disabled for 10ms second\n");
  1047. return -1;
  1048. }
  1049. AT_WRITE_REG(hw, REG_MASTER_CTRL, ctrl_data);
  1050. /* driver control speed/duplex */
  1051. AT_READ_REG(hw, REG_MAC_CTRL, &ctrl_data);
  1052. AT_WRITE_REG(hw, REG_MAC_CTRL, ctrl_data | MAC_CTRL_SPEED_MODE_SW);
  1053. /* clk switch setting */
  1054. AT_READ_REG(hw, REG_SERDES, &ctrl_data);
  1055. switch (hw->nic_type) {
  1056. case athr_l2c_b:
  1057. ctrl_data &= ~(SERDES_PHY_CLK_SLOWDOWN |
  1058. SERDES_MAC_CLK_SLOWDOWN);
  1059. AT_WRITE_REG(hw, REG_SERDES, ctrl_data);
  1060. break;
  1061. case athr_l2c_b2:
  1062. case athr_l1d_2:
  1063. ctrl_data |= SERDES_PHY_CLK_SLOWDOWN | SERDES_MAC_CLK_SLOWDOWN;
  1064. AT_WRITE_REG(hw, REG_SERDES, ctrl_data);
  1065. break;
  1066. default:
  1067. break;
  1068. }
  1069. return 0;
  1070. }
  1071. static void atl1c_disable_l0s_l1(struct atl1c_hw *hw)
  1072. {
  1073. u16 ctrl_flags = hw->ctrl_flags;
  1074. hw->ctrl_flags &= ~(ATL1C_ASPM_L0S_SUPPORT | ATL1C_ASPM_L1_SUPPORT);
  1075. atl1c_set_aspm(hw, SPEED_0);
  1076. hw->ctrl_flags = ctrl_flags;
  1077. }
  1078. /*
  1079. * Set ASPM state.
  1080. * Enable/disable L0s/L1 depend on link state.
  1081. */
  1082. static void atl1c_set_aspm(struct atl1c_hw *hw, u16 link_speed)
  1083. {
  1084. u32 pm_ctrl_data;
  1085. u32 link_l1_timer;
  1086. AT_READ_REG(hw, REG_PM_CTRL, &pm_ctrl_data);
  1087. pm_ctrl_data &= ~(PM_CTRL_ASPM_L1_EN |
  1088. PM_CTRL_ASPM_L0S_EN |
  1089. PM_CTRL_MAC_ASPM_CHK);
  1090. /* L1 timer */
  1091. if (hw->nic_type == athr_l2c_b2 || hw->nic_type == athr_l1d_2) {
  1092. pm_ctrl_data &= ~PMCTRL_TXL1_AFTER_L0S;
  1093. link_l1_timer =
  1094. link_speed == SPEED_1000 || link_speed == SPEED_100 ?
  1095. L1D_PMCTRL_L1_ENTRY_TM_16US : 1;
  1096. pm_ctrl_data = FIELD_SETX(pm_ctrl_data,
  1097. L1D_PMCTRL_L1_ENTRY_TM, link_l1_timer);
  1098. } else {
  1099. link_l1_timer = hw->nic_type == athr_l2c_b ?
  1100. L2CB1_PM_CTRL_L1_ENTRY_TM : L1C_PM_CTRL_L1_ENTRY_TM;
  1101. if (link_speed != SPEED_1000 && link_speed != SPEED_100)
  1102. link_l1_timer = 1;
  1103. pm_ctrl_data = FIELD_SETX(pm_ctrl_data,
  1104. PM_CTRL_L1_ENTRY_TIMER, link_l1_timer);
  1105. }
  1106. /* L0S/L1 enable */
  1107. if (hw->ctrl_flags & ATL1C_ASPM_L0S_SUPPORT)
  1108. pm_ctrl_data |= PM_CTRL_ASPM_L0S_EN | PM_CTRL_MAC_ASPM_CHK;
  1109. if (hw->ctrl_flags & ATL1C_ASPM_L1_SUPPORT)
  1110. pm_ctrl_data |= PM_CTRL_ASPM_L1_EN | PM_CTRL_MAC_ASPM_CHK;
  1111. /* l2cb & l1d & l2cb2 & l1d2 */
  1112. if (hw->nic_type == athr_l2c_b || hw->nic_type == athr_l1d ||
  1113. hw->nic_type == athr_l2c_b2 || hw->nic_type == athr_l1d_2) {
  1114. pm_ctrl_data = FIELD_SETX(pm_ctrl_data,
  1115. PM_CTRL_PM_REQ_TIMER, PM_CTRL_PM_REQ_TO_DEF);
  1116. pm_ctrl_data |= PM_CTRL_RCVR_WT_TIMER |
  1117. PM_CTRL_SERDES_PD_EX_L1 |
  1118. PM_CTRL_CLK_SWH_L1;
  1119. pm_ctrl_data &= ~(PM_CTRL_SERDES_L1_EN |
  1120. PM_CTRL_SERDES_PLL_L1_EN |
  1121. PM_CTRL_SERDES_BUFS_RX_L1_EN |
  1122. PM_CTRL_SA_DLY_EN |
  1123. PM_CTRL_HOTRST);
  1124. /* disable l0s if link down or l2cb */
  1125. if (link_speed == SPEED_0 || hw->nic_type == athr_l2c_b)
  1126. pm_ctrl_data &= ~PM_CTRL_ASPM_L0S_EN;
  1127. } else { /* l1c */
  1128. pm_ctrl_data =
  1129. FIELD_SETX(pm_ctrl_data, PM_CTRL_L1_ENTRY_TIMER, 0);
  1130. if (link_speed != SPEED_0) {
  1131. pm_ctrl_data |= PM_CTRL_SERDES_L1_EN |
  1132. PM_CTRL_SERDES_PLL_L1_EN |
  1133. PM_CTRL_SERDES_BUFS_RX_L1_EN;
  1134. pm_ctrl_data &= ~(PM_CTRL_SERDES_PD_EX_L1 |
  1135. PM_CTRL_CLK_SWH_L1 |
  1136. PM_CTRL_ASPM_L0S_EN |
  1137. PM_CTRL_ASPM_L1_EN);
  1138. } else { /* link down */
  1139. pm_ctrl_data |= PM_CTRL_CLK_SWH_L1;
  1140. pm_ctrl_data &= ~(PM_CTRL_SERDES_L1_EN |
  1141. PM_CTRL_SERDES_PLL_L1_EN |
  1142. PM_CTRL_SERDES_BUFS_RX_L1_EN |
  1143. PM_CTRL_ASPM_L0S_EN);
  1144. }
  1145. }
  1146. AT_WRITE_REG(hw, REG_PM_CTRL, pm_ctrl_data);
  1147. return;
  1148. }
  1149. static void atl1c_setup_mac_ctrl(struct atl1c_adapter *adapter)
  1150. {
  1151. struct atl1c_hw *hw = &adapter->hw;
  1152. struct net_device *netdev = adapter->netdev;
  1153. u32 mac_ctrl_data;
  1154. mac_ctrl_data = MAC_CTRL_TX_EN | MAC_CTRL_RX_EN;
  1155. mac_ctrl_data |= (MAC_CTRL_TX_FLOW | MAC_CTRL_RX_FLOW);
  1156. if (adapter->link_duplex == FULL_DUPLEX) {
  1157. hw->mac_duplex = true;
  1158. mac_ctrl_data |= MAC_CTRL_DUPLX;
  1159. }
  1160. if (adapter->link_speed == SPEED_1000)
  1161. hw->mac_speed = atl1c_mac_speed_1000;
  1162. else
  1163. hw->mac_speed = atl1c_mac_speed_10_100;
  1164. mac_ctrl_data |= (hw->mac_speed & MAC_CTRL_SPEED_MASK) <<
  1165. MAC_CTRL_SPEED_SHIFT;
  1166. mac_ctrl_data |= (MAC_CTRL_ADD_CRC | MAC_CTRL_PAD);
  1167. mac_ctrl_data |= ((hw->preamble_len & MAC_CTRL_PRMLEN_MASK) <<
  1168. MAC_CTRL_PRMLEN_SHIFT);
  1169. __atl1c_vlan_mode(netdev->features, &mac_ctrl_data);
  1170. mac_ctrl_data |= MAC_CTRL_BC_EN;
  1171. if (netdev->flags & IFF_PROMISC)
  1172. mac_ctrl_data |= MAC_CTRL_PROMIS_EN;
  1173. if (netdev->flags & IFF_ALLMULTI)
  1174. mac_ctrl_data |= MAC_CTRL_MC_ALL_EN;
  1175. mac_ctrl_data |= MAC_CTRL_SINGLE_PAUSE_EN;
  1176. if (hw->nic_type == athr_l1d || hw->nic_type == athr_l2c_b2 ||
  1177. hw->nic_type == athr_l1d_2) {
  1178. mac_ctrl_data |= MAC_CTRL_SPEED_MODE_SW;
  1179. mac_ctrl_data |= MAC_CTRL_HASH_ALG_CRC32;
  1180. }
  1181. AT_WRITE_REG(hw, REG_MAC_CTRL, mac_ctrl_data);
  1182. }
  1183. /*
  1184. * atl1c_configure - Configure Transmit&Receive Unit after Reset
  1185. * @adapter: board private structure
  1186. *
  1187. * Configure the Tx /Rx unit of the MAC after a reset.
  1188. */
  1189. static int atl1c_configure(struct atl1c_adapter *adapter)
  1190. {
  1191. struct atl1c_hw *hw = &adapter->hw;
  1192. u32 master_ctrl_data = 0;
  1193. u32 intr_modrt_data;
  1194. u32 data;
  1195. AT_READ_REG(hw, REG_MASTER_CTRL, &master_ctrl_data);
  1196. master_ctrl_data &= ~(MASTER_CTRL_TX_ITIMER_EN |
  1197. MASTER_CTRL_RX_ITIMER_EN |
  1198. MASTER_CTRL_INT_RDCLR);
  1199. /* clear interrupt status */
  1200. AT_WRITE_REG(hw, REG_ISR, 0xFFFFFFFF);
  1201. /* Clear any WOL status */
  1202. AT_WRITE_REG(hw, REG_WOL_CTRL, 0);
  1203. /* set Interrupt Clear Timer
  1204. * HW will enable self to assert interrupt event to system after
  1205. * waiting x-time for software to notify it accept interrupt.
  1206. */
  1207. data = CLK_GATING_EN_ALL;
  1208. if (hw->ctrl_flags & ATL1C_CLK_GATING_EN) {
  1209. if (hw->nic_type == athr_l2c_b)
  1210. data &= ~CLK_GATING_RXMAC_EN;
  1211. } else
  1212. data = 0;
  1213. AT_WRITE_REG(hw, REG_CLK_GATING_CTRL, data);
  1214. AT_WRITE_REG(hw, REG_INT_RETRIG_TIMER,
  1215. hw->ict & INT_RETRIG_TIMER_MASK);
  1216. atl1c_configure_des_ring(adapter);
  1217. if (hw->ctrl_flags & ATL1C_INTR_MODRT_ENABLE) {
  1218. intr_modrt_data = (hw->tx_imt & IRQ_MODRT_TIMER_MASK) <<
  1219. IRQ_MODRT_TX_TIMER_SHIFT;
  1220. intr_modrt_data |= (hw->rx_imt & IRQ_MODRT_TIMER_MASK) <<
  1221. IRQ_MODRT_RX_TIMER_SHIFT;
  1222. AT_WRITE_REG(hw, REG_IRQ_MODRT_TIMER_INIT, intr_modrt_data);
  1223. master_ctrl_data |=
  1224. MASTER_CTRL_TX_ITIMER_EN | MASTER_CTRL_RX_ITIMER_EN;
  1225. }
  1226. if (hw->ctrl_flags & ATL1C_INTR_CLEAR_ON_READ)
  1227. master_ctrl_data |= MASTER_CTRL_INT_RDCLR;
  1228. master_ctrl_data |= MASTER_CTRL_SA_TIMER_EN;
  1229. AT_WRITE_REG(hw, REG_MASTER_CTRL, master_ctrl_data);
  1230. AT_WRITE_REG(hw, REG_SMB_STAT_TIMER,
  1231. hw->smb_timer & SMB_STAT_TIMER_MASK);
  1232. /* set MTU */
  1233. AT_WRITE_REG(hw, REG_MTU, hw->max_frame_size + ETH_HLEN +
  1234. VLAN_HLEN + ETH_FCS_LEN);
  1235. atl1c_configure_tx(adapter);
  1236. atl1c_configure_rx(adapter);
  1237. atl1c_configure_dma(adapter);
  1238. return 0;
  1239. }
  1240. static void atl1c_update_hw_stats(struct atl1c_adapter *adapter)
  1241. {
  1242. u16 hw_reg_addr = 0;
  1243. unsigned long *stats_item = NULL;
  1244. u32 data;
  1245. /* update rx status */
  1246. hw_reg_addr = REG_MAC_RX_STATUS_BIN;
  1247. stats_item = &adapter->hw_stats.rx_ok;
  1248. while (hw_reg_addr <= REG_MAC_RX_STATUS_END) {
  1249. AT_READ_REG(&adapter->hw, hw_reg_addr, &data);
  1250. *stats_item += data;
  1251. stats_item++;
  1252. hw_reg_addr += 4;
  1253. }
  1254. /* update tx status */
  1255. hw_reg_addr = REG_MAC_TX_STATUS_BIN;
  1256. stats_item = &adapter->hw_stats.tx_ok;
  1257. while (hw_reg_addr <= REG_MAC_TX_STATUS_END) {
  1258. AT_READ_REG(&adapter->hw, hw_reg_addr, &data);
  1259. *stats_item += data;
  1260. stats_item++;
  1261. hw_reg_addr += 4;
  1262. }
  1263. }
  1264. /*
  1265. * atl1c_get_stats - Get System Network Statistics
  1266. * @netdev: network interface device structure
  1267. *
  1268. * Returns the address of the device statistics structure.
  1269. * The statistics are actually updated from the timer callback.
  1270. */
  1271. static struct net_device_stats *atl1c_get_stats(struct net_device *netdev)
  1272. {
  1273. struct atl1c_adapter *adapter = netdev_priv(netdev);
  1274. struct atl1c_hw_stats *hw_stats = &adapter->hw_stats;
  1275. struct net_device_stats *net_stats = &netdev->stats;
  1276. atl1c_update_hw_stats(adapter);
  1277. net_stats->rx_packets = hw_stats->rx_ok;
  1278. net_stats->tx_packets = hw_stats->tx_ok;
  1279. net_stats->rx_bytes = hw_stats->rx_byte_cnt;
  1280. net_stats->tx_bytes = hw_stats->tx_byte_cnt;
  1281. net_stats->multicast = hw_stats->rx_mcast;
  1282. net_stats->collisions = hw_stats->tx_1_col +
  1283. hw_stats->tx_2_col * 2 +
  1284. hw_stats->tx_late_col + hw_stats->tx_abort_col;
  1285. net_stats->rx_errors = hw_stats->rx_frag + hw_stats->rx_fcs_err +
  1286. hw_stats->rx_len_err + hw_stats->rx_sz_ov +
  1287. hw_stats->rx_rrd_ov + hw_stats->rx_align_err;
  1288. net_stats->rx_fifo_errors = hw_stats->rx_rxf_ov;
  1289. net_stats->rx_length_errors = hw_stats->rx_len_err;
  1290. net_stats->rx_crc_errors = hw_stats->rx_fcs_err;
  1291. net_stats->rx_frame_errors = hw_stats->rx_align_err;
  1292. net_stats->rx_over_errors = hw_stats->rx_rrd_ov + hw_stats->rx_rxf_ov;
  1293. net_stats->rx_missed_errors = hw_stats->rx_rrd_ov + hw_stats->rx_rxf_ov;
  1294. net_stats->tx_errors = hw_stats->tx_late_col + hw_stats->tx_abort_col +
  1295. hw_stats->tx_underrun + hw_stats->tx_trunc;
  1296. net_stats->tx_fifo_errors = hw_stats->tx_underrun;
  1297. net_stats->tx_aborted_errors = hw_stats->tx_abort_col;
  1298. net_stats->tx_window_errors = hw_stats->tx_late_col;
  1299. return net_stats;
  1300. }
  1301. static inline void atl1c_clear_phy_int(struct atl1c_adapter *adapter)
  1302. {
  1303. u16 phy_data;
  1304. spin_lock(&adapter->mdio_lock);
  1305. atl1c_read_phy_reg(&adapter->hw, MII_ISR, &phy_data);
  1306. spin_unlock(&adapter->mdio_lock);
  1307. }
  1308. static bool atl1c_clean_tx_irq(struct atl1c_adapter *adapter,
  1309. enum atl1c_trans_queue type)
  1310. {
  1311. struct atl1c_tpd_ring *tpd_ring = (struct atl1c_tpd_ring *)
  1312. &adapter->tpd_ring[type];
  1313. struct atl1c_buffer *buffer_info;
  1314. struct pci_dev *pdev = adapter->pdev;
  1315. u16 next_to_clean = atomic_read(&tpd_ring->next_to_clean);
  1316. u16 hw_next_to_clean;
  1317. u16 reg;
  1318. reg = type == atl1c_trans_high ? REG_TPD_PRI1_CIDX : REG_TPD_PRI0_CIDX;
  1319. AT_READ_REGW(&adapter->hw, reg, &hw_next_to_clean);
  1320. while (next_to_clean != hw_next_to_clean) {
  1321. buffer_info = &tpd_ring->buffer_info[next_to_clean];
  1322. atl1c_clean_buffer(pdev, buffer_info, 1);
  1323. if (++next_to_clean == tpd_ring->count)
  1324. next_to_clean = 0;
  1325. atomic_set(&tpd_ring->next_to_clean, next_to_clean);
  1326. }
  1327. if (netif_queue_stopped(adapter->netdev) &&
  1328. netif_carrier_ok(adapter->netdev)) {
  1329. netif_wake_queue(adapter->netdev);
  1330. }
  1331. return true;
  1332. }
  1333. /*
  1334. * atl1c_intr - Interrupt Handler
  1335. * @irq: interrupt number
  1336. * @data: pointer to a network interface device structure
  1337. * @pt_regs: CPU registers structure
  1338. */
  1339. static irqreturn_t atl1c_intr(int irq, void *data)
  1340. {
  1341. struct net_device *netdev = data;
  1342. struct atl1c_adapter *adapter = netdev_priv(netdev);
  1343. struct pci_dev *pdev = adapter->pdev;
  1344. struct atl1c_hw *hw = &adapter->hw;
  1345. int max_ints = AT_MAX_INT_WORK;
  1346. int handled = IRQ_NONE;
  1347. u32 status;
  1348. u32 reg_data;
  1349. do {
  1350. AT_READ_REG(hw, REG_ISR, &reg_data);
  1351. status = reg_data & hw->intr_mask;
  1352. if (status == 0 || (status & ISR_DIS_INT) != 0) {
  1353. if (max_ints != AT_MAX_INT_WORK)
  1354. handled = IRQ_HANDLED;
  1355. break;
  1356. }
  1357. /* link event */
  1358. if (status & ISR_GPHY)
  1359. atl1c_clear_phy_int(adapter);
  1360. /* Ack ISR */
  1361. AT_WRITE_REG(hw, REG_ISR, status | ISR_DIS_INT);
  1362. if (status & ISR_RX_PKT) {
  1363. if (likely(napi_schedule_prep(&adapter->napi))) {
  1364. hw->intr_mask &= ~ISR_RX_PKT;
  1365. AT_WRITE_REG(hw, REG_IMR, hw->intr_mask);
  1366. __napi_schedule(&adapter->napi);
  1367. }
  1368. }
  1369. if (status & ISR_TX_PKT)
  1370. atl1c_clean_tx_irq(adapter, atl1c_trans_normal);
  1371. handled = IRQ_HANDLED;
  1372. /* check if PCIE PHY Link down */
  1373. if (status & ISR_ERROR) {
  1374. if (netif_msg_hw(adapter))
  1375. dev_err(&pdev->dev,
  1376. "atl1c hardware error (status = 0x%x)\n",
  1377. status & ISR_ERROR);
  1378. /* reset MAC */
  1379. set_bit(ATL1C_WORK_EVENT_RESET, &adapter->work_event);
  1380. schedule_work(&adapter->common_task);
  1381. return IRQ_HANDLED;
  1382. }
  1383. if (status & ISR_OVER)
  1384. if (netif_msg_intr(adapter))
  1385. dev_warn(&pdev->dev,
  1386. "TX/RX overflow (status = 0x%x)\n",
  1387. status & ISR_OVER);
  1388. /* link event */
  1389. if (status & (ISR_GPHY | ISR_MANUAL)) {
  1390. netdev->stats.tx_carrier_errors++;
  1391. atl1c_link_chg_event(adapter);
  1392. break;
  1393. }
  1394. } while (--max_ints > 0);
  1395. /* re-enable Interrupt*/
  1396. AT_WRITE_REG(&adapter->hw, REG_ISR, 0);
  1397. return handled;
  1398. }
  1399. static inline void atl1c_rx_checksum(struct atl1c_adapter *adapter,
  1400. struct sk_buff *skb, struct atl1c_recv_ret_status *prrs)
  1401. {
  1402. /*
  1403. * The pid field in RRS in not correct sometimes, so we
  1404. * cannot figure out if the packet is fragmented or not,
  1405. * so we tell the KERNEL CHECKSUM_NONE
  1406. */
  1407. skb_checksum_none_assert(skb);
  1408. }
  1409. static int atl1c_alloc_rx_buffer(struct atl1c_adapter *adapter)
  1410. {
  1411. struct atl1c_rfd_ring *rfd_ring = &adapter->rfd_ring;
  1412. struct pci_dev *pdev = adapter->pdev;
  1413. struct atl1c_buffer *buffer_info, *next_info;
  1414. struct sk_buff *skb;
  1415. void *vir_addr = NULL;
  1416. u16 num_alloc = 0;
  1417. u16 rfd_next_to_use, next_next;
  1418. struct atl1c_rx_free_desc *rfd_desc;
  1419. next_next = rfd_next_to_use = rfd_ring->next_to_use;
  1420. if (++next_next == rfd_ring->count)
  1421. next_next = 0;
  1422. buffer_info = &rfd_ring->buffer_info[rfd_next_to_use];
  1423. next_info = &rfd_ring->buffer_info[next_next];
  1424. while (next_info->flags & ATL1C_BUFFER_FREE) {
  1425. rfd_desc = ATL1C_RFD_DESC(rfd_ring, rfd_next_to_use);
  1426. skb = netdev_alloc_skb(adapter->netdev, adapter->rx_buffer_len);
  1427. if (unlikely(!skb)) {
  1428. if (netif_msg_rx_err(adapter))
  1429. dev_warn(&pdev->dev, "alloc rx buffer failed\n");
  1430. break;
  1431. }
  1432. /*
  1433. * Make buffer alignment 2 beyond a 16 byte boundary
  1434. * this will result in a 16 byte aligned IP header after
  1435. * the 14 byte MAC header is removed
  1436. */
  1437. vir_addr = skb->data;
  1438. ATL1C_SET_BUFFER_STATE(buffer_info, ATL1C_BUFFER_BUSY);
  1439. buffer_info->skb = skb;
  1440. buffer_info->length = adapter->rx_buffer_len;
  1441. buffer_info->dma = pci_map_single(pdev, vir_addr,
  1442. buffer_info->length,
  1443. PCI_DMA_FROMDEVICE);
  1444. ATL1C_SET_PCIMAP_TYPE(buffer_info, ATL1C_PCIMAP_SINGLE,
  1445. ATL1C_PCIMAP_FROMDEVICE);
  1446. rfd_desc->buffer_addr = cpu_to_le64(buffer_info->dma);
  1447. rfd_next_to_use = next_next;
  1448. if (++next_next == rfd_ring->count)
  1449. next_next = 0;
  1450. buffer_info = &rfd_ring->buffer_info[rfd_next_to_use];
  1451. next_info = &rfd_ring->buffer_info[next_next];
  1452. num_alloc++;
  1453. }
  1454. if (num_alloc) {
  1455. /* TODO: update mailbox here */
  1456. wmb();
  1457. rfd_ring->next_to_use = rfd_next_to_use;
  1458. AT_WRITE_REG(&adapter->hw, REG_MB_RFD0_PROD_IDX,
  1459. rfd_ring->next_to_use & MB_RFDX_PROD_IDX_MASK);
  1460. }
  1461. return num_alloc;
  1462. }
  1463. static void atl1c_clean_rrd(struct atl1c_rrd_ring *rrd_ring,
  1464. struct atl1c_recv_ret_status *rrs, u16 num)
  1465. {
  1466. u16 i;
  1467. /* the relationship between rrd and rfd is one map one */
  1468. for (i = 0; i < num; i++, rrs = ATL1C_RRD_DESC(rrd_ring,
  1469. rrd_ring->next_to_clean)) {
  1470. rrs->word3 &= ~RRS_RXD_UPDATED;
  1471. if (++rrd_ring->next_to_clean == rrd_ring->count)
  1472. rrd_ring->next_to_clean = 0;
  1473. }
  1474. }
  1475. static void atl1c_clean_rfd(struct atl1c_rfd_ring *rfd_ring,
  1476. struct atl1c_recv_ret_status *rrs, u16 num)
  1477. {
  1478. u16 i;
  1479. u16 rfd_index;
  1480. struct atl1c_buffer *buffer_info = rfd_ring->buffer_info;
  1481. rfd_index = (rrs->word0 >> RRS_RX_RFD_INDEX_SHIFT) &
  1482. RRS_RX_RFD_INDEX_MASK;
  1483. for (i = 0; i < num; i++) {
  1484. buffer_info[rfd_index].skb = NULL;
  1485. ATL1C_SET_BUFFER_STATE(&buffer_info[rfd_index],
  1486. ATL1C_BUFFER_FREE);
  1487. if (++rfd_index == rfd_ring->count)
  1488. rfd_index = 0;
  1489. }
  1490. rfd_ring->next_to_clean = rfd_index;
  1491. }
  1492. static void atl1c_clean_rx_irq(struct atl1c_adapter *adapter,
  1493. int *work_done, int work_to_do)
  1494. {
  1495. u16 rfd_num, rfd_index;
  1496. u16 count = 0;
  1497. u16 length;
  1498. struct pci_dev *pdev = adapter->pdev;
  1499. struct net_device *netdev = adapter->netdev;
  1500. struct atl1c_rfd_ring *rfd_ring = &adapter->rfd_ring;
  1501. struct atl1c_rrd_ring *rrd_ring = &adapter->rrd_ring;
  1502. struct sk_buff *skb;
  1503. struct atl1c_recv_ret_status *rrs;
  1504. struct atl1c_buffer *buffer_info;
  1505. while (1) {
  1506. if (*work_done >= work_to_do)
  1507. break;
  1508. rrs = ATL1C_RRD_DESC(rrd_ring, rrd_ring->next_to_clean);
  1509. if (likely(RRS_RXD_IS_VALID(rrs->word3))) {
  1510. rfd_num = (rrs->word0 >> RRS_RX_RFD_CNT_SHIFT) &
  1511. RRS_RX_RFD_CNT_MASK;
  1512. if (unlikely(rfd_num != 1))
  1513. /* TODO support mul rfd*/
  1514. if (netif_msg_rx_err(adapter))
  1515. dev_warn(&pdev->dev,
  1516. "Multi rfd not support yet!\n");
  1517. goto rrs_checked;
  1518. } else {
  1519. break;
  1520. }
  1521. rrs_checked:
  1522. atl1c_clean_rrd(rrd_ring, rrs, rfd_num);
  1523. if (rrs->word3 & (RRS_RX_ERR_SUM | RRS_802_3_LEN_ERR)) {
  1524. atl1c_clean_rfd(rfd_ring, rrs, rfd_num);
  1525. if (netif_msg_rx_err(adapter))
  1526. dev_warn(&pdev->dev,
  1527. "wrong packet! rrs word3 is %x\n",
  1528. rrs->word3);
  1529. continue;
  1530. }
  1531. length = le16_to_cpu((rrs->word3 >> RRS_PKT_SIZE_SHIFT) &
  1532. RRS_PKT_SIZE_MASK);
  1533. /* Good Receive */
  1534. if (likely(rfd_num == 1)) {
  1535. rfd_index = (rrs->word0 >> RRS_RX_RFD_INDEX_SHIFT) &
  1536. RRS_RX_RFD_INDEX_MASK;
  1537. buffer_info = &rfd_ring->buffer_info[rfd_index];
  1538. pci_unmap_single(pdev, buffer_info->dma,
  1539. buffer_info->length, PCI_DMA_FROMDEVICE);
  1540. skb = buffer_info->skb;
  1541. } else {
  1542. /* TODO */
  1543. if (netif_msg_rx_err(adapter))
  1544. dev_warn(&pdev->dev,
  1545. "Multi rfd not support yet!\n");
  1546. break;
  1547. }
  1548. atl1c_clean_rfd(rfd_ring, rrs, rfd_num);
  1549. skb_put(skb, length - ETH_FCS_LEN);
  1550. skb->protocol = eth_type_trans(skb, netdev);
  1551. atl1c_rx_checksum(adapter, skb, rrs);
  1552. if (rrs->word3 & RRS_VLAN_INS) {
  1553. u16 vlan;
  1554. AT_TAG_TO_VLAN(rrs->vlan_tag, vlan);
  1555. vlan = le16_to_cpu(vlan);
  1556. __vlan_hwaccel_put_tag(skb, vlan);
  1557. }
  1558. netif_receive_skb(skb);
  1559. (*work_done)++;
  1560. count++;
  1561. }
  1562. if (count)
  1563. atl1c_alloc_rx_buffer(adapter);
  1564. }
  1565. /*
  1566. * atl1c_clean - NAPI Rx polling callback
  1567. * @adapter: board private structure
  1568. */
  1569. static int atl1c_clean(struct napi_struct *napi, int budget)
  1570. {
  1571. struct atl1c_adapter *adapter =
  1572. container_of(napi, struct atl1c_adapter, napi);
  1573. int work_done = 0;
  1574. /* Keep link state information with original netdev */
  1575. if (!netif_carrier_ok(adapter->netdev))
  1576. goto quit_polling;
  1577. /* just enable one RXQ */
  1578. atl1c_clean_rx_irq(adapter, &work_done, budget);
  1579. if (work_done < budget) {
  1580. quit_polling:
  1581. napi_complete(napi);
  1582. adapter->hw.intr_mask |= ISR_RX_PKT;
  1583. AT_WRITE_REG(&adapter->hw, REG_IMR, adapter->hw.intr_mask);
  1584. }
  1585. return work_done;
  1586. }
  1587. #ifdef CONFIG_NET_POLL_CONTROLLER
  1588. /*
  1589. * Polling 'interrupt' - used by things like netconsole to send skbs
  1590. * without having to re-enable interrupts. It's not called while
  1591. * the interrupt routine is executing.
  1592. */
  1593. static void atl1c_netpoll(struct net_device *netdev)
  1594. {
  1595. struct atl1c_adapter *adapter = netdev_priv(netdev);
  1596. disable_irq(adapter->pdev->irq);
  1597. atl1c_intr(adapter->pdev->irq, netdev);
  1598. enable_irq(adapter->pdev->irq);
  1599. }
  1600. #endif
  1601. static inline u16 atl1c_tpd_avail(struct atl1c_adapter *adapter, enum atl1c_trans_queue type)
  1602. {
  1603. struct atl1c_tpd_ring *tpd_ring = &adapter->tpd_ring[type];
  1604. u16 next_to_use = 0;
  1605. u16 next_to_clean = 0;
  1606. next_to_clean = atomic_read(&tpd_ring->next_to_clean);
  1607. next_to_use = tpd_ring->next_to_use;
  1608. return (u16)(next_to_clean > next_to_use) ?
  1609. (next_to_clean - next_to_use - 1) :
  1610. (tpd_ring->count + next_to_clean - next_to_use - 1);
  1611. }
  1612. /*
  1613. * get next usable tpd
  1614. * Note: should call atl1c_tdp_avail to make sure
  1615. * there is enough tpd to use
  1616. */
  1617. static struct atl1c_tpd_desc *atl1c_get_tpd(struct atl1c_adapter *adapter,
  1618. enum atl1c_trans_queue type)
  1619. {
  1620. struct atl1c_tpd_ring *tpd_ring = &adapter->tpd_ring[type];
  1621. struct atl1c_tpd_desc *tpd_desc;
  1622. u16 next_to_use = 0;
  1623. next_to_use = tpd_ring->next_to_use;
  1624. if (++tpd_ring->next_to_use == tpd_ring->count)
  1625. tpd_ring->next_to_use = 0;
  1626. tpd_desc = ATL1C_TPD_DESC(tpd_ring, next_to_use);
  1627. memset(tpd_desc, 0, sizeof(struct atl1c_tpd_desc));
  1628. return tpd_desc;
  1629. }
  1630. static struct atl1c_buffer *
  1631. atl1c_get_tx_buffer(struct atl1c_adapter *adapter, struct atl1c_tpd_desc *tpd)
  1632. {
  1633. struct atl1c_tpd_ring *tpd_ring = adapter->tpd_ring;
  1634. return &tpd_ring->buffer_info[tpd -
  1635. (struct atl1c_tpd_desc *)tpd_ring->desc];
  1636. }
  1637. /* Calculate the transmit packet descript needed*/
  1638. static u16 atl1c_cal_tpd_req(const struct sk_buff *skb)
  1639. {
  1640. u16 tpd_req;
  1641. u16 proto_hdr_len = 0;
  1642. tpd_req = skb_shinfo(skb)->nr_frags + 1;
  1643. if (skb_is_gso(skb)) {
  1644. proto_hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
  1645. if (proto_hdr_len < skb_headlen(skb))
  1646. tpd_req++;
  1647. if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
  1648. tpd_req++;
  1649. }
  1650. return tpd_req;
  1651. }
  1652. static int atl1c_tso_csum(struct atl1c_adapter *adapter,
  1653. struct sk_buff *skb,
  1654. struct atl1c_tpd_desc **tpd,
  1655. enum atl1c_trans_queue type)
  1656. {
  1657. struct pci_dev *pdev = adapter->pdev;
  1658. u8 hdr_len;
  1659. u32 real_len;
  1660. unsigned short offload_type;
  1661. int err;
  1662. if (skb_is_gso(skb)) {
  1663. if (skb_header_cloned(skb)) {
  1664. err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
  1665. if (unlikely(err))
  1666. return -1;
  1667. }
  1668. offload_type = skb_shinfo(skb)->gso_type;
  1669. if (offload_type & SKB_GSO_TCPV4) {
  1670. real_len = (((unsigned char *)ip_hdr(skb) - skb->data)
  1671. + ntohs(ip_hdr(skb)->tot_len));
  1672. if (real_len < skb->len)
  1673. pskb_trim(skb, real_len);
  1674. hdr_len = (skb_transport_offset(skb) + tcp_hdrlen(skb));
  1675. if (unlikely(skb->len == hdr_len)) {
  1676. /* only xsum need */
  1677. if (netif_msg_tx_queued(adapter))
  1678. dev_warn(&pdev->dev,
  1679. "IPV4 tso with zero data??\n");
  1680. goto check_sum;
  1681. } else {
  1682. ip_hdr(skb)->check = 0;
  1683. tcp_hdr(skb)->check = ~csum_tcpudp_magic(
  1684. ip_hdr(skb)->saddr,
  1685. ip_hdr(skb)->daddr,
  1686. 0, IPPROTO_TCP, 0);
  1687. (*tpd)->word1 |= 1 << TPD_IPV4_PACKET_SHIFT;
  1688. }
  1689. }
  1690. if (offload_type & SKB_GSO_TCPV6) {
  1691. struct atl1c_tpd_ext_desc *etpd =
  1692. *(struct atl1c_tpd_ext_desc **)(tpd);
  1693. memset(etpd, 0, sizeof(struct atl1c_tpd_ext_desc));
  1694. *tpd = atl1c_get_tpd(adapter, type);
  1695. ipv6_hdr(skb)->payload_len = 0;
  1696. /* check payload == 0 byte ? */
  1697. hdr_len = (skb_transport_offset(skb) + tcp_hdrlen(skb));
  1698. if (unlikely(skb->len == hdr_len)) {
  1699. /* only xsum need */
  1700. if (netif_msg_tx_queued(adapter))
  1701. dev_warn(&pdev->dev,
  1702. "IPV6 tso with zero data??\n");
  1703. goto check_sum;
  1704. } else
  1705. tcp_hdr(skb)->check = ~csum_ipv6_magic(
  1706. &ipv6_hdr(skb)->saddr,
  1707. &ipv6_hdr(skb)->daddr,
  1708. 0, IPPROTO_TCP, 0);
  1709. etpd->word1 |= 1 << TPD_LSO_EN_SHIFT;
  1710. etpd->word1 |= 1 << TPD_LSO_VER_SHIFT;
  1711. etpd->pkt_len = cpu_to_le32(skb->len);
  1712. (*tpd)->word1 |= 1 << TPD_LSO_VER_SHIFT;
  1713. }
  1714. (*tpd)->word1 |= 1 << TPD_LSO_EN_SHIFT;
  1715. (*tpd)->word1 |= (skb_transport_offset(skb) & TPD_TCPHDR_OFFSET_MASK) <<
  1716. TPD_TCPHDR_OFFSET_SHIFT;
  1717. (*tpd)->word1 |= (skb_shinfo(skb)->gso_size & TPD_MSS_MASK) <<
  1718. TPD_MSS_SHIFT;
  1719. return 0;
  1720. }
  1721. check_sum:
  1722. if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) {
  1723. u8 css, cso;
  1724. cso = skb_checksum_start_offset(skb);
  1725. if (unlikely(cso & 0x1)) {
  1726. if (netif_msg_tx_err(adapter))
  1727. dev_err(&adapter->pdev->dev,
  1728. "payload offset should not an event number\n");
  1729. return -1;
  1730. } else {
  1731. css = cso + skb->csum_offset;
  1732. (*tpd)->word1 |= ((cso >> 1) & TPD_PLOADOFFSET_MASK) <<
  1733. TPD_PLOADOFFSET_SHIFT;
  1734. (*tpd)->word1 |= ((css >> 1) & TPD_CCSUM_OFFSET_MASK) <<
  1735. TPD_CCSUM_OFFSET_SHIFT;
  1736. (*tpd)->word1 |= 1 << TPD_CCSUM_EN_SHIFT;
  1737. }
  1738. }
  1739. return 0;
  1740. }
  1741. static void atl1c_tx_map(struct atl1c_adapter *adapter,
  1742. struct sk_buff *skb, struct atl1c_tpd_desc *tpd,
  1743. enum atl1c_trans_queue type)
  1744. {
  1745. struct atl1c_tpd_desc *use_tpd = NULL;
  1746. struct atl1c_buffer *buffer_info = NULL;
  1747. u16 buf_len = skb_headlen(skb);
  1748. u16 map_len = 0;
  1749. u16 mapped_len = 0;
  1750. u16 hdr_len = 0;
  1751. u16 nr_frags;
  1752. u16 f;
  1753. int tso;
  1754. nr_frags = skb_shinfo(skb)->nr_frags;
  1755. tso = (tpd->word1 >> TPD_LSO_EN_SHIFT) & TPD_LSO_EN_MASK;
  1756. if (tso) {
  1757. /* TSO */
  1758. map_len = hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
  1759. use_tpd = tpd;
  1760. buffer_info = atl1c_get_tx_buffer(adapter, use_tpd);
  1761. buffer_info->length = map_len;
  1762. buffer_info->dma = pci_map_single(adapter->pdev,
  1763. skb->data, hdr_len, PCI_DMA_TODEVICE);
  1764. ATL1C_SET_BUFFER_STATE(buffer_info, ATL1C_BUFFER_BUSY);
  1765. ATL1C_SET_PCIMAP_TYPE(buffer_info, ATL1C_PCIMAP_SINGLE,
  1766. ATL1C_PCIMAP_TODEVICE);
  1767. mapped_len += map_len;
  1768. use_tpd->buffer_addr = cpu_to_le64(buffer_info->dma);
  1769. use_tpd->buffer_len = cpu_to_le16(buffer_info->length);
  1770. }
  1771. if (mapped_len < buf_len) {
  1772. /* mapped_len == 0, means we should use the first tpd,
  1773. which is given by caller */
  1774. if (mapped_len == 0)
  1775. use_tpd = tpd;
  1776. else {
  1777. use_tpd = atl1c_get_tpd(adapter, type);
  1778. memcpy(use_tpd, tpd, sizeof(struct atl1c_tpd_desc));
  1779. }
  1780. buffer_info = atl1c_get_tx_buffer(adapter, use_tpd);
  1781. buffer_info->length = buf_len - mapped_len;
  1782. buffer_info->dma =
  1783. pci_map_single(adapter->pdev, skb->data + mapped_len,
  1784. buffer_info->length, PCI_DMA_TODEVICE);
  1785. ATL1C_SET_BUFFER_STATE(buffer_info, ATL1C_BUFFER_BUSY);
  1786. ATL1C_SET_PCIMAP_TYPE(buffer_info, ATL1C_PCIMAP_SINGLE,
  1787. ATL1C_PCIMAP_TODEVICE);
  1788. use_tpd->buffer_addr = cpu_to_le64(buffer_info->dma);
  1789. use_tpd->buffer_len = cpu_to_le16(buffer_info->length);
  1790. }
  1791. for (f = 0; f < nr_frags; f++) {
  1792. struct skb_frag_struct *frag;
  1793. frag = &skb_shinfo(skb)->frags[f];
  1794. use_tpd = atl1c_get_tpd(adapter, type);
  1795. memcpy(use_tpd, tpd, sizeof(struct atl1c_tpd_desc));
  1796. buffer_info = atl1c_get_tx_buffer(adapter, use_tpd);
  1797. buffer_info->length = skb_frag_size(frag);
  1798. buffer_info->dma = skb_frag_dma_map(&adapter->pdev->dev,
  1799. frag, 0,
  1800. buffer_info->length,
  1801. DMA_TO_DEVICE);
  1802. ATL1C_SET_BUFFER_STATE(buffer_info, ATL1C_BUFFER_BUSY);
  1803. ATL1C_SET_PCIMAP_TYPE(buffer_info, ATL1C_PCIMAP_PAGE,
  1804. ATL1C_PCIMAP_TODEVICE);
  1805. use_tpd->buffer_addr = cpu_to_le64(buffer_info->dma);
  1806. use_tpd->buffer_len = cpu_to_le16(buffer_info->length);
  1807. }
  1808. /* The last tpd */
  1809. use_tpd->word1 |= 1 << TPD_EOP_SHIFT;
  1810. /* The last buffer info contain the skb address,
  1811. so it will be free after unmap */
  1812. buffer_info->skb = skb;
  1813. }
  1814. static void atl1c_tx_queue(struct atl1c_adapter *adapter, struct sk_buff *skb,
  1815. struct atl1c_tpd_desc *tpd, enum atl1c_trans_queue type)
  1816. {
  1817. struct atl1c_tpd_ring *tpd_ring = &adapter->tpd_ring[type];
  1818. u16 reg;
  1819. reg = type == atl1c_trans_high ? REG_TPD_PRI1_PIDX : REG_TPD_PRI0_PIDX;
  1820. AT_WRITE_REGW(&adapter->hw, reg, tpd_ring->next_to_use);
  1821. }
  1822. static netdev_tx_t atl1c_xmit_frame(struct sk_buff *skb,
  1823. struct net_device *netdev)
  1824. {
  1825. struct atl1c_adapter *adapter = netdev_priv(netdev);
  1826. unsigned long flags;
  1827. u16 tpd_req = 1;
  1828. struct atl1c_tpd_desc *tpd;
  1829. enum atl1c_trans_queue type = atl1c_trans_normal;
  1830. if (test_bit(__AT_DOWN, &adapter->flags)) {
  1831. dev_kfree_skb_any(skb);
  1832. return NETDEV_TX_OK;
  1833. }
  1834. tpd_req = atl1c_cal_tpd_req(skb);
  1835. if (!spin_trylock_irqsave(&adapter->tx_lock, flags)) {
  1836. if (netif_msg_pktdata(adapter))
  1837. dev_info(&adapter->pdev->dev, "tx locked\n");
  1838. return NETDEV_TX_LOCKED;
  1839. }
  1840. if (atl1c_tpd_avail(adapter, type) < tpd_req) {
  1841. /* no enough descriptor, just stop queue */
  1842. netif_stop_queue(netdev);
  1843. spin_unlock_irqrestore(&adapter->tx_lock, flags);
  1844. return NETDEV_TX_BUSY;
  1845. }
  1846. tpd = atl1c_get_tpd(adapter, type);
  1847. /* do TSO and check sum */
  1848. if (atl1c_tso_csum(adapter, skb, &tpd, type) != 0) {
  1849. spin_unlock_irqrestore(&adapter->tx_lock, flags);
  1850. dev_kfree_skb_any(skb);
  1851. return NETDEV_TX_OK;
  1852. }
  1853. if (unlikely(vlan_tx_tag_present(skb))) {
  1854. u16 vlan = vlan_tx_tag_get(skb);
  1855. __le16 tag;
  1856. vlan = cpu_to_le16(vlan);
  1857. AT_VLAN_TO_TAG(vlan, tag);
  1858. tpd->word1 |= 1 << TPD_INS_VTAG_SHIFT;
  1859. tpd->vlan_tag = tag;
  1860. }
  1861. if (skb_network_offset(skb) != ETH_HLEN)
  1862. tpd->word1 |= 1 << TPD_ETH_TYPE_SHIFT; /* Ethernet frame */
  1863. atl1c_tx_map(adapter, skb, tpd, type);
  1864. atl1c_tx_queue(adapter, skb, tpd, type);
  1865. spin_unlock_irqrestore(&adapter->tx_lock, flags);
  1866. return NETDEV_TX_OK;
  1867. }
  1868. static void atl1c_free_irq(struct atl1c_adapter *adapter)
  1869. {
  1870. struct net_device *netdev = adapter->netdev;
  1871. free_irq(adapter->pdev->irq, netdev);
  1872. if (adapter->have_msi)
  1873. pci_disable_msi(adapter->pdev);
  1874. }
  1875. static int atl1c_request_irq(struct atl1c_adapter *adapter)
  1876. {
  1877. struct pci_dev *pdev = adapter->pdev;
  1878. struct net_device *netdev = adapter->netdev;
  1879. int flags = 0;
  1880. int err = 0;
  1881. adapter->have_msi = true;
  1882. err = pci_enable_msi(adapter->pdev);
  1883. if (err) {
  1884. if (netif_msg_ifup(adapter))
  1885. dev_err(&pdev->dev,
  1886. "Unable to allocate MSI interrupt Error: %d\n",
  1887. err);
  1888. adapter->have_msi = false;
  1889. }
  1890. if (!adapter->have_msi)
  1891. flags |= IRQF_SHARED;
  1892. err = request_irq(adapter->pdev->irq, atl1c_intr, flags,
  1893. netdev->name, netdev);
  1894. if (err) {
  1895. if (netif_msg_ifup(adapter))
  1896. dev_err(&pdev->dev,
  1897. "Unable to allocate interrupt Error: %d\n",
  1898. err);
  1899. if (adapter->have_msi)
  1900. pci_disable_msi(adapter->pdev);
  1901. return err;
  1902. }
  1903. if (netif_msg_ifup(adapter))
  1904. dev_dbg(&pdev->dev, "atl1c_request_irq OK\n");
  1905. return err;
  1906. }
  1907. static int atl1c_up(struct atl1c_adapter *adapter)
  1908. {
  1909. struct net_device *netdev = adapter->netdev;
  1910. int num;
  1911. int err;
  1912. netif_carrier_off(netdev);
  1913. atl1c_init_ring_ptrs(adapter);
  1914. atl1c_set_multi(netdev);
  1915. atl1c_restore_vlan(adapter);
  1916. num = atl1c_alloc_rx_buffer(adapter);
  1917. if (unlikely(num == 0)) {
  1918. err = -ENOMEM;
  1919. goto err_alloc_rx;
  1920. }
  1921. if (atl1c_configure(adapter)) {
  1922. err = -EIO;
  1923. goto err_up;
  1924. }
  1925. err = atl1c_request_irq(adapter);
  1926. if (unlikely(err))
  1927. goto err_up;
  1928. clear_bit(__AT_DOWN, &adapter->flags);
  1929. napi_enable(&adapter->napi);
  1930. atl1c_irq_enable(adapter);
  1931. atl1c_check_link_status(adapter);
  1932. netif_start_queue(netdev);
  1933. return err;
  1934. err_up:
  1935. err_alloc_rx:
  1936. atl1c_clean_rx_ring(adapter);
  1937. return err;
  1938. }
  1939. static void atl1c_down(struct atl1c_adapter *adapter)
  1940. {
  1941. struct net_device *netdev = adapter->netdev;
  1942. atl1c_del_timer(adapter);
  1943. adapter->work_event = 0; /* clear all event */
  1944. /* signal that we're down so the interrupt handler does not
  1945. * reschedule our watchdog timer */
  1946. set_bit(__AT_DOWN, &adapter->flags);
  1947. netif_carrier_off(netdev);
  1948. napi_disable(&adapter->napi);
  1949. atl1c_irq_disable(adapter);
  1950. atl1c_free_irq(adapter);
  1951. /* disable ASPM if device inactive */
  1952. atl1c_disable_l0s_l1(&adapter->hw);
  1953. /* reset MAC to disable all RX/TX */
  1954. atl1c_reset_mac(&adapter->hw);
  1955. msleep(1);
  1956. adapter->link_speed = SPEED_0;
  1957. adapter->link_duplex = -1;
  1958. atl1c_clean_tx_ring(adapter, atl1c_trans_normal);
  1959. atl1c_clean_tx_ring(adapter, atl1c_trans_high);
  1960. atl1c_clean_rx_ring(adapter);
  1961. }
  1962. /*
  1963. * atl1c_open - Called when a network interface is made active
  1964. * @netdev: network interface device structure
  1965. *
  1966. * Returns 0 on success, negative value on failure
  1967. *
  1968. * The open entry point is called when a network interface is made
  1969. * active by the system (IFF_UP). At this point all resources needed
  1970. * for transmit and receive operations are allocated, the interrupt
  1971. * handler is registered with the OS, the watchdog timer is started,
  1972. * and the stack is notified that the interface is ready.
  1973. */
  1974. static int atl1c_open(struct net_device *netdev)
  1975. {
  1976. struct atl1c_adapter *adapter = netdev_priv(netdev);
  1977. int err;
  1978. /* disallow open during test */
  1979. if (test_bit(__AT_TESTING, &adapter->flags))
  1980. return -EBUSY;
  1981. /* allocate rx/tx dma buffer & descriptors */
  1982. err = atl1c_setup_ring_resources(adapter);
  1983. if (unlikely(err))
  1984. return err;
  1985. err = atl1c_up(adapter);
  1986. if (unlikely(err))
  1987. goto err_up;
  1988. if (adapter->hw.ctrl_flags & ATL1C_FPGA_VERSION) {
  1989. u32 phy_data;
  1990. AT_READ_REG(&adapter->hw, REG_MDIO_CTRL, &phy_data);
  1991. phy_data |= MDIO_CTRL_AP_EN;
  1992. AT_WRITE_REG(&adapter->hw, REG_MDIO_CTRL, phy_data);
  1993. }
  1994. return 0;
  1995. err_up:
  1996. atl1c_free_irq(adapter);
  1997. atl1c_free_ring_resources(adapter);
  1998. atl1c_reset_mac(&adapter->hw);
  1999. return err;
  2000. }
  2001. /*
  2002. * atl1c_close - Disables a network interface
  2003. * @netdev: network interface device structure
  2004. *
  2005. * Returns 0, this is not allowed to fail
  2006. *
  2007. * The close entry point is called when an interface is de-activated
  2008. * by the OS. The hardware is still under the drivers control, but
  2009. * needs to be disabled. A global MAC reset is issued to stop the
  2010. * hardware, and all transmit and receive resources are freed.
  2011. */
  2012. static int atl1c_close(struct net_device *netdev)
  2013. {
  2014. struct atl1c_adapter *adapter = netdev_priv(netdev);
  2015. WARN_ON(test_bit(__AT_RESETTING, &adapter->flags));
  2016. atl1c_down(adapter);
  2017. atl1c_free_ring_resources(adapter);
  2018. return 0;
  2019. }
  2020. static int atl1c_suspend(struct device *dev)
  2021. {
  2022. struct pci_dev *pdev = to_pci_dev(dev);
  2023. struct net_device *netdev = pci_get_drvdata(pdev);
  2024. struct atl1c_adapter *adapter = netdev_priv(netdev);
  2025. struct atl1c_hw *hw = &adapter->hw;
  2026. u32 mac_ctrl_data = 0;
  2027. u32 master_ctrl_data = 0;
  2028. u32 wol_ctrl_data = 0;
  2029. u16 mii_intr_status_data = 0;
  2030. u32 wufc = adapter->wol;
  2031. atl1c_disable_l0s_l1(hw);
  2032. if (netif_running(netdev)) {
  2033. WARN_ON(test_bit(__AT_RESETTING, &adapter->flags));
  2034. atl1c_down(adapter);
  2035. }
  2036. netif_device_detach(netdev);
  2037. if (wufc)
  2038. if (atl1c_phy_power_saving(hw) != 0)
  2039. dev_dbg(&pdev->dev, "phy power saving failed");
  2040. AT_READ_REG(hw, REG_MASTER_CTRL, &master_ctrl_data);
  2041. AT_READ_REG(hw, REG_MAC_CTRL, &mac_ctrl_data);
  2042. master_ctrl_data &= ~MASTER_CTRL_CLK_SEL_DIS;
  2043. mac_ctrl_data &= ~(MAC_CTRL_PRMLEN_MASK << MAC_CTRL_PRMLEN_SHIFT);
  2044. mac_ctrl_data |= (((u32)adapter->hw.preamble_len &
  2045. MAC_CTRL_PRMLEN_MASK) <<
  2046. MAC_CTRL_PRMLEN_SHIFT);
  2047. mac_ctrl_data &= ~(MAC_CTRL_SPEED_MASK << MAC_CTRL_SPEED_SHIFT);
  2048. mac_ctrl_data &= ~MAC_CTRL_DUPLX;
  2049. if (wufc) {
  2050. mac_ctrl_data |= MAC_CTRL_RX_EN;
  2051. if (adapter->link_speed == SPEED_1000 ||
  2052. adapter->link_speed == SPEED_0) {
  2053. mac_ctrl_data |= atl1c_mac_speed_1000 <<
  2054. MAC_CTRL_SPEED_SHIFT;
  2055. mac_ctrl_data |= MAC_CTRL_DUPLX;
  2056. } else
  2057. mac_ctrl_data |= atl1c_mac_speed_10_100 <<
  2058. MAC_CTRL_SPEED_SHIFT;
  2059. if (adapter->link_duplex == DUPLEX_FULL)
  2060. mac_ctrl_data |= MAC_CTRL_DUPLX;
  2061. /* turn on magic packet wol */
  2062. if (wufc & AT_WUFC_MAG) {
  2063. wol_ctrl_data |= WOL_MAGIC_EN | WOL_MAGIC_PME_EN;
  2064. if (hw->nic_type == athr_l2c_b &&
  2065. hw->revision_id == L2CB_V11) {
  2066. wol_ctrl_data |=
  2067. WOL_PATTERN_EN | WOL_PATTERN_PME_EN;
  2068. }
  2069. }
  2070. if (wufc & AT_WUFC_LNKC) {
  2071. wol_ctrl_data |= WOL_LINK_CHG_EN | WOL_LINK_CHG_PME_EN;
  2072. /* only link up can wake up */
  2073. if (atl1c_write_phy_reg(hw, MII_IER, IER_LINK_UP) != 0) {
  2074. dev_dbg(&pdev->dev, "%s: read write phy "
  2075. "register failed.\n",
  2076. atl1c_driver_name);
  2077. }
  2078. }
  2079. /* clear phy interrupt */
  2080. atl1c_read_phy_reg(hw, MII_ISR, &mii_intr_status_data);
  2081. /* Config MAC Ctrl register */
  2082. __atl1c_vlan_mode(netdev->features, &mac_ctrl_data);
  2083. /* magic packet maybe Broadcast&multicast&Unicast frame */
  2084. if (wufc & AT_WUFC_MAG)
  2085. mac_ctrl_data |= MAC_CTRL_BC_EN;
  2086. dev_dbg(&pdev->dev,
  2087. "%s: suspend MAC=0x%x\n",
  2088. atl1c_driver_name, mac_ctrl_data);
  2089. AT_WRITE_REG(hw, REG_MASTER_CTRL, master_ctrl_data);
  2090. AT_WRITE_REG(hw, REG_WOL_CTRL, wol_ctrl_data);
  2091. AT_WRITE_REG(hw, REG_MAC_CTRL, mac_ctrl_data);
  2092. AT_WRITE_REG(hw, REG_GPHY_CTRL, GPHY_CTRL_DEFAULT |
  2093. GPHY_CTRL_EXT_RESET);
  2094. } else {
  2095. AT_WRITE_REG(hw, REG_GPHY_CTRL, GPHY_CTRL_POWER_SAVING);
  2096. master_ctrl_data |= MASTER_CTRL_CLK_SEL_DIS;
  2097. mac_ctrl_data |= atl1c_mac_speed_10_100 << MAC_CTRL_SPEED_SHIFT;
  2098. mac_ctrl_data |= MAC_CTRL_DUPLX;
  2099. AT_WRITE_REG(hw, REG_MASTER_CTRL, master_ctrl_data);
  2100. AT_WRITE_REG(hw, REG_MAC_CTRL, mac_ctrl_data);
  2101. AT_WRITE_REG(hw, REG_WOL_CTRL, 0);
  2102. hw->phy_configured = false; /* re-init PHY when resume */
  2103. }
  2104. return 0;
  2105. }
  2106. #ifdef CONFIG_PM_SLEEP
  2107. static int atl1c_resume(struct device *dev)
  2108. {
  2109. struct pci_dev *pdev = to_pci_dev(dev);
  2110. struct net_device *netdev = pci_get_drvdata(pdev);
  2111. struct atl1c_adapter *adapter = netdev_priv(netdev);
  2112. AT_WRITE_REG(&adapter->hw, REG_WOL_CTRL, 0);
  2113. atl1c_reset_pcie(&adapter->hw, ATL1C_PCIE_L0S_L1_DISABLE);
  2114. atl1c_phy_reset(&adapter->hw);
  2115. atl1c_reset_mac(&adapter->hw);
  2116. atl1c_phy_init(&adapter->hw);
  2117. #if 0
  2118. AT_READ_REG(&adapter->hw, REG_PM_CTRLSTAT, &pm_data);
  2119. pm_data &= ~PM_CTRLSTAT_PME_EN;
  2120. AT_WRITE_REG(&adapter->hw, REG_PM_CTRLSTAT, pm_data);
  2121. #endif
  2122. netif_device_attach(netdev);
  2123. if (netif_running(netdev))
  2124. atl1c_up(adapter);
  2125. return 0;
  2126. }
  2127. #endif
  2128. static void atl1c_shutdown(struct pci_dev *pdev)
  2129. {
  2130. struct net_device *netdev = pci_get_drvdata(pdev);
  2131. struct atl1c_adapter *adapter = netdev_priv(netdev);
  2132. atl1c_suspend(&pdev->dev);
  2133. pci_wake_from_d3(pdev, adapter->wol);
  2134. pci_set_power_state(pdev, PCI_D3hot);
  2135. }
  2136. static const struct net_device_ops atl1c_netdev_ops = {
  2137. .ndo_open = atl1c_open,
  2138. .ndo_stop = atl1c_close,
  2139. .ndo_validate_addr = eth_validate_addr,
  2140. .ndo_start_xmit = atl1c_xmit_frame,
  2141. .ndo_set_mac_address = atl1c_set_mac_addr,
  2142. .ndo_set_rx_mode = atl1c_set_multi,
  2143. .ndo_change_mtu = atl1c_change_mtu,
  2144. .ndo_fix_features = atl1c_fix_features,
  2145. .ndo_set_features = atl1c_set_features,
  2146. .ndo_do_ioctl = atl1c_ioctl,
  2147. .ndo_tx_timeout = atl1c_tx_timeout,
  2148. .ndo_get_stats = atl1c_get_stats,
  2149. #ifdef CONFIG_NET_POLL_CONTROLLER
  2150. .ndo_poll_controller = atl1c_netpoll,
  2151. #endif
  2152. };
  2153. static int atl1c_init_netdev(struct net_device *netdev, struct pci_dev *pdev)
  2154. {
  2155. SET_NETDEV_DEV(netdev, &pdev->dev);
  2156. pci_set_drvdata(pdev, netdev);
  2157. netdev->netdev_ops = &atl1c_netdev_ops;
  2158. netdev->watchdog_timeo = AT_TX_WATCHDOG;
  2159. atl1c_set_ethtool_ops(netdev);
  2160. /* TODO: add when ready */
  2161. netdev->hw_features = NETIF_F_SG |
  2162. NETIF_F_HW_CSUM |
  2163. NETIF_F_HW_VLAN_RX |
  2164. NETIF_F_TSO |
  2165. NETIF_F_TSO6;
  2166. netdev->features = netdev->hw_features |
  2167. NETIF_F_HW_VLAN_TX;
  2168. return 0;
  2169. }
  2170. /*
  2171. * atl1c_probe - Device Initialization Routine
  2172. * @pdev: PCI device information struct
  2173. * @ent: entry in atl1c_pci_tbl
  2174. *
  2175. * Returns 0 on success, negative on failure
  2176. *
  2177. * atl1c_probe initializes an adapter identified by a pci_dev structure.
  2178. * The OS initialization, configuring of the adapter private structure,
  2179. * and a hardware reset occur.
  2180. */
  2181. static int __devinit atl1c_probe(struct pci_dev *pdev,
  2182. const struct pci_device_id *ent)
  2183. {
  2184. struct net_device *netdev;
  2185. struct atl1c_adapter *adapter;
  2186. static int cards_found;
  2187. int err = 0;
  2188. /* enable device (incl. PCI PM wakeup and hotplug setup) */
  2189. err = pci_enable_device_mem(pdev);
  2190. if (err) {
  2191. dev_err(&pdev->dev, "cannot enable PCI device\n");
  2192. return err;
  2193. }
  2194. /*
  2195. * The atl1c chip can DMA to 64-bit addresses, but it uses a single
  2196. * shared register for the high 32 bits, so only a single, aligned,
  2197. * 4 GB physical address range can be used at a time.
  2198. *
  2199. * Supporting 64-bit DMA on this hardware is more trouble than it's
  2200. * worth. It is far easier to limit to 32-bit DMA than update
  2201. * various kernel subsystems to support the mechanics required by a
  2202. * fixed-high-32-bit system.
  2203. */
  2204. if ((pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) != 0) ||
  2205. (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)) != 0)) {
  2206. dev_err(&pdev->dev, "No usable DMA configuration,aborting\n");
  2207. goto err_dma;
  2208. }
  2209. err = pci_request_regions(pdev, atl1c_driver_name);
  2210. if (err) {
  2211. dev_err(&pdev->dev, "cannot obtain PCI resources\n");
  2212. goto err_pci_reg;
  2213. }
  2214. pci_set_master(pdev);
  2215. netdev = alloc_etherdev(sizeof(struct atl1c_adapter));
  2216. if (netdev == NULL) {
  2217. err = -ENOMEM;
  2218. goto err_alloc_etherdev;
  2219. }
  2220. err = atl1c_init_netdev(netdev, pdev);
  2221. if (err) {
  2222. dev_err(&pdev->dev, "init netdevice failed\n");
  2223. goto err_init_netdev;
  2224. }
  2225. adapter = netdev_priv(netdev);
  2226. adapter->bd_number = cards_found;
  2227. adapter->netdev = netdev;
  2228. adapter->pdev = pdev;
  2229. adapter->hw.adapter = adapter;
  2230. adapter->msg_enable = netif_msg_init(-1, atl1c_default_msg);
  2231. adapter->hw.hw_addr = ioremap(pci_resource_start(pdev, 0), pci_resource_len(pdev, 0));
  2232. if (!adapter->hw.hw_addr) {
  2233. err = -EIO;
  2234. dev_err(&pdev->dev, "cannot map device registers\n");
  2235. goto err_ioremap;
  2236. }
  2237. /* init mii data */
  2238. adapter->mii.dev = netdev;
  2239. adapter->mii.mdio_read = atl1c_mdio_read;
  2240. adapter->mii.mdio_write = atl1c_mdio_write;
  2241. adapter->mii.phy_id_mask = 0x1f;
  2242. adapter->mii.reg_num_mask = MDIO_CTRL_REG_MASK;
  2243. netif_napi_add(netdev, &adapter->napi, atl1c_clean, 64);
  2244. setup_timer(&adapter->phy_config_timer, atl1c_phy_config,
  2245. (unsigned long)adapter);
  2246. /* setup the private structure */
  2247. err = atl1c_sw_init(adapter);
  2248. if (err) {
  2249. dev_err(&pdev->dev, "net device private data init failed\n");
  2250. goto err_sw_init;
  2251. }
  2252. atl1c_reset_pcie(&adapter->hw, ATL1C_PCIE_L0S_L1_DISABLE);
  2253. /* Init GPHY as early as possible due to power saving issue */
  2254. atl1c_phy_reset(&adapter->hw);
  2255. err = atl1c_reset_mac(&adapter->hw);
  2256. if (err) {
  2257. err = -EIO;
  2258. goto err_reset;
  2259. }
  2260. /* reset the controller to
  2261. * put the device in a known good starting state */
  2262. err = atl1c_phy_init(&adapter->hw);
  2263. if (err) {
  2264. err = -EIO;
  2265. goto err_reset;
  2266. }
  2267. if (atl1c_read_mac_addr(&adapter->hw)) {
  2268. /* got a random MAC address, set NET_ADDR_RANDOM to netdev */
  2269. netdev->addr_assign_type |= NET_ADDR_RANDOM;
  2270. }
  2271. memcpy(netdev->dev_addr, adapter->hw.mac_addr, netdev->addr_len);
  2272. memcpy(netdev->perm_addr, adapter->hw.mac_addr, netdev->addr_len);
  2273. if (netif_msg_probe(adapter))
  2274. dev_dbg(&pdev->dev, "mac address : %pM\n",
  2275. adapter->hw.mac_addr);
  2276. atl1c_hw_set_mac_addr(&adapter->hw);
  2277. INIT_WORK(&adapter->common_task, atl1c_common_task);
  2278. adapter->work_event = 0;
  2279. err = register_netdev(netdev);
  2280. if (err) {
  2281. dev_err(&pdev->dev, "register netdevice failed\n");
  2282. goto err_register;
  2283. }
  2284. if (netif_msg_probe(adapter))
  2285. dev_info(&pdev->dev, "version %s\n", ATL1C_DRV_VERSION);
  2286. cards_found++;
  2287. return 0;
  2288. err_reset:
  2289. err_register:
  2290. err_sw_init:
  2291. iounmap(adapter->hw.hw_addr);
  2292. err_init_netdev:
  2293. err_ioremap:
  2294. free_netdev(netdev);
  2295. err_alloc_etherdev:
  2296. pci_release_regions(pdev);
  2297. err_pci_reg:
  2298. err_dma:
  2299. pci_disable_device(pdev);
  2300. return err;
  2301. }
  2302. /*
  2303. * atl1c_remove - Device Removal Routine
  2304. * @pdev: PCI device information struct
  2305. *
  2306. * atl1c_remove is called by the PCI subsystem to alert the driver
  2307. * that it should release a PCI device. The could be caused by a
  2308. * Hot-Plug event, or because the driver is going to be removed from
  2309. * memory.
  2310. */
  2311. static void __devexit atl1c_remove(struct pci_dev *pdev)
  2312. {
  2313. struct net_device *netdev = pci_get_drvdata(pdev);
  2314. struct atl1c_adapter *adapter = netdev_priv(netdev);
  2315. unregister_netdev(netdev);
  2316. atl1c_phy_disable(&adapter->hw);
  2317. iounmap(adapter->hw.hw_addr);
  2318. pci_release_regions(pdev);
  2319. pci_disable_device(pdev);
  2320. free_netdev(netdev);
  2321. }
  2322. /*
  2323. * atl1c_io_error_detected - called when PCI error is detected
  2324. * @pdev: Pointer to PCI device
  2325. * @state: The current pci connection state
  2326. *
  2327. * This function is called after a PCI bus error affecting
  2328. * this device has been detected.
  2329. */
  2330. static pci_ers_result_t atl1c_io_error_detected(struct pci_dev *pdev,
  2331. pci_channel_state_t state)
  2332. {
  2333. struct net_device *netdev = pci_get_drvdata(pdev);
  2334. struct atl1c_adapter *adapter = netdev_priv(netdev);
  2335. netif_device_detach(netdev);
  2336. if (state == pci_channel_io_perm_failure)
  2337. return PCI_ERS_RESULT_DISCONNECT;
  2338. if (netif_running(netdev))
  2339. atl1c_down(adapter);
  2340. pci_disable_device(pdev);
  2341. /* Request a slot slot reset. */
  2342. return PCI_ERS_RESULT_NEED_RESET;
  2343. }
  2344. /*
  2345. * atl1c_io_slot_reset - called after the pci bus has been reset.
  2346. * @pdev: Pointer to PCI device
  2347. *
  2348. * Restart the card from scratch, as if from a cold-boot. Implementation
  2349. * resembles the first-half of the e1000_resume routine.
  2350. */
  2351. static pci_ers_result_t atl1c_io_slot_reset(struct pci_dev *pdev)
  2352. {
  2353. struct net_device *netdev = pci_get_drvdata(pdev);
  2354. struct atl1c_adapter *adapter = netdev_priv(netdev);
  2355. if (pci_enable_device(pdev)) {
  2356. if (netif_msg_hw(adapter))
  2357. dev_err(&pdev->dev,
  2358. "Cannot re-enable PCI device after reset\n");
  2359. return PCI_ERS_RESULT_DISCONNECT;
  2360. }
  2361. pci_set_master(pdev);
  2362. pci_enable_wake(pdev, PCI_D3hot, 0);
  2363. pci_enable_wake(pdev, PCI_D3cold, 0);
  2364. atl1c_reset_mac(&adapter->hw);
  2365. return PCI_ERS_RESULT_RECOVERED;
  2366. }
  2367. /*
  2368. * atl1c_io_resume - called when traffic can start flowing again.
  2369. * @pdev: Pointer to PCI device
  2370. *
  2371. * This callback is called when the error recovery driver tells us that
  2372. * its OK to resume normal operation. Implementation resembles the
  2373. * second-half of the atl1c_resume routine.
  2374. */
  2375. static void atl1c_io_resume(struct pci_dev *pdev)
  2376. {
  2377. struct net_device *netdev = pci_get_drvdata(pdev);
  2378. struct atl1c_adapter *adapter = netdev_priv(netdev);
  2379. if (netif_running(netdev)) {
  2380. if (atl1c_up(adapter)) {
  2381. if (netif_msg_hw(adapter))
  2382. dev_err(&pdev->dev,
  2383. "Cannot bring device back up after reset\n");
  2384. return;
  2385. }
  2386. }
  2387. netif_device_attach(netdev);
  2388. }
  2389. static struct pci_error_handlers atl1c_err_handler = {
  2390. .error_detected = atl1c_io_error_detected,
  2391. .slot_reset = atl1c_io_slot_reset,
  2392. .resume = atl1c_io_resume,
  2393. };
  2394. static SIMPLE_DEV_PM_OPS(atl1c_pm_ops, atl1c_suspend, atl1c_resume);
  2395. static struct pci_driver atl1c_driver = {
  2396. .name = atl1c_driver_name,
  2397. .id_table = atl1c_pci_tbl,
  2398. .probe = atl1c_probe,
  2399. .remove = __devexit_p(atl1c_remove),
  2400. .shutdown = atl1c_shutdown,
  2401. .err_handler = &atl1c_err_handler,
  2402. .driver.pm = &atl1c_pm_ops,
  2403. };
  2404. /*
  2405. * atl1c_init_module - Driver Registration Routine
  2406. *
  2407. * atl1c_init_module is the first routine called when the driver is
  2408. * loaded. All it does is register with the PCI subsystem.
  2409. */
  2410. static int __init atl1c_init_module(void)
  2411. {
  2412. return pci_register_driver(&atl1c_driver);
  2413. }
  2414. /*
  2415. * atl1c_exit_module - Driver Exit Cleanup Routine
  2416. *
  2417. * atl1c_exit_module is called just before the driver is removed
  2418. * from memory.
  2419. */
  2420. static void __exit atl1c_exit_module(void)
  2421. {
  2422. pci_unregister_driver(&atl1c_driver);
  2423. }
  2424. module_init(atl1c_init_module);
  2425. module_exit(atl1c_exit_module);