omapdss.h 17 KB

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  1. /*
  2. * Copyright (C) 2008 Nokia Corporation
  3. * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms of the GNU General Public License version 2 as published by
  7. * the Free Software Foundation.
  8. *
  9. * This program is distributed in the hope that it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12. * more details.
  13. *
  14. * You should have received a copy of the GNU General Public License along with
  15. * this program. If not, see <http://www.gnu.org/licenses/>.
  16. */
  17. #ifndef __OMAP_OMAPDSS_H
  18. #define __OMAP_OMAPDSS_H
  19. #include <linux/list.h>
  20. #include <linux/kobject.h>
  21. #include <linux/device.h>
  22. #include <linux/platform_device.h>
  23. #include <asm/atomic.h>
  24. #define DISPC_IRQ_FRAMEDONE (1 << 0)
  25. #define DISPC_IRQ_VSYNC (1 << 1)
  26. #define DISPC_IRQ_EVSYNC_EVEN (1 << 2)
  27. #define DISPC_IRQ_EVSYNC_ODD (1 << 3)
  28. #define DISPC_IRQ_ACBIAS_COUNT_STAT (1 << 4)
  29. #define DISPC_IRQ_PROG_LINE_NUM (1 << 5)
  30. #define DISPC_IRQ_GFX_FIFO_UNDERFLOW (1 << 6)
  31. #define DISPC_IRQ_GFX_END_WIN (1 << 7)
  32. #define DISPC_IRQ_PAL_GAMMA_MASK (1 << 8)
  33. #define DISPC_IRQ_OCP_ERR (1 << 9)
  34. #define DISPC_IRQ_VID1_FIFO_UNDERFLOW (1 << 10)
  35. #define DISPC_IRQ_VID1_END_WIN (1 << 11)
  36. #define DISPC_IRQ_VID2_FIFO_UNDERFLOW (1 << 12)
  37. #define DISPC_IRQ_VID2_END_WIN (1 << 13)
  38. #define DISPC_IRQ_SYNC_LOST (1 << 14)
  39. #define DISPC_IRQ_SYNC_LOST_DIGIT (1 << 15)
  40. #define DISPC_IRQ_WAKEUP (1 << 16)
  41. #define DISPC_IRQ_SYNC_LOST2 (1 << 17)
  42. #define DISPC_IRQ_VSYNC2 (1 << 18)
  43. #define DISPC_IRQ_ACBIAS_COUNT_STAT2 (1 << 21)
  44. #define DISPC_IRQ_FRAMEDONE2 (1 << 22)
  45. struct omap_dss_device;
  46. struct omap_overlay_manager;
  47. enum omap_display_type {
  48. OMAP_DISPLAY_TYPE_NONE = 0,
  49. OMAP_DISPLAY_TYPE_DPI = 1 << 0,
  50. OMAP_DISPLAY_TYPE_DBI = 1 << 1,
  51. OMAP_DISPLAY_TYPE_SDI = 1 << 2,
  52. OMAP_DISPLAY_TYPE_DSI = 1 << 3,
  53. OMAP_DISPLAY_TYPE_VENC = 1 << 4,
  54. OMAP_DISPLAY_TYPE_HDMI = 1 << 5,
  55. };
  56. enum omap_plane {
  57. OMAP_DSS_GFX = 0,
  58. OMAP_DSS_VIDEO1 = 1,
  59. OMAP_DSS_VIDEO2 = 2
  60. };
  61. enum omap_channel {
  62. OMAP_DSS_CHANNEL_LCD = 0,
  63. OMAP_DSS_CHANNEL_DIGIT = 1,
  64. OMAP_DSS_CHANNEL_LCD2 = 2,
  65. };
  66. enum omap_color_mode {
  67. OMAP_DSS_COLOR_CLUT1 = 1 << 0, /* BITMAP 1 */
  68. OMAP_DSS_COLOR_CLUT2 = 1 << 1, /* BITMAP 2 */
  69. OMAP_DSS_COLOR_CLUT4 = 1 << 2, /* BITMAP 4 */
  70. OMAP_DSS_COLOR_CLUT8 = 1 << 3, /* BITMAP 8 */
  71. OMAP_DSS_COLOR_RGB12U = 1 << 4, /* RGB12, 16-bit container */
  72. OMAP_DSS_COLOR_ARGB16 = 1 << 5, /* ARGB16 */
  73. OMAP_DSS_COLOR_RGB16 = 1 << 6, /* RGB16 */
  74. OMAP_DSS_COLOR_RGB24U = 1 << 7, /* RGB24, 32-bit container */
  75. OMAP_DSS_COLOR_RGB24P = 1 << 8, /* RGB24, 24-bit container */
  76. OMAP_DSS_COLOR_YUV2 = 1 << 9, /* YUV2 4:2:2 co-sited */
  77. OMAP_DSS_COLOR_UYVY = 1 << 10, /* UYVY 4:2:2 co-sited */
  78. OMAP_DSS_COLOR_ARGB32 = 1 << 11, /* ARGB32 */
  79. OMAP_DSS_COLOR_RGBA32 = 1 << 12, /* RGBA32 */
  80. OMAP_DSS_COLOR_RGBX32 = 1 << 13, /* RGBx32 */
  81. };
  82. enum omap_lcd_display_type {
  83. OMAP_DSS_LCD_DISPLAY_STN,
  84. OMAP_DSS_LCD_DISPLAY_TFT,
  85. };
  86. enum omap_dss_load_mode {
  87. OMAP_DSS_LOAD_CLUT_AND_FRAME = 0,
  88. OMAP_DSS_LOAD_CLUT_ONLY = 1,
  89. OMAP_DSS_LOAD_FRAME_ONLY = 2,
  90. OMAP_DSS_LOAD_CLUT_ONCE_FRAME = 3,
  91. };
  92. enum omap_dss_trans_key_type {
  93. OMAP_DSS_COLOR_KEY_GFX_DST = 0,
  94. OMAP_DSS_COLOR_KEY_VID_SRC = 1,
  95. };
  96. enum omap_rfbi_te_mode {
  97. OMAP_DSS_RFBI_TE_MODE_1 = 1,
  98. OMAP_DSS_RFBI_TE_MODE_2 = 2,
  99. };
  100. enum omap_panel_config {
  101. OMAP_DSS_LCD_IVS = 1<<0,
  102. OMAP_DSS_LCD_IHS = 1<<1,
  103. OMAP_DSS_LCD_IPC = 1<<2,
  104. OMAP_DSS_LCD_IEO = 1<<3,
  105. OMAP_DSS_LCD_RF = 1<<4,
  106. OMAP_DSS_LCD_ONOFF = 1<<5,
  107. OMAP_DSS_LCD_TFT = 1<<20,
  108. };
  109. enum omap_dss_venc_type {
  110. OMAP_DSS_VENC_TYPE_COMPOSITE,
  111. OMAP_DSS_VENC_TYPE_SVIDEO,
  112. };
  113. enum omap_display_caps {
  114. OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE = 1 << 0,
  115. OMAP_DSS_DISPLAY_CAP_TEAR_ELIM = 1 << 1,
  116. };
  117. enum omap_dss_update_mode {
  118. OMAP_DSS_UPDATE_DISABLED = 0,
  119. OMAP_DSS_UPDATE_AUTO,
  120. OMAP_DSS_UPDATE_MANUAL,
  121. };
  122. enum omap_dss_display_state {
  123. OMAP_DSS_DISPLAY_DISABLED = 0,
  124. OMAP_DSS_DISPLAY_ACTIVE,
  125. OMAP_DSS_DISPLAY_SUSPENDED,
  126. };
  127. /* XXX perhaps this should be removed */
  128. enum omap_dss_overlay_managers {
  129. OMAP_DSS_OVL_MGR_LCD,
  130. OMAP_DSS_OVL_MGR_TV,
  131. OMAP_DSS_OVL_MGR_LCD2,
  132. };
  133. enum omap_dss_rotation_type {
  134. OMAP_DSS_ROT_DMA = 0,
  135. OMAP_DSS_ROT_VRFB = 1,
  136. };
  137. /* clockwise rotation angle */
  138. enum omap_dss_rotation_angle {
  139. OMAP_DSS_ROT_0 = 0,
  140. OMAP_DSS_ROT_90 = 1,
  141. OMAP_DSS_ROT_180 = 2,
  142. OMAP_DSS_ROT_270 = 3,
  143. };
  144. enum omap_overlay_caps {
  145. OMAP_DSS_OVL_CAP_SCALE = 1 << 0,
  146. OMAP_DSS_OVL_CAP_DISPC = 1 << 1,
  147. };
  148. enum omap_overlay_manager_caps {
  149. OMAP_DSS_OVL_MGR_CAP_DISPC = 1 << 0,
  150. };
  151. enum omap_dss_clk_source {
  152. OMAP_DSS_CLK_SRC_FCK = 0, /* OMAP2/3: DSS1_ALWON_FCLK
  153. * OMAP4: DSS_FCLK */
  154. OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC, /* OMAP3: DSI1_PLL_FCLK
  155. * OMAP4: PLL1_CLK1 */
  156. OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI, /* OMAP3: DSI2_PLL_FCLK
  157. * OMAP4: PLL1_CLK2 */
  158. OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC, /* OMAP4: PLL2_CLK1 */
  159. OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI, /* OMAP4: PLL2_CLK2 */
  160. };
  161. /* RFBI */
  162. struct rfbi_timings {
  163. int cs_on_time;
  164. int cs_off_time;
  165. int we_on_time;
  166. int we_off_time;
  167. int re_on_time;
  168. int re_off_time;
  169. int we_cycle_time;
  170. int re_cycle_time;
  171. int cs_pulse_width;
  172. int access_time;
  173. int clk_div;
  174. u32 tim[5]; /* set by rfbi_convert_timings() */
  175. int converted;
  176. };
  177. void omap_rfbi_write_command(const void *buf, u32 len);
  178. void omap_rfbi_read_data(void *buf, u32 len);
  179. void omap_rfbi_write_data(const void *buf, u32 len);
  180. void omap_rfbi_write_pixels(const void __iomem *buf, int scr_width,
  181. u16 x, u16 y,
  182. u16 w, u16 h);
  183. int omap_rfbi_enable_te(bool enable, unsigned line);
  184. int omap_rfbi_setup_te(enum omap_rfbi_te_mode mode,
  185. unsigned hs_pulse_time, unsigned vs_pulse_time,
  186. int hs_pol_inv, int vs_pol_inv, int extif_div);
  187. void rfbi_bus_lock(void);
  188. void rfbi_bus_unlock(void);
  189. /* DSI */
  190. void dsi_bus_lock(struct omap_dss_device *dssdev);
  191. void dsi_bus_unlock(struct omap_dss_device *dssdev);
  192. int dsi_vc_dcs_write(struct omap_dss_device *dssdev, int channel, u8 *data,
  193. int len);
  194. int dsi_vc_dcs_write_0(struct omap_dss_device *dssdev, int channel,
  195. u8 dcs_cmd);
  196. int dsi_vc_dcs_write_1(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
  197. u8 param);
  198. int dsi_vc_dcs_write_nosync(struct omap_dss_device *dssdev, int channel,
  199. u8 *data, int len);
  200. int dsi_vc_dcs_read(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
  201. u8 *buf, int buflen);
  202. int dsi_vc_dcs_read_1(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
  203. u8 *data);
  204. int dsi_vc_dcs_read_2(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
  205. u8 *data1, u8 *data2);
  206. int dsi_vc_set_max_rx_packet_size(struct omap_dss_device *dssdev, int channel,
  207. u16 len);
  208. int dsi_vc_send_null(struct omap_dss_device *dssdev, int channel);
  209. int dsi_vc_send_bta_sync(struct omap_dss_device *dssdev, int channel);
  210. /* Board specific data */
  211. struct omap_dss_board_info {
  212. int (*get_last_off_on_transaction_id)(struct device *dev);
  213. int num_devices;
  214. struct omap_dss_device **devices;
  215. struct omap_dss_device *default_device;
  216. void (*dsi_mux_pads)(bool enable);
  217. };
  218. #if defined(CONFIG_OMAP2_DSS_MODULE) || defined(CONFIG_OMAP2_DSS)
  219. /* Init with the board info */
  220. extern int omap_display_init(struct omap_dss_board_info *board_data);
  221. #else
  222. static inline int omap_display_init(struct omap_dss_board_info *board_data)
  223. {
  224. return 0;
  225. }
  226. #endif
  227. struct omap_display_platform_data {
  228. struct omap_dss_board_info *board_data;
  229. /* TODO: Additional members to be added when PM is considered */
  230. bool (*opt_clock_available)(const char *clk_role);
  231. };
  232. struct omap_video_timings {
  233. /* Unit: pixels */
  234. u16 x_res;
  235. /* Unit: pixels */
  236. u16 y_res;
  237. /* Unit: KHz */
  238. u32 pixel_clock;
  239. /* Unit: pixel clocks */
  240. u16 hsw; /* Horizontal synchronization pulse width */
  241. /* Unit: pixel clocks */
  242. u16 hfp; /* Horizontal front porch */
  243. /* Unit: pixel clocks */
  244. u16 hbp; /* Horizontal back porch */
  245. /* Unit: line clocks */
  246. u16 vsw; /* Vertical synchronization pulse width */
  247. /* Unit: line clocks */
  248. u16 vfp; /* Vertical front porch */
  249. /* Unit: line clocks */
  250. u16 vbp; /* Vertical back porch */
  251. };
  252. #ifdef CONFIG_OMAP2_DSS_VENC
  253. /* Hardcoded timings for tv modes. Venc only uses these to
  254. * identify the mode, and does not actually use the configs
  255. * itself. However, the configs should be something that
  256. * a normal monitor can also show */
  257. extern const struct omap_video_timings omap_dss_pal_timings;
  258. extern const struct omap_video_timings omap_dss_ntsc_timings;
  259. #endif
  260. struct omap_overlay_info {
  261. bool enabled;
  262. u32 paddr;
  263. void __iomem *vaddr;
  264. u16 screen_width;
  265. u16 width;
  266. u16 height;
  267. enum omap_color_mode color_mode;
  268. u8 rotation;
  269. enum omap_dss_rotation_type rotation_type;
  270. bool mirror;
  271. u16 pos_x;
  272. u16 pos_y;
  273. u16 out_width; /* if 0, out_width == width */
  274. u16 out_height; /* if 0, out_height == height */
  275. u8 global_alpha;
  276. u8 pre_mult_alpha;
  277. };
  278. struct omap_overlay {
  279. struct kobject kobj;
  280. struct list_head list;
  281. /* static fields */
  282. const char *name;
  283. int id;
  284. enum omap_color_mode supported_modes;
  285. enum omap_overlay_caps caps;
  286. /* dynamic fields */
  287. struct omap_overlay_manager *manager;
  288. struct omap_overlay_info info;
  289. /* if true, info has been changed, but not applied() yet */
  290. bool info_dirty;
  291. int (*set_manager)(struct omap_overlay *ovl,
  292. struct omap_overlay_manager *mgr);
  293. int (*unset_manager)(struct omap_overlay *ovl);
  294. int (*set_overlay_info)(struct omap_overlay *ovl,
  295. struct omap_overlay_info *info);
  296. void (*get_overlay_info)(struct omap_overlay *ovl,
  297. struct omap_overlay_info *info);
  298. int (*wait_for_go)(struct omap_overlay *ovl);
  299. };
  300. struct omap_overlay_manager_info {
  301. u32 default_color;
  302. enum omap_dss_trans_key_type trans_key_type;
  303. u32 trans_key;
  304. bool trans_enabled;
  305. bool alpha_enabled;
  306. };
  307. struct omap_overlay_manager {
  308. struct kobject kobj;
  309. struct list_head list;
  310. /* static fields */
  311. const char *name;
  312. int id;
  313. enum omap_overlay_manager_caps caps;
  314. int num_overlays;
  315. struct omap_overlay **overlays;
  316. enum omap_display_type supported_displays;
  317. /* dynamic fields */
  318. struct omap_dss_device *device;
  319. struct omap_overlay_manager_info info;
  320. bool device_changed;
  321. /* if true, info has been changed but not applied() yet */
  322. bool info_dirty;
  323. int (*set_device)(struct omap_overlay_manager *mgr,
  324. struct omap_dss_device *dssdev);
  325. int (*unset_device)(struct omap_overlay_manager *mgr);
  326. int (*set_manager_info)(struct omap_overlay_manager *mgr,
  327. struct omap_overlay_manager_info *info);
  328. void (*get_manager_info)(struct omap_overlay_manager *mgr,
  329. struct omap_overlay_manager_info *info);
  330. int (*apply)(struct omap_overlay_manager *mgr);
  331. int (*wait_for_go)(struct omap_overlay_manager *mgr);
  332. int (*wait_for_vsync)(struct omap_overlay_manager *mgr);
  333. int (*enable)(struct omap_overlay_manager *mgr);
  334. int (*disable)(struct omap_overlay_manager *mgr);
  335. };
  336. struct omap_dss_device {
  337. struct device dev;
  338. enum omap_display_type type;
  339. enum omap_channel channel;
  340. union {
  341. struct {
  342. u8 data_lines;
  343. } dpi;
  344. struct {
  345. u8 channel;
  346. u8 data_lines;
  347. } rfbi;
  348. struct {
  349. u8 datapairs;
  350. } sdi;
  351. struct {
  352. u8 clk_lane;
  353. u8 clk_pol;
  354. u8 data1_lane;
  355. u8 data1_pol;
  356. u8 data2_lane;
  357. u8 data2_pol;
  358. int module;
  359. bool ext_te;
  360. u8 ext_te_gpio;
  361. } dsi;
  362. struct {
  363. enum omap_dss_venc_type type;
  364. bool invert_polarity;
  365. } venc;
  366. } phy;
  367. struct {
  368. struct {
  369. struct {
  370. u16 lck_div;
  371. u16 pck_div;
  372. enum omap_dss_clk_source lcd_clk_src;
  373. } channel;
  374. enum omap_dss_clk_source dispc_fclk_src;
  375. } dispc;
  376. struct {
  377. u16 regn;
  378. u16 regm;
  379. u16 regm_dispc;
  380. u16 regm_dsi;
  381. u16 lp_clk_div;
  382. enum omap_dss_clk_source dsi_fclk_src;
  383. } dsi;
  384. struct {
  385. u16 regn;
  386. u16 regm2;
  387. } hdmi;
  388. } clocks;
  389. struct {
  390. struct omap_video_timings timings;
  391. int acbi; /* ac-bias pin transitions per interrupt */
  392. /* Unit: line clocks */
  393. int acb; /* ac-bias pin frequency */
  394. enum omap_panel_config config;
  395. } panel;
  396. struct {
  397. u8 pixel_size;
  398. struct rfbi_timings rfbi_timings;
  399. } ctrl;
  400. int reset_gpio;
  401. int max_backlight_level;
  402. const char *name;
  403. /* used to match device to driver */
  404. const char *driver_name;
  405. void *data;
  406. struct omap_dss_driver *driver;
  407. /* helper variable for driver suspend/resume */
  408. bool activate_after_resume;
  409. enum omap_display_caps caps;
  410. struct omap_overlay_manager *manager;
  411. enum omap_dss_display_state state;
  412. /* platform specific */
  413. int (*platform_enable)(struct omap_dss_device *dssdev);
  414. void (*platform_disable)(struct omap_dss_device *dssdev);
  415. int (*set_backlight)(struct omap_dss_device *dssdev, int level);
  416. int (*get_backlight)(struct omap_dss_device *dssdev);
  417. };
  418. struct omap_dss_driver {
  419. struct device_driver driver;
  420. int (*probe)(struct omap_dss_device *);
  421. void (*remove)(struct omap_dss_device *);
  422. int (*enable)(struct omap_dss_device *display);
  423. void (*disable)(struct omap_dss_device *display);
  424. int (*suspend)(struct omap_dss_device *display);
  425. int (*resume)(struct omap_dss_device *display);
  426. int (*run_test)(struct omap_dss_device *display, int test);
  427. int (*set_update_mode)(struct omap_dss_device *dssdev,
  428. enum omap_dss_update_mode);
  429. enum omap_dss_update_mode (*get_update_mode)(
  430. struct omap_dss_device *dssdev);
  431. int (*update)(struct omap_dss_device *dssdev,
  432. u16 x, u16 y, u16 w, u16 h);
  433. int (*sync)(struct omap_dss_device *dssdev);
  434. int (*enable_te)(struct omap_dss_device *dssdev, bool enable);
  435. int (*get_te)(struct omap_dss_device *dssdev);
  436. u8 (*get_rotate)(struct omap_dss_device *dssdev);
  437. int (*set_rotate)(struct omap_dss_device *dssdev, u8 rotate);
  438. bool (*get_mirror)(struct omap_dss_device *dssdev);
  439. int (*set_mirror)(struct omap_dss_device *dssdev, bool enable);
  440. int (*memory_read)(struct omap_dss_device *dssdev,
  441. void *buf, size_t size,
  442. u16 x, u16 y, u16 w, u16 h);
  443. void (*get_resolution)(struct omap_dss_device *dssdev,
  444. u16 *xres, u16 *yres);
  445. void (*get_dimensions)(struct omap_dss_device *dssdev,
  446. u32 *width, u32 *height);
  447. int (*get_recommended_bpp)(struct omap_dss_device *dssdev);
  448. int (*check_timings)(struct omap_dss_device *dssdev,
  449. struct omap_video_timings *timings);
  450. void (*set_timings)(struct omap_dss_device *dssdev,
  451. struct omap_video_timings *timings);
  452. void (*get_timings)(struct omap_dss_device *dssdev,
  453. struct omap_video_timings *timings);
  454. int (*set_wss)(struct omap_dss_device *dssdev, u32 wss);
  455. u32 (*get_wss)(struct omap_dss_device *dssdev);
  456. };
  457. int omap_dss_register_driver(struct omap_dss_driver *);
  458. void omap_dss_unregister_driver(struct omap_dss_driver *);
  459. void omap_dss_get_device(struct omap_dss_device *dssdev);
  460. void omap_dss_put_device(struct omap_dss_device *dssdev);
  461. #define for_each_dss_dev(d) while ((d = omap_dss_get_next_device(d)) != NULL)
  462. struct omap_dss_device *omap_dss_get_next_device(struct omap_dss_device *from);
  463. struct omap_dss_device *omap_dss_find_device(void *data,
  464. int (*match)(struct omap_dss_device *dssdev, void *data));
  465. int omap_dss_start_device(struct omap_dss_device *dssdev);
  466. void omap_dss_stop_device(struct omap_dss_device *dssdev);
  467. int omap_dss_get_num_overlay_managers(void);
  468. struct omap_overlay_manager *omap_dss_get_overlay_manager(int num);
  469. int omap_dss_get_num_overlays(void);
  470. struct omap_overlay *omap_dss_get_overlay(int num);
  471. void omapdss_default_get_resolution(struct omap_dss_device *dssdev,
  472. u16 *xres, u16 *yres);
  473. int omapdss_default_get_recommended_bpp(struct omap_dss_device *dssdev);
  474. typedef void (*omap_dispc_isr_t) (void *arg, u32 mask);
  475. int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask);
  476. int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask);
  477. int omap_dispc_wait_for_irq_timeout(u32 irqmask, unsigned long timeout);
  478. int omap_dispc_wait_for_irq_interruptible_timeout(u32 irqmask,
  479. unsigned long timeout);
  480. #define to_dss_driver(x) container_of((x), struct omap_dss_driver, driver)
  481. #define to_dss_device(x) container_of((x), struct omap_dss_device, dev)
  482. void omapdss_dsi_vc_enable_hs(struct omap_dss_device *dssdev, int channel,
  483. bool enable);
  484. int omapdss_dsi_enable_te(struct omap_dss_device *dssdev, bool enable);
  485. int omap_dsi_prepare_update(struct omap_dss_device *dssdev,
  486. u16 *x, u16 *y, u16 *w, u16 *h,
  487. bool enlarge_update_area);
  488. int omap_dsi_update(struct omap_dss_device *dssdev,
  489. int channel,
  490. u16 x, u16 y, u16 w, u16 h,
  491. void (*callback)(int, void *), void *data);
  492. int omap_dsi_request_vc(struct omap_dss_device *dssdev, int *channel);
  493. int omap_dsi_set_vc_id(struct omap_dss_device *dssdev, int channel, int vc_id);
  494. void omap_dsi_release_vc(struct omap_dss_device *dssdev, int channel);
  495. int omapdss_dsi_display_enable(struct omap_dss_device *dssdev);
  496. void omapdss_dsi_display_disable(struct omap_dss_device *dssdev,
  497. bool disconnect_lanes, bool enter_ulps);
  498. int omapdss_dpi_display_enable(struct omap_dss_device *dssdev);
  499. void omapdss_dpi_display_disable(struct omap_dss_device *dssdev);
  500. void dpi_set_timings(struct omap_dss_device *dssdev,
  501. struct omap_video_timings *timings);
  502. int dpi_check_timings(struct omap_dss_device *dssdev,
  503. struct omap_video_timings *timings);
  504. int omapdss_sdi_display_enable(struct omap_dss_device *dssdev);
  505. void omapdss_sdi_display_disable(struct omap_dss_device *dssdev);
  506. int omapdss_rfbi_display_enable(struct omap_dss_device *dssdev);
  507. void omapdss_rfbi_display_disable(struct omap_dss_device *dssdev);
  508. int omap_rfbi_prepare_update(struct omap_dss_device *dssdev,
  509. u16 *x, u16 *y, u16 *w, u16 *h);
  510. int omap_rfbi_update(struct omap_dss_device *dssdev,
  511. u16 x, u16 y, u16 w, u16 h,
  512. void (*callback)(void *), void *data);
  513. #endif