stex.c 34 KB

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  1. /*
  2. * SuperTrak EX Series Storage Controller driver for Linux
  3. *
  4. * Copyright (C) 2005, 2006 Promise Technology Inc.
  5. *
  6. * This program is free software; you can redistribute it and/or
  7. * modify it under the terms of the GNU General Public License
  8. * as published by the Free Software Foundation; either version
  9. * 2 of the License, or (at your option) any later version.
  10. *
  11. * Written By:
  12. * Ed Lin <promise_linux@promise.com>
  13. *
  14. * Version: 3.0.0.1
  15. *
  16. */
  17. #include <linux/init.h>
  18. #include <linux/errno.h>
  19. #include <linux/kernel.h>
  20. #include <linux/delay.h>
  21. #include <linux/sched.h>
  22. #include <linux/time.h>
  23. #include <linux/pci.h>
  24. #include <linux/blkdev.h>
  25. #include <linux/interrupt.h>
  26. #include <linux/types.h>
  27. #include <linux/module.h>
  28. #include <linux/spinlock.h>
  29. #include <asm/io.h>
  30. #include <asm/irq.h>
  31. #include <asm/byteorder.h>
  32. #include <scsi/scsi.h>
  33. #include <scsi/scsi_device.h>
  34. #include <scsi/scsi_cmnd.h>
  35. #include <scsi/scsi_host.h>
  36. #include <scsi/scsi_tcq.h>
  37. #define DRV_NAME "stex"
  38. #define ST_DRIVER_VERSION "3.0.0.1"
  39. #define ST_VER_MAJOR 3
  40. #define ST_VER_MINOR 0
  41. #define ST_OEM 0
  42. #define ST_BUILD_VER 1
  43. enum {
  44. /* MU register offset */
  45. IMR0 = 0x10, /* MU_INBOUND_MESSAGE_REG0 */
  46. IMR1 = 0x14, /* MU_INBOUND_MESSAGE_REG1 */
  47. OMR0 = 0x18, /* MU_OUTBOUND_MESSAGE_REG0 */
  48. OMR1 = 0x1c, /* MU_OUTBOUND_MESSAGE_REG1 */
  49. IDBL = 0x20, /* MU_INBOUND_DOORBELL */
  50. IIS = 0x24, /* MU_INBOUND_INTERRUPT_STATUS */
  51. IIM = 0x28, /* MU_INBOUND_INTERRUPT_MASK */
  52. ODBL = 0x2c, /* MU_OUTBOUND_DOORBELL */
  53. OIS = 0x30, /* MU_OUTBOUND_INTERRUPT_STATUS */
  54. OIM = 0x3c, /* MU_OUTBOUND_INTERRUPT_MASK */
  55. /* MU register value */
  56. MU_INBOUND_DOORBELL_HANDSHAKE = 1,
  57. MU_INBOUND_DOORBELL_REQHEADCHANGED = 2,
  58. MU_INBOUND_DOORBELL_STATUSTAILCHANGED = 4,
  59. MU_INBOUND_DOORBELL_HMUSTOPPED = 8,
  60. MU_INBOUND_DOORBELL_RESET = 16,
  61. MU_OUTBOUND_DOORBELL_HANDSHAKE = 1,
  62. MU_OUTBOUND_DOORBELL_REQUESTTAILCHANGED = 2,
  63. MU_OUTBOUND_DOORBELL_STATUSHEADCHANGED = 4,
  64. MU_OUTBOUND_DOORBELL_BUSCHANGE = 8,
  65. MU_OUTBOUND_DOORBELL_HASEVENT = 16,
  66. /* MU status code */
  67. MU_STATE_STARTING = 1,
  68. MU_STATE_FMU_READY_FOR_HANDSHAKE = 2,
  69. MU_STATE_SEND_HANDSHAKE_FRAME = 3,
  70. MU_STATE_STARTED = 4,
  71. MU_STATE_RESETTING = 5,
  72. MU_MAX_DELAY = 120,
  73. MU_HANDSHAKE_SIGNATURE = 0x55aaaa55,
  74. MU_HANDSHAKE_SIGNATURE_HALF = 0x5a5a0000,
  75. MU_HARD_RESET_WAIT = 30000,
  76. HMU_PARTNER_TYPE = 2,
  77. /* firmware returned values */
  78. SRB_STATUS_SUCCESS = 0x01,
  79. SRB_STATUS_ERROR = 0x04,
  80. SRB_STATUS_BUSY = 0x05,
  81. SRB_STATUS_INVALID_REQUEST = 0x06,
  82. SRB_STATUS_SELECTION_TIMEOUT = 0x0A,
  83. SRB_SEE_SENSE = 0x80,
  84. /* task attribute */
  85. TASK_ATTRIBUTE_SIMPLE = 0x0,
  86. TASK_ATTRIBUTE_HEADOFQUEUE = 0x1,
  87. TASK_ATTRIBUTE_ORDERED = 0x2,
  88. TASK_ATTRIBUTE_ACA = 0x4,
  89. /* request count, etc. */
  90. MU_MAX_REQUEST = 32,
  91. /* one message wasted, use MU_MAX_REQUEST+1
  92. to handle MU_MAX_REQUEST messages */
  93. MU_REQ_COUNT = (MU_MAX_REQUEST + 1),
  94. MU_STATUS_COUNT = (MU_MAX_REQUEST + 1),
  95. STEX_CDB_LENGTH = MAX_COMMAND_SIZE,
  96. REQ_VARIABLE_LEN = 1024,
  97. STATUS_VAR_LEN = 128,
  98. ST_CAN_QUEUE = MU_MAX_REQUEST,
  99. ST_CMD_PER_LUN = MU_MAX_REQUEST,
  100. ST_MAX_SG = 32,
  101. /* sg flags */
  102. SG_CF_EOT = 0x80, /* end of table */
  103. SG_CF_64B = 0x40, /* 64 bit item */
  104. SG_CF_HOST = 0x20, /* sg in host memory */
  105. ST_MAX_ARRAY_SUPPORTED = 16,
  106. ST_MAX_TARGET_NUM = (ST_MAX_ARRAY_SUPPORTED+1),
  107. ST_MAX_LUN_PER_TARGET = 16,
  108. st_shasta = 0,
  109. st_vsc = 1,
  110. st_vsc1 = 2,
  111. st_yosemite = 3,
  112. PASSTHRU_REQ_TYPE = 0x00000001,
  113. PASSTHRU_REQ_NO_WAKEUP = 0x00000100,
  114. ST_INTERNAL_TIMEOUT = 30,
  115. ST_TO_CMD = 0,
  116. ST_FROM_CMD = 1,
  117. /* vendor specific commands of Promise */
  118. MGT_CMD = 0xd8,
  119. SINBAND_MGT_CMD = 0xd9,
  120. ARRAY_CMD = 0xe0,
  121. CONTROLLER_CMD = 0xe1,
  122. DEBUGGING_CMD = 0xe2,
  123. PASSTHRU_CMD = 0xe3,
  124. PASSTHRU_GET_ADAPTER = 0x05,
  125. PASSTHRU_GET_DRVVER = 0x10,
  126. CTLR_CONFIG_CMD = 0x03,
  127. CTLR_SHUTDOWN = 0x0d,
  128. CTLR_POWER_STATE_CHANGE = 0x0e,
  129. CTLR_POWER_SAVING = 0x01,
  130. PASSTHRU_SIGNATURE = 0x4e415041,
  131. MGT_CMD_SIGNATURE = 0xba,
  132. INQUIRY_EVPD = 0x01,
  133. ST_ADDITIONAL_MEM = 0x200000,
  134. };
  135. /* SCSI inquiry data */
  136. typedef struct st_inq {
  137. u8 DeviceType :5;
  138. u8 DeviceTypeQualifier :3;
  139. u8 DeviceTypeModifier :7;
  140. u8 RemovableMedia :1;
  141. u8 Versions;
  142. u8 ResponseDataFormat :4;
  143. u8 HiSupport :1;
  144. u8 NormACA :1;
  145. u8 ReservedBit :1;
  146. u8 AERC :1;
  147. u8 AdditionalLength;
  148. u8 Reserved[2];
  149. u8 SoftReset :1;
  150. u8 CommandQueue :1;
  151. u8 Reserved2 :1;
  152. u8 LinkedCommands :1;
  153. u8 Synchronous :1;
  154. u8 Wide16Bit :1;
  155. u8 Wide32Bit :1;
  156. u8 RelativeAddressing :1;
  157. u8 VendorId[8];
  158. u8 ProductId[16];
  159. u8 ProductRevisionLevel[4];
  160. u8 VendorSpecific[20];
  161. u8 Reserved3[40];
  162. } ST_INQ;
  163. struct st_sgitem {
  164. u8 ctrl; /* SG_CF_xxx */
  165. u8 reserved[3];
  166. __le32 count;
  167. __le32 addr;
  168. __le32 addr_hi;
  169. };
  170. struct st_sgtable {
  171. __le16 sg_count;
  172. __le16 max_sg_count;
  173. __le32 sz_in_byte;
  174. struct st_sgitem table[ST_MAX_SG];
  175. };
  176. struct handshake_frame {
  177. __le32 rb_phy; /* request payload queue physical address */
  178. __le32 rb_phy_hi;
  179. __le16 req_sz; /* size of each request payload */
  180. __le16 req_cnt; /* count of reqs the buffer can hold */
  181. __le16 status_sz; /* size of each status payload */
  182. __le16 status_cnt; /* count of status the buffer can hold */
  183. __le32 hosttime; /* seconds from Jan 1, 1970 (GMT) */
  184. __le32 hosttime_hi;
  185. u8 partner_type; /* who sends this frame */
  186. u8 reserved0[7];
  187. __le32 partner_ver_major;
  188. __le32 partner_ver_minor;
  189. __le32 partner_ver_oem;
  190. __le32 partner_ver_build;
  191. __le32 extra_offset; /* NEW */
  192. __le32 extra_size; /* NEW */
  193. u32 reserved1[2];
  194. };
  195. struct req_msg {
  196. __le16 tag;
  197. u8 lun;
  198. u8 target;
  199. u8 task_attr;
  200. u8 task_manage;
  201. u8 prd_entry;
  202. u8 payload_sz; /* payload size in 4-byte, not used */
  203. u8 cdb[STEX_CDB_LENGTH];
  204. u8 variable[REQ_VARIABLE_LEN];
  205. };
  206. struct status_msg {
  207. __le16 tag;
  208. u8 lun;
  209. u8 target;
  210. u8 srb_status;
  211. u8 scsi_status;
  212. u8 reserved;
  213. u8 payload_sz; /* payload size in 4-byte */
  214. u8 variable[STATUS_VAR_LEN];
  215. };
  216. struct ver_info {
  217. u32 major;
  218. u32 minor;
  219. u32 oem;
  220. u32 build;
  221. u32 reserved[2];
  222. };
  223. struct st_frame {
  224. u32 base[6];
  225. u32 rom_addr;
  226. struct ver_info drv_ver;
  227. struct ver_info bios_ver;
  228. u32 bus;
  229. u32 slot;
  230. u32 irq_level;
  231. u32 irq_vec;
  232. u32 id;
  233. u32 subid;
  234. u32 dimm_size;
  235. u8 dimm_type;
  236. u8 reserved[3];
  237. u32 channel;
  238. u32 reserved1;
  239. };
  240. struct st_drvver {
  241. u32 major;
  242. u32 minor;
  243. u32 oem;
  244. u32 build;
  245. u32 signature[2];
  246. u8 console_id;
  247. u8 host_no;
  248. u8 reserved0[2];
  249. u32 reserved[3];
  250. };
  251. #define MU_REQ_BUFFER_SIZE (MU_REQ_COUNT * sizeof(struct req_msg))
  252. #define MU_STATUS_BUFFER_SIZE (MU_STATUS_COUNT * sizeof(struct status_msg))
  253. #define MU_BUFFER_SIZE (MU_REQ_BUFFER_SIZE + MU_STATUS_BUFFER_SIZE)
  254. #define STEX_EXTRA_SIZE max(sizeof(struct st_frame), sizeof(ST_INQ))
  255. #define STEX_BUFFER_SIZE (MU_BUFFER_SIZE + STEX_EXTRA_SIZE)
  256. struct st_ccb {
  257. struct req_msg *req;
  258. struct scsi_cmnd *cmd;
  259. void *sense_buffer;
  260. unsigned int sense_bufflen;
  261. int sg_count;
  262. u32 req_type;
  263. u8 srb_status;
  264. u8 scsi_status;
  265. };
  266. struct st_hba {
  267. void __iomem *mmio_base; /* iomapped PCI memory space */
  268. void *dma_mem;
  269. dma_addr_t dma_handle;
  270. size_t dma_size;
  271. struct Scsi_Host *host;
  272. struct pci_dev *pdev;
  273. u32 req_head;
  274. u32 req_tail;
  275. u32 status_head;
  276. u32 status_tail;
  277. struct status_msg *status_buffer;
  278. void *copy_buffer; /* temp buffer for driver-handled commands */
  279. struct st_ccb ccb[MU_MAX_REQUEST];
  280. struct st_ccb *wait_ccb;
  281. wait_queue_head_t waitq;
  282. unsigned int mu_status;
  283. int out_req_cnt;
  284. unsigned int cardtype;
  285. };
  286. static const char console_inq_page[] =
  287. {
  288. 0x03,0x00,0x03,0x03,0xFA,0x00,0x00,0x30,
  289. 0x50,0x72,0x6F,0x6D,0x69,0x73,0x65,0x20, /* "Promise " */
  290. 0x52,0x41,0x49,0x44,0x20,0x43,0x6F,0x6E, /* "RAID Con" */
  291. 0x73,0x6F,0x6C,0x65,0x20,0x20,0x20,0x20, /* "sole " */
  292. 0x31,0x2E,0x30,0x30,0x20,0x20,0x20,0x20, /* "1.00 " */
  293. 0x53,0x58,0x2F,0x52,0x53,0x41,0x46,0x2D, /* "SX/RSAF-" */
  294. 0x54,0x45,0x31,0x2E,0x30,0x30,0x20,0x20, /* "TE1.00 " */
  295. 0x0C,0x20,0x20,0x20,0x20,0x20,0x20,0x20
  296. };
  297. MODULE_AUTHOR("Ed Lin");
  298. MODULE_DESCRIPTION("Promise Technology SuperTrak EX Controllers");
  299. MODULE_LICENSE("GPL");
  300. MODULE_VERSION(ST_DRIVER_VERSION);
  301. static void stex_gettime(__le32 *time)
  302. {
  303. struct timeval tv;
  304. do_gettimeofday(&tv);
  305. *time = cpu_to_le32(tv.tv_sec & 0xffffffff);
  306. *(time + 1) = cpu_to_le32((tv.tv_sec >> 16) >> 16);
  307. }
  308. static struct status_msg *stex_get_status(struct st_hba *hba)
  309. {
  310. struct status_msg *status =
  311. hba->status_buffer + hba->status_tail;
  312. ++hba->status_tail;
  313. hba->status_tail %= MU_STATUS_COUNT;
  314. return status;
  315. }
  316. static void stex_set_sense(struct scsi_cmnd *cmd, u8 sk, u8 asc, u8 ascq)
  317. {
  318. cmd->result = (DRIVER_SENSE << 24) | SAM_STAT_CHECK_CONDITION;
  319. cmd->sense_buffer[0] = 0x70; /* fixed format, current */
  320. cmd->sense_buffer[2] = sk;
  321. cmd->sense_buffer[7] = 18 - 8; /* additional sense length */
  322. cmd->sense_buffer[12] = asc;
  323. cmd->sense_buffer[13] = ascq;
  324. }
  325. static void stex_invalid_field(struct scsi_cmnd *cmd,
  326. void (*done)(struct scsi_cmnd *))
  327. {
  328. /* "Invalid field in cbd" */
  329. stex_set_sense(cmd, ILLEGAL_REQUEST, 0x24, 0x0);
  330. done(cmd);
  331. }
  332. static struct req_msg *stex_alloc_req(struct st_hba *hba)
  333. {
  334. struct req_msg *req = ((struct req_msg *)hba->dma_mem) +
  335. hba->req_head;
  336. ++hba->req_head;
  337. hba->req_head %= MU_REQ_COUNT;
  338. return req;
  339. }
  340. static int stex_map_sg(struct st_hba *hba,
  341. struct req_msg *req, struct st_ccb *ccb)
  342. {
  343. struct pci_dev *pdev = hba->pdev;
  344. struct scsi_cmnd *cmd;
  345. dma_addr_t dma_handle;
  346. struct scatterlist *src;
  347. struct st_sgtable *dst;
  348. int i;
  349. cmd = ccb->cmd;
  350. dst = (struct st_sgtable *)req->variable;
  351. dst->max_sg_count = cpu_to_le16(ST_MAX_SG);
  352. dst->sz_in_byte = cpu_to_le32(cmd->request_bufflen);
  353. if (cmd->use_sg) {
  354. int n_elem;
  355. src = (struct scatterlist *) cmd->request_buffer;
  356. n_elem = pci_map_sg(pdev, src,
  357. cmd->use_sg, cmd->sc_data_direction);
  358. if (n_elem <= 0)
  359. return -EIO;
  360. ccb->sg_count = n_elem;
  361. dst->sg_count = cpu_to_le16((u16)n_elem);
  362. for (i = 0; i < n_elem; i++, src++) {
  363. dst->table[i].count = cpu_to_le32((u32)sg_dma_len(src));
  364. dst->table[i].addr =
  365. cpu_to_le32(sg_dma_address(src) & 0xffffffff);
  366. dst->table[i].addr_hi =
  367. cpu_to_le32((sg_dma_address(src) >> 16) >> 16);
  368. dst->table[i].ctrl = SG_CF_64B | SG_CF_HOST;
  369. }
  370. dst->table[--i].ctrl |= SG_CF_EOT;
  371. return 0;
  372. }
  373. dma_handle = pci_map_single(pdev, cmd->request_buffer,
  374. cmd->request_bufflen, cmd->sc_data_direction);
  375. cmd->SCp.dma_handle = dma_handle;
  376. ccb->sg_count = 1;
  377. dst->sg_count = cpu_to_le16(1);
  378. dst->table[0].addr = cpu_to_le32(dma_handle & 0xffffffff);
  379. dst->table[0].addr_hi = cpu_to_le32((dma_handle >> 16) >> 16);
  380. dst->table[0].count = cpu_to_le32((u32)cmd->request_bufflen);
  381. dst->table[0].ctrl = SG_CF_EOT | SG_CF_64B | SG_CF_HOST;
  382. return 0;
  383. }
  384. static void stex_internal_copy(struct scsi_cmnd *cmd,
  385. const void *src, size_t *count, int sg_count, int direction)
  386. {
  387. size_t lcount;
  388. size_t len;
  389. void *s, *d, *base = NULL;
  390. if (*count > cmd->request_bufflen)
  391. *count = cmd->request_bufflen;
  392. lcount = *count;
  393. while (lcount) {
  394. len = lcount;
  395. s = (void *)src;
  396. if (cmd->use_sg) {
  397. size_t offset = *count - lcount;
  398. s += offset;
  399. base = scsi_kmap_atomic_sg(cmd->request_buffer,
  400. sg_count, &offset, &len);
  401. if (base == NULL) {
  402. *count -= lcount;
  403. return;
  404. }
  405. d = base + offset;
  406. } else
  407. d = cmd->request_buffer;
  408. if (direction == ST_TO_CMD)
  409. memcpy(d, s, len);
  410. else
  411. memcpy(s, d, len);
  412. lcount -= len;
  413. if (cmd->use_sg)
  414. scsi_kunmap_atomic_sg(base);
  415. }
  416. }
  417. static int stex_direct_copy(struct scsi_cmnd *cmd,
  418. const void *src, size_t count)
  419. {
  420. struct st_hba *hba = (struct st_hba *) &cmd->device->host->hostdata[0];
  421. size_t cp_len = count;
  422. int n_elem = 0;
  423. if (cmd->use_sg) {
  424. n_elem = pci_map_sg(hba->pdev, cmd->request_buffer,
  425. cmd->use_sg, cmd->sc_data_direction);
  426. if (n_elem <= 0)
  427. return 0;
  428. }
  429. stex_internal_copy(cmd, src, &cp_len, n_elem, ST_TO_CMD);
  430. if (cmd->use_sg)
  431. pci_unmap_sg(hba->pdev, cmd->request_buffer,
  432. cmd->use_sg, cmd->sc_data_direction);
  433. return cp_len == count;
  434. }
  435. static void stex_controller_info(struct st_hba *hba, struct st_ccb *ccb)
  436. {
  437. struct st_frame *p;
  438. size_t count = sizeof(struct st_frame);
  439. p = hba->copy_buffer;
  440. stex_internal_copy(ccb->cmd, p, &count, ccb->sg_count, ST_FROM_CMD);
  441. memset(p->base, 0, sizeof(u32)*6);
  442. *(unsigned long *)(p->base) = pci_resource_start(hba->pdev, 0);
  443. p->rom_addr = 0;
  444. p->drv_ver.major = ST_VER_MAJOR;
  445. p->drv_ver.minor = ST_VER_MINOR;
  446. p->drv_ver.oem = ST_OEM;
  447. p->drv_ver.build = ST_BUILD_VER;
  448. p->bus = hba->pdev->bus->number;
  449. p->slot = hba->pdev->devfn;
  450. p->irq_level = 0;
  451. p->irq_vec = hba->pdev->irq;
  452. p->id = hba->pdev->vendor << 16 | hba->pdev->device;
  453. p->subid =
  454. hba->pdev->subsystem_vendor << 16 | hba->pdev->subsystem_device;
  455. stex_internal_copy(ccb->cmd, p, &count, ccb->sg_count, ST_TO_CMD);
  456. }
  457. static void
  458. stex_send_cmd(struct st_hba *hba, struct req_msg *req, u16 tag)
  459. {
  460. req->tag = cpu_to_le16(tag);
  461. req->task_attr = TASK_ATTRIBUTE_SIMPLE;
  462. req->task_manage = 0; /* not supported yet */
  463. hba->ccb[tag].req = req;
  464. hba->out_req_cnt++;
  465. writel(hba->req_head, hba->mmio_base + IMR0);
  466. writel(MU_INBOUND_DOORBELL_REQHEADCHANGED, hba->mmio_base + IDBL);
  467. readl(hba->mmio_base + IDBL); /* flush */
  468. }
  469. static int
  470. stex_slave_alloc(struct scsi_device *sdev)
  471. {
  472. /* Cheat: usually extracted from Inquiry data */
  473. sdev->tagged_supported = 1;
  474. scsi_activate_tcq(sdev, sdev->host->can_queue);
  475. return 0;
  476. }
  477. static int
  478. stex_slave_config(struct scsi_device *sdev)
  479. {
  480. sdev->use_10_for_rw = 1;
  481. sdev->use_10_for_ms = 1;
  482. sdev->timeout = 60 * HZ;
  483. sdev->tagged_supported = 1;
  484. return 0;
  485. }
  486. static void
  487. stex_slave_destroy(struct scsi_device *sdev)
  488. {
  489. scsi_deactivate_tcq(sdev, 1);
  490. }
  491. static int
  492. stex_queuecommand(struct scsi_cmnd *cmd, void (* done)(struct scsi_cmnd *))
  493. {
  494. struct st_hba *hba;
  495. struct Scsi_Host *host;
  496. unsigned int id,lun;
  497. struct req_msg *req;
  498. u16 tag;
  499. host = cmd->device->host;
  500. id = cmd->device->id;
  501. lun = cmd->device->channel; /* firmware lun issue work around */
  502. hba = (struct st_hba *) &host->hostdata[0];
  503. switch (cmd->cmnd[0]) {
  504. case MODE_SENSE_10:
  505. {
  506. static char ms10_caching_page[12] =
  507. { 0, 0x12, 0, 0, 0, 0, 0, 0, 0x8, 0xa, 0x4, 0 };
  508. unsigned char page;
  509. page = cmd->cmnd[2] & 0x3f;
  510. if (page == 0x8 || page == 0x3f) {
  511. stex_direct_copy(cmd, ms10_caching_page,
  512. sizeof(ms10_caching_page));
  513. cmd->result = DID_OK << 16 | COMMAND_COMPLETE << 8;
  514. done(cmd);
  515. } else
  516. stex_invalid_field(cmd, done);
  517. return 0;
  518. }
  519. case INQUIRY:
  520. if (id != ST_MAX_ARRAY_SUPPORTED)
  521. break;
  522. if (lun == 0 && (cmd->cmnd[1] & INQUIRY_EVPD) == 0) {
  523. stex_direct_copy(cmd, console_inq_page,
  524. sizeof(console_inq_page));
  525. cmd->result = DID_OK << 16 | COMMAND_COMPLETE << 8;
  526. done(cmd);
  527. } else
  528. stex_invalid_field(cmd, done);
  529. return 0;
  530. case PASSTHRU_CMD:
  531. if (cmd->cmnd[1] == PASSTHRU_GET_DRVVER) {
  532. struct st_drvver ver;
  533. ver.major = ST_VER_MAJOR;
  534. ver.minor = ST_VER_MINOR;
  535. ver.oem = ST_OEM;
  536. ver.build = ST_BUILD_VER;
  537. ver.signature[0] = PASSTHRU_SIGNATURE;
  538. ver.console_id = ST_MAX_ARRAY_SUPPORTED;
  539. ver.host_no = hba->host->host_no;
  540. cmd->result = stex_direct_copy(cmd, &ver, sizeof(ver)) ?
  541. DID_OK << 16 | COMMAND_COMPLETE << 8 :
  542. DID_ERROR << 16 | COMMAND_COMPLETE << 8;
  543. done(cmd);
  544. return 0;
  545. }
  546. default:
  547. break;
  548. }
  549. cmd->scsi_done = done;
  550. tag = cmd->request->tag;
  551. if (unlikely(tag >= host->can_queue))
  552. return SCSI_MLQUEUE_HOST_BUSY;
  553. req = stex_alloc_req(hba);
  554. if (hba->cardtype == st_yosemite) {
  555. req->lun = lun * (ST_MAX_TARGET_NUM - 1) + id;
  556. req->target = 0;
  557. } else {
  558. req->lun = lun;
  559. req->target = id;
  560. }
  561. /* cdb */
  562. memcpy(req->cdb, cmd->cmnd, STEX_CDB_LENGTH);
  563. hba->ccb[tag].cmd = cmd;
  564. hba->ccb[tag].sense_bufflen = SCSI_SENSE_BUFFERSIZE;
  565. hba->ccb[tag].sense_buffer = cmd->sense_buffer;
  566. hba->ccb[tag].req_type = 0;
  567. if (cmd->sc_data_direction != DMA_NONE)
  568. stex_map_sg(hba, req, &hba->ccb[tag]);
  569. stex_send_cmd(hba, req, tag);
  570. return 0;
  571. }
  572. static void stex_unmap_sg(struct st_hba *hba, struct scsi_cmnd *cmd)
  573. {
  574. if (cmd->sc_data_direction != DMA_NONE) {
  575. if (cmd->use_sg)
  576. pci_unmap_sg(hba->pdev, cmd->request_buffer,
  577. cmd->use_sg, cmd->sc_data_direction);
  578. else
  579. pci_unmap_single(hba->pdev, cmd->SCp.dma_handle,
  580. cmd->request_bufflen, cmd->sc_data_direction);
  581. }
  582. }
  583. static void stex_scsi_done(struct st_ccb *ccb)
  584. {
  585. struct scsi_cmnd *cmd = ccb->cmd;
  586. int result;
  587. if (ccb->srb_status == SRB_STATUS_SUCCESS || ccb->srb_status == 0) {
  588. result = ccb->scsi_status;
  589. switch (ccb->scsi_status) {
  590. case SAM_STAT_GOOD:
  591. result |= DID_OK << 16 | COMMAND_COMPLETE << 8;
  592. break;
  593. case SAM_STAT_CHECK_CONDITION:
  594. result |= DRIVER_SENSE << 24;
  595. break;
  596. case SAM_STAT_BUSY:
  597. result |= DID_BUS_BUSY << 16 | COMMAND_COMPLETE << 8;
  598. break;
  599. default:
  600. result |= DID_ERROR << 16 | COMMAND_COMPLETE << 8;
  601. break;
  602. }
  603. }
  604. else if (ccb->srb_status & SRB_SEE_SENSE)
  605. result = DRIVER_SENSE << 24 | SAM_STAT_CHECK_CONDITION;
  606. else switch (ccb->srb_status) {
  607. case SRB_STATUS_SELECTION_TIMEOUT:
  608. result = DID_NO_CONNECT << 16 | COMMAND_COMPLETE << 8;
  609. break;
  610. case SRB_STATUS_BUSY:
  611. result = DID_BUS_BUSY << 16 | COMMAND_COMPLETE << 8;
  612. break;
  613. case SRB_STATUS_INVALID_REQUEST:
  614. case SRB_STATUS_ERROR:
  615. default:
  616. result = DID_ERROR << 16 | COMMAND_COMPLETE << 8;
  617. break;
  618. }
  619. cmd->result = result;
  620. cmd->scsi_done(cmd);
  621. }
  622. static void stex_copy_data(struct st_ccb *ccb,
  623. struct status_msg *resp, unsigned int variable)
  624. {
  625. size_t count = variable;
  626. if (resp->scsi_status != SAM_STAT_GOOD) {
  627. if (ccb->sense_buffer != NULL)
  628. memcpy(ccb->sense_buffer, resp->variable,
  629. min(variable, ccb->sense_bufflen));
  630. return;
  631. }
  632. if (ccb->cmd == NULL)
  633. return;
  634. stex_internal_copy(ccb->cmd,
  635. resp->variable, &count, ccb->sg_count, ST_TO_CMD);
  636. }
  637. static void stex_ys_commands(struct st_hba *hba,
  638. struct st_ccb *ccb, struct status_msg *resp)
  639. {
  640. size_t count;
  641. if (ccb->cmd->cmnd[0] == MGT_CMD &&
  642. resp->scsi_status != SAM_STAT_CHECK_CONDITION) {
  643. ccb->cmd->request_bufflen =
  644. le32_to_cpu(*(__le32 *)&resp->variable[0]);
  645. return;
  646. }
  647. if (resp->srb_status != 0)
  648. return;
  649. /* determine inquiry command status by DeviceTypeQualifier */
  650. if (ccb->cmd->cmnd[0] == INQUIRY &&
  651. resp->scsi_status == SAM_STAT_GOOD) {
  652. ST_INQ *inq_data;
  653. count = STEX_EXTRA_SIZE;
  654. stex_internal_copy(ccb->cmd, hba->copy_buffer,
  655. &count, ccb->sg_count, ST_FROM_CMD);
  656. inq_data = (ST_INQ *)hba->copy_buffer;
  657. if (inq_data->DeviceTypeQualifier != 0)
  658. ccb->srb_status = SRB_STATUS_SELECTION_TIMEOUT;
  659. else
  660. ccb->srb_status = SRB_STATUS_SUCCESS;
  661. } else if (ccb->cmd->cmnd[0] == REPORT_LUNS) {
  662. u8 *report_lun_data = (u8 *)hba->copy_buffer;
  663. count = STEX_EXTRA_SIZE;
  664. stex_internal_copy(ccb->cmd, report_lun_data,
  665. &count, ccb->sg_count, ST_FROM_CMD);
  666. if (report_lun_data[2] || report_lun_data[3]) {
  667. report_lun_data[2] = 0x00;
  668. report_lun_data[3] = 0x08;
  669. stex_internal_copy(ccb->cmd, report_lun_data,
  670. &count, ccb->sg_count, ST_TO_CMD);
  671. }
  672. }
  673. }
  674. static void stex_mu_intr(struct st_hba *hba, u32 doorbell)
  675. {
  676. void __iomem *base = hba->mmio_base;
  677. struct status_msg *resp;
  678. struct st_ccb *ccb;
  679. unsigned int size;
  680. u16 tag;
  681. if (!(doorbell & MU_OUTBOUND_DOORBELL_STATUSHEADCHANGED))
  682. return;
  683. /* status payloads */
  684. hba->status_head = readl(base + OMR1);
  685. if (unlikely(hba->status_head >= MU_STATUS_COUNT)) {
  686. printk(KERN_WARNING DRV_NAME "(%s): invalid status head\n",
  687. pci_name(hba->pdev));
  688. return;
  689. }
  690. /*
  691. * it's not a valid status payload if:
  692. * 1. there are no pending requests(e.g. during init stage)
  693. * 2. there are some pending requests, but the controller is in
  694. * reset status, and its type is not st_yosemite
  695. * firmware of st_yosemite in reset status will return pending requests
  696. * to driver, so we allow it to pass
  697. */
  698. if (unlikely(hba->out_req_cnt <= 0 ||
  699. (hba->mu_status == MU_STATE_RESETTING &&
  700. hba->cardtype != st_yosemite))) {
  701. hba->status_tail = hba->status_head;
  702. goto update_status;
  703. }
  704. while (hba->status_tail != hba->status_head) {
  705. resp = stex_get_status(hba);
  706. tag = le16_to_cpu(resp->tag);
  707. if (unlikely(tag >= hba->host->can_queue)) {
  708. printk(KERN_WARNING DRV_NAME
  709. "(%s): invalid tag\n", pci_name(hba->pdev));
  710. continue;
  711. }
  712. ccb = &hba->ccb[tag];
  713. if (hba->wait_ccb == ccb)
  714. hba->wait_ccb = NULL;
  715. if (unlikely(ccb->req == NULL)) {
  716. printk(KERN_WARNING DRV_NAME
  717. "(%s): lagging req\n", pci_name(hba->pdev));
  718. hba->out_req_cnt--;
  719. continue;
  720. }
  721. size = resp->payload_sz * sizeof(u32); /* payload size */
  722. if (unlikely(size < sizeof(*resp) - STATUS_VAR_LEN ||
  723. size > sizeof(*resp))) {
  724. printk(KERN_WARNING DRV_NAME "(%s): bad status size\n",
  725. pci_name(hba->pdev));
  726. } else {
  727. size -= sizeof(*resp) - STATUS_VAR_LEN; /* copy size */
  728. if (size)
  729. stex_copy_data(ccb, resp, size);
  730. }
  731. ccb->srb_status = resp->srb_status;
  732. ccb->scsi_status = resp->scsi_status;
  733. if (likely(ccb->cmd != NULL)) {
  734. if (hba->cardtype == st_yosemite)
  735. stex_ys_commands(hba, ccb, resp);
  736. if (unlikely(ccb->cmd->cmnd[0] == PASSTHRU_CMD &&
  737. ccb->cmd->cmnd[1] == PASSTHRU_GET_ADAPTER))
  738. stex_controller_info(hba, ccb);
  739. stex_unmap_sg(hba, ccb->cmd);
  740. stex_scsi_done(ccb);
  741. hba->out_req_cnt--;
  742. } else if (ccb->req_type & PASSTHRU_REQ_TYPE) {
  743. hba->out_req_cnt--;
  744. if (ccb->req_type & PASSTHRU_REQ_NO_WAKEUP) {
  745. ccb->req_type = 0;
  746. continue;
  747. }
  748. ccb->req_type = 0;
  749. if (waitqueue_active(&hba->waitq))
  750. wake_up(&hba->waitq);
  751. }
  752. }
  753. update_status:
  754. writel(hba->status_head, base + IMR1);
  755. readl(base + IMR1); /* flush */
  756. }
  757. static irqreturn_t stex_intr(int irq, void *__hba)
  758. {
  759. struct st_hba *hba = __hba;
  760. void __iomem *base = hba->mmio_base;
  761. u32 data;
  762. unsigned long flags;
  763. int handled = 0;
  764. spin_lock_irqsave(hba->host->host_lock, flags);
  765. data = readl(base + ODBL);
  766. if (data && data != 0xffffffff) {
  767. /* clear the interrupt */
  768. writel(data, base + ODBL);
  769. readl(base + ODBL); /* flush */
  770. stex_mu_intr(hba, data);
  771. handled = 1;
  772. }
  773. spin_unlock_irqrestore(hba->host->host_lock, flags);
  774. return IRQ_RETVAL(handled);
  775. }
  776. static int stex_handshake(struct st_hba *hba)
  777. {
  778. void __iomem *base = hba->mmio_base;
  779. struct handshake_frame *h;
  780. dma_addr_t status_phys;
  781. u32 data;
  782. unsigned long before;
  783. if (readl(base + OMR0) != MU_HANDSHAKE_SIGNATURE) {
  784. writel(MU_INBOUND_DOORBELL_HANDSHAKE, base + IDBL);
  785. readl(base + IDBL);
  786. before = jiffies;
  787. while (readl(base + OMR0) != MU_HANDSHAKE_SIGNATURE) {
  788. if (time_after(jiffies, before + MU_MAX_DELAY * HZ)) {
  789. printk(KERN_ERR DRV_NAME
  790. "(%s): no handshake signature\n",
  791. pci_name(hba->pdev));
  792. return -1;
  793. }
  794. rmb();
  795. msleep(1);
  796. }
  797. }
  798. udelay(10);
  799. data = readl(base + OMR1);
  800. if ((data & 0xffff0000) == MU_HANDSHAKE_SIGNATURE_HALF) {
  801. data &= 0x0000ffff;
  802. if (hba->host->can_queue > data)
  803. hba->host->can_queue = data;
  804. }
  805. h = (struct handshake_frame *)(hba->dma_mem + MU_REQ_BUFFER_SIZE);
  806. h->rb_phy = cpu_to_le32(hba->dma_handle);
  807. h->rb_phy_hi = cpu_to_le32((hba->dma_handle >> 16) >> 16);
  808. h->req_sz = cpu_to_le16(sizeof(struct req_msg));
  809. h->req_cnt = cpu_to_le16(MU_REQ_COUNT);
  810. h->status_sz = cpu_to_le16(sizeof(struct status_msg));
  811. h->status_cnt = cpu_to_le16(MU_STATUS_COUNT);
  812. stex_gettime(&h->hosttime);
  813. h->partner_type = HMU_PARTNER_TYPE;
  814. if (hba->dma_size > STEX_BUFFER_SIZE) {
  815. h->extra_offset = cpu_to_le32(STEX_BUFFER_SIZE);
  816. h->extra_size = cpu_to_le32(ST_ADDITIONAL_MEM);
  817. } else
  818. h->extra_offset = h->extra_size = 0;
  819. status_phys = hba->dma_handle + MU_REQ_BUFFER_SIZE;
  820. writel(status_phys, base + IMR0);
  821. readl(base + IMR0);
  822. writel((status_phys >> 16) >> 16, base + IMR1);
  823. readl(base + IMR1);
  824. writel((status_phys >> 16) >> 16, base + OMR0); /* old fw compatible */
  825. readl(base + OMR0);
  826. writel(MU_INBOUND_DOORBELL_HANDSHAKE, base + IDBL);
  827. readl(base + IDBL); /* flush */
  828. udelay(10);
  829. before = jiffies;
  830. while (readl(base + OMR0) != MU_HANDSHAKE_SIGNATURE) {
  831. if (time_after(jiffies, before + MU_MAX_DELAY * HZ)) {
  832. printk(KERN_ERR DRV_NAME
  833. "(%s): no signature after handshake frame\n",
  834. pci_name(hba->pdev));
  835. return -1;
  836. }
  837. rmb();
  838. msleep(1);
  839. }
  840. writel(0, base + IMR0);
  841. readl(base + IMR0);
  842. writel(0, base + OMR0);
  843. readl(base + OMR0);
  844. writel(0, base + IMR1);
  845. readl(base + IMR1);
  846. writel(0, base + OMR1);
  847. readl(base + OMR1); /* flush */
  848. hba->mu_status = MU_STATE_STARTED;
  849. return 0;
  850. }
  851. static int stex_abort(struct scsi_cmnd *cmd)
  852. {
  853. struct Scsi_Host *host = cmd->device->host;
  854. struct st_hba *hba = (struct st_hba *)host->hostdata;
  855. u16 tag = cmd->request->tag;
  856. void __iomem *base;
  857. u32 data;
  858. int result = SUCCESS;
  859. unsigned long flags;
  860. base = hba->mmio_base;
  861. spin_lock_irqsave(host->host_lock, flags);
  862. if (tag < host->can_queue && hba->ccb[tag].cmd == cmd)
  863. hba->wait_ccb = &hba->ccb[tag];
  864. else {
  865. for (tag = 0; tag < host->can_queue; tag++)
  866. if (hba->ccb[tag].cmd == cmd) {
  867. hba->wait_ccb = &hba->ccb[tag];
  868. break;
  869. }
  870. if (tag >= host->can_queue)
  871. goto out;
  872. }
  873. data = readl(base + ODBL);
  874. if (data == 0 || data == 0xffffffff)
  875. goto fail_out;
  876. writel(data, base + ODBL);
  877. readl(base + ODBL); /* flush */
  878. stex_mu_intr(hba, data);
  879. if (hba->wait_ccb == NULL) {
  880. printk(KERN_WARNING DRV_NAME
  881. "(%s): lost interrupt\n", pci_name(hba->pdev));
  882. goto out;
  883. }
  884. fail_out:
  885. stex_unmap_sg(hba, cmd);
  886. hba->wait_ccb->req = NULL; /* nullify the req's future return */
  887. hba->wait_ccb = NULL;
  888. result = FAILED;
  889. out:
  890. spin_unlock_irqrestore(host->host_lock, flags);
  891. return result;
  892. }
  893. static void stex_hard_reset(struct st_hba *hba)
  894. {
  895. struct pci_bus *bus;
  896. int i;
  897. u16 pci_cmd;
  898. u8 pci_bctl;
  899. for (i = 0; i < 16; i++)
  900. pci_read_config_dword(hba->pdev, i * 4,
  901. &hba->pdev->saved_config_space[i]);
  902. /* Reset secondary bus. Our controller(MU/ATU) is the only device on
  903. secondary bus. Consult Intel 80331/3 developer's manual for detail */
  904. bus = hba->pdev->bus;
  905. pci_read_config_byte(bus->self, PCI_BRIDGE_CONTROL, &pci_bctl);
  906. pci_bctl |= PCI_BRIDGE_CTL_BUS_RESET;
  907. pci_write_config_byte(bus->self, PCI_BRIDGE_CONTROL, pci_bctl);
  908. msleep(1);
  909. pci_bctl &= ~PCI_BRIDGE_CTL_BUS_RESET;
  910. pci_write_config_byte(bus->self, PCI_BRIDGE_CONTROL, pci_bctl);
  911. for (i = 0; i < MU_HARD_RESET_WAIT; i++) {
  912. pci_read_config_word(hba->pdev, PCI_COMMAND, &pci_cmd);
  913. if (pci_cmd != 0xffff && (pci_cmd & PCI_COMMAND_MASTER))
  914. break;
  915. msleep(1);
  916. }
  917. ssleep(5);
  918. for (i = 0; i < 16; i++)
  919. pci_write_config_dword(hba->pdev, i * 4,
  920. hba->pdev->saved_config_space[i]);
  921. }
  922. static int stex_reset(struct scsi_cmnd *cmd)
  923. {
  924. struct st_hba *hba;
  925. unsigned long flags;
  926. unsigned long before;
  927. hba = (struct st_hba *) &cmd->device->host->hostdata[0];
  928. hba->mu_status = MU_STATE_RESETTING;
  929. if (hba->cardtype == st_shasta)
  930. stex_hard_reset(hba);
  931. if (hba->cardtype != st_yosemite) {
  932. if (stex_handshake(hba)) {
  933. printk(KERN_WARNING DRV_NAME
  934. "(%s): resetting: handshake failed\n",
  935. pci_name(hba->pdev));
  936. return FAILED;
  937. }
  938. spin_lock_irqsave(hba->host->host_lock, flags);
  939. hba->req_head = 0;
  940. hba->req_tail = 0;
  941. hba->status_head = 0;
  942. hba->status_tail = 0;
  943. hba->out_req_cnt = 0;
  944. spin_unlock_irqrestore(hba->host->host_lock, flags);
  945. return SUCCESS;
  946. }
  947. /* st_yosemite */
  948. writel(MU_INBOUND_DOORBELL_RESET, hba->mmio_base + IDBL);
  949. readl(hba->mmio_base + IDBL); /* flush */
  950. before = jiffies;
  951. while (hba->out_req_cnt > 0) {
  952. if (time_after(jiffies, before + ST_INTERNAL_TIMEOUT * HZ)) {
  953. printk(KERN_WARNING DRV_NAME
  954. "(%s): reset timeout\n", pci_name(hba->pdev));
  955. return FAILED;
  956. }
  957. msleep(1);
  958. }
  959. hba->mu_status = MU_STATE_STARTED;
  960. return SUCCESS;
  961. }
  962. static int stex_biosparam(struct scsi_device *sdev,
  963. struct block_device *bdev, sector_t capacity, int geom[])
  964. {
  965. int heads = 255, sectors = 63;
  966. if (capacity < 0x200000) {
  967. heads = 64;
  968. sectors = 32;
  969. }
  970. sector_div(capacity, heads * sectors);
  971. geom[0] = heads;
  972. geom[1] = sectors;
  973. geom[2] = capacity;
  974. return 0;
  975. }
  976. static struct scsi_host_template driver_template = {
  977. .module = THIS_MODULE,
  978. .name = DRV_NAME,
  979. .proc_name = DRV_NAME,
  980. .bios_param = stex_biosparam,
  981. .queuecommand = stex_queuecommand,
  982. .slave_alloc = stex_slave_alloc,
  983. .slave_configure = stex_slave_config,
  984. .slave_destroy = stex_slave_destroy,
  985. .eh_abort_handler = stex_abort,
  986. .eh_host_reset_handler = stex_reset,
  987. .can_queue = ST_CAN_QUEUE,
  988. .this_id = -1,
  989. .sg_tablesize = ST_MAX_SG,
  990. .cmd_per_lun = ST_CMD_PER_LUN,
  991. };
  992. static int stex_set_dma_mask(struct pci_dev * pdev)
  993. {
  994. int ret;
  995. if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)
  996. && !pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK))
  997. return 0;
  998. ret = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
  999. if (!ret)
  1000. ret = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
  1001. return ret;
  1002. }
  1003. static int __devinit
  1004. stex_probe(struct pci_dev *pdev, const struct pci_device_id *id)
  1005. {
  1006. struct st_hba *hba;
  1007. struct Scsi_Host *host;
  1008. int err;
  1009. err = pci_enable_device(pdev);
  1010. if (err)
  1011. return err;
  1012. pci_set_master(pdev);
  1013. host = scsi_host_alloc(&driver_template, sizeof(struct st_hba));
  1014. if (!host) {
  1015. printk(KERN_ERR DRV_NAME "(%s): scsi_host_alloc failed\n",
  1016. pci_name(pdev));
  1017. err = -ENOMEM;
  1018. goto out_disable;
  1019. }
  1020. hba = (struct st_hba *)host->hostdata;
  1021. memset(hba, 0, sizeof(struct st_hba));
  1022. err = pci_request_regions(pdev, DRV_NAME);
  1023. if (err < 0) {
  1024. printk(KERN_ERR DRV_NAME "(%s): request regions failed\n",
  1025. pci_name(pdev));
  1026. goto out_scsi_host_put;
  1027. }
  1028. hba->mmio_base = ioremap(pci_resource_start(pdev, 0),
  1029. pci_resource_len(pdev, 0));
  1030. if ( !hba->mmio_base) {
  1031. printk(KERN_ERR DRV_NAME "(%s): memory map failed\n",
  1032. pci_name(pdev));
  1033. err = -ENOMEM;
  1034. goto out_release_regions;
  1035. }
  1036. err = stex_set_dma_mask(pdev);
  1037. if (err) {
  1038. printk(KERN_ERR DRV_NAME "(%s): set dma mask failed\n",
  1039. pci_name(pdev));
  1040. goto out_iounmap;
  1041. }
  1042. hba->cardtype = (unsigned int) id->driver_data;
  1043. if (hba->cardtype == st_vsc && (pdev->subsystem_device & 0xf) == 0x1)
  1044. hba->cardtype = st_vsc1;
  1045. hba->dma_size = (hba->cardtype == st_vsc1) ?
  1046. (STEX_BUFFER_SIZE + ST_ADDITIONAL_MEM) : (STEX_BUFFER_SIZE);
  1047. hba->dma_mem = dma_alloc_coherent(&pdev->dev,
  1048. hba->dma_size, &hba->dma_handle, GFP_KERNEL);
  1049. if (!hba->dma_mem) {
  1050. err = -ENOMEM;
  1051. printk(KERN_ERR DRV_NAME "(%s): dma mem alloc failed\n",
  1052. pci_name(pdev));
  1053. goto out_iounmap;
  1054. }
  1055. hba->status_buffer =
  1056. (struct status_msg *)(hba->dma_mem + MU_REQ_BUFFER_SIZE);
  1057. hba->copy_buffer = hba->dma_mem + MU_BUFFER_SIZE;
  1058. hba->mu_status = MU_STATE_STARTING;
  1059. /* firmware uses id/lun pair for a logical drive, but lun would be
  1060. always 0 if CONFIG_SCSI_MULTI_LUN not configured, so we use
  1061. channel to map lun here */
  1062. host->max_channel = ST_MAX_LUN_PER_TARGET - 1;
  1063. host->max_id = ST_MAX_TARGET_NUM;
  1064. host->max_lun = 1;
  1065. host->unique_id = host->host_no;
  1066. host->max_cmd_len = STEX_CDB_LENGTH;
  1067. hba->host = host;
  1068. hba->pdev = pdev;
  1069. init_waitqueue_head(&hba->waitq);
  1070. err = request_irq(pdev->irq, stex_intr, IRQF_SHARED, DRV_NAME, hba);
  1071. if (err) {
  1072. printk(KERN_ERR DRV_NAME "(%s): request irq failed\n",
  1073. pci_name(pdev));
  1074. goto out_pci_free;
  1075. }
  1076. err = stex_handshake(hba);
  1077. if (err)
  1078. goto out_free_irq;
  1079. err = scsi_init_shared_tag_map(host, host->can_queue);
  1080. if (err) {
  1081. printk(KERN_ERR DRV_NAME "(%s): init shared queue failed\n",
  1082. pci_name(pdev));
  1083. goto out_free_irq;
  1084. }
  1085. pci_set_drvdata(pdev, hba);
  1086. err = scsi_add_host(host, &pdev->dev);
  1087. if (err) {
  1088. printk(KERN_ERR DRV_NAME "(%s): scsi_add_host failed\n",
  1089. pci_name(pdev));
  1090. goto out_free_irq;
  1091. }
  1092. scsi_scan_host(host);
  1093. return 0;
  1094. out_free_irq:
  1095. free_irq(pdev->irq, hba);
  1096. out_pci_free:
  1097. dma_free_coherent(&pdev->dev, hba->dma_size,
  1098. hba->dma_mem, hba->dma_handle);
  1099. out_iounmap:
  1100. iounmap(hba->mmio_base);
  1101. out_release_regions:
  1102. pci_release_regions(pdev);
  1103. out_scsi_host_put:
  1104. scsi_host_put(host);
  1105. out_disable:
  1106. pci_disable_device(pdev);
  1107. return err;
  1108. }
  1109. static void stex_hba_stop(struct st_hba *hba)
  1110. {
  1111. struct req_msg *req;
  1112. unsigned long flags;
  1113. unsigned long before;
  1114. u16 tag = 0;
  1115. spin_lock_irqsave(hba->host->host_lock, flags);
  1116. req = stex_alloc_req(hba);
  1117. memset(req->cdb, 0, STEX_CDB_LENGTH);
  1118. if (hba->cardtype == st_yosemite) {
  1119. req->cdb[0] = MGT_CMD;
  1120. req->cdb[1] = MGT_CMD_SIGNATURE;
  1121. req->cdb[2] = CTLR_CONFIG_CMD;
  1122. req->cdb[3] = CTLR_SHUTDOWN;
  1123. } else {
  1124. req->cdb[0] = CONTROLLER_CMD;
  1125. req->cdb[1] = CTLR_POWER_STATE_CHANGE;
  1126. req->cdb[2] = CTLR_POWER_SAVING;
  1127. }
  1128. hba->ccb[tag].cmd = NULL;
  1129. hba->ccb[tag].sg_count = 0;
  1130. hba->ccb[tag].sense_bufflen = 0;
  1131. hba->ccb[tag].sense_buffer = NULL;
  1132. hba->ccb[tag].req_type |= PASSTHRU_REQ_TYPE;
  1133. stex_send_cmd(hba, req, tag);
  1134. spin_unlock_irqrestore(hba->host->host_lock, flags);
  1135. before = jiffies;
  1136. while (hba->ccb[tag].req_type & PASSTHRU_REQ_TYPE) {
  1137. if (time_after(jiffies, before + ST_INTERNAL_TIMEOUT * HZ))
  1138. return;
  1139. msleep(10);
  1140. }
  1141. }
  1142. static void stex_hba_free(struct st_hba *hba)
  1143. {
  1144. free_irq(hba->pdev->irq, hba);
  1145. iounmap(hba->mmio_base);
  1146. pci_release_regions(hba->pdev);
  1147. dma_free_coherent(&hba->pdev->dev, hba->dma_size,
  1148. hba->dma_mem, hba->dma_handle);
  1149. }
  1150. static void stex_remove(struct pci_dev *pdev)
  1151. {
  1152. struct st_hba *hba = pci_get_drvdata(pdev);
  1153. scsi_remove_host(hba->host);
  1154. pci_set_drvdata(pdev, NULL);
  1155. stex_hba_stop(hba);
  1156. stex_hba_free(hba);
  1157. scsi_host_put(hba->host);
  1158. pci_disable_device(pdev);
  1159. }
  1160. static void stex_shutdown(struct pci_dev *pdev)
  1161. {
  1162. struct st_hba *hba = pci_get_drvdata(pdev);
  1163. stex_hba_stop(hba);
  1164. }
  1165. static struct pci_device_id stex_pci_tbl[] = {
  1166. /* st_shasta */
  1167. { 0x105a, 0x8350, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  1168. st_shasta }, /* SuperTrak EX8350/8300/16350/16300 */
  1169. { 0x105a, 0xc350, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  1170. st_shasta }, /* SuperTrak EX12350 */
  1171. { 0x105a, 0x4302, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  1172. st_shasta }, /* SuperTrak EX4350 */
  1173. { 0x105a, 0xe350, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  1174. st_shasta }, /* SuperTrak EX24350 */
  1175. /* st_vsc */
  1176. { 0x105a, 0x7250, PCI_ANY_ID, PCI_ANY_ID, 0, 0, st_vsc },
  1177. /* st_yosemite */
  1178. { 0x105a, 0x8650, PCI_ANY_ID, 0x4600, 0, 0,
  1179. st_yosemite }, /* SuperTrak EX4650 */
  1180. { 0x105a, 0x8650, PCI_ANY_ID, 0x4610, 0, 0,
  1181. st_yosemite }, /* SuperTrak EX4650o */
  1182. { 0x105a, 0x8650, PCI_ANY_ID, 0x8600, 0, 0,
  1183. st_yosemite }, /* SuperTrak EX8650EL */
  1184. { 0x105a, 0x8650, PCI_ANY_ID, 0x8601, 0, 0,
  1185. st_yosemite }, /* SuperTrak EX8650 */
  1186. { 0x105a, 0x8650, PCI_ANY_ID, 0x8602, 0, 0,
  1187. st_yosemite }, /* SuperTrak EX8654 */
  1188. { 0x105a, 0x8650, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  1189. st_yosemite }, /* generic st_yosemite */
  1190. { } /* terminate list */
  1191. };
  1192. MODULE_DEVICE_TABLE(pci, stex_pci_tbl);
  1193. static struct pci_driver stex_pci_driver = {
  1194. .name = DRV_NAME,
  1195. .id_table = stex_pci_tbl,
  1196. .probe = stex_probe,
  1197. .remove = __devexit_p(stex_remove),
  1198. .shutdown = stex_shutdown,
  1199. };
  1200. static int __init stex_init(void)
  1201. {
  1202. printk(KERN_INFO DRV_NAME
  1203. ": Promise SuperTrak EX Driver version: %s\n",
  1204. ST_DRIVER_VERSION);
  1205. return pci_register_driver(&stex_pci_driver);
  1206. }
  1207. static void __exit stex_exit(void)
  1208. {
  1209. pci_unregister_driver(&stex_pci_driver);
  1210. }
  1211. module_init(stex_init);
  1212. module_exit(stex_exit);