wss_lib.c 66 KB

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  1. /*
  2. * Copyright (c) by Jaroslav Kysela <perex@perex.cz>
  3. * Routines for control of CS4231(A)/CS4232/InterWave & compatible chips
  4. *
  5. * Bugs:
  6. * - sometimes record brokes playback with WSS portion of
  7. * Yamaha OPL3-SA3 chip
  8. * - CS4231 (GUS MAX) - still trouble with occasional noises
  9. * - broken initialization?
  10. *
  11. * This program is free software; you can redistribute it and/or modify
  12. * it under the terms of the GNU General Public License as published by
  13. * the Free Software Foundation; either version 2 of the License, or
  14. * (at your option) any later version.
  15. *
  16. * This program is distributed in the hope that it will be useful,
  17. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  19. * GNU General Public License for more details.
  20. *
  21. * You should have received a copy of the GNU General Public License
  22. * along with this program; if not, write to the Free Software
  23. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  24. *
  25. */
  26. #include <linux/delay.h>
  27. #include <linux/pm.h>
  28. #include <linux/init.h>
  29. #include <linux/interrupt.h>
  30. #include <linux/slab.h>
  31. #include <linux/ioport.h>
  32. #include <sound/core.h>
  33. #include <sound/wss.h>
  34. #include <sound/pcm_params.h>
  35. #include <sound/tlv.h>
  36. #include <asm/io.h>
  37. #include <asm/dma.h>
  38. #include <asm/irq.h>
  39. MODULE_AUTHOR("Jaroslav Kysela <perex@perex.cz>");
  40. MODULE_DESCRIPTION("Routines for control of CS4231(A)/CS4232/InterWave & compatible chips");
  41. MODULE_LICENSE("GPL");
  42. #if 0
  43. #define SNDRV_DEBUG_MCE
  44. #endif
  45. /*
  46. * Some variables
  47. */
  48. static unsigned char freq_bits[14] = {
  49. /* 5510 */ 0x00 | CS4231_XTAL2,
  50. /* 6620 */ 0x0E | CS4231_XTAL2,
  51. /* 8000 */ 0x00 | CS4231_XTAL1,
  52. /* 9600 */ 0x0E | CS4231_XTAL1,
  53. /* 11025 */ 0x02 | CS4231_XTAL2,
  54. /* 16000 */ 0x02 | CS4231_XTAL1,
  55. /* 18900 */ 0x04 | CS4231_XTAL2,
  56. /* 22050 */ 0x06 | CS4231_XTAL2,
  57. /* 27042 */ 0x04 | CS4231_XTAL1,
  58. /* 32000 */ 0x06 | CS4231_XTAL1,
  59. /* 33075 */ 0x0C | CS4231_XTAL2,
  60. /* 37800 */ 0x08 | CS4231_XTAL2,
  61. /* 44100 */ 0x0A | CS4231_XTAL2,
  62. /* 48000 */ 0x0C | CS4231_XTAL1
  63. };
  64. static unsigned int rates[14] = {
  65. 5510, 6620, 8000, 9600, 11025, 16000, 18900, 22050,
  66. 27042, 32000, 33075, 37800, 44100, 48000
  67. };
  68. static struct snd_pcm_hw_constraint_list hw_constraints_rates = {
  69. .count = ARRAY_SIZE(rates),
  70. .list = rates,
  71. .mask = 0,
  72. };
  73. static int snd_wss_xrate(struct snd_pcm_runtime *runtime)
  74. {
  75. return snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
  76. &hw_constraints_rates);
  77. }
  78. static unsigned char snd_wss_original_image[32] =
  79. {
  80. 0x00, /* 00/00 - lic */
  81. 0x00, /* 01/01 - ric */
  82. 0x9f, /* 02/02 - la1ic */
  83. 0x9f, /* 03/03 - ra1ic */
  84. 0x9f, /* 04/04 - la2ic */
  85. 0x9f, /* 05/05 - ra2ic */
  86. 0xbf, /* 06/06 - loc */
  87. 0xbf, /* 07/07 - roc */
  88. 0x20, /* 08/08 - pdfr */
  89. CS4231_AUTOCALIB, /* 09/09 - ic */
  90. 0x00, /* 0a/10 - pc */
  91. 0x00, /* 0b/11 - ti */
  92. CS4231_MODE2, /* 0c/12 - mi */
  93. 0xfc, /* 0d/13 - lbc */
  94. 0x00, /* 0e/14 - pbru */
  95. 0x00, /* 0f/15 - pbrl */
  96. 0x80, /* 10/16 - afei */
  97. 0x01, /* 11/17 - afeii */
  98. 0x9f, /* 12/18 - llic */
  99. 0x9f, /* 13/19 - rlic */
  100. 0x00, /* 14/20 - tlb */
  101. 0x00, /* 15/21 - thb */
  102. 0x00, /* 16/22 - la3mic/reserved */
  103. 0x00, /* 17/23 - ra3mic/reserved */
  104. 0x00, /* 18/24 - afs */
  105. 0x00, /* 19/25 - lamoc/version */
  106. 0xcf, /* 1a/26 - mioc */
  107. 0x00, /* 1b/27 - ramoc/reserved */
  108. 0x20, /* 1c/28 - cdfr */
  109. 0x00, /* 1d/29 - res4 */
  110. 0x00, /* 1e/30 - cbru */
  111. 0x00, /* 1f/31 - cbrl */
  112. };
  113. static unsigned char snd_opti93x_original_image[32] =
  114. {
  115. 0x00, /* 00/00 - l_mixout_outctrl */
  116. 0x00, /* 01/01 - r_mixout_outctrl */
  117. 0x88, /* 02/02 - l_cd_inctrl */
  118. 0x88, /* 03/03 - r_cd_inctrl */
  119. 0x88, /* 04/04 - l_a1/fm_inctrl */
  120. 0x88, /* 05/05 - r_a1/fm_inctrl */
  121. 0x80, /* 06/06 - l_dac_inctrl */
  122. 0x80, /* 07/07 - r_dac_inctrl */
  123. 0x00, /* 08/08 - ply_dataform_reg */
  124. 0x00, /* 09/09 - if_conf */
  125. 0x00, /* 0a/10 - pin_ctrl */
  126. 0x00, /* 0b/11 - err_init_reg */
  127. 0x0a, /* 0c/12 - id_reg */
  128. 0x00, /* 0d/13 - reserved */
  129. 0x00, /* 0e/14 - ply_upcount_reg */
  130. 0x00, /* 0f/15 - ply_lowcount_reg */
  131. 0x88, /* 10/16 - reserved/l_a1_inctrl */
  132. 0x88, /* 11/17 - reserved/r_a1_inctrl */
  133. 0x88, /* 12/18 - l_line_inctrl */
  134. 0x88, /* 13/19 - r_line_inctrl */
  135. 0x88, /* 14/20 - l_mic_inctrl */
  136. 0x88, /* 15/21 - r_mic_inctrl */
  137. 0x80, /* 16/22 - l_out_outctrl */
  138. 0x80, /* 17/23 - r_out_outctrl */
  139. 0x00, /* 18/24 - reserved */
  140. 0x00, /* 19/25 - reserved */
  141. 0x00, /* 1a/26 - reserved */
  142. 0x00, /* 1b/27 - reserved */
  143. 0x00, /* 1c/28 - cap_dataform_reg */
  144. 0x00, /* 1d/29 - reserved */
  145. 0x00, /* 1e/30 - cap_upcount_reg */
  146. 0x00 /* 1f/31 - cap_lowcount_reg */
  147. };
  148. /*
  149. * Basic I/O functions
  150. */
  151. static inline void wss_outb(struct snd_wss *chip, u8 offset, u8 val)
  152. {
  153. outb(val, chip->port + offset);
  154. }
  155. static inline u8 wss_inb(struct snd_wss *chip, u8 offset)
  156. {
  157. return inb(chip->port + offset);
  158. }
  159. static void snd_wss_wait(struct snd_wss *chip)
  160. {
  161. int timeout;
  162. for (timeout = 250;
  163. timeout > 0 && (wss_inb(chip, CS4231P(REGSEL)) & CS4231_INIT);
  164. timeout--)
  165. udelay(100);
  166. }
  167. static void snd_wss_outm(struct snd_wss *chip, unsigned char reg,
  168. unsigned char mask, unsigned char value)
  169. {
  170. unsigned char tmp = (chip->image[reg] & mask) | value;
  171. snd_wss_wait(chip);
  172. #ifdef CONFIG_SND_DEBUG
  173. if (wss_inb(chip, CS4231P(REGSEL)) & CS4231_INIT)
  174. snd_printk("outm: auto calibration time out - reg = 0x%x, value = 0x%x\n", reg, value);
  175. #endif
  176. chip->image[reg] = tmp;
  177. if (!chip->calibrate_mute) {
  178. wss_outb(chip, CS4231P(REGSEL), chip->mce_bit | reg);
  179. wmb();
  180. wss_outb(chip, CS4231P(REG), tmp);
  181. mb();
  182. }
  183. }
  184. static void snd_wss_dout(struct snd_wss *chip, unsigned char reg,
  185. unsigned char value)
  186. {
  187. int timeout;
  188. for (timeout = 250;
  189. timeout > 0 && (wss_inb(chip, CS4231P(REGSEL)) & CS4231_INIT);
  190. timeout--)
  191. udelay(10);
  192. wss_outb(chip, CS4231P(REGSEL), chip->mce_bit | reg);
  193. wss_outb(chip, CS4231P(REG), value);
  194. mb();
  195. }
  196. void snd_wss_out(struct snd_wss *chip, unsigned char reg, unsigned char value)
  197. {
  198. snd_wss_wait(chip);
  199. #ifdef CONFIG_SND_DEBUG
  200. if (wss_inb(chip, CS4231P(REGSEL)) & CS4231_INIT)
  201. snd_printk(KERN_DEBUG "out: auto calibration time out "
  202. "- reg = 0x%x, value = 0x%x\n", reg, value);
  203. #endif
  204. wss_outb(chip, CS4231P(REGSEL), chip->mce_bit | reg);
  205. wss_outb(chip, CS4231P(REG), value);
  206. chip->image[reg] = value;
  207. mb();
  208. snd_printdd("codec out - reg 0x%x = 0x%x\n",
  209. chip->mce_bit | reg, value);
  210. }
  211. EXPORT_SYMBOL(snd_wss_out);
  212. unsigned char snd_wss_in(struct snd_wss *chip, unsigned char reg)
  213. {
  214. snd_wss_wait(chip);
  215. #ifdef CONFIG_SND_DEBUG
  216. if (wss_inb(chip, CS4231P(REGSEL)) & CS4231_INIT)
  217. snd_printk(KERN_DEBUG "in: auto calibration time out "
  218. "- reg = 0x%x\n", reg);
  219. #endif
  220. wss_outb(chip, CS4231P(REGSEL), chip->mce_bit | reg);
  221. mb();
  222. return wss_inb(chip, CS4231P(REG));
  223. }
  224. EXPORT_SYMBOL(snd_wss_in);
  225. void snd_cs4236_ext_out(struct snd_wss *chip, unsigned char reg,
  226. unsigned char val)
  227. {
  228. wss_outb(chip, CS4231P(REGSEL), chip->mce_bit | 0x17);
  229. wss_outb(chip, CS4231P(REG),
  230. reg | (chip->image[CS4236_EXT_REG] & 0x01));
  231. wss_outb(chip, CS4231P(REG), val);
  232. chip->eimage[CS4236_REG(reg)] = val;
  233. #if 0
  234. printk(KERN_DEBUG "ext out : reg = 0x%x, val = 0x%x\n", reg, val);
  235. #endif
  236. }
  237. EXPORT_SYMBOL(snd_cs4236_ext_out);
  238. unsigned char snd_cs4236_ext_in(struct snd_wss *chip, unsigned char reg)
  239. {
  240. wss_outb(chip, CS4231P(REGSEL), chip->mce_bit | 0x17);
  241. wss_outb(chip, CS4231P(REG),
  242. reg | (chip->image[CS4236_EXT_REG] & 0x01));
  243. #if 1
  244. return wss_inb(chip, CS4231P(REG));
  245. #else
  246. {
  247. unsigned char res;
  248. res = wss_inb(chip, CS4231P(REG));
  249. printk(KERN_DEBUG "ext in : reg = 0x%x, val = 0x%x\n",
  250. reg, res);
  251. return res;
  252. }
  253. #endif
  254. }
  255. EXPORT_SYMBOL(snd_cs4236_ext_in);
  256. #if 0
  257. static void snd_wss_debug(struct snd_wss *chip)
  258. {
  259. printk(KERN_DEBUG
  260. "CS4231 REGS: INDEX = 0x%02x "
  261. " STATUS = 0x%02x\n",
  262. wss_inb(chip, CS4231P(REGSEL)),
  263. wss_inb(chip, CS4231P(STATUS)));
  264. printk(KERN_DEBUG
  265. " 0x00: left input = 0x%02x "
  266. " 0x10: alt 1 (CFIG 2) = 0x%02x\n",
  267. snd_wss_in(chip, 0x00),
  268. snd_wss_in(chip, 0x10));
  269. printk(KERN_DEBUG
  270. " 0x01: right input = 0x%02x "
  271. " 0x11: alt 2 (CFIG 3) = 0x%02x\n",
  272. snd_wss_in(chip, 0x01),
  273. snd_wss_in(chip, 0x11));
  274. printk(KERN_DEBUG
  275. " 0x02: GF1 left input = 0x%02x "
  276. " 0x12: left line in = 0x%02x\n",
  277. snd_wss_in(chip, 0x02),
  278. snd_wss_in(chip, 0x12));
  279. printk(KERN_DEBUG
  280. " 0x03: GF1 right input = 0x%02x "
  281. " 0x13: right line in = 0x%02x\n",
  282. snd_wss_in(chip, 0x03),
  283. snd_wss_in(chip, 0x13));
  284. printk(KERN_DEBUG
  285. " 0x04: CD left input = 0x%02x "
  286. " 0x14: timer low = 0x%02x\n",
  287. snd_wss_in(chip, 0x04),
  288. snd_wss_in(chip, 0x14));
  289. printk(KERN_DEBUG
  290. " 0x05: CD right input = 0x%02x "
  291. " 0x15: timer high = 0x%02x\n",
  292. snd_wss_in(chip, 0x05),
  293. snd_wss_in(chip, 0x15));
  294. printk(KERN_DEBUG
  295. " 0x06: left output = 0x%02x "
  296. " 0x16: left MIC (PnP) = 0x%02x\n",
  297. snd_wss_in(chip, 0x06),
  298. snd_wss_in(chip, 0x16));
  299. printk(KERN_DEBUG
  300. " 0x07: right output = 0x%02x "
  301. " 0x17: right MIC (PnP) = 0x%02x\n",
  302. snd_wss_in(chip, 0x07),
  303. snd_wss_in(chip, 0x17));
  304. printk(KERN_DEBUG
  305. " 0x08: playback format = 0x%02x "
  306. " 0x18: IRQ status = 0x%02x\n",
  307. snd_wss_in(chip, 0x08),
  308. snd_wss_in(chip, 0x18));
  309. printk(KERN_DEBUG
  310. " 0x09: iface (CFIG 1) = 0x%02x "
  311. " 0x19: left line out = 0x%02x\n",
  312. snd_wss_in(chip, 0x09),
  313. snd_wss_in(chip, 0x19));
  314. printk(KERN_DEBUG
  315. " 0x0a: pin control = 0x%02x "
  316. " 0x1a: mono control = 0x%02x\n",
  317. snd_wss_in(chip, 0x0a),
  318. snd_wss_in(chip, 0x1a));
  319. printk(KERN_DEBUG
  320. " 0x0b: init & status = 0x%02x "
  321. " 0x1b: right line out = 0x%02x\n",
  322. snd_wss_in(chip, 0x0b),
  323. snd_wss_in(chip, 0x1b));
  324. printk(KERN_DEBUG
  325. " 0x0c: revision & mode = 0x%02x "
  326. " 0x1c: record format = 0x%02x\n",
  327. snd_wss_in(chip, 0x0c),
  328. snd_wss_in(chip, 0x1c));
  329. printk(KERN_DEBUG
  330. " 0x0d: loopback = 0x%02x "
  331. " 0x1d: var freq (PnP) = 0x%02x\n",
  332. snd_wss_in(chip, 0x0d),
  333. snd_wss_in(chip, 0x1d));
  334. printk(KERN_DEBUG
  335. " 0x0e: ply upr count = 0x%02x "
  336. " 0x1e: ply lwr count = 0x%02x\n",
  337. snd_wss_in(chip, 0x0e),
  338. snd_wss_in(chip, 0x1e));
  339. printk(KERN_DEBUG
  340. " 0x0f: rec upr count = 0x%02x "
  341. " 0x1f: rec lwr count = 0x%02x\n",
  342. snd_wss_in(chip, 0x0f),
  343. snd_wss_in(chip, 0x1f));
  344. }
  345. #endif
  346. /*
  347. * CS4231 detection / MCE routines
  348. */
  349. static void snd_wss_busy_wait(struct snd_wss *chip)
  350. {
  351. int timeout;
  352. /* huh.. looks like this sequence is proper for CS4231A chip (GUS MAX) */
  353. for (timeout = 5; timeout > 0; timeout--)
  354. wss_inb(chip, CS4231P(REGSEL));
  355. /* end of cleanup sequence */
  356. for (timeout = 25000;
  357. timeout > 0 && (wss_inb(chip, CS4231P(REGSEL)) & CS4231_INIT);
  358. timeout--)
  359. udelay(10);
  360. }
  361. void snd_wss_mce_up(struct snd_wss *chip)
  362. {
  363. unsigned long flags;
  364. int timeout;
  365. snd_wss_wait(chip);
  366. #ifdef CONFIG_SND_DEBUG
  367. if (wss_inb(chip, CS4231P(REGSEL)) & CS4231_INIT)
  368. snd_printk(KERN_DEBUG
  369. "mce_up - auto calibration time out (0)\n");
  370. #endif
  371. spin_lock_irqsave(&chip->reg_lock, flags);
  372. chip->mce_bit |= CS4231_MCE;
  373. timeout = wss_inb(chip, CS4231P(REGSEL));
  374. if (timeout == 0x80)
  375. snd_printk(KERN_DEBUG "mce_up [0x%lx]: "
  376. "serious init problem - codec still busy\n",
  377. chip->port);
  378. if (!(timeout & CS4231_MCE))
  379. wss_outb(chip, CS4231P(REGSEL),
  380. chip->mce_bit | (timeout & 0x1f));
  381. spin_unlock_irqrestore(&chip->reg_lock, flags);
  382. }
  383. EXPORT_SYMBOL(snd_wss_mce_up);
  384. void snd_wss_mce_down(struct snd_wss *chip)
  385. {
  386. unsigned long flags;
  387. unsigned long end_time;
  388. int timeout;
  389. int hw_mask = WSS_HW_CS4231_MASK | WSS_HW_CS4232_MASK | WSS_HW_AD1848;
  390. snd_wss_busy_wait(chip);
  391. #ifdef CONFIG_SND_DEBUG
  392. if (wss_inb(chip, CS4231P(REGSEL)) & CS4231_INIT)
  393. snd_printk(KERN_DEBUG "mce_down [0x%lx] - "
  394. "auto calibration time out (0)\n",
  395. (long)CS4231P(REGSEL));
  396. #endif
  397. spin_lock_irqsave(&chip->reg_lock, flags);
  398. chip->mce_bit &= ~CS4231_MCE;
  399. timeout = wss_inb(chip, CS4231P(REGSEL));
  400. wss_outb(chip, CS4231P(REGSEL), chip->mce_bit | (timeout & 0x1f));
  401. spin_unlock_irqrestore(&chip->reg_lock, flags);
  402. if (timeout == 0x80)
  403. snd_printk(KERN_DEBUG "mce_down [0x%lx]: "
  404. "serious init problem - codec still busy\n",
  405. chip->port);
  406. if ((timeout & CS4231_MCE) == 0 || !(chip->hardware & hw_mask))
  407. return;
  408. /*
  409. * Wait for (possible -- during init auto-calibration may not be set)
  410. * calibration process to start. Needs upto 5 sample periods on AD1848
  411. * which at the slowest possible rate of 5.5125 kHz means 907 us.
  412. */
  413. msleep(1);
  414. snd_printdd("(1) jiffies = %lu\n", jiffies);
  415. /* check condition up to 250 ms */
  416. end_time = jiffies + msecs_to_jiffies(250);
  417. while (snd_wss_in(chip, CS4231_TEST_INIT) &
  418. CS4231_CALIB_IN_PROGRESS) {
  419. if (time_after(jiffies, end_time)) {
  420. snd_printk(KERN_ERR "mce_down - "
  421. "auto calibration time out (2)\n");
  422. return;
  423. }
  424. msleep(1);
  425. }
  426. snd_printdd("(2) jiffies = %lu\n", jiffies);
  427. /* check condition up to 100 ms */
  428. end_time = jiffies + msecs_to_jiffies(100);
  429. while (wss_inb(chip, CS4231P(REGSEL)) & CS4231_INIT) {
  430. if (time_after(jiffies, end_time)) {
  431. snd_printk(KERN_ERR "mce_down - auto calibration time out (3)\n");
  432. return;
  433. }
  434. msleep(1);
  435. }
  436. snd_printdd("(3) jiffies = %lu\n", jiffies);
  437. snd_printd("mce_down - exit = 0x%x\n", wss_inb(chip, CS4231P(REGSEL)));
  438. }
  439. EXPORT_SYMBOL(snd_wss_mce_down);
  440. static unsigned int snd_wss_get_count(unsigned char format, unsigned int size)
  441. {
  442. switch (format & 0xe0) {
  443. case CS4231_LINEAR_16:
  444. case CS4231_LINEAR_16_BIG:
  445. size >>= 1;
  446. break;
  447. case CS4231_ADPCM_16:
  448. return size >> 2;
  449. }
  450. if (format & CS4231_STEREO)
  451. size >>= 1;
  452. return size;
  453. }
  454. static int snd_wss_trigger(struct snd_pcm_substream *substream,
  455. int cmd)
  456. {
  457. struct snd_wss *chip = snd_pcm_substream_chip(substream);
  458. int result = 0;
  459. unsigned int what;
  460. struct snd_pcm_substream *s;
  461. int do_start;
  462. switch (cmd) {
  463. case SNDRV_PCM_TRIGGER_START:
  464. case SNDRV_PCM_TRIGGER_RESUME:
  465. do_start = 1; break;
  466. case SNDRV_PCM_TRIGGER_STOP:
  467. case SNDRV_PCM_TRIGGER_SUSPEND:
  468. do_start = 0; break;
  469. default:
  470. return -EINVAL;
  471. }
  472. what = 0;
  473. snd_pcm_group_for_each_entry(s, substream) {
  474. if (s == chip->playback_substream) {
  475. what |= CS4231_PLAYBACK_ENABLE;
  476. snd_pcm_trigger_done(s, substream);
  477. } else if (s == chip->capture_substream) {
  478. what |= CS4231_RECORD_ENABLE;
  479. snd_pcm_trigger_done(s, substream);
  480. }
  481. }
  482. spin_lock(&chip->reg_lock);
  483. if (do_start) {
  484. chip->image[CS4231_IFACE_CTRL] |= what;
  485. if (chip->trigger)
  486. chip->trigger(chip, what, 1);
  487. } else {
  488. chip->image[CS4231_IFACE_CTRL] &= ~what;
  489. if (chip->trigger)
  490. chip->trigger(chip, what, 0);
  491. }
  492. snd_wss_out(chip, CS4231_IFACE_CTRL, chip->image[CS4231_IFACE_CTRL]);
  493. spin_unlock(&chip->reg_lock);
  494. #if 0
  495. snd_wss_debug(chip);
  496. #endif
  497. return result;
  498. }
  499. /*
  500. * CODEC I/O
  501. */
  502. static unsigned char snd_wss_get_rate(unsigned int rate)
  503. {
  504. int i;
  505. for (i = 0; i < ARRAY_SIZE(rates); i++)
  506. if (rate == rates[i])
  507. return freq_bits[i];
  508. // snd_BUG();
  509. return freq_bits[ARRAY_SIZE(rates) - 1];
  510. }
  511. static unsigned char snd_wss_get_format(struct snd_wss *chip,
  512. int format,
  513. int channels)
  514. {
  515. unsigned char rformat;
  516. rformat = CS4231_LINEAR_8;
  517. switch (format) {
  518. case SNDRV_PCM_FORMAT_MU_LAW: rformat = CS4231_ULAW_8; break;
  519. case SNDRV_PCM_FORMAT_A_LAW: rformat = CS4231_ALAW_8; break;
  520. case SNDRV_PCM_FORMAT_S16_LE: rformat = CS4231_LINEAR_16; break;
  521. case SNDRV_PCM_FORMAT_S16_BE: rformat = CS4231_LINEAR_16_BIG; break;
  522. case SNDRV_PCM_FORMAT_IMA_ADPCM: rformat = CS4231_ADPCM_16; break;
  523. }
  524. if (channels > 1)
  525. rformat |= CS4231_STEREO;
  526. #if 0
  527. snd_printk(KERN_DEBUG "get_format: 0x%x (mode=0x%x)\n", format, mode);
  528. #endif
  529. return rformat;
  530. }
  531. static void snd_wss_calibrate_mute(struct snd_wss *chip, int mute)
  532. {
  533. unsigned long flags;
  534. mute = mute ? 0x80 : 0;
  535. spin_lock_irqsave(&chip->reg_lock, flags);
  536. if (chip->calibrate_mute == mute) {
  537. spin_unlock_irqrestore(&chip->reg_lock, flags);
  538. return;
  539. }
  540. if (!mute) {
  541. snd_wss_dout(chip, CS4231_LEFT_INPUT,
  542. chip->image[CS4231_LEFT_INPUT]);
  543. snd_wss_dout(chip, CS4231_RIGHT_INPUT,
  544. chip->image[CS4231_RIGHT_INPUT]);
  545. snd_wss_dout(chip, CS4231_LOOPBACK,
  546. chip->image[CS4231_LOOPBACK]);
  547. }
  548. snd_wss_dout(chip, CS4231_AUX1_LEFT_INPUT,
  549. mute | chip->image[CS4231_AUX1_LEFT_INPUT]);
  550. snd_wss_dout(chip, CS4231_AUX1_RIGHT_INPUT,
  551. mute | chip->image[CS4231_AUX1_RIGHT_INPUT]);
  552. snd_wss_dout(chip, CS4231_AUX2_LEFT_INPUT,
  553. mute | chip->image[CS4231_AUX2_LEFT_INPUT]);
  554. snd_wss_dout(chip, CS4231_AUX2_RIGHT_INPUT,
  555. mute | chip->image[CS4231_AUX2_RIGHT_INPUT]);
  556. snd_wss_dout(chip, CS4231_LEFT_OUTPUT,
  557. mute | chip->image[CS4231_LEFT_OUTPUT]);
  558. snd_wss_dout(chip, CS4231_RIGHT_OUTPUT,
  559. mute | chip->image[CS4231_RIGHT_OUTPUT]);
  560. if (!(chip->hardware & WSS_HW_AD1848_MASK)) {
  561. snd_wss_dout(chip, CS4231_LEFT_LINE_IN,
  562. mute | chip->image[CS4231_LEFT_LINE_IN]);
  563. snd_wss_dout(chip, CS4231_RIGHT_LINE_IN,
  564. mute | chip->image[CS4231_RIGHT_LINE_IN]);
  565. snd_wss_dout(chip, CS4231_MONO_CTRL,
  566. mute ? 0xc0 : chip->image[CS4231_MONO_CTRL]);
  567. }
  568. if (chip->hardware == WSS_HW_INTERWAVE) {
  569. snd_wss_dout(chip, CS4231_LEFT_MIC_INPUT,
  570. mute | chip->image[CS4231_LEFT_MIC_INPUT]);
  571. snd_wss_dout(chip, CS4231_RIGHT_MIC_INPUT,
  572. mute | chip->image[CS4231_RIGHT_MIC_INPUT]);
  573. snd_wss_dout(chip, CS4231_LINE_LEFT_OUTPUT,
  574. mute | chip->image[CS4231_LINE_LEFT_OUTPUT]);
  575. snd_wss_dout(chip, CS4231_LINE_RIGHT_OUTPUT,
  576. mute | chip->image[CS4231_LINE_RIGHT_OUTPUT]);
  577. }
  578. chip->calibrate_mute = mute;
  579. spin_unlock_irqrestore(&chip->reg_lock, flags);
  580. }
  581. static void snd_wss_playback_format(struct snd_wss *chip,
  582. struct snd_pcm_hw_params *params,
  583. unsigned char pdfr)
  584. {
  585. unsigned long flags;
  586. int full_calib = 1;
  587. mutex_lock(&chip->mce_mutex);
  588. snd_wss_calibrate_mute(chip, 1);
  589. if (chip->hardware == WSS_HW_CS4231A ||
  590. (chip->hardware & WSS_HW_CS4232_MASK)) {
  591. spin_lock_irqsave(&chip->reg_lock, flags);
  592. if ((chip->image[CS4231_PLAYBK_FORMAT] & 0x0f) == (pdfr & 0x0f)) { /* rate is same? */
  593. snd_wss_out(chip, CS4231_ALT_FEATURE_1,
  594. chip->image[CS4231_ALT_FEATURE_1] | 0x10);
  595. chip->image[CS4231_PLAYBK_FORMAT] = pdfr;
  596. snd_wss_out(chip, CS4231_PLAYBK_FORMAT,
  597. chip->image[CS4231_PLAYBK_FORMAT]);
  598. snd_wss_out(chip, CS4231_ALT_FEATURE_1,
  599. chip->image[CS4231_ALT_FEATURE_1] &= ~0x10);
  600. udelay(100); /* Fixes audible clicks at least on GUS MAX */
  601. full_calib = 0;
  602. }
  603. spin_unlock_irqrestore(&chip->reg_lock, flags);
  604. }
  605. if (full_calib) {
  606. snd_wss_mce_up(chip);
  607. spin_lock_irqsave(&chip->reg_lock, flags);
  608. if (chip->hardware != WSS_HW_INTERWAVE && !chip->single_dma) {
  609. if (chip->image[CS4231_IFACE_CTRL] & CS4231_RECORD_ENABLE)
  610. pdfr = (pdfr & 0xf0) |
  611. (chip->image[CS4231_REC_FORMAT] & 0x0f);
  612. } else {
  613. chip->image[CS4231_PLAYBK_FORMAT] = pdfr;
  614. }
  615. snd_wss_out(chip, CS4231_PLAYBK_FORMAT, pdfr);
  616. spin_unlock_irqrestore(&chip->reg_lock, flags);
  617. if (chip->hardware == WSS_HW_OPL3SA2)
  618. udelay(100); /* this seems to help */
  619. snd_wss_mce_down(chip);
  620. }
  621. snd_wss_calibrate_mute(chip, 0);
  622. mutex_unlock(&chip->mce_mutex);
  623. }
  624. static void snd_wss_capture_format(struct snd_wss *chip,
  625. struct snd_pcm_hw_params *params,
  626. unsigned char cdfr)
  627. {
  628. unsigned long flags;
  629. int full_calib = 1;
  630. mutex_lock(&chip->mce_mutex);
  631. snd_wss_calibrate_mute(chip, 1);
  632. if (chip->hardware == WSS_HW_CS4231A ||
  633. (chip->hardware & WSS_HW_CS4232_MASK)) {
  634. spin_lock_irqsave(&chip->reg_lock, flags);
  635. if ((chip->image[CS4231_PLAYBK_FORMAT] & 0x0f) == (cdfr & 0x0f) || /* rate is same? */
  636. (chip->image[CS4231_IFACE_CTRL] & CS4231_PLAYBACK_ENABLE)) {
  637. snd_wss_out(chip, CS4231_ALT_FEATURE_1,
  638. chip->image[CS4231_ALT_FEATURE_1] | 0x20);
  639. snd_wss_out(chip, CS4231_REC_FORMAT,
  640. chip->image[CS4231_REC_FORMAT] = cdfr);
  641. snd_wss_out(chip, CS4231_ALT_FEATURE_1,
  642. chip->image[CS4231_ALT_FEATURE_1] &= ~0x20);
  643. full_calib = 0;
  644. }
  645. spin_unlock_irqrestore(&chip->reg_lock, flags);
  646. }
  647. if (full_calib) {
  648. snd_wss_mce_up(chip);
  649. spin_lock_irqsave(&chip->reg_lock, flags);
  650. if (chip->hardware != WSS_HW_INTERWAVE &&
  651. !(chip->image[CS4231_IFACE_CTRL] & CS4231_PLAYBACK_ENABLE)) {
  652. if (chip->single_dma)
  653. snd_wss_out(chip, CS4231_PLAYBK_FORMAT, cdfr);
  654. else
  655. snd_wss_out(chip, CS4231_PLAYBK_FORMAT,
  656. (chip->image[CS4231_PLAYBK_FORMAT] & 0xf0) |
  657. (cdfr & 0x0f));
  658. spin_unlock_irqrestore(&chip->reg_lock, flags);
  659. snd_wss_mce_down(chip);
  660. snd_wss_mce_up(chip);
  661. spin_lock_irqsave(&chip->reg_lock, flags);
  662. }
  663. if (chip->hardware & WSS_HW_AD1848_MASK)
  664. snd_wss_out(chip, CS4231_PLAYBK_FORMAT, cdfr);
  665. else
  666. snd_wss_out(chip, CS4231_REC_FORMAT, cdfr);
  667. spin_unlock_irqrestore(&chip->reg_lock, flags);
  668. snd_wss_mce_down(chip);
  669. }
  670. snd_wss_calibrate_mute(chip, 0);
  671. mutex_unlock(&chip->mce_mutex);
  672. }
  673. /*
  674. * Timer interface
  675. */
  676. static unsigned long snd_wss_timer_resolution(struct snd_timer *timer)
  677. {
  678. struct snd_wss *chip = snd_timer_chip(timer);
  679. if (chip->hardware & WSS_HW_CS4236B_MASK)
  680. return 14467;
  681. else
  682. return chip->image[CS4231_PLAYBK_FORMAT] & 1 ? 9969 : 9920;
  683. }
  684. static int snd_wss_timer_start(struct snd_timer *timer)
  685. {
  686. unsigned long flags;
  687. unsigned int ticks;
  688. struct snd_wss *chip = snd_timer_chip(timer);
  689. spin_lock_irqsave(&chip->reg_lock, flags);
  690. ticks = timer->sticks;
  691. if ((chip->image[CS4231_ALT_FEATURE_1] & CS4231_TIMER_ENABLE) == 0 ||
  692. (unsigned char)(ticks >> 8) != chip->image[CS4231_TIMER_HIGH] ||
  693. (unsigned char)ticks != chip->image[CS4231_TIMER_LOW]) {
  694. chip->image[CS4231_TIMER_HIGH] = (unsigned char) (ticks >> 8);
  695. snd_wss_out(chip, CS4231_TIMER_HIGH,
  696. chip->image[CS4231_TIMER_HIGH]);
  697. chip->image[CS4231_TIMER_LOW] = (unsigned char) ticks;
  698. snd_wss_out(chip, CS4231_TIMER_LOW,
  699. chip->image[CS4231_TIMER_LOW]);
  700. snd_wss_out(chip, CS4231_ALT_FEATURE_1,
  701. chip->image[CS4231_ALT_FEATURE_1] |
  702. CS4231_TIMER_ENABLE);
  703. }
  704. spin_unlock_irqrestore(&chip->reg_lock, flags);
  705. return 0;
  706. }
  707. static int snd_wss_timer_stop(struct snd_timer *timer)
  708. {
  709. unsigned long flags;
  710. struct snd_wss *chip = snd_timer_chip(timer);
  711. spin_lock_irqsave(&chip->reg_lock, flags);
  712. chip->image[CS4231_ALT_FEATURE_1] &= ~CS4231_TIMER_ENABLE;
  713. snd_wss_out(chip, CS4231_ALT_FEATURE_1,
  714. chip->image[CS4231_ALT_FEATURE_1]);
  715. spin_unlock_irqrestore(&chip->reg_lock, flags);
  716. return 0;
  717. }
  718. static void snd_wss_init(struct snd_wss *chip)
  719. {
  720. unsigned long flags;
  721. snd_wss_mce_down(chip);
  722. #ifdef SNDRV_DEBUG_MCE
  723. snd_printk(KERN_DEBUG "init: (1)\n");
  724. #endif
  725. snd_wss_mce_up(chip);
  726. spin_lock_irqsave(&chip->reg_lock, flags);
  727. chip->image[CS4231_IFACE_CTRL] &= ~(CS4231_PLAYBACK_ENABLE |
  728. CS4231_PLAYBACK_PIO |
  729. CS4231_RECORD_ENABLE |
  730. CS4231_RECORD_PIO |
  731. CS4231_CALIB_MODE);
  732. chip->image[CS4231_IFACE_CTRL] |= CS4231_AUTOCALIB;
  733. snd_wss_out(chip, CS4231_IFACE_CTRL, chip->image[CS4231_IFACE_CTRL]);
  734. spin_unlock_irqrestore(&chip->reg_lock, flags);
  735. snd_wss_mce_down(chip);
  736. #ifdef SNDRV_DEBUG_MCE
  737. snd_printk(KERN_DEBUG "init: (2)\n");
  738. #endif
  739. snd_wss_mce_up(chip);
  740. spin_lock_irqsave(&chip->reg_lock, flags);
  741. snd_wss_out(chip,
  742. CS4231_ALT_FEATURE_1, chip->image[CS4231_ALT_FEATURE_1]);
  743. spin_unlock_irqrestore(&chip->reg_lock, flags);
  744. snd_wss_mce_down(chip);
  745. #ifdef SNDRV_DEBUG_MCE
  746. snd_printk(KERN_DEBUG "init: (3) - afei = 0x%x\n",
  747. chip->image[CS4231_ALT_FEATURE_1]);
  748. #endif
  749. spin_lock_irqsave(&chip->reg_lock, flags);
  750. snd_wss_out(chip, CS4231_ALT_FEATURE_2,
  751. chip->image[CS4231_ALT_FEATURE_2]);
  752. spin_unlock_irqrestore(&chip->reg_lock, flags);
  753. snd_wss_mce_up(chip);
  754. spin_lock_irqsave(&chip->reg_lock, flags);
  755. snd_wss_out(chip, CS4231_PLAYBK_FORMAT,
  756. chip->image[CS4231_PLAYBK_FORMAT]);
  757. spin_unlock_irqrestore(&chip->reg_lock, flags);
  758. snd_wss_mce_down(chip);
  759. #ifdef SNDRV_DEBUG_MCE
  760. snd_printk(KERN_DEBUG "init: (4)\n");
  761. #endif
  762. snd_wss_mce_up(chip);
  763. spin_lock_irqsave(&chip->reg_lock, flags);
  764. if (!(chip->hardware & WSS_HW_AD1848_MASK))
  765. snd_wss_out(chip, CS4231_REC_FORMAT,
  766. chip->image[CS4231_REC_FORMAT]);
  767. spin_unlock_irqrestore(&chip->reg_lock, flags);
  768. snd_wss_mce_down(chip);
  769. #ifdef SNDRV_DEBUG_MCE
  770. snd_printk(KERN_DEBUG "init: (5)\n");
  771. #endif
  772. }
  773. static int snd_wss_open(struct snd_wss *chip, unsigned int mode)
  774. {
  775. unsigned long flags;
  776. mutex_lock(&chip->open_mutex);
  777. if ((chip->mode & mode) ||
  778. ((chip->mode & WSS_MODE_OPEN) && chip->single_dma)) {
  779. mutex_unlock(&chip->open_mutex);
  780. return -EAGAIN;
  781. }
  782. if (chip->mode & WSS_MODE_OPEN) {
  783. chip->mode |= mode;
  784. mutex_unlock(&chip->open_mutex);
  785. return 0;
  786. }
  787. /* ok. now enable and ack CODEC IRQ */
  788. spin_lock_irqsave(&chip->reg_lock, flags);
  789. if (!(chip->hardware & WSS_HW_AD1848_MASK)) {
  790. snd_wss_out(chip, CS4231_IRQ_STATUS,
  791. CS4231_PLAYBACK_IRQ |
  792. CS4231_RECORD_IRQ |
  793. CS4231_TIMER_IRQ);
  794. snd_wss_out(chip, CS4231_IRQ_STATUS, 0);
  795. }
  796. wss_outb(chip, CS4231P(STATUS), 0); /* clear IRQ */
  797. wss_outb(chip, CS4231P(STATUS), 0); /* clear IRQ */
  798. chip->image[CS4231_PIN_CTRL] |= CS4231_IRQ_ENABLE;
  799. snd_wss_out(chip, CS4231_PIN_CTRL, chip->image[CS4231_PIN_CTRL]);
  800. if (!(chip->hardware & WSS_HW_AD1848_MASK)) {
  801. snd_wss_out(chip, CS4231_IRQ_STATUS,
  802. CS4231_PLAYBACK_IRQ |
  803. CS4231_RECORD_IRQ |
  804. CS4231_TIMER_IRQ);
  805. snd_wss_out(chip, CS4231_IRQ_STATUS, 0);
  806. }
  807. spin_unlock_irqrestore(&chip->reg_lock, flags);
  808. chip->mode = mode;
  809. mutex_unlock(&chip->open_mutex);
  810. return 0;
  811. }
  812. static void snd_wss_close(struct snd_wss *chip, unsigned int mode)
  813. {
  814. unsigned long flags;
  815. mutex_lock(&chip->open_mutex);
  816. chip->mode &= ~mode;
  817. if (chip->mode & WSS_MODE_OPEN) {
  818. mutex_unlock(&chip->open_mutex);
  819. return;
  820. }
  821. snd_wss_calibrate_mute(chip, 1);
  822. /* disable IRQ */
  823. spin_lock_irqsave(&chip->reg_lock, flags);
  824. if (!(chip->hardware & WSS_HW_AD1848_MASK))
  825. snd_wss_out(chip, CS4231_IRQ_STATUS, 0);
  826. wss_outb(chip, CS4231P(STATUS), 0); /* clear IRQ */
  827. wss_outb(chip, CS4231P(STATUS), 0); /* clear IRQ */
  828. chip->image[CS4231_PIN_CTRL] &= ~CS4231_IRQ_ENABLE;
  829. snd_wss_out(chip, CS4231_PIN_CTRL, chip->image[CS4231_PIN_CTRL]);
  830. /* now disable record & playback */
  831. if (chip->image[CS4231_IFACE_CTRL] & (CS4231_PLAYBACK_ENABLE | CS4231_PLAYBACK_PIO |
  832. CS4231_RECORD_ENABLE | CS4231_RECORD_PIO)) {
  833. spin_unlock_irqrestore(&chip->reg_lock, flags);
  834. snd_wss_mce_up(chip);
  835. spin_lock_irqsave(&chip->reg_lock, flags);
  836. chip->image[CS4231_IFACE_CTRL] &= ~(CS4231_PLAYBACK_ENABLE | CS4231_PLAYBACK_PIO |
  837. CS4231_RECORD_ENABLE | CS4231_RECORD_PIO);
  838. snd_wss_out(chip, CS4231_IFACE_CTRL,
  839. chip->image[CS4231_IFACE_CTRL]);
  840. spin_unlock_irqrestore(&chip->reg_lock, flags);
  841. snd_wss_mce_down(chip);
  842. spin_lock_irqsave(&chip->reg_lock, flags);
  843. }
  844. /* clear IRQ again */
  845. if (!(chip->hardware & WSS_HW_AD1848_MASK))
  846. snd_wss_out(chip, CS4231_IRQ_STATUS, 0);
  847. wss_outb(chip, CS4231P(STATUS), 0); /* clear IRQ */
  848. wss_outb(chip, CS4231P(STATUS), 0); /* clear IRQ */
  849. spin_unlock_irqrestore(&chip->reg_lock, flags);
  850. snd_wss_calibrate_mute(chip, 0);
  851. chip->mode = 0;
  852. mutex_unlock(&chip->open_mutex);
  853. }
  854. /*
  855. * timer open/close
  856. */
  857. static int snd_wss_timer_open(struct snd_timer *timer)
  858. {
  859. struct snd_wss *chip = snd_timer_chip(timer);
  860. snd_wss_open(chip, WSS_MODE_TIMER);
  861. return 0;
  862. }
  863. static int snd_wss_timer_close(struct snd_timer *timer)
  864. {
  865. struct snd_wss *chip = snd_timer_chip(timer);
  866. snd_wss_close(chip, WSS_MODE_TIMER);
  867. return 0;
  868. }
  869. static struct snd_timer_hardware snd_wss_timer_table =
  870. {
  871. .flags = SNDRV_TIMER_HW_AUTO,
  872. .resolution = 9945,
  873. .ticks = 65535,
  874. .open = snd_wss_timer_open,
  875. .close = snd_wss_timer_close,
  876. .c_resolution = snd_wss_timer_resolution,
  877. .start = snd_wss_timer_start,
  878. .stop = snd_wss_timer_stop,
  879. };
  880. /*
  881. * ok.. exported functions..
  882. */
  883. static int snd_wss_playback_hw_params(struct snd_pcm_substream *substream,
  884. struct snd_pcm_hw_params *hw_params)
  885. {
  886. struct snd_wss *chip = snd_pcm_substream_chip(substream);
  887. unsigned char new_pdfr;
  888. int err;
  889. if ((err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params))) < 0)
  890. return err;
  891. new_pdfr = snd_wss_get_format(chip, params_format(hw_params),
  892. params_channels(hw_params)) |
  893. snd_wss_get_rate(params_rate(hw_params));
  894. chip->set_playback_format(chip, hw_params, new_pdfr);
  895. return 0;
  896. }
  897. static int snd_wss_playback_hw_free(struct snd_pcm_substream *substream)
  898. {
  899. return snd_pcm_lib_free_pages(substream);
  900. }
  901. static int snd_wss_playback_prepare(struct snd_pcm_substream *substream)
  902. {
  903. struct snd_wss *chip = snd_pcm_substream_chip(substream);
  904. struct snd_pcm_runtime *runtime = substream->runtime;
  905. unsigned long flags;
  906. unsigned int size = snd_pcm_lib_buffer_bytes(substream);
  907. unsigned int count = snd_pcm_lib_period_bytes(substream);
  908. spin_lock_irqsave(&chip->reg_lock, flags);
  909. chip->p_dma_size = size;
  910. chip->image[CS4231_IFACE_CTRL] &= ~(CS4231_PLAYBACK_ENABLE | CS4231_PLAYBACK_PIO);
  911. snd_dma_program(chip->dma1, runtime->dma_addr, size, DMA_MODE_WRITE | DMA_AUTOINIT);
  912. count = snd_wss_get_count(chip->image[CS4231_PLAYBK_FORMAT], count) - 1;
  913. snd_wss_out(chip, CS4231_PLY_LWR_CNT, (unsigned char) count);
  914. snd_wss_out(chip, CS4231_PLY_UPR_CNT, (unsigned char) (count >> 8));
  915. spin_unlock_irqrestore(&chip->reg_lock, flags);
  916. #if 0
  917. snd_wss_debug(chip);
  918. #endif
  919. return 0;
  920. }
  921. static int snd_wss_capture_hw_params(struct snd_pcm_substream *substream,
  922. struct snd_pcm_hw_params *hw_params)
  923. {
  924. struct snd_wss *chip = snd_pcm_substream_chip(substream);
  925. unsigned char new_cdfr;
  926. int err;
  927. if ((err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params))) < 0)
  928. return err;
  929. new_cdfr = snd_wss_get_format(chip, params_format(hw_params),
  930. params_channels(hw_params)) |
  931. snd_wss_get_rate(params_rate(hw_params));
  932. chip->set_capture_format(chip, hw_params, new_cdfr);
  933. return 0;
  934. }
  935. static int snd_wss_capture_hw_free(struct snd_pcm_substream *substream)
  936. {
  937. return snd_pcm_lib_free_pages(substream);
  938. }
  939. static int snd_wss_capture_prepare(struct snd_pcm_substream *substream)
  940. {
  941. struct snd_wss *chip = snd_pcm_substream_chip(substream);
  942. struct snd_pcm_runtime *runtime = substream->runtime;
  943. unsigned long flags;
  944. unsigned int size = snd_pcm_lib_buffer_bytes(substream);
  945. unsigned int count = snd_pcm_lib_period_bytes(substream);
  946. spin_lock_irqsave(&chip->reg_lock, flags);
  947. chip->c_dma_size = size;
  948. chip->image[CS4231_IFACE_CTRL] &= ~(CS4231_RECORD_ENABLE | CS4231_RECORD_PIO);
  949. snd_dma_program(chip->dma2, runtime->dma_addr, size, DMA_MODE_READ | DMA_AUTOINIT);
  950. if (chip->hardware & WSS_HW_AD1848_MASK)
  951. count = snd_wss_get_count(chip->image[CS4231_PLAYBK_FORMAT],
  952. count);
  953. else
  954. count = snd_wss_get_count(chip->image[CS4231_REC_FORMAT],
  955. count);
  956. count--;
  957. if (chip->single_dma && chip->hardware != WSS_HW_INTERWAVE) {
  958. snd_wss_out(chip, CS4231_PLY_LWR_CNT, (unsigned char) count);
  959. snd_wss_out(chip, CS4231_PLY_UPR_CNT,
  960. (unsigned char) (count >> 8));
  961. } else {
  962. snd_wss_out(chip, CS4231_REC_LWR_CNT, (unsigned char) count);
  963. snd_wss_out(chip, CS4231_REC_UPR_CNT,
  964. (unsigned char) (count >> 8));
  965. }
  966. spin_unlock_irqrestore(&chip->reg_lock, flags);
  967. return 0;
  968. }
  969. void snd_wss_overrange(struct snd_wss *chip)
  970. {
  971. unsigned long flags;
  972. unsigned char res;
  973. spin_lock_irqsave(&chip->reg_lock, flags);
  974. res = snd_wss_in(chip, CS4231_TEST_INIT);
  975. spin_unlock_irqrestore(&chip->reg_lock, flags);
  976. if (res & (0x08 | 0x02)) /* detect overrange only above 0dB; may be user selectable? */
  977. chip->capture_substream->runtime->overrange++;
  978. }
  979. EXPORT_SYMBOL(snd_wss_overrange);
  980. irqreturn_t snd_wss_interrupt(int irq, void *dev_id)
  981. {
  982. struct snd_wss *chip = dev_id;
  983. unsigned char status;
  984. if (chip->hardware & WSS_HW_AD1848_MASK)
  985. /* pretend it was the only possible irq for AD1848 */
  986. status = CS4231_PLAYBACK_IRQ;
  987. else
  988. status = snd_wss_in(chip, CS4231_IRQ_STATUS);
  989. if (status & CS4231_TIMER_IRQ) {
  990. if (chip->timer)
  991. snd_timer_interrupt(chip->timer, chip->timer->sticks);
  992. }
  993. if (chip->single_dma && chip->hardware != WSS_HW_INTERWAVE) {
  994. if (status & CS4231_PLAYBACK_IRQ) {
  995. if (chip->mode & WSS_MODE_PLAY) {
  996. if (chip->playback_substream)
  997. snd_pcm_period_elapsed(chip->playback_substream);
  998. }
  999. if (chip->mode & WSS_MODE_RECORD) {
  1000. if (chip->capture_substream) {
  1001. snd_wss_overrange(chip);
  1002. snd_pcm_period_elapsed(chip->capture_substream);
  1003. }
  1004. }
  1005. }
  1006. } else {
  1007. if (status & CS4231_PLAYBACK_IRQ) {
  1008. if (chip->playback_substream)
  1009. snd_pcm_period_elapsed(chip->playback_substream);
  1010. }
  1011. if (status & CS4231_RECORD_IRQ) {
  1012. if (chip->capture_substream) {
  1013. snd_wss_overrange(chip);
  1014. snd_pcm_period_elapsed(chip->capture_substream);
  1015. }
  1016. }
  1017. }
  1018. spin_lock(&chip->reg_lock);
  1019. status = ~CS4231_ALL_IRQS | ~status;
  1020. if (chip->hardware & WSS_HW_AD1848_MASK)
  1021. wss_outb(chip, CS4231P(STATUS), 0);
  1022. else
  1023. snd_wss_outm(chip, CS4231_IRQ_STATUS, status, 0);
  1024. spin_unlock(&chip->reg_lock);
  1025. return IRQ_HANDLED;
  1026. }
  1027. EXPORT_SYMBOL(snd_wss_interrupt);
  1028. static snd_pcm_uframes_t snd_wss_playback_pointer(struct snd_pcm_substream *substream)
  1029. {
  1030. struct snd_wss *chip = snd_pcm_substream_chip(substream);
  1031. size_t ptr;
  1032. if (!(chip->image[CS4231_IFACE_CTRL] & CS4231_PLAYBACK_ENABLE))
  1033. return 0;
  1034. ptr = snd_dma_pointer(chip->dma1, chip->p_dma_size);
  1035. return bytes_to_frames(substream->runtime, ptr);
  1036. }
  1037. static snd_pcm_uframes_t snd_wss_capture_pointer(struct snd_pcm_substream *substream)
  1038. {
  1039. struct snd_wss *chip = snd_pcm_substream_chip(substream);
  1040. size_t ptr;
  1041. if (!(chip->image[CS4231_IFACE_CTRL] & CS4231_RECORD_ENABLE))
  1042. return 0;
  1043. ptr = snd_dma_pointer(chip->dma2, chip->c_dma_size);
  1044. return bytes_to_frames(substream->runtime, ptr);
  1045. }
  1046. /*
  1047. */
  1048. static int snd_ad1848_probe(struct snd_wss *chip)
  1049. {
  1050. unsigned long timeout = jiffies + msecs_to_jiffies(1000);
  1051. unsigned long flags;
  1052. unsigned char r;
  1053. unsigned short hardware = 0;
  1054. int err = 0;
  1055. int i;
  1056. while (wss_inb(chip, CS4231P(REGSEL)) & CS4231_INIT) {
  1057. if (time_after(jiffies, timeout))
  1058. return -ENODEV;
  1059. cond_resched();
  1060. }
  1061. spin_lock_irqsave(&chip->reg_lock, flags);
  1062. /* set CS423x MODE 1 */
  1063. snd_wss_dout(chip, CS4231_MISC_INFO, 0);
  1064. snd_wss_dout(chip, CS4231_RIGHT_INPUT, 0x45); /* 0x55 & ~0x10 */
  1065. r = snd_wss_in(chip, CS4231_RIGHT_INPUT);
  1066. if (r != 0x45) {
  1067. /* RMGE always high on AD1847 */
  1068. if ((r & ~CS4231_ENABLE_MIC_GAIN) != 0x45) {
  1069. err = -ENODEV;
  1070. goto out;
  1071. }
  1072. hardware = WSS_HW_AD1847;
  1073. } else {
  1074. snd_wss_dout(chip, CS4231_LEFT_INPUT, 0xaa);
  1075. r = snd_wss_in(chip, CS4231_LEFT_INPUT);
  1076. /* L/RMGE always low on AT2320 */
  1077. if ((r | CS4231_ENABLE_MIC_GAIN) != 0xaa) {
  1078. err = -ENODEV;
  1079. goto out;
  1080. }
  1081. }
  1082. /* clear pending IRQ */
  1083. wss_inb(chip, CS4231P(STATUS));
  1084. wss_outb(chip, CS4231P(STATUS), 0);
  1085. mb();
  1086. if ((chip->hardware & WSS_HW_TYPE_MASK) != WSS_HW_DETECT)
  1087. goto out;
  1088. if (hardware) {
  1089. chip->hardware = hardware;
  1090. goto out;
  1091. }
  1092. r = snd_wss_in(chip, CS4231_MISC_INFO);
  1093. /* set CS423x MODE 2 */
  1094. snd_wss_dout(chip, CS4231_MISC_INFO, CS4231_MODE2);
  1095. for (i = 0; i < 16; i++) {
  1096. if (snd_wss_in(chip, i) != snd_wss_in(chip, 16 + i)) {
  1097. /* we have more than 16 registers: check ID */
  1098. if ((r & 0xf) != 0xa)
  1099. goto out_mode;
  1100. /*
  1101. * on CMI8330, CS4231_VERSION is volume control and
  1102. * can be set to 0
  1103. */
  1104. snd_wss_dout(chip, CS4231_VERSION, 0);
  1105. r = snd_wss_in(chip, CS4231_VERSION) & 0xe7;
  1106. if (!r)
  1107. chip->hardware = WSS_HW_CMI8330;
  1108. goto out_mode;
  1109. }
  1110. }
  1111. if (r & 0x80)
  1112. chip->hardware = WSS_HW_CS4248;
  1113. else
  1114. chip->hardware = WSS_HW_AD1848;
  1115. out_mode:
  1116. snd_wss_dout(chip, CS4231_MISC_INFO, 0);
  1117. out:
  1118. spin_unlock_irqrestore(&chip->reg_lock, flags);
  1119. return err;
  1120. }
  1121. static int snd_wss_probe(struct snd_wss *chip)
  1122. {
  1123. unsigned long flags;
  1124. int i, id, rev, regnum;
  1125. unsigned char *ptr;
  1126. unsigned int hw;
  1127. id = snd_ad1848_probe(chip);
  1128. if (id < 0)
  1129. return id;
  1130. hw = chip->hardware;
  1131. if ((hw & WSS_HW_TYPE_MASK) == WSS_HW_DETECT) {
  1132. for (i = 0; i < 50; i++) {
  1133. mb();
  1134. if (wss_inb(chip, CS4231P(REGSEL)) & CS4231_INIT)
  1135. msleep(2);
  1136. else {
  1137. spin_lock_irqsave(&chip->reg_lock, flags);
  1138. snd_wss_out(chip, CS4231_MISC_INFO,
  1139. CS4231_MODE2);
  1140. id = snd_wss_in(chip, CS4231_MISC_INFO) & 0x0f;
  1141. spin_unlock_irqrestore(&chip->reg_lock, flags);
  1142. if (id == 0x0a)
  1143. break; /* this is valid value */
  1144. }
  1145. }
  1146. snd_printdd("wss: port = 0x%lx, id = 0x%x\n", chip->port, id);
  1147. if (id != 0x0a)
  1148. return -ENODEV; /* no valid device found */
  1149. rev = snd_wss_in(chip, CS4231_VERSION) & 0xe7;
  1150. snd_printdd("CS4231: VERSION (I25) = 0x%x\n", rev);
  1151. if (rev == 0x80) {
  1152. unsigned char tmp = snd_wss_in(chip, 23);
  1153. snd_wss_out(chip, 23, ~tmp);
  1154. if (snd_wss_in(chip, 23) != tmp)
  1155. chip->hardware = WSS_HW_AD1845;
  1156. else
  1157. chip->hardware = WSS_HW_CS4231;
  1158. } else if (rev == 0xa0) {
  1159. chip->hardware = WSS_HW_CS4231A;
  1160. } else if (rev == 0xa2) {
  1161. chip->hardware = WSS_HW_CS4232;
  1162. } else if (rev == 0xb2) {
  1163. chip->hardware = WSS_HW_CS4232A;
  1164. } else if (rev == 0x83) {
  1165. chip->hardware = WSS_HW_CS4236;
  1166. } else if (rev == 0x03) {
  1167. chip->hardware = WSS_HW_CS4236B;
  1168. } else {
  1169. snd_printk(KERN_ERR
  1170. "unknown CS chip with version 0x%x\n", rev);
  1171. return -ENODEV; /* unknown CS4231 chip? */
  1172. }
  1173. }
  1174. spin_lock_irqsave(&chip->reg_lock, flags);
  1175. wss_inb(chip, CS4231P(STATUS)); /* clear any pendings IRQ */
  1176. wss_outb(chip, CS4231P(STATUS), 0);
  1177. mb();
  1178. spin_unlock_irqrestore(&chip->reg_lock, flags);
  1179. if (!(chip->hardware & WSS_HW_AD1848_MASK))
  1180. chip->image[CS4231_MISC_INFO] = CS4231_MODE2;
  1181. switch (chip->hardware) {
  1182. case WSS_HW_INTERWAVE:
  1183. chip->image[CS4231_MISC_INFO] = CS4231_IW_MODE3;
  1184. break;
  1185. case WSS_HW_CS4235:
  1186. case WSS_HW_CS4236B:
  1187. case WSS_HW_CS4237B:
  1188. case WSS_HW_CS4238B:
  1189. case WSS_HW_CS4239:
  1190. if (hw == WSS_HW_DETECT3)
  1191. chip->image[CS4231_MISC_INFO] = CS4231_4236_MODE3;
  1192. else
  1193. chip->hardware = WSS_HW_CS4236;
  1194. break;
  1195. }
  1196. chip->image[CS4231_IFACE_CTRL] =
  1197. (chip->image[CS4231_IFACE_CTRL] & ~CS4231_SINGLE_DMA) |
  1198. (chip->single_dma ? CS4231_SINGLE_DMA : 0);
  1199. if (chip->hardware != WSS_HW_OPTI93X) {
  1200. chip->image[CS4231_ALT_FEATURE_1] = 0x80;
  1201. chip->image[CS4231_ALT_FEATURE_2] =
  1202. chip->hardware == WSS_HW_INTERWAVE ? 0xc2 : 0x01;
  1203. }
  1204. ptr = (unsigned char *) &chip->image;
  1205. regnum = (chip->hardware & WSS_HW_AD1848_MASK) ? 16 : 32;
  1206. snd_wss_mce_down(chip);
  1207. spin_lock_irqsave(&chip->reg_lock, flags);
  1208. for (i = 0; i < regnum; i++) /* ok.. fill all registers */
  1209. snd_wss_out(chip, i, *ptr++);
  1210. spin_unlock_irqrestore(&chip->reg_lock, flags);
  1211. snd_wss_mce_up(chip);
  1212. snd_wss_mce_down(chip);
  1213. mdelay(2);
  1214. /* ok.. try check hardware version for CS4236+ chips */
  1215. if ((hw & WSS_HW_TYPE_MASK) == WSS_HW_DETECT) {
  1216. if (chip->hardware == WSS_HW_CS4236B) {
  1217. rev = snd_cs4236_ext_in(chip, CS4236_VERSION);
  1218. snd_cs4236_ext_out(chip, CS4236_VERSION, 0xff);
  1219. id = snd_cs4236_ext_in(chip, CS4236_VERSION);
  1220. snd_cs4236_ext_out(chip, CS4236_VERSION, rev);
  1221. snd_printdd("CS4231: ext version; rev = 0x%x, id = 0x%x\n", rev, id);
  1222. if ((id & 0x1f) == 0x1d) { /* CS4235 */
  1223. chip->hardware = WSS_HW_CS4235;
  1224. switch (id >> 5) {
  1225. case 4:
  1226. case 5:
  1227. case 6:
  1228. break;
  1229. default:
  1230. snd_printk(KERN_WARNING
  1231. "unknown CS4235 chip "
  1232. "(enhanced version = 0x%x)\n",
  1233. id);
  1234. }
  1235. } else if ((id & 0x1f) == 0x0b) { /* CS4236/B */
  1236. switch (id >> 5) {
  1237. case 4:
  1238. case 5:
  1239. case 6:
  1240. case 7:
  1241. chip->hardware = WSS_HW_CS4236B;
  1242. break;
  1243. default:
  1244. snd_printk(KERN_WARNING
  1245. "unknown CS4236 chip "
  1246. "(enhanced version = 0x%x)\n",
  1247. id);
  1248. }
  1249. } else if ((id & 0x1f) == 0x08) { /* CS4237B */
  1250. chip->hardware = WSS_HW_CS4237B;
  1251. switch (id >> 5) {
  1252. case 4:
  1253. case 5:
  1254. case 6:
  1255. case 7:
  1256. break;
  1257. default:
  1258. snd_printk(KERN_WARNING
  1259. "unknown CS4237B chip "
  1260. "(enhanced version = 0x%x)\n",
  1261. id);
  1262. }
  1263. } else if ((id & 0x1f) == 0x09) { /* CS4238B */
  1264. chip->hardware = WSS_HW_CS4238B;
  1265. switch (id >> 5) {
  1266. case 5:
  1267. case 6:
  1268. case 7:
  1269. break;
  1270. default:
  1271. snd_printk(KERN_WARNING
  1272. "unknown CS4238B chip "
  1273. "(enhanced version = 0x%x)\n",
  1274. id);
  1275. }
  1276. } else if ((id & 0x1f) == 0x1e) { /* CS4239 */
  1277. chip->hardware = WSS_HW_CS4239;
  1278. switch (id >> 5) {
  1279. case 4:
  1280. case 5:
  1281. case 6:
  1282. break;
  1283. default:
  1284. snd_printk(KERN_WARNING
  1285. "unknown CS4239 chip "
  1286. "(enhanced version = 0x%x)\n",
  1287. id);
  1288. }
  1289. } else {
  1290. snd_printk(KERN_WARNING
  1291. "unknown CS4236/CS423xB chip "
  1292. "(enhanced version = 0x%x)\n", id);
  1293. }
  1294. }
  1295. }
  1296. return 0; /* all things are ok.. */
  1297. }
  1298. /*
  1299. */
  1300. static struct snd_pcm_hardware snd_wss_playback =
  1301. {
  1302. .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
  1303. SNDRV_PCM_INFO_MMAP_VALID |
  1304. SNDRV_PCM_INFO_RESUME |
  1305. SNDRV_PCM_INFO_SYNC_START),
  1306. .formats = (SNDRV_PCM_FMTBIT_MU_LAW | SNDRV_PCM_FMTBIT_A_LAW | SNDRV_PCM_FMTBIT_IMA_ADPCM |
  1307. SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S16_BE),
  1308. .rates = SNDRV_PCM_RATE_KNOT | SNDRV_PCM_RATE_8000_48000,
  1309. .rate_min = 5510,
  1310. .rate_max = 48000,
  1311. .channels_min = 1,
  1312. .channels_max = 2,
  1313. .buffer_bytes_max = (128*1024),
  1314. .period_bytes_min = 64,
  1315. .period_bytes_max = (128*1024),
  1316. .periods_min = 1,
  1317. .periods_max = 1024,
  1318. .fifo_size = 0,
  1319. };
  1320. static struct snd_pcm_hardware snd_wss_capture =
  1321. {
  1322. .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
  1323. SNDRV_PCM_INFO_MMAP_VALID |
  1324. SNDRV_PCM_INFO_RESUME |
  1325. SNDRV_PCM_INFO_SYNC_START),
  1326. .formats = (SNDRV_PCM_FMTBIT_MU_LAW | SNDRV_PCM_FMTBIT_A_LAW | SNDRV_PCM_FMTBIT_IMA_ADPCM |
  1327. SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S16_BE),
  1328. .rates = SNDRV_PCM_RATE_KNOT | SNDRV_PCM_RATE_8000_48000,
  1329. .rate_min = 5510,
  1330. .rate_max = 48000,
  1331. .channels_min = 1,
  1332. .channels_max = 2,
  1333. .buffer_bytes_max = (128*1024),
  1334. .period_bytes_min = 64,
  1335. .period_bytes_max = (128*1024),
  1336. .periods_min = 1,
  1337. .periods_max = 1024,
  1338. .fifo_size = 0,
  1339. };
  1340. /*
  1341. */
  1342. static int snd_wss_playback_open(struct snd_pcm_substream *substream)
  1343. {
  1344. struct snd_wss *chip = snd_pcm_substream_chip(substream);
  1345. struct snd_pcm_runtime *runtime = substream->runtime;
  1346. int err;
  1347. runtime->hw = snd_wss_playback;
  1348. /* hardware limitation of older chipsets */
  1349. if (chip->hardware & WSS_HW_AD1848_MASK)
  1350. runtime->hw.formats &= ~(SNDRV_PCM_FMTBIT_IMA_ADPCM |
  1351. SNDRV_PCM_FMTBIT_S16_BE);
  1352. /* hardware bug in InterWave chipset */
  1353. if (chip->hardware == WSS_HW_INTERWAVE && chip->dma1 > 3)
  1354. runtime->hw.formats &= ~SNDRV_PCM_FMTBIT_MU_LAW;
  1355. /* hardware limitation of cheap chips */
  1356. if (chip->hardware == WSS_HW_CS4235 ||
  1357. chip->hardware == WSS_HW_CS4239)
  1358. runtime->hw.formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE;
  1359. snd_pcm_limit_isa_dma_size(chip->dma1, &runtime->hw.buffer_bytes_max);
  1360. snd_pcm_limit_isa_dma_size(chip->dma1, &runtime->hw.period_bytes_max);
  1361. if (chip->claim_dma) {
  1362. if ((err = chip->claim_dma(chip, chip->dma_private_data, chip->dma1)) < 0)
  1363. return err;
  1364. }
  1365. err = snd_wss_open(chip, WSS_MODE_PLAY);
  1366. if (err < 0) {
  1367. if (chip->release_dma)
  1368. chip->release_dma(chip, chip->dma_private_data, chip->dma1);
  1369. snd_free_pages(runtime->dma_area, runtime->dma_bytes);
  1370. return err;
  1371. }
  1372. chip->playback_substream = substream;
  1373. snd_pcm_set_sync(substream);
  1374. chip->rate_constraint(runtime);
  1375. return 0;
  1376. }
  1377. static int snd_wss_capture_open(struct snd_pcm_substream *substream)
  1378. {
  1379. struct snd_wss *chip = snd_pcm_substream_chip(substream);
  1380. struct snd_pcm_runtime *runtime = substream->runtime;
  1381. int err;
  1382. runtime->hw = snd_wss_capture;
  1383. /* hardware limitation of older chipsets */
  1384. if (chip->hardware & WSS_HW_AD1848_MASK)
  1385. runtime->hw.formats &= ~(SNDRV_PCM_FMTBIT_IMA_ADPCM |
  1386. SNDRV_PCM_FMTBIT_S16_BE);
  1387. /* hardware limitation of cheap chips */
  1388. if (chip->hardware == WSS_HW_CS4235 ||
  1389. chip->hardware == WSS_HW_CS4239 ||
  1390. chip->hardware == WSS_HW_OPTI93X)
  1391. runtime->hw.formats = SNDRV_PCM_FMTBIT_U8 |
  1392. SNDRV_PCM_FMTBIT_S16_LE;
  1393. snd_pcm_limit_isa_dma_size(chip->dma2, &runtime->hw.buffer_bytes_max);
  1394. snd_pcm_limit_isa_dma_size(chip->dma2, &runtime->hw.period_bytes_max);
  1395. if (chip->claim_dma) {
  1396. if ((err = chip->claim_dma(chip, chip->dma_private_data, chip->dma2)) < 0)
  1397. return err;
  1398. }
  1399. err = snd_wss_open(chip, WSS_MODE_RECORD);
  1400. if (err < 0) {
  1401. if (chip->release_dma)
  1402. chip->release_dma(chip, chip->dma_private_data, chip->dma2);
  1403. snd_free_pages(runtime->dma_area, runtime->dma_bytes);
  1404. return err;
  1405. }
  1406. chip->capture_substream = substream;
  1407. snd_pcm_set_sync(substream);
  1408. chip->rate_constraint(runtime);
  1409. return 0;
  1410. }
  1411. static int snd_wss_playback_close(struct snd_pcm_substream *substream)
  1412. {
  1413. struct snd_wss *chip = snd_pcm_substream_chip(substream);
  1414. chip->playback_substream = NULL;
  1415. snd_wss_close(chip, WSS_MODE_PLAY);
  1416. return 0;
  1417. }
  1418. static int snd_wss_capture_close(struct snd_pcm_substream *substream)
  1419. {
  1420. struct snd_wss *chip = snd_pcm_substream_chip(substream);
  1421. chip->capture_substream = NULL;
  1422. snd_wss_close(chip, WSS_MODE_RECORD);
  1423. return 0;
  1424. }
  1425. static void snd_wss_thinkpad_twiddle(struct snd_wss *chip, int on)
  1426. {
  1427. int tmp;
  1428. if (!chip->thinkpad_flag)
  1429. return;
  1430. outb(0x1c, AD1848_THINKPAD_CTL_PORT1);
  1431. tmp = inb(AD1848_THINKPAD_CTL_PORT2);
  1432. if (on)
  1433. /* turn it on */
  1434. tmp |= AD1848_THINKPAD_CS4248_ENABLE_BIT;
  1435. else
  1436. /* turn it off */
  1437. tmp &= ~AD1848_THINKPAD_CS4248_ENABLE_BIT;
  1438. outb(tmp, AD1848_THINKPAD_CTL_PORT2);
  1439. }
  1440. #ifdef CONFIG_PM
  1441. /* lowlevel suspend callback for CS4231 */
  1442. static void snd_wss_suspend(struct snd_wss *chip)
  1443. {
  1444. int reg;
  1445. unsigned long flags;
  1446. snd_pcm_suspend_all(chip->pcm);
  1447. spin_lock_irqsave(&chip->reg_lock, flags);
  1448. for (reg = 0; reg < 32; reg++)
  1449. chip->image[reg] = snd_wss_in(chip, reg);
  1450. spin_unlock_irqrestore(&chip->reg_lock, flags);
  1451. if (chip->thinkpad_flag)
  1452. snd_wss_thinkpad_twiddle(chip, 0);
  1453. }
  1454. /* lowlevel resume callback for CS4231 */
  1455. static void snd_wss_resume(struct snd_wss *chip)
  1456. {
  1457. int reg;
  1458. unsigned long flags;
  1459. /* int timeout; */
  1460. if (chip->thinkpad_flag)
  1461. snd_wss_thinkpad_twiddle(chip, 1);
  1462. snd_wss_mce_up(chip);
  1463. spin_lock_irqsave(&chip->reg_lock, flags);
  1464. for (reg = 0; reg < 32; reg++) {
  1465. switch (reg) {
  1466. case CS4231_VERSION:
  1467. break;
  1468. default:
  1469. snd_wss_out(chip, reg, chip->image[reg]);
  1470. break;
  1471. }
  1472. }
  1473. spin_unlock_irqrestore(&chip->reg_lock, flags);
  1474. #if 1
  1475. snd_wss_mce_down(chip);
  1476. #else
  1477. /* The following is a workaround to avoid freeze after resume on TP600E.
  1478. This is the first half of copy of snd_wss_mce_down(), but doesn't
  1479. include rescheduling. -- iwai
  1480. */
  1481. snd_wss_busy_wait(chip);
  1482. spin_lock_irqsave(&chip->reg_lock, flags);
  1483. chip->mce_bit &= ~CS4231_MCE;
  1484. timeout = wss_inb(chip, CS4231P(REGSEL));
  1485. wss_outb(chip, CS4231P(REGSEL), chip->mce_bit | (timeout & 0x1f));
  1486. spin_unlock_irqrestore(&chip->reg_lock, flags);
  1487. if (timeout == 0x80)
  1488. snd_printk(KERN_ERR "down [0x%lx]: serious init problem "
  1489. "- codec still busy\n", chip->port);
  1490. if ((timeout & CS4231_MCE) == 0 ||
  1491. !(chip->hardware & (WSS_HW_CS4231_MASK | WSS_HW_CS4232_MASK))) {
  1492. return;
  1493. }
  1494. snd_wss_busy_wait(chip);
  1495. #endif
  1496. }
  1497. #endif /* CONFIG_PM */
  1498. static int snd_wss_free(struct snd_wss *chip)
  1499. {
  1500. release_and_free_resource(chip->res_port);
  1501. release_and_free_resource(chip->res_cport);
  1502. if (chip->irq >= 0) {
  1503. disable_irq(chip->irq);
  1504. if (!(chip->hwshare & WSS_HWSHARE_IRQ))
  1505. free_irq(chip->irq, (void *) chip);
  1506. }
  1507. if (!(chip->hwshare & WSS_HWSHARE_DMA1) && chip->dma1 >= 0) {
  1508. snd_dma_disable(chip->dma1);
  1509. free_dma(chip->dma1);
  1510. }
  1511. if (!(chip->hwshare & WSS_HWSHARE_DMA2) &&
  1512. chip->dma2 >= 0 && chip->dma2 != chip->dma1) {
  1513. snd_dma_disable(chip->dma2);
  1514. free_dma(chip->dma2);
  1515. }
  1516. if (chip->timer)
  1517. snd_device_free(chip->card, chip->timer);
  1518. kfree(chip);
  1519. return 0;
  1520. }
  1521. static int snd_wss_dev_free(struct snd_device *device)
  1522. {
  1523. struct snd_wss *chip = device->device_data;
  1524. return snd_wss_free(chip);
  1525. }
  1526. const char *snd_wss_chip_id(struct snd_wss *chip)
  1527. {
  1528. switch (chip->hardware) {
  1529. case WSS_HW_CS4231:
  1530. return "CS4231";
  1531. case WSS_HW_CS4231A:
  1532. return "CS4231A";
  1533. case WSS_HW_CS4232:
  1534. return "CS4232";
  1535. case WSS_HW_CS4232A:
  1536. return "CS4232A";
  1537. case WSS_HW_CS4235:
  1538. return "CS4235";
  1539. case WSS_HW_CS4236:
  1540. return "CS4236";
  1541. case WSS_HW_CS4236B:
  1542. return "CS4236B";
  1543. case WSS_HW_CS4237B:
  1544. return "CS4237B";
  1545. case WSS_HW_CS4238B:
  1546. return "CS4238B";
  1547. case WSS_HW_CS4239:
  1548. return "CS4239";
  1549. case WSS_HW_INTERWAVE:
  1550. return "AMD InterWave";
  1551. case WSS_HW_OPL3SA2:
  1552. return chip->card->shortname;
  1553. case WSS_HW_AD1845:
  1554. return "AD1845";
  1555. case WSS_HW_OPTI93X:
  1556. return "OPTi 93x";
  1557. case WSS_HW_AD1847:
  1558. return "AD1847";
  1559. case WSS_HW_AD1848:
  1560. return "AD1848";
  1561. case WSS_HW_CS4248:
  1562. return "CS4248";
  1563. case WSS_HW_CMI8330:
  1564. return "CMI8330/C3D";
  1565. default:
  1566. return "???";
  1567. }
  1568. }
  1569. EXPORT_SYMBOL(snd_wss_chip_id);
  1570. static int snd_wss_new(struct snd_card *card,
  1571. unsigned short hardware,
  1572. unsigned short hwshare,
  1573. struct snd_wss **rchip)
  1574. {
  1575. struct snd_wss *chip;
  1576. *rchip = NULL;
  1577. chip = kzalloc(sizeof(*chip), GFP_KERNEL);
  1578. if (chip == NULL)
  1579. return -ENOMEM;
  1580. chip->hardware = hardware;
  1581. chip->hwshare = hwshare;
  1582. spin_lock_init(&chip->reg_lock);
  1583. mutex_init(&chip->mce_mutex);
  1584. mutex_init(&chip->open_mutex);
  1585. chip->card = card;
  1586. chip->rate_constraint = snd_wss_xrate;
  1587. chip->set_playback_format = snd_wss_playback_format;
  1588. chip->set_capture_format = snd_wss_capture_format;
  1589. if (chip->hardware == WSS_HW_OPTI93X)
  1590. memcpy(&chip->image, &snd_opti93x_original_image,
  1591. sizeof(snd_opti93x_original_image));
  1592. else
  1593. memcpy(&chip->image, &snd_wss_original_image,
  1594. sizeof(snd_wss_original_image));
  1595. if (chip->hardware & WSS_HW_AD1848_MASK) {
  1596. chip->image[CS4231_PIN_CTRL] = 0;
  1597. chip->image[CS4231_TEST_INIT] = 0;
  1598. }
  1599. *rchip = chip;
  1600. return 0;
  1601. }
  1602. int snd_wss_create(struct snd_card *card,
  1603. unsigned long port,
  1604. unsigned long cport,
  1605. int irq, int dma1, int dma2,
  1606. unsigned short hardware,
  1607. unsigned short hwshare,
  1608. struct snd_wss **rchip)
  1609. {
  1610. static struct snd_device_ops ops = {
  1611. .dev_free = snd_wss_dev_free,
  1612. };
  1613. struct snd_wss *chip;
  1614. int err;
  1615. err = snd_wss_new(card, hardware, hwshare, &chip);
  1616. if (err < 0)
  1617. return err;
  1618. chip->irq = -1;
  1619. chip->dma1 = -1;
  1620. chip->dma2 = -1;
  1621. chip->res_port = request_region(port, 4, "WSS");
  1622. if (!chip->res_port) {
  1623. snd_printk(KERN_ERR "wss: can't grab port 0x%lx\n", port);
  1624. snd_wss_free(chip);
  1625. return -EBUSY;
  1626. }
  1627. chip->port = port;
  1628. if ((long)cport >= 0) {
  1629. chip->res_cport = request_region(cport, 8, "CS4232 Control");
  1630. if (!chip->res_cport) {
  1631. snd_printk(KERN_ERR
  1632. "wss: can't grab control port 0x%lx\n", cport);
  1633. snd_wss_free(chip);
  1634. return -ENODEV;
  1635. }
  1636. }
  1637. chip->cport = cport;
  1638. if (!(hwshare & WSS_HWSHARE_IRQ))
  1639. if (request_irq(irq, snd_wss_interrupt, IRQF_DISABLED,
  1640. "WSS", (void *) chip)) {
  1641. snd_printk(KERN_ERR "wss: can't grab IRQ %d\n", irq);
  1642. snd_wss_free(chip);
  1643. return -EBUSY;
  1644. }
  1645. chip->irq = irq;
  1646. if (!(hwshare & WSS_HWSHARE_DMA1) && request_dma(dma1, "WSS - 1")) {
  1647. snd_printk(KERN_ERR "wss: can't grab DMA1 %d\n", dma1);
  1648. snd_wss_free(chip);
  1649. return -EBUSY;
  1650. }
  1651. chip->dma1 = dma1;
  1652. if (!(hwshare & WSS_HWSHARE_DMA2) && dma1 != dma2 &&
  1653. dma2 >= 0 && request_dma(dma2, "WSS - 2")) {
  1654. snd_printk(KERN_ERR "wss: can't grab DMA2 %d\n", dma2);
  1655. snd_wss_free(chip);
  1656. return -EBUSY;
  1657. }
  1658. if (dma1 == dma2 || dma2 < 0) {
  1659. chip->single_dma = 1;
  1660. chip->dma2 = chip->dma1;
  1661. } else
  1662. chip->dma2 = dma2;
  1663. if (hardware == WSS_HW_THINKPAD) {
  1664. chip->thinkpad_flag = 1;
  1665. chip->hardware = WSS_HW_DETECT; /* reset */
  1666. snd_wss_thinkpad_twiddle(chip, 1);
  1667. }
  1668. /* global setup */
  1669. if (snd_wss_probe(chip) < 0) {
  1670. snd_wss_free(chip);
  1671. return -ENODEV;
  1672. }
  1673. snd_wss_init(chip);
  1674. #if 0
  1675. if (chip->hardware & WSS_HW_CS4232_MASK) {
  1676. if (chip->res_cport == NULL)
  1677. snd_printk(KERN_ERR "CS4232 control port features are "
  1678. "not accessible\n");
  1679. }
  1680. #endif
  1681. /* Register device */
  1682. err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
  1683. if (err < 0) {
  1684. snd_wss_free(chip);
  1685. return err;
  1686. }
  1687. #ifdef CONFIG_PM
  1688. /* Power Management */
  1689. chip->suspend = snd_wss_suspend;
  1690. chip->resume = snd_wss_resume;
  1691. #endif
  1692. *rchip = chip;
  1693. return 0;
  1694. }
  1695. EXPORT_SYMBOL(snd_wss_create);
  1696. static struct snd_pcm_ops snd_wss_playback_ops = {
  1697. .open = snd_wss_playback_open,
  1698. .close = snd_wss_playback_close,
  1699. .ioctl = snd_pcm_lib_ioctl,
  1700. .hw_params = snd_wss_playback_hw_params,
  1701. .hw_free = snd_wss_playback_hw_free,
  1702. .prepare = snd_wss_playback_prepare,
  1703. .trigger = snd_wss_trigger,
  1704. .pointer = snd_wss_playback_pointer,
  1705. };
  1706. static struct snd_pcm_ops snd_wss_capture_ops = {
  1707. .open = snd_wss_capture_open,
  1708. .close = snd_wss_capture_close,
  1709. .ioctl = snd_pcm_lib_ioctl,
  1710. .hw_params = snd_wss_capture_hw_params,
  1711. .hw_free = snd_wss_capture_hw_free,
  1712. .prepare = snd_wss_capture_prepare,
  1713. .trigger = snd_wss_trigger,
  1714. .pointer = snd_wss_capture_pointer,
  1715. };
  1716. int snd_wss_pcm(struct snd_wss *chip, int device, struct snd_pcm **rpcm)
  1717. {
  1718. struct snd_pcm *pcm;
  1719. int err;
  1720. err = snd_pcm_new(chip->card, "WSS", device, 1, 1, &pcm);
  1721. if (err < 0)
  1722. return err;
  1723. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_wss_playback_ops);
  1724. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_wss_capture_ops);
  1725. /* global setup */
  1726. pcm->private_data = chip;
  1727. pcm->info_flags = 0;
  1728. if (chip->single_dma)
  1729. pcm->info_flags |= SNDRV_PCM_INFO_HALF_DUPLEX;
  1730. if (chip->hardware != WSS_HW_INTERWAVE)
  1731. pcm->info_flags |= SNDRV_PCM_INFO_JOINT_DUPLEX;
  1732. strcpy(pcm->name, snd_wss_chip_id(chip));
  1733. snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
  1734. snd_dma_isa_data(),
  1735. 64*1024, chip->dma1 > 3 || chip->dma2 > 3 ? 128*1024 : 64*1024);
  1736. chip->pcm = pcm;
  1737. if (rpcm)
  1738. *rpcm = pcm;
  1739. return 0;
  1740. }
  1741. EXPORT_SYMBOL(snd_wss_pcm);
  1742. static void snd_wss_timer_free(struct snd_timer *timer)
  1743. {
  1744. struct snd_wss *chip = timer->private_data;
  1745. chip->timer = NULL;
  1746. }
  1747. int snd_wss_timer(struct snd_wss *chip, int device, struct snd_timer **rtimer)
  1748. {
  1749. struct snd_timer *timer;
  1750. struct snd_timer_id tid;
  1751. int err;
  1752. /* Timer initialization */
  1753. tid.dev_class = SNDRV_TIMER_CLASS_CARD;
  1754. tid.dev_sclass = SNDRV_TIMER_SCLASS_NONE;
  1755. tid.card = chip->card->number;
  1756. tid.device = device;
  1757. tid.subdevice = 0;
  1758. if ((err = snd_timer_new(chip->card, "CS4231", &tid, &timer)) < 0)
  1759. return err;
  1760. strcpy(timer->name, snd_wss_chip_id(chip));
  1761. timer->private_data = chip;
  1762. timer->private_free = snd_wss_timer_free;
  1763. timer->hw = snd_wss_timer_table;
  1764. chip->timer = timer;
  1765. if (rtimer)
  1766. *rtimer = timer;
  1767. return 0;
  1768. }
  1769. EXPORT_SYMBOL(snd_wss_timer);
  1770. /*
  1771. * MIXER part
  1772. */
  1773. static int snd_wss_info_mux(struct snd_kcontrol *kcontrol,
  1774. struct snd_ctl_elem_info *uinfo)
  1775. {
  1776. static char *texts[4] = {
  1777. "Line", "Aux", "Mic", "Mix"
  1778. };
  1779. static char *opl3sa_texts[4] = {
  1780. "Line", "CD", "Mic", "Mix"
  1781. };
  1782. static char *gusmax_texts[4] = {
  1783. "Line", "Synth", "Mic", "Mix"
  1784. };
  1785. char **ptexts = texts;
  1786. struct snd_wss *chip = snd_kcontrol_chip(kcontrol);
  1787. if (snd_BUG_ON(!chip->card))
  1788. return -EINVAL;
  1789. uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
  1790. uinfo->count = 2;
  1791. uinfo->value.enumerated.items = 4;
  1792. if (uinfo->value.enumerated.item > 3)
  1793. uinfo->value.enumerated.item = 3;
  1794. if (!strcmp(chip->card->driver, "GUS MAX"))
  1795. ptexts = gusmax_texts;
  1796. switch (chip->hardware) {
  1797. case WSS_HW_INTERWAVE:
  1798. ptexts = gusmax_texts;
  1799. break;
  1800. case WSS_HW_OPL3SA2:
  1801. ptexts = opl3sa_texts;
  1802. break;
  1803. }
  1804. strcpy(uinfo->value.enumerated.name, ptexts[uinfo->value.enumerated.item]);
  1805. return 0;
  1806. }
  1807. static int snd_wss_get_mux(struct snd_kcontrol *kcontrol,
  1808. struct snd_ctl_elem_value *ucontrol)
  1809. {
  1810. struct snd_wss *chip = snd_kcontrol_chip(kcontrol);
  1811. unsigned long flags;
  1812. spin_lock_irqsave(&chip->reg_lock, flags);
  1813. ucontrol->value.enumerated.item[0] = (chip->image[CS4231_LEFT_INPUT] & CS4231_MIXS_ALL) >> 6;
  1814. ucontrol->value.enumerated.item[1] = (chip->image[CS4231_RIGHT_INPUT] & CS4231_MIXS_ALL) >> 6;
  1815. spin_unlock_irqrestore(&chip->reg_lock, flags);
  1816. return 0;
  1817. }
  1818. static int snd_wss_put_mux(struct snd_kcontrol *kcontrol,
  1819. struct snd_ctl_elem_value *ucontrol)
  1820. {
  1821. struct snd_wss *chip = snd_kcontrol_chip(kcontrol);
  1822. unsigned long flags;
  1823. unsigned short left, right;
  1824. int change;
  1825. if (ucontrol->value.enumerated.item[0] > 3 ||
  1826. ucontrol->value.enumerated.item[1] > 3)
  1827. return -EINVAL;
  1828. left = ucontrol->value.enumerated.item[0] << 6;
  1829. right = ucontrol->value.enumerated.item[1] << 6;
  1830. spin_lock_irqsave(&chip->reg_lock, flags);
  1831. left = (chip->image[CS4231_LEFT_INPUT] & ~CS4231_MIXS_ALL) | left;
  1832. right = (chip->image[CS4231_RIGHT_INPUT] & ~CS4231_MIXS_ALL) | right;
  1833. change = left != chip->image[CS4231_LEFT_INPUT] ||
  1834. right != chip->image[CS4231_RIGHT_INPUT];
  1835. snd_wss_out(chip, CS4231_LEFT_INPUT, left);
  1836. snd_wss_out(chip, CS4231_RIGHT_INPUT, right);
  1837. spin_unlock_irqrestore(&chip->reg_lock, flags);
  1838. return change;
  1839. }
  1840. int snd_wss_info_single(struct snd_kcontrol *kcontrol,
  1841. struct snd_ctl_elem_info *uinfo)
  1842. {
  1843. int mask = (kcontrol->private_value >> 16) & 0xff;
  1844. uinfo->type = mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
  1845. uinfo->count = 1;
  1846. uinfo->value.integer.min = 0;
  1847. uinfo->value.integer.max = mask;
  1848. return 0;
  1849. }
  1850. EXPORT_SYMBOL(snd_wss_info_single);
  1851. int snd_wss_get_single(struct snd_kcontrol *kcontrol,
  1852. struct snd_ctl_elem_value *ucontrol)
  1853. {
  1854. struct snd_wss *chip = snd_kcontrol_chip(kcontrol);
  1855. unsigned long flags;
  1856. int reg = kcontrol->private_value & 0xff;
  1857. int shift = (kcontrol->private_value >> 8) & 0xff;
  1858. int mask = (kcontrol->private_value >> 16) & 0xff;
  1859. int invert = (kcontrol->private_value >> 24) & 0xff;
  1860. spin_lock_irqsave(&chip->reg_lock, flags);
  1861. ucontrol->value.integer.value[0] = (chip->image[reg] >> shift) & mask;
  1862. spin_unlock_irqrestore(&chip->reg_lock, flags);
  1863. if (invert)
  1864. ucontrol->value.integer.value[0] = mask - ucontrol->value.integer.value[0];
  1865. return 0;
  1866. }
  1867. EXPORT_SYMBOL(snd_wss_get_single);
  1868. int snd_wss_put_single(struct snd_kcontrol *kcontrol,
  1869. struct snd_ctl_elem_value *ucontrol)
  1870. {
  1871. struct snd_wss *chip = snd_kcontrol_chip(kcontrol);
  1872. unsigned long flags;
  1873. int reg = kcontrol->private_value & 0xff;
  1874. int shift = (kcontrol->private_value >> 8) & 0xff;
  1875. int mask = (kcontrol->private_value >> 16) & 0xff;
  1876. int invert = (kcontrol->private_value >> 24) & 0xff;
  1877. int change;
  1878. unsigned short val;
  1879. val = (ucontrol->value.integer.value[0] & mask);
  1880. if (invert)
  1881. val = mask - val;
  1882. val <<= shift;
  1883. spin_lock_irqsave(&chip->reg_lock, flags);
  1884. val = (chip->image[reg] & ~(mask << shift)) | val;
  1885. change = val != chip->image[reg];
  1886. snd_wss_out(chip, reg, val);
  1887. spin_unlock_irqrestore(&chip->reg_lock, flags);
  1888. return change;
  1889. }
  1890. EXPORT_SYMBOL(snd_wss_put_single);
  1891. int snd_wss_info_double(struct snd_kcontrol *kcontrol,
  1892. struct snd_ctl_elem_info *uinfo)
  1893. {
  1894. int mask = (kcontrol->private_value >> 24) & 0xff;
  1895. uinfo->type = mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
  1896. uinfo->count = 2;
  1897. uinfo->value.integer.min = 0;
  1898. uinfo->value.integer.max = mask;
  1899. return 0;
  1900. }
  1901. EXPORT_SYMBOL(snd_wss_info_double);
  1902. int snd_wss_get_double(struct snd_kcontrol *kcontrol,
  1903. struct snd_ctl_elem_value *ucontrol)
  1904. {
  1905. struct snd_wss *chip = snd_kcontrol_chip(kcontrol);
  1906. unsigned long flags;
  1907. int left_reg = kcontrol->private_value & 0xff;
  1908. int right_reg = (kcontrol->private_value >> 8) & 0xff;
  1909. int shift_left = (kcontrol->private_value >> 16) & 0x07;
  1910. int shift_right = (kcontrol->private_value >> 19) & 0x07;
  1911. int mask = (kcontrol->private_value >> 24) & 0xff;
  1912. int invert = (kcontrol->private_value >> 22) & 1;
  1913. spin_lock_irqsave(&chip->reg_lock, flags);
  1914. ucontrol->value.integer.value[0] = (chip->image[left_reg] >> shift_left) & mask;
  1915. ucontrol->value.integer.value[1] = (chip->image[right_reg] >> shift_right) & mask;
  1916. spin_unlock_irqrestore(&chip->reg_lock, flags);
  1917. if (invert) {
  1918. ucontrol->value.integer.value[0] = mask - ucontrol->value.integer.value[0];
  1919. ucontrol->value.integer.value[1] = mask - ucontrol->value.integer.value[1];
  1920. }
  1921. return 0;
  1922. }
  1923. EXPORT_SYMBOL(snd_wss_get_double);
  1924. int snd_wss_put_double(struct snd_kcontrol *kcontrol,
  1925. struct snd_ctl_elem_value *ucontrol)
  1926. {
  1927. struct snd_wss *chip = snd_kcontrol_chip(kcontrol);
  1928. unsigned long flags;
  1929. int left_reg = kcontrol->private_value & 0xff;
  1930. int right_reg = (kcontrol->private_value >> 8) & 0xff;
  1931. int shift_left = (kcontrol->private_value >> 16) & 0x07;
  1932. int shift_right = (kcontrol->private_value >> 19) & 0x07;
  1933. int mask = (kcontrol->private_value >> 24) & 0xff;
  1934. int invert = (kcontrol->private_value >> 22) & 1;
  1935. int change;
  1936. unsigned short val1, val2;
  1937. val1 = ucontrol->value.integer.value[0] & mask;
  1938. val2 = ucontrol->value.integer.value[1] & mask;
  1939. if (invert) {
  1940. val1 = mask - val1;
  1941. val2 = mask - val2;
  1942. }
  1943. val1 <<= shift_left;
  1944. val2 <<= shift_right;
  1945. spin_lock_irqsave(&chip->reg_lock, flags);
  1946. if (left_reg != right_reg) {
  1947. val1 = (chip->image[left_reg] & ~(mask << shift_left)) | val1;
  1948. val2 = (chip->image[right_reg] & ~(mask << shift_right)) | val2;
  1949. change = val1 != chip->image[left_reg] ||
  1950. val2 != chip->image[right_reg];
  1951. snd_wss_out(chip, left_reg, val1);
  1952. snd_wss_out(chip, right_reg, val2);
  1953. } else {
  1954. mask = (mask << shift_left) | (mask << shift_right);
  1955. val1 = (chip->image[left_reg] & ~mask) | val1 | val2;
  1956. change = val1 != chip->image[left_reg];
  1957. snd_wss_out(chip, left_reg, val1);
  1958. }
  1959. spin_unlock_irqrestore(&chip->reg_lock, flags);
  1960. return change;
  1961. }
  1962. EXPORT_SYMBOL(snd_wss_put_double);
  1963. static const DECLARE_TLV_DB_SCALE(db_scale_6bit, -9450, 150, 0);
  1964. static const DECLARE_TLV_DB_SCALE(db_scale_5bit_12db_max, -3450, 150, 0);
  1965. static const DECLARE_TLV_DB_SCALE(db_scale_rec_gain, 0, 150, 0);
  1966. static struct snd_kcontrol_new snd_ad1848_controls[] = {
  1967. WSS_DOUBLE("PCM Playback Switch", 0, CS4231_LEFT_OUTPUT, CS4231_RIGHT_OUTPUT,
  1968. 7, 7, 1, 1),
  1969. WSS_DOUBLE_TLV("PCM Playback Volume", 0,
  1970. CS4231_LEFT_OUTPUT, CS4231_RIGHT_OUTPUT, 0, 0, 63, 1,
  1971. db_scale_6bit),
  1972. WSS_DOUBLE("Aux Playback Switch", 0,
  1973. CS4231_AUX1_LEFT_INPUT, CS4231_AUX1_RIGHT_INPUT, 7, 7, 1, 1),
  1974. WSS_DOUBLE_TLV("Aux Playback Volume", 0,
  1975. CS4231_AUX1_LEFT_INPUT, CS4231_AUX1_RIGHT_INPUT, 0, 0, 31, 1,
  1976. db_scale_5bit_12db_max),
  1977. WSS_DOUBLE("Aux Playback Switch", 1,
  1978. CS4231_AUX2_LEFT_INPUT, CS4231_AUX2_RIGHT_INPUT, 7, 7, 1, 1),
  1979. WSS_DOUBLE_TLV("Aux Playback Volume", 1,
  1980. CS4231_AUX2_LEFT_INPUT, CS4231_AUX2_RIGHT_INPUT, 0, 0, 31, 1,
  1981. db_scale_5bit_12db_max),
  1982. WSS_DOUBLE_TLV("Capture Volume", 0, CS4231_LEFT_INPUT, CS4231_RIGHT_INPUT,
  1983. 0, 0, 15, 0, db_scale_rec_gain),
  1984. {
  1985. .name = "Capture Source",
  1986. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1987. .info = snd_wss_info_mux,
  1988. .get = snd_wss_get_mux,
  1989. .put = snd_wss_put_mux,
  1990. },
  1991. WSS_SINGLE("Loopback Capture Switch", 0, CS4231_LOOPBACK, 0, 1, 0),
  1992. WSS_SINGLE_TLV("Loopback Capture Volume", 0, CS4231_LOOPBACK, 1, 63, 0,
  1993. db_scale_6bit),
  1994. };
  1995. static struct snd_kcontrol_new snd_wss_controls[] = {
  1996. WSS_DOUBLE("PCM Playback Switch", 0,
  1997. CS4231_LEFT_OUTPUT, CS4231_RIGHT_OUTPUT, 7, 7, 1, 1),
  1998. WSS_DOUBLE("PCM Playback Volume", 0,
  1999. CS4231_LEFT_OUTPUT, CS4231_RIGHT_OUTPUT, 0, 0, 63, 1),
  2000. WSS_DOUBLE("Line Playback Switch", 0,
  2001. CS4231_LEFT_LINE_IN, CS4231_RIGHT_LINE_IN, 7, 7, 1, 1),
  2002. WSS_DOUBLE("Line Playback Volume", 0,
  2003. CS4231_LEFT_LINE_IN, CS4231_RIGHT_LINE_IN, 0, 0, 31, 1),
  2004. WSS_DOUBLE("Aux Playback Switch", 0,
  2005. CS4231_AUX1_LEFT_INPUT, CS4231_AUX1_RIGHT_INPUT, 7, 7, 1, 1),
  2006. WSS_DOUBLE("Aux Playback Volume", 0,
  2007. CS4231_AUX1_LEFT_INPUT, CS4231_AUX1_RIGHT_INPUT, 0, 0, 31, 1),
  2008. WSS_DOUBLE("Aux Playback Switch", 1,
  2009. CS4231_AUX2_LEFT_INPUT, CS4231_AUX2_RIGHT_INPUT, 7, 7, 1, 1),
  2010. WSS_DOUBLE("Aux Playback Volume", 1,
  2011. CS4231_AUX2_LEFT_INPUT, CS4231_AUX2_RIGHT_INPUT, 0, 0, 31, 1),
  2012. WSS_SINGLE("Mono Playback Switch", 0,
  2013. CS4231_MONO_CTRL, 7, 1, 1),
  2014. WSS_SINGLE("Mono Playback Volume", 0,
  2015. CS4231_MONO_CTRL, 0, 15, 1),
  2016. WSS_SINGLE("Mono Output Playback Switch", 0,
  2017. CS4231_MONO_CTRL, 6, 1, 1),
  2018. WSS_SINGLE("Mono Output Playback Bypass", 0,
  2019. CS4231_MONO_CTRL, 5, 1, 0),
  2020. WSS_DOUBLE("Capture Volume", 0,
  2021. CS4231_LEFT_INPUT, CS4231_RIGHT_INPUT, 0, 0, 15, 0),
  2022. {
  2023. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  2024. .name = "Capture Source",
  2025. .info = snd_wss_info_mux,
  2026. .get = snd_wss_get_mux,
  2027. .put = snd_wss_put_mux,
  2028. },
  2029. WSS_DOUBLE("Mic Boost", 0,
  2030. CS4231_LEFT_INPUT, CS4231_RIGHT_INPUT, 5, 5, 1, 0),
  2031. WSS_SINGLE("Loopback Capture Switch", 0,
  2032. CS4231_LOOPBACK, 0, 1, 0),
  2033. WSS_SINGLE("Loopback Capture Volume", 0,
  2034. CS4231_LOOPBACK, 2, 63, 1)
  2035. };
  2036. static struct snd_kcontrol_new snd_opti93x_controls[] = {
  2037. WSS_DOUBLE("Master Playback Switch", 0,
  2038. OPTi93X_OUT_LEFT, OPTi93X_OUT_RIGHT, 7, 7, 1, 1),
  2039. WSS_DOUBLE("Master Playback Volume", 0,
  2040. OPTi93X_OUT_LEFT, OPTi93X_OUT_RIGHT, 1, 1, 31, 1),
  2041. WSS_DOUBLE("PCM Playback Switch", 0,
  2042. CS4231_LEFT_OUTPUT, CS4231_RIGHT_OUTPUT, 7, 7, 1, 1),
  2043. WSS_DOUBLE("PCM Playback Volume", 0,
  2044. CS4231_LEFT_OUTPUT, CS4231_RIGHT_OUTPUT, 0, 0, 31, 1),
  2045. WSS_DOUBLE("FM Playback Switch", 0,
  2046. CS4231_AUX2_LEFT_INPUT, CS4231_AUX2_RIGHT_INPUT, 7, 7, 1, 1),
  2047. WSS_DOUBLE("FM Playback Volume", 0,
  2048. CS4231_AUX2_LEFT_INPUT, CS4231_AUX2_RIGHT_INPUT, 1, 1, 15, 1),
  2049. WSS_DOUBLE("Line Playback Switch", 0,
  2050. CS4231_LEFT_LINE_IN, CS4231_RIGHT_LINE_IN, 7, 7, 1, 1),
  2051. WSS_DOUBLE("Line Playback Volume", 0,
  2052. CS4231_LEFT_LINE_IN, CS4231_RIGHT_LINE_IN, 0, 0, 15, 1),
  2053. WSS_DOUBLE("Mic Playback Switch", 0,
  2054. OPTi93X_MIC_LEFT_INPUT, OPTi93X_MIC_RIGHT_INPUT, 7, 7, 1, 1),
  2055. WSS_DOUBLE("Mic Playback Volume", 0,
  2056. OPTi93X_MIC_LEFT_INPUT, OPTi93X_MIC_RIGHT_INPUT, 1, 1, 15, 1),
  2057. WSS_DOUBLE("Mic Boost", 0,
  2058. CS4231_LEFT_INPUT, CS4231_RIGHT_INPUT, 5, 5, 1, 0),
  2059. WSS_DOUBLE("CD Playback Switch", 0,
  2060. CS4231_AUX1_LEFT_INPUT, CS4231_AUX1_RIGHT_INPUT, 7, 7, 1, 1),
  2061. WSS_DOUBLE("CD Playback Volume", 0,
  2062. CS4231_AUX1_LEFT_INPUT, CS4231_AUX1_RIGHT_INPUT, 1, 1, 15, 1),
  2063. WSS_DOUBLE("Aux Playback Switch", 0,
  2064. OPTi931_AUX_LEFT_INPUT, OPTi931_AUX_RIGHT_INPUT, 7, 7, 1, 1),
  2065. WSS_DOUBLE("Aux Playback Volume", 0,
  2066. OPTi931_AUX_LEFT_INPUT, OPTi931_AUX_RIGHT_INPUT, 1, 1, 15, 1),
  2067. WSS_DOUBLE("Capture Volume", 0,
  2068. CS4231_LEFT_INPUT, CS4231_RIGHT_INPUT, 0, 0, 15, 0),
  2069. {
  2070. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  2071. .name = "Capture Source",
  2072. .info = snd_wss_info_mux,
  2073. .get = snd_wss_get_mux,
  2074. .put = snd_wss_put_mux,
  2075. }
  2076. };
  2077. int snd_wss_mixer(struct snd_wss *chip)
  2078. {
  2079. struct snd_card *card;
  2080. unsigned int idx;
  2081. int err;
  2082. if (snd_BUG_ON(!chip || !chip->pcm))
  2083. return -EINVAL;
  2084. card = chip->card;
  2085. strcpy(card->mixername, chip->pcm->name);
  2086. if (chip->hardware == WSS_HW_OPTI93X)
  2087. for (idx = 0; idx < ARRAY_SIZE(snd_opti93x_controls); idx++) {
  2088. err = snd_ctl_add(card,
  2089. snd_ctl_new1(&snd_opti93x_controls[idx],
  2090. chip));
  2091. if (err < 0)
  2092. return err;
  2093. }
  2094. else if (chip->hardware & WSS_HW_AD1848_MASK)
  2095. for (idx = 0; idx < ARRAY_SIZE(snd_ad1848_controls); idx++) {
  2096. err = snd_ctl_add(card,
  2097. snd_ctl_new1(&snd_ad1848_controls[idx],
  2098. chip));
  2099. if (err < 0)
  2100. return err;
  2101. }
  2102. else
  2103. for (idx = 0; idx < ARRAY_SIZE(snd_wss_controls); idx++) {
  2104. err = snd_ctl_add(card,
  2105. snd_ctl_new1(&snd_wss_controls[idx],
  2106. chip));
  2107. if (err < 0)
  2108. return err;
  2109. }
  2110. return 0;
  2111. }
  2112. EXPORT_SYMBOL(snd_wss_mixer);
  2113. const struct snd_pcm_ops *snd_wss_get_pcm_ops(int direction)
  2114. {
  2115. return direction == SNDRV_PCM_STREAM_PLAYBACK ?
  2116. &snd_wss_playback_ops : &snd_wss_capture_ops;
  2117. }
  2118. EXPORT_SYMBOL(snd_wss_get_pcm_ops);
  2119. /*
  2120. * INIT part
  2121. */
  2122. static int __init alsa_wss_init(void)
  2123. {
  2124. return 0;
  2125. }
  2126. static void __exit alsa_wss_exit(void)
  2127. {
  2128. }
  2129. module_init(alsa_wss_init);
  2130. module_exit(alsa_wss_exit);