iwl-agn.c 111 KB

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  1. /******************************************************************************
  2. *
  3. * Copyright(c) 2003 - 2010 Intel Corporation. All rights reserved.
  4. *
  5. * Portions of this file are derived from the ipw3945 project, as well
  6. * as portions of the ieee80211 subsystem header files.
  7. *
  8. * This program is free software; you can redistribute it and/or modify it
  9. * under the terms of version 2 of the GNU General Public License as
  10. * published by the Free Software Foundation.
  11. *
  12. * This program is distributed in the hope that it will be useful, but WITHOUT
  13. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  15. * more details.
  16. *
  17. * You should have received a copy of the GNU General Public License along with
  18. * this program; if not, write to the Free Software Foundation, Inc.,
  19. * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  20. *
  21. * The full GNU General Public License is included in this distribution in the
  22. * file called LICENSE.
  23. *
  24. * Contact Information:
  25. * Intel Linux Wireless <ilw@linux.intel.com>
  26. * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27. *
  28. *****************************************************************************/
  29. #include <linux/kernel.h>
  30. #include <linux/module.h>
  31. #include <linux/init.h>
  32. #include <linux/pci.h>
  33. #include <linux/dma-mapping.h>
  34. #include <linux/delay.h>
  35. #include <linux/sched.h>
  36. #include <linux/skbuff.h>
  37. #include <linux/netdevice.h>
  38. #include <linux/wireless.h>
  39. #include <linux/firmware.h>
  40. #include <linux/etherdevice.h>
  41. #include <linux/if_arp.h>
  42. #include <net/mac80211.h>
  43. #include <asm/div64.h>
  44. #define DRV_NAME "iwlagn"
  45. #include "iwl-eeprom.h"
  46. #include "iwl-dev.h"
  47. #include "iwl-core.h"
  48. #include "iwl-io.h"
  49. #include "iwl-helpers.h"
  50. #include "iwl-sta.h"
  51. #include "iwl-calib.h"
  52. #include "iwl-agn.h"
  53. /******************************************************************************
  54. *
  55. * module boiler plate
  56. *
  57. ******************************************************************************/
  58. /*
  59. * module name, copyright, version, etc.
  60. */
  61. #define DRV_DESCRIPTION "Intel(R) Wireless WiFi Link AGN driver for Linux"
  62. #ifdef CONFIG_IWLWIFI_DEBUG
  63. #define VD "d"
  64. #else
  65. #define VD
  66. #endif
  67. #define DRV_VERSION IWLWIFI_VERSION VD
  68. MODULE_DESCRIPTION(DRV_DESCRIPTION);
  69. MODULE_VERSION(DRV_VERSION);
  70. MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
  71. MODULE_LICENSE("GPL");
  72. MODULE_ALIAS("iwl4965");
  73. /*************** STATION TABLE MANAGEMENT ****
  74. * mac80211 should be examined to determine if sta_info is duplicating
  75. * the functionality provided here
  76. */
  77. /**************************************************************/
  78. /**
  79. * iwl_commit_rxon - commit staging_rxon to hardware
  80. *
  81. * The RXON command in staging_rxon is committed to the hardware and
  82. * the active_rxon structure is updated with the new data. This
  83. * function correctly transitions out of the RXON_ASSOC_MSK state if
  84. * a HW tune is required based on the RXON structure changes.
  85. */
  86. int iwl_commit_rxon(struct iwl_priv *priv)
  87. {
  88. /* cast away the const for active_rxon in this function */
  89. struct iwl_rxon_cmd *active_rxon = (void *)&priv->active_rxon;
  90. int ret;
  91. bool new_assoc =
  92. !!(priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK);
  93. if (!iwl_is_alive(priv))
  94. return -EBUSY;
  95. /* always get timestamp with Rx frame */
  96. priv->staging_rxon.flags |= RXON_FLG_TSF2HOST_MSK;
  97. ret = iwl_check_rxon_cmd(priv);
  98. if (ret) {
  99. IWL_ERR(priv, "Invalid RXON configuration. Not committing.\n");
  100. return -EINVAL;
  101. }
  102. /*
  103. * receive commit_rxon request
  104. * abort any previous channel switch if still in process
  105. */
  106. if (priv->switch_rxon.switch_in_progress &&
  107. (priv->switch_rxon.channel != priv->staging_rxon.channel)) {
  108. IWL_DEBUG_11H(priv, "abort channel switch on %d\n",
  109. le16_to_cpu(priv->switch_rxon.channel));
  110. priv->switch_rxon.switch_in_progress = false;
  111. }
  112. /* If we don't need to send a full RXON, we can use
  113. * iwl_rxon_assoc_cmd which is used to reconfigure filter
  114. * and other flags for the current radio configuration. */
  115. if (!iwl_full_rxon_required(priv)) {
  116. ret = iwl_send_rxon_assoc(priv);
  117. if (ret) {
  118. IWL_ERR(priv, "Error setting RXON_ASSOC (%d)\n", ret);
  119. return ret;
  120. }
  121. memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
  122. iwl_print_rx_config_cmd(priv);
  123. return 0;
  124. }
  125. /* station table will be cleared */
  126. priv->assoc_station_added = 0;
  127. /* If we are currently associated and the new config requires
  128. * an RXON_ASSOC and the new config wants the associated mask enabled,
  129. * we must clear the associated from the active configuration
  130. * before we apply the new config */
  131. if (iwl_is_associated(priv) && new_assoc) {
  132. IWL_DEBUG_INFO(priv, "Toggling associated bit on current RXON\n");
  133. active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  134. ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
  135. sizeof(struct iwl_rxon_cmd),
  136. &priv->active_rxon);
  137. /* If the mask clearing failed then we set
  138. * active_rxon back to what it was previously */
  139. if (ret) {
  140. active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
  141. IWL_ERR(priv, "Error clearing ASSOC_MSK (%d)\n", ret);
  142. return ret;
  143. }
  144. }
  145. IWL_DEBUG_INFO(priv, "Sending RXON\n"
  146. "* with%s RXON_FILTER_ASSOC_MSK\n"
  147. "* channel = %d\n"
  148. "* bssid = %pM\n",
  149. (new_assoc ? "" : "out"),
  150. le16_to_cpu(priv->staging_rxon.channel),
  151. priv->staging_rxon.bssid_addr);
  152. iwl_set_rxon_hwcrypto(priv, !priv->cfg->mod_params->sw_crypto);
  153. /* Apply the new configuration
  154. * RXON unassoc clears the station table in uCode, send it before
  155. * we add the bcast station. If assoc bit is set, we will send RXON
  156. * after having added the bcast and bssid station.
  157. */
  158. if (!new_assoc) {
  159. ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
  160. sizeof(struct iwl_rxon_cmd), &priv->staging_rxon);
  161. if (ret) {
  162. IWL_ERR(priv, "Error setting new RXON (%d)\n", ret);
  163. return ret;
  164. }
  165. memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
  166. }
  167. iwl_clear_stations_table(priv);
  168. priv->start_calib = 0;
  169. /* Add the broadcast address so we can send broadcast frames */
  170. priv->cfg->ops->lib->add_bcast_station(priv);
  171. /* If we have set the ASSOC_MSK and we are in BSS mode then
  172. * add the IWL_AP_ID to the station rate table */
  173. if (new_assoc) {
  174. if (priv->iw_mode == NL80211_IFTYPE_STATION) {
  175. ret = iwl_rxon_add_station(priv,
  176. priv->active_rxon.bssid_addr, 1);
  177. if (ret == IWL_INVALID_STATION) {
  178. IWL_ERR(priv,
  179. "Error adding AP address for TX.\n");
  180. return -EIO;
  181. }
  182. priv->assoc_station_added = 1;
  183. if (priv->default_wep_key &&
  184. iwl_send_static_wepkey_cmd(priv, 0))
  185. IWL_ERR(priv,
  186. "Could not send WEP static key.\n");
  187. }
  188. /*
  189. * allow CTS-to-self if possible for new association.
  190. * this is relevant only for 5000 series and up,
  191. * but will not damage 4965
  192. */
  193. priv->staging_rxon.flags |= RXON_FLG_SELF_CTS_EN;
  194. /* Apply the new configuration
  195. * RXON assoc doesn't clear the station table in uCode,
  196. */
  197. ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
  198. sizeof(struct iwl_rxon_cmd), &priv->staging_rxon);
  199. if (ret) {
  200. IWL_ERR(priv, "Error setting new RXON (%d)\n", ret);
  201. return ret;
  202. }
  203. memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
  204. }
  205. iwl_print_rx_config_cmd(priv);
  206. iwl_init_sensitivity(priv);
  207. /* If we issue a new RXON command which required a tune then we must
  208. * send a new TXPOWER command or we won't be able to Tx any frames */
  209. ret = iwl_set_tx_power(priv, priv->tx_power_user_lmt, true);
  210. if (ret) {
  211. IWL_ERR(priv, "Error sending TX power (%d)\n", ret);
  212. return ret;
  213. }
  214. return 0;
  215. }
  216. void iwl_update_chain_flags(struct iwl_priv *priv)
  217. {
  218. if (priv->cfg->ops->hcmd->set_rxon_chain)
  219. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  220. iwlcore_commit_rxon(priv);
  221. }
  222. static void iwl_clear_free_frames(struct iwl_priv *priv)
  223. {
  224. struct list_head *element;
  225. IWL_DEBUG_INFO(priv, "%d frames on pre-allocated heap on clear.\n",
  226. priv->frames_count);
  227. while (!list_empty(&priv->free_frames)) {
  228. element = priv->free_frames.next;
  229. list_del(element);
  230. kfree(list_entry(element, struct iwl_frame, list));
  231. priv->frames_count--;
  232. }
  233. if (priv->frames_count) {
  234. IWL_WARN(priv, "%d frames still in use. Did we lose one?\n",
  235. priv->frames_count);
  236. priv->frames_count = 0;
  237. }
  238. }
  239. static struct iwl_frame *iwl_get_free_frame(struct iwl_priv *priv)
  240. {
  241. struct iwl_frame *frame;
  242. struct list_head *element;
  243. if (list_empty(&priv->free_frames)) {
  244. frame = kzalloc(sizeof(*frame), GFP_KERNEL);
  245. if (!frame) {
  246. IWL_ERR(priv, "Could not allocate frame!\n");
  247. return NULL;
  248. }
  249. priv->frames_count++;
  250. return frame;
  251. }
  252. element = priv->free_frames.next;
  253. list_del(element);
  254. return list_entry(element, struct iwl_frame, list);
  255. }
  256. static void iwl_free_frame(struct iwl_priv *priv, struct iwl_frame *frame)
  257. {
  258. memset(frame, 0, sizeof(*frame));
  259. list_add(&frame->list, &priv->free_frames);
  260. }
  261. static u32 iwl_fill_beacon_frame(struct iwl_priv *priv,
  262. struct ieee80211_hdr *hdr,
  263. int left)
  264. {
  265. if (!iwl_is_associated(priv) || !priv->ibss_beacon ||
  266. ((priv->iw_mode != NL80211_IFTYPE_ADHOC) &&
  267. (priv->iw_mode != NL80211_IFTYPE_AP)))
  268. return 0;
  269. if (priv->ibss_beacon->len > left)
  270. return 0;
  271. memcpy(hdr, priv->ibss_beacon->data, priv->ibss_beacon->len);
  272. return priv->ibss_beacon->len;
  273. }
  274. /* Parse the beacon frame to find the TIM element and set tim_idx & tim_size */
  275. static void iwl_set_beacon_tim(struct iwl_priv *priv,
  276. struct iwl_tx_beacon_cmd *tx_beacon_cmd,
  277. u8 *beacon, u32 frame_size)
  278. {
  279. u16 tim_idx;
  280. struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)beacon;
  281. /*
  282. * The index is relative to frame start but we start looking at the
  283. * variable-length part of the beacon.
  284. */
  285. tim_idx = mgmt->u.beacon.variable - beacon;
  286. /* Parse variable-length elements of beacon to find WLAN_EID_TIM */
  287. while ((tim_idx < (frame_size - 2)) &&
  288. (beacon[tim_idx] != WLAN_EID_TIM))
  289. tim_idx += beacon[tim_idx+1] + 2;
  290. /* If TIM field was found, set variables */
  291. if ((tim_idx < (frame_size - 1)) && (beacon[tim_idx] == WLAN_EID_TIM)) {
  292. tx_beacon_cmd->tim_idx = cpu_to_le16(tim_idx);
  293. tx_beacon_cmd->tim_size = beacon[tim_idx+1];
  294. } else
  295. IWL_WARN(priv, "Unable to find TIM Element in beacon\n");
  296. }
  297. static unsigned int iwl_hw_get_beacon_cmd(struct iwl_priv *priv,
  298. struct iwl_frame *frame)
  299. {
  300. struct iwl_tx_beacon_cmd *tx_beacon_cmd;
  301. u32 frame_size;
  302. u32 rate_flags;
  303. u32 rate;
  304. /*
  305. * We have to set up the TX command, the TX Beacon command, and the
  306. * beacon contents.
  307. */
  308. /* Initialize memory */
  309. tx_beacon_cmd = &frame->u.beacon;
  310. memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
  311. /* Set up TX beacon contents */
  312. frame_size = iwl_fill_beacon_frame(priv, tx_beacon_cmd->frame,
  313. sizeof(frame->u) - sizeof(*tx_beacon_cmd));
  314. if (WARN_ON_ONCE(frame_size > MAX_MPDU_SIZE))
  315. return 0;
  316. /* Set up TX command fields */
  317. tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
  318. tx_beacon_cmd->tx.sta_id = priv->hw_params.bcast_sta_id;
  319. tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
  320. tx_beacon_cmd->tx.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK |
  321. TX_CMD_FLG_TSF_MSK | TX_CMD_FLG_STA_RATE_MSK;
  322. /* Set up TX beacon command fields */
  323. iwl_set_beacon_tim(priv, tx_beacon_cmd, (u8 *)tx_beacon_cmd->frame,
  324. frame_size);
  325. /* Set up packet rate and flags */
  326. rate = iwl_rate_get_lowest_plcp(priv);
  327. priv->mgmt_tx_ant = iwl_toggle_tx_ant(priv, priv->mgmt_tx_ant);
  328. rate_flags = iwl_ant_idx_to_flags(priv->mgmt_tx_ant);
  329. if ((rate >= IWL_FIRST_CCK_RATE) && (rate <= IWL_LAST_CCK_RATE))
  330. rate_flags |= RATE_MCS_CCK_MSK;
  331. tx_beacon_cmd->tx.rate_n_flags = iwl_hw_set_rate_n_flags(rate,
  332. rate_flags);
  333. return sizeof(*tx_beacon_cmd) + frame_size;
  334. }
  335. static int iwl_send_beacon_cmd(struct iwl_priv *priv)
  336. {
  337. struct iwl_frame *frame;
  338. unsigned int frame_size;
  339. int rc;
  340. frame = iwl_get_free_frame(priv);
  341. if (!frame) {
  342. IWL_ERR(priv, "Could not obtain free frame buffer for beacon "
  343. "command.\n");
  344. return -ENOMEM;
  345. }
  346. frame_size = iwl_hw_get_beacon_cmd(priv, frame);
  347. if (!frame_size) {
  348. IWL_ERR(priv, "Error configuring the beacon command\n");
  349. iwl_free_frame(priv, frame);
  350. return -EINVAL;
  351. }
  352. rc = iwl_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size,
  353. &frame->u.cmd[0]);
  354. iwl_free_frame(priv, frame);
  355. return rc;
  356. }
  357. static inline dma_addr_t iwl_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx)
  358. {
  359. struct iwl_tfd_tb *tb = &tfd->tbs[idx];
  360. dma_addr_t addr = get_unaligned_le32(&tb->lo);
  361. if (sizeof(dma_addr_t) > sizeof(u32))
  362. addr |=
  363. ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16;
  364. return addr;
  365. }
  366. static inline u16 iwl_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx)
  367. {
  368. struct iwl_tfd_tb *tb = &tfd->tbs[idx];
  369. return le16_to_cpu(tb->hi_n_len) >> 4;
  370. }
  371. static inline void iwl_tfd_set_tb(struct iwl_tfd *tfd, u8 idx,
  372. dma_addr_t addr, u16 len)
  373. {
  374. struct iwl_tfd_tb *tb = &tfd->tbs[idx];
  375. u16 hi_n_len = len << 4;
  376. put_unaligned_le32(addr, &tb->lo);
  377. if (sizeof(dma_addr_t) > sizeof(u32))
  378. hi_n_len |= ((addr >> 16) >> 16) & 0xF;
  379. tb->hi_n_len = cpu_to_le16(hi_n_len);
  380. tfd->num_tbs = idx + 1;
  381. }
  382. static inline u8 iwl_tfd_get_num_tbs(struct iwl_tfd *tfd)
  383. {
  384. return tfd->num_tbs & 0x1f;
  385. }
  386. /**
  387. * iwl_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
  388. * @priv - driver private data
  389. * @txq - tx queue
  390. *
  391. * Does NOT advance any TFD circular buffer read/write indexes
  392. * Does NOT free the TFD itself (which is within circular buffer)
  393. */
  394. void iwl_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
  395. {
  396. struct iwl_tfd *tfd_tmp = (struct iwl_tfd *)txq->tfds;
  397. struct iwl_tfd *tfd;
  398. struct pci_dev *dev = priv->pci_dev;
  399. int index = txq->q.read_ptr;
  400. int i;
  401. int num_tbs;
  402. tfd = &tfd_tmp[index];
  403. /* Sanity check on number of chunks */
  404. num_tbs = iwl_tfd_get_num_tbs(tfd);
  405. if (num_tbs >= IWL_NUM_OF_TBS) {
  406. IWL_ERR(priv, "Too many chunks: %i\n", num_tbs);
  407. /* @todo issue fatal error, it is quite serious situation */
  408. return;
  409. }
  410. /* Unmap tx_cmd */
  411. if (num_tbs)
  412. pci_unmap_single(dev,
  413. pci_unmap_addr(&txq->meta[index], mapping),
  414. pci_unmap_len(&txq->meta[index], len),
  415. PCI_DMA_BIDIRECTIONAL);
  416. /* Unmap chunks, if any. */
  417. for (i = 1; i < num_tbs; i++) {
  418. pci_unmap_single(dev, iwl_tfd_tb_get_addr(tfd, i),
  419. iwl_tfd_tb_get_len(tfd, i), PCI_DMA_TODEVICE);
  420. if (txq->txb) {
  421. dev_kfree_skb(txq->txb[txq->q.read_ptr].skb[i - 1]);
  422. txq->txb[txq->q.read_ptr].skb[i - 1] = NULL;
  423. }
  424. }
  425. }
  426. int iwl_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv,
  427. struct iwl_tx_queue *txq,
  428. dma_addr_t addr, u16 len,
  429. u8 reset, u8 pad)
  430. {
  431. struct iwl_queue *q;
  432. struct iwl_tfd *tfd, *tfd_tmp;
  433. u32 num_tbs;
  434. q = &txq->q;
  435. tfd_tmp = (struct iwl_tfd *)txq->tfds;
  436. tfd = &tfd_tmp[q->write_ptr];
  437. if (reset)
  438. memset(tfd, 0, sizeof(*tfd));
  439. num_tbs = iwl_tfd_get_num_tbs(tfd);
  440. /* Each TFD can point to a maximum 20 Tx buffers */
  441. if (num_tbs >= IWL_NUM_OF_TBS) {
  442. IWL_ERR(priv, "Error can not send more than %d chunks\n",
  443. IWL_NUM_OF_TBS);
  444. return -EINVAL;
  445. }
  446. BUG_ON(addr & ~DMA_BIT_MASK(36));
  447. if (unlikely(addr & ~IWL_TX_DMA_MASK))
  448. IWL_ERR(priv, "Unaligned address = %llx\n",
  449. (unsigned long long)addr);
  450. iwl_tfd_set_tb(tfd, num_tbs, addr, len);
  451. return 0;
  452. }
  453. /*
  454. * Tell nic where to find circular buffer of Tx Frame Descriptors for
  455. * given Tx queue, and enable the DMA channel used for that queue.
  456. *
  457. * 4965 supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA
  458. * channels supported in hardware.
  459. */
  460. int iwl_hw_tx_queue_init(struct iwl_priv *priv,
  461. struct iwl_tx_queue *txq)
  462. {
  463. int txq_id = txq->q.id;
  464. /* Circular buffer (TFD queue in DRAM) physical base address */
  465. iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id),
  466. txq->q.dma_addr >> 8);
  467. return 0;
  468. }
  469. /******************************************************************************
  470. *
  471. * Generic RX handler implementations
  472. *
  473. ******************************************************************************/
  474. static void iwl_rx_reply_alive(struct iwl_priv *priv,
  475. struct iwl_rx_mem_buffer *rxb)
  476. {
  477. struct iwl_rx_packet *pkt = rxb_addr(rxb);
  478. struct iwl_alive_resp *palive;
  479. struct delayed_work *pwork;
  480. palive = &pkt->u.alive_frame;
  481. IWL_DEBUG_INFO(priv, "Alive ucode status 0x%08X revision "
  482. "0x%01X 0x%01X\n",
  483. palive->is_valid, palive->ver_type,
  484. palive->ver_subtype);
  485. if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
  486. IWL_DEBUG_INFO(priv, "Initialization Alive received.\n");
  487. memcpy(&priv->card_alive_init,
  488. &pkt->u.alive_frame,
  489. sizeof(struct iwl_init_alive_resp));
  490. pwork = &priv->init_alive_start;
  491. } else {
  492. IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
  493. memcpy(&priv->card_alive, &pkt->u.alive_frame,
  494. sizeof(struct iwl_alive_resp));
  495. pwork = &priv->alive_start;
  496. }
  497. /* We delay the ALIVE response by 5ms to
  498. * give the HW RF Kill time to activate... */
  499. if (palive->is_valid == UCODE_VALID_OK)
  500. queue_delayed_work(priv->workqueue, pwork,
  501. msecs_to_jiffies(5));
  502. else
  503. IWL_WARN(priv, "uCode did not respond OK.\n");
  504. }
  505. static void iwl_bg_beacon_update(struct work_struct *work)
  506. {
  507. struct iwl_priv *priv =
  508. container_of(work, struct iwl_priv, beacon_update);
  509. struct sk_buff *beacon;
  510. /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
  511. beacon = ieee80211_beacon_get(priv->hw, priv->vif);
  512. if (!beacon) {
  513. IWL_ERR(priv, "update beacon failed\n");
  514. return;
  515. }
  516. mutex_lock(&priv->mutex);
  517. /* new beacon skb is allocated every time; dispose previous.*/
  518. if (priv->ibss_beacon)
  519. dev_kfree_skb(priv->ibss_beacon);
  520. priv->ibss_beacon = beacon;
  521. mutex_unlock(&priv->mutex);
  522. iwl_send_beacon_cmd(priv);
  523. }
  524. /**
  525. * iwl_bg_statistics_periodic - Timer callback to queue statistics
  526. *
  527. * This callback is provided in order to send a statistics request.
  528. *
  529. * This timer function is continually reset to execute within
  530. * REG_RECALIB_PERIOD seconds since the last STATISTICS_NOTIFICATION
  531. * was received. We need to ensure we receive the statistics in order
  532. * to update the temperature used for calibrating the TXPOWER.
  533. */
  534. static void iwl_bg_statistics_periodic(unsigned long data)
  535. {
  536. struct iwl_priv *priv = (struct iwl_priv *)data;
  537. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  538. return;
  539. /* dont send host command if rf-kill is on */
  540. if (!iwl_is_ready_rf(priv))
  541. return;
  542. iwl_send_statistics_request(priv, CMD_ASYNC, false);
  543. }
  544. static void iwl_print_cont_event_trace(struct iwl_priv *priv, u32 base,
  545. u32 start_idx, u32 num_events,
  546. u32 mode)
  547. {
  548. u32 i;
  549. u32 ptr; /* SRAM byte address of log data */
  550. u32 ev, time, data; /* event log data */
  551. unsigned long reg_flags;
  552. if (mode == 0)
  553. ptr = base + (4 * sizeof(u32)) + (start_idx * 2 * sizeof(u32));
  554. else
  555. ptr = base + (4 * sizeof(u32)) + (start_idx * 3 * sizeof(u32));
  556. /* Make sure device is powered up for SRAM reads */
  557. spin_lock_irqsave(&priv->reg_lock, reg_flags);
  558. if (iwl_grab_nic_access(priv)) {
  559. spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
  560. return;
  561. }
  562. /* Set starting address; reads will auto-increment */
  563. _iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, ptr);
  564. rmb();
  565. /*
  566. * "time" is actually "data" for mode 0 (no timestamp).
  567. * place event id # at far right for easier visual parsing.
  568. */
  569. for (i = 0; i < num_events; i++) {
  570. ev = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  571. time = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  572. if (mode == 0) {
  573. trace_iwlwifi_dev_ucode_cont_event(priv,
  574. 0, time, ev);
  575. } else {
  576. data = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  577. trace_iwlwifi_dev_ucode_cont_event(priv,
  578. time, data, ev);
  579. }
  580. }
  581. /* Allow device to power down */
  582. iwl_release_nic_access(priv);
  583. spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
  584. }
  585. static void iwl_continuous_event_trace(struct iwl_priv *priv)
  586. {
  587. u32 capacity; /* event log capacity in # entries */
  588. u32 base; /* SRAM byte address of event log header */
  589. u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
  590. u32 num_wraps; /* # times uCode wrapped to top of log */
  591. u32 next_entry; /* index of next entry to be written by uCode */
  592. if (priv->ucode_type == UCODE_INIT)
  593. base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
  594. else
  595. base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
  596. if (priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
  597. capacity = iwl_read_targ_mem(priv, base);
  598. num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
  599. mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
  600. next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
  601. } else
  602. return;
  603. if (num_wraps == priv->event_log.num_wraps) {
  604. iwl_print_cont_event_trace(priv,
  605. base, priv->event_log.next_entry,
  606. next_entry - priv->event_log.next_entry,
  607. mode);
  608. priv->event_log.non_wraps_count++;
  609. } else {
  610. if ((num_wraps - priv->event_log.num_wraps) > 1)
  611. priv->event_log.wraps_more_count++;
  612. else
  613. priv->event_log.wraps_once_count++;
  614. trace_iwlwifi_dev_ucode_wrap_event(priv,
  615. num_wraps - priv->event_log.num_wraps,
  616. next_entry, priv->event_log.next_entry);
  617. if (next_entry < priv->event_log.next_entry) {
  618. iwl_print_cont_event_trace(priv, base,
  619. priv->event_log.next_entry,
  620. capacity - priv->event_log.next_entry,
  621. mode);
  622. iwl_print_cont_event_trace(priv, base, 0,
  623. next_entry, mode);
  624. } else {
  625. iwl_print_cont_event_trace(priv, base,
  626. next_entry, capacity - next_entry,
  627. mode);
  628. iwl_print_cont_event_trace(priv, base, 0,
  629. next_entry, mode);
  630. }
  631. }
  632. priv->event_log.num_wraps = num_wraps;
  633. priv->event_log.next_entry = next_entry;
  634. }
  635. /**
  636. * iwl_bg_ucode_trace - Timer callback to log ucode event
  637. *
  638. * The timer is continually set to execute every
  639. * UCODE_TRACE_PERIOD milliseconds after the last timer expired
  640. * this function is to perform continuous uCode event logging operation
  641. * if enabled
  642. */
  643. static void iwl_bg_ucode_trace(unsigned long data)
  644. {
  645. struct iwl_priv *priv = (struct iwl_priv *)data;
  646. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  647. return;
  648. if (priv->event_log.ucode_trace) {
  649. iwl_continuous_event_trace(priv);
  650. /* Reschedule the timer to occur in UCODE_TRACE_PERIOD */
  651. mod_timer(&priv->ucode_trace,
  652. jiffies + msecs_to_jiffies(UCODE_TRACE_PERIOD));
  653. }
  654. }
  655. static void iwl_rx_beacon_notif(struct iwl_priv *priv,
  656. struct iwl_rx_mem_buffer *rxb)
  657. {
  658. #ifdef CONFIG_IWLWIFI_DEBUG
  659. struct iwl_rx_packet *pkt = rxb_addr(rxb);
  660. struct iwl4965_beacon_notif *beacon =
  661. (struct iwl4965_beacon_notif *)pkt->u.raw;
  662. u8 rate = iwl_hw_get_rate(beacon->beacon_notify_hdr.rate_n_flags);
  663. IWL_DEBUG_RX(priv, "beacon status %x retries %d iss %d "
  664. "tsf %d %d rate %d\n",
  665. le32_to_cpu(beacon->beacon_notify_hdr.u.status) & TX_STATUS_MSK,
  666. beacon->beacon_notify_hdr.failure_frame,
  667. le32_to_cpu(beacon->ibss_mgr_status),
  668. le32_to_cpu(beacon->high_tsf),
  669. le32_to_cpu(beacon->low_tsf), rate);
  670. #endif
  671. if ((priv->iw_mode == NL80211_IFTYPE_AP) &&
  672. (!test_bit(STATUS_EXIT_PENDING, &priv->status)))
  673. queue_work(priv->workqueue, &priv->beacon_update);
  674. }
  675. /* Handle notification from uCode that card's power state is changing
  676. * due to software, hardware, or critical temperature RFKILL */
  677. static void iwl_rx_card_state_notif(struct iwl_priv *priv,
  678. struct iwl_rx_mem_buffer *rxb)
  679. {
  680. struct iwl_rx_packet *pkt = rxb_addr(rxb);
  681. u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
  682. unsigned long status = priv->status;
  683. IWL_DEBUG_RF_KILL(priv, "Card state received: HW:%s SW:%s CT:%s\n",
  684. (flags & HW_CARD_DISABLED) ? "Kill" : "On",
  685. (flags & SW_CARD_DISABLED) ? "Kill" : "On",
  686. (flags & CT_CARD_DISABLED) ?
  687. "Reached" : "Not reached");
  688. if (flags & (SW_CARD_DISABLED | HW_CARD_DISABLED |
  689. CT_CARD_DISABLED)) {
  690. iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
  691. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  692. iwl_write_direct32(priv, HBUS_TARG_MBX_C,
  693. HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
  694. if (!(flags & RXON_CARD_DISABLED)) {
  695. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
  696. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  697. iwl_write_direct32(priv, HBUS_TARG_MBX_C,
  698. HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
  699. }
  700. if (flags & CT_CARD_DISABLED)
  701. iwl_tt_enter_ct_kill(priv);
  702. }
  703. if (!(flags & CT_CARD_DISABLED))
  704. iwl_tt_exit_ct_kill(priv);
  705. if (flags & HW_CARD_DISABLED)
  706. set_bit(STATUS_RF_KILL_HW, &priv->status);
  707. else
  708. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  709. if (!(flags & RXON_CARD_DISABLED))
  710. iwl_scan_cancel(priv);
  711. if ((test_bit(STATUS_RF_KILL_HW, &status) !=
  712. test_bit(STATUS_RF_KILL_HW, &priv->status)))
  713. wiphy_rfkill_set_hw_state(priv->hw->wiphy,
  714. test_bit(STATUS_RF_KILL_HW, &priv->status));
  715. else
  716. wake_up_interruptible(&priv->wait_command_queue);
  717. }
  718. int iwl_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src)
  719. {
  720. if (src == IWL_PWR_SRC_VAUX) {
  721. if (pci_pme_capable(priv->pci_dev, PCI_D3cold))
  722. iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
  723. APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
  724. ~APMG_PS_CTRL_MSK_PWR_SRC);
  725. } else {
  726. iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
  727. APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
  728. ~APMG_PS_CTRL_MSK_PWR_SRC);
  729. }
  730. return 0;
  731. }
  732. /**
  733. * iwl_setup_rx_handlers - Initialize Rx handler callbacks
  734. *
  735. * Setup the RX handlers for each of the reply types sent from the uCode
  736. * to the host.
  737. *
  738. * This function chains into the hardware specific files for them to setup
  739. * any hardware specific handlers as well.
  740. */
  741. static void iwl_setup_rx_handlers(struct iwl_priv *priv)
  742. {
  743. priv->rx_handlers[REPLY_ALIVE] = iwl_rx_reply_alive;
  744. priv->rx_handlers[REPLY_ERROR] = iwl_rx_reply_error;
  745. priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl_rx_csa;
  746. priv->rx_handlers[SPECTRUM_MEASURE_NOTIFICATION] =
  747. iwl_rx_spectrum_measure_notif;
  748. priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl_rx_pm_sleep_notif;
  749. priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] =
  750. iwl_rx_pm_debug_statistics_notif;
  751. priv->rx_handlers[BEACON_NOTIFICATION] = iwl_rx_beacon_notif;
  752. /*
  753. * The same handler is used for both the REPLY to a discrete
  754. * statistics request from the host as well as for the periodic
  755. * statistics notifications (after received beacons) from the uCode.
  756. */
  757. priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl_reply_statistics;
  758. priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl_rx_statistics;
  759. iwl_setup_rx_scan_handlers(priv);
  760. /* status change handler */
  761. priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl_rx_card_state_notif;
  762. priv->rx_handlers[MISSED_BEACONS_NOTIFICATION] =
  763. iwl_rx_missed_beacon_notif;
  764. /* Rx handlers */
  765. priv->rx_handlers[REPLY_RX_PHY_CMD] = iwl_rx_reply_rx_phy;
  766. priv->rx_handlers[REPLY_RX_MPDU_CMD] = iwl_rx_reply_rx;
  767. /* block ack */
  768. priv->rx_handlers[REPLY_COMPRESSED_BA] = iwl_rx_reply_compressed_ba;
  769. /* Set up hardware specific Rx handlers */
  770. priv->cfg->ops->lib->rx_handler_setup(priv);
  771. }
  772. /**
  773. * iwl_rx_handle - Main entry function for receiving responses from uCode
  774. *
  775. * Uses the priv->rx_handlers callback function array to invoke
  776. * the appropriate handlers, including command responses,
  777. * frame-received notifications, and other notifications.
  778. */
  779. void iwl_rx_handle(struct iwl_priv *priv)
  780. {
  781. struct iwl_rx_mem_buffer *rxb;
  782. struct iwl_rx_packet *pkt;
  783. struct iwl_rx_queue *rxq = &priv->rxq;
  784. u32 r, i;
  785. int reclaim;
  786. unsigned long flags;
  787. u8 fill_rx = 0;
  788. u32 count = 8;
  789. int total_empty;
  790. /* uCode's read index (stored in shared DRAM) indicates the last Rx
  791. * buffer that the driver may process (last buffer filled by ucode). */
  792. r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF;
  793. i = rxq->read;
  794. /* Rx interrupt, but nothing sent from uCode */
  795. if (i == r)
  796. IWL_DEBUG_RX(priv, "r = %d, i = %d\n", r, i);
  797. /* calculate total frames need to be restock after handling RX */
  798. total_empty = r - rxq->write_actual;
  799. if (total_empty < 0)
  800. total_empty += RX_QUEUE_SIZE;
  801. if (total_empty > (RX_QUEUE_SIZE / 2))
  802. fill_rx = 1;
  803. while (i != r) {
  804. rxb = rxq->queue[i];
  805. /* If an RXB doesn't have a Rx queue slot associated with it,
  806. * then a bug has been introduced in the queue refilling
  807. * routines -- catch it here */
  808. BUG_ON(rxb == NULL);
  809. rxq->queue[i] = NULL;
  810. pci_unmap_page(priv->pci_dev, rxb->page_dma,
  811. PAGE_SIZE << priv->hw_params.rx_page_order,
  812. PCI_DMA_FROMDEVICE);
  813. pkt = rxb_addr(rxb);
  814. trace_iwlwifi_dev_rx(priv, pkt,
  815. le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK);
  816. /* Reclaim a command buffer only if this packet is a response
  817. * to a (driver-originated) command.
  818. * If the packet (e.g. Rx frame) originated from uCode,
  819. * there is no command buffer to reclaim.
  820. * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
  821. * but apparently a few don't get set; catch them here. */
  822. reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
  823. (pkt->hdr.cmd != REPLY_RX_PHY_CMD) &&
  824. (pkt->hdr.cmd != REPLY_RX) &&
  825. (pkt->hdr.cmd != REPLY_RX_MPDU_CMD) &&
  826. (pkt->hdr.cmd != REPLY_COMPRESSED_BA) &&
  827. (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
  828. (pkt->hdr.cmd != REPLY_TX);
  829. /* Based on type of command response or notification,
  830. * handle those that need handling via function in
  831. * rx_handlers table. See iwl_setup_rx_handlers() */
  832. if (priv->rx_handlers[pkt->hdr.cmd]) {
  833. IWL_DEBUG_RX(priv, "r = %d, i = %d, %s, 0x%02x\n", r,
  834. i, get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
  835. priv->isr_stats.rx_handlers[pkt->hdr.cmd]++;
  836. priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
  837. } else {
  838. /* No handling needed */
  839. IWL_DEBUG_RX(priv,
  840. "r %d i %d No handler needed for %s, 0x%02x\n",
  841. r, i, get_cmd_string(pkt->hdr.cmd),
  842. pkt->hdr.cmd);
  843. }
  844. /*
  845. * XXX: After here, we should always check rxb->page
  846. * against NULL before touching it or its virtual
  847. * memory (pkt). Because some rx_handler might have
  848. * already taken or freed the pages.
  849. */
  850. if (reclaim) {
  851. /* Invoke any callbacks, transfer the buffer to caller,
  852. * and fire off the (possibly) blocking iwl_send_cmd()
  853. * as we reclaim the driver command queue */
  854. if (rxb->page)
  855. iwl_tx_cmd_complete(priv, rxb);
  856. else
  857. IWL_WARN(priv, "Claim null rxb?\n");
  858. }
  859. /* Reuse the page if possible. For notification packets and
  860. * SKBs that fail to Rx correctly, add them back into the
  861. * rx_free list for reuse later. */
  862. spin_lock_irqsave(&rxq->lock, flags);
  863. if (rxb->page != NULL) {
  864. rxb->page_dma = pci_map_page(priv->pci_dev, rxb->page,
  865. 0, PAGE_SIZE << priv->hw_params.rx_page_order,
  866. PCI_DMA_FROMDEVICE);
  867. list_add_tail(&rxb->list, &rxq->rx_free);
  868. rxq->free_count++;
  869. } else
  870. list_add_tail(&rxb->list, &rxq->rx_used);
  871. spin_unlock_irqrestore(&rxq->lock, flags);
  872. i = (i + 1) & RX_QUEUE_MASK;
  873. /* If there are a lot of unused frames,
  874. * restock the Rx queue so ucode wont assert. */
  875. if (fill_rx) {
  876. count++;
  877. if (count >= 8) {
  878. rxq->read = i;
  879. iwl_rx_replenish_now(priv);
  880. count = 0;
  881. }
  882. }
  883. }
  884. /* Backtrack one entry */
  885. rxq->read = i;
  886. if (fill_rx)
  887. iwl_rx_replenish_now(priv);
  888. else
  889. iwl_rx_queue_restock(priv);
  890. }
  891. /* call this function to flush any scheduled tasklet */
  892. static inline void iwl_synchronize_irq(struct iwl_priv *priv)
  893. {
  894. /* wait to make sure we flush pending tasklet*/
  895. synchronize_irq(priv->pci_dev->irq);
  896. tasklet_kill(&priv->irq_tasklet);
  897. }
  898. static void iwl_irq_tasklet_legacy(struct iwl_priv *priv)
  899. {
  900. u32 inta, handled = 0;
  901. u32 inta_fh;
  902. unsigned long flags;
  903. u32 i;
  904. #ifdef CONFIG_IWLWIFI_DEBUG
  905. u32 inta_mask;
  906. #endif
  907. spin_lock_irqsave(&priv->lock, flags);
  908. /* Ack/clear/reset pending uCode interrupts.
  909. * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
  910. * and will clear only when CSR_FH_INT_STATUS gets cleared. */
  911. inta = iwl_read32(priv, CSR_INT);
  912. iwl_write32(priv, CSR_INT, inta);
  913. /* Ack/clear/reset pending flow-handler (DMA) interrupts.
  914. * Any new interrupts that happen after this, either while we're
  915. * in this tasklet, or later, will show up in next ISR/tasklet. */
  916. inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
  917. iwl_write32(priv, CSR_FH_INT_STATUS, inta_fh);
  918. #ifdef CONFIG_IWLWIFI_DEBUG
  919. if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
  920. /* just for debug */
  921. inta_mask = iwl_read32(priv, CSR_INT_MASK);
  922. IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
  923. inta, inta_mask, inta_fh);
  924. }
  925. #endif
  926. spin_unlock_irqrestore(&priv->lock, flags);
  927. /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
  928. * atomic, make sure that inta covers all the interrupts that
  929. * we've discovered, even if FH interrupt came in just after
  930. * reading CSR_INT. */
  931. if (inta_fh & CSR49_FH_INT_RX_MASK)
  932. inta |= CSR_INT_BIT_FH_RX;
  933. if (inta_fh & CSR49_FH_INT_TX_MASK)
  934. inta |= CSR_INT_BIT_FH_TX;
  935. /* Now service all interrupt bits discovered above. */
  936. if (inta & CSR_INT_BIT_HW_ERR) {
  937. IWL_ERR(priv, "Hardware error detected. Restarting.\n");
  938. /* Tell the device to stop sending interrupts */
  939. iwl_disable_interrupts(priv);
  940. priv->isr_stats.hw++;
  941. iwl_irq_handle_error(priv);
  942. handled |= CSR_INT_BIT_HW_ERR;
  943. return;
  944. }
  945. #ifdef CONFIG_IWLWIFI_DEBUG
  946. if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
  947. /* NIC fires this, but we don't use it, redundant with WAKEUP */
  948. if (inta & CSR_INT_BIT_SCD) {
  949. IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
  950. "the frame/frames.\n");
  951. priv->isr_stats.sch++;
  952. }
  953. /* Alive notification via Rx interrupt will do the real work */
  954. if (inta & CSR_INT_BIT_ALIVE) {
  955. IWL_DEBUG_ISR(priv, "Alive interrupt\n");
  956. priv->isr_stats.alive++;
  957. }
  958. }
  959. #endif
  960. /* Safely ignore these bits for debug checks below */
  961. inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
  962. /* HW RF KILL switch toggled */
  963. if (inta & CSR_INT_BIT_RF_KILL) {
  964. int hw_rf_kill = 0;
  965. if (!(iwl_read32(priv, CSR_GP_CNTRL) &
  966. CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
  967. hw_rf_kill = 1;
  968. IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
  969. hw_rf_kill ? "disable radio" : "enable radio");
  970. priv->isr_stats.rfkill++;
  971. /* driver only loads ucode once setting the interface up.
  972. * the driver allows loading the ucode even if the radio
  973. * is killed. Hence update the killswitch state here. The
  974. * rfkill handler will care about restarting if needed.
  975. */
  976. if (!test_bit(STATUS_ALIVE, &priv->status)) {
  977. if (hw_rf_kill)
  978. set_bit(STATUS_RF_KILL_HW, &priv->status);
  979. else
  980. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  981. wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
  982. }
  983. handled |= CSR_INT_BIT_RF_KILL;
  984. }
  985. /* Chip got too hot and stopped itself */
  986. if (inta & CSR_INT_BIT_CT_KILL) {
  987. IWL_ERR(priv, "Microcode CT kill error detected.\n");
  988. priv->isr_stats.ctkill++;
  989. handled |= CSR_INT_BIT_CT_KILL;
  990. }
  991. /* Error detected by uCode */
  992. if (inta & CSR_INT_BIT_SW_ERR) {
  993. IWL_ERR(priv, "Microcode SW error detected. "
  994. " Restarting 0x%X.\n", inta);
  995. priv->isr_stats.sw++;
  996. priv->isr_stats.sw_err = inta;
  997. iwl_irq_handle_error(priv);
  998. handled |= CSR_INT_BIT_SW_ERR;
  999. }
  1000. /*
  1001. * uCode wakes up after power-down sleep.
  1002. * Tell device about any new tx or host commands enqueued,
  1003. * and about any Rx buffers made available while asleep.
  1004. */
  1005. if (inta & CSR_INT_BIT_WAKEUP) {
  1006. IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
  1007. iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
  1008. for (i = 0; i < priv->hw_params.max_txq_num; i++)
  1009. iwl_txq_update_write_ptr(priv, &priv->txq[i]);
  1010. priv->isr_stats.wakeup++;
  1011. handled |= CSR_INT_BIT_WAKEUP;
  1012. }
  1013. /* All uCode command responses, including Tx command responses,
  1014. * Rx "responses" (frame-received notification), and other
  1015. * notifications from uCode come through here*/
  1016. if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
  1017. iwl_rx_handle(priv);
  1018. priv->isr_stats.rx++;
  1019. handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
  1020. }
  1021. /* This "Tx" DMA channel is used only for loading uCode */
  1022. if (inta & CSR_INT_BIT_FH_TX) {
  1023. IWL_DEBUG_ISR(priv, "uCode load interrupt\n");
  1024. priv->isr_stats.tx++;
  1025. handled |= CSR_INT_BIT_FH_TX;
  1026. /* Wake up uCode load routine, now that load is complete */
  1027. priv->ucode_write_complete = 1;
  1028. wake_up_interruptible(&priv->wait_command_queue);
  1029. }
  1030. if (inta & ~handled) {
  1031. IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
  1032. priv->isr_stats.unhandled++;
  1033. }
  1034. if (inta & ~(priv->inta_mask)) {
  1035. IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
  1036. inta & ~priv->inta_mask);
  1037. IWL_WARN(priv, " with FH_INT = 0x%08x\n", inta_fh);
  1038. }
  1039. /* Re-enable all interrupts */
  1040. /* only Re-enable if diabled by irq */
  1041. if (test_bit(STATUS_INT_ENABLED, &priv->status))
  1042. iwl_enable_interrupts(priv);
  1043. #ifdef CONFIG_IWLWIFI_DEBUG
  1044. if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
  1045. inta = iwl_read32(priv, CSR_INT);
  1046. inta_mask = iwl_read32(priv, CSR_INT_MASK);
  1047. inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
  1048. IWL_DEBUG_ISR(priv, "End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
  1049. "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
  1050. }
  1051. #endif
  1052. }
  1053. /* tasklet for iwlagn interrupt */
  1054. static void iwl_irq_tasklet(struct iwl_priv *priv)
  1055. {
  1056. u32 inta = 0;
  1057. u32 handled = 0;
  1058. unsigned long flags;
  1059. u32 i;
  1060. #ifdef CONFIG_IWLWIFI_DEBUG
  1061. u32 inta_mask;
  1062. #endif
  1063. spin_lock_irqsave(&priv->lock, flags);
  1064. /* Ack/clear/reset pending uCode interrupts.
  1065. * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
  1066. */
  1067. iwl_write32(priv, CSR_INT, priv->_agn.inta);
  1068. inta = priv->_agn.inta;
  1069. #ifdef CONFIG_IWLWIFI_DEBUG
  1070. if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
  1071. /* just for debug */
  1072. inta_mask = iwl_read32(priv, CSR_INT_MASK);
  1073. IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x\n ",
  1074. inta, inta_mask);
  1075. }
  1076. #endif
  1077. spin_unlock_irqrestore(&priv->lock, flags);
  1078. /* saved interrupt in inta variable now we can reset priv->_agn.inta */
  1079. priv->_agn.inta = 0;
  1080. /* Now service all interrupt bits discovered above. */
  1081. if (inta & CSR_INT_BIT_HW_ERR) {
  1082. IWL_ERR(priv, "Hardware error detected. Restarting.\n");
  1083. /* Tell the device to stop sending interrupts */
  1084. iwl_disable_interrupts(priv);
  1085. priv->isr_stats.hw++;
  1086. iwl_irq_handle_error(priv);
  1087. handled |= CSR_INT_BIT_HW_ERR;
  1088. return;
  1089. }
  1090. #ifdef CONFIG_IWLWIFI_DEBUG
  1091. if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
  1092. /* NIC fires this, but we don't use it, redundant with WAKEUP */
  1093. if (inta & CSR_INT_BIT_SCD) {
  1094. IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
  1095. "the frame/frames.\n");
  1096. priv->isr_stats.sch++;
  1097. }
  1098. /* Alive notification via Rx interrupt will do the real work */
  1099. if (inta & CSR_INT_BIT_ALIVE) {
  1100. IWL_DEBUG_ISR(priv, "Alive interrupt\n");
  1101. priv->isr_stats.alive++;
  1102. }
  1103. }
  1104. #endif
  1105. /* Safely ignore these bits for debug checks below */
  1106. inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
  1107. /* HW RF KILL switch toggled */
  1108. if (inta & CSR_INT_BIT_RF_KILL) {
  1109. int hw_rf_kill = 0;
  1110. if (!(iwl_read32(priv, CSR_GP_CNTRL) &
  1111. CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
  1112. hw_rf_kill = 1;
  1113. IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
  1114. hw_rf_kill ? "disable radio" : "enable radio");
  1115. priv->isr_stats.rfkill++;
  1116. /* driver only loads ucode once setting the interface up.
  1117. * the driver allows loading the ucode even if the radio
  1118. * is killed. Hence update the killswitch state here. The
  1119. * rfkill handler will care about restarting if needed.
  1120. */
  1121. if (!test_bit(STATUS_ALIVE, &priv->status)) {
  1122. if (hw_rf_kill)
  1123. set_bit(STATUS_RF_KILL_HW, &priv->status);
  1124. else
  1125. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  1126. wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
  1127. }
  1128. handled |= CSR_INT_BIT_RF_KILL;
  1129. }
  1130. /* Chip got too hot and stopped itself */
  1131. if (inta & CSR_INT_BIT_CT_KILL) {
  1132. IWL_ERR(priv, "Microcode CT kill error detected.\n");
  1133. priv->isr_stats.ctkill++;
  1134. handled |= CSR_INT_BIT_CT_KILL;
  1135. }
  1136. /* Error detected by uCode */
  1137. if (inta & CSR_INT_BIT_SW_ERR) {
  1138. IWL_ERR(priv, "Microcode SW error detected. "
  1139. " Restarting 0x%X.\n", inta);
  1140. priv->isr_stats.sw++;
  1141. priv->isr_stats.sw_err = inta;
  1142. iwl_irq_handle_error(priv);
  1143. handled |= CSR_INT_BIT_SW_ERR;
  1144. }
  1145. /* uCode wakes up after power-down sleep */
  1146. if (inta & CSR_INT_BIT_WAKEUP) {
  1147. IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
  1148. iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
  1149. for (i = 0; i < priv->hw_params.max_txq_num; i++)
  1150. iwl_txq_update_write_ptr(priv, &priv->txq[i]);
  1151. priv->isr_stats.wakeup++;
  1152. handled |= CSR_INT_BIT_WAKEUP;
  1153. }
  1154. /* All uCode command responses, including Tx command responses,
  1155. * Rx "responses" (frame-received notification), and other
  1156. * notifications from uCode come through here*/
  1157. if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX |
  1158. CSR_INT_BIT_RX_PERIODIC)) {
  1159. IWL_DEBUG_ISR(priv, "Rx interrupt\n");
  1160. if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
  1161. handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
  1162. iwl_write32(priv, CSR_FH_INT_STATUS,
  1163. CSR49_FH_INT_RX_MASK);
  1164. }
  1165. if (inta & CSR_INT_BIT_RX_PERIODIC) {
  1166. handled |= CSR_INT_BIT_RX_PERIODIC;
  1167. iwl_write32(priv, CSR_INT, CSR_INT_BIT_RX_PERIODIC);
  1168. }
  1169. /* Sending RX interrupt require many steps to be done in the
  1170. * the device:
  1171. * 1- write interrupt to current index in ICT table.
  1172. * 2- dma RX frame.
  1173. * 3- update RX shared data to indicate last write index.
  1174. * 4- send interrupt.
  1175. * This could lead to RX race, driver could receive RX interrupt
  1176. * but the shared data changes does not reflect this;
  1177. * periodic interrupt will detect any dangling Rx activity.
  1178. */
  1179. /* Disable periodic interrupt; we use it as just a one-shot. */
  1180. iwl_write8(priv, CSR_INT_PERIODIC_REG,
  1181. CSR_INT_PERIODIC_DIS);
  1182. iwl_rx_handle(priv);
  1183. /*
  1184. * Enable periodic interrupt in 8 msec only if we received
  1185. * real RX interrupt (instead of just periodic int), to catch
  1186. * any dangling Rx interrupt. If it was just the periodic
  1187. * interrupt, there was no dangling Rx activity, and no need
  1188. * to extend the periodic interrupt; one-shot is enough.
  1189. */
  1190. if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX))
  1191. iwl_write8(priv, CSR_INT_PERIODIC_REG,
  1192. CSR_INT_PERIODIC_ENA);
  1193. priv->isr_stats.rx++;
  1194. }
  1195. /* This "Tx" DMA channel is used only for loading uCode */
  1196. if (inta & CSR_INT_BIT_FH_TX) {
  1197. iwl_write32(priv, CSR_FH_INT_STATUS, CSR49_FH_INT_TX_MASK);
  1198. IWL_DEBUG_ISR(priv, "uCode load interrupt\n");
  1199. priv->isr_stats.tx++;
  1200. handled |= CSR_INT_BIT_FH_TX;
  1201. /* Wake up uCode load routine, now that load is complete */
  1202. priv->ucode_write_complete = 1;
  1203. wake_up_interruptible(&priv->wait_command_queue);
  1204. }
  1205. if (inta & ~handled) {
  1206. IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
  1207. priv->isr_stats.unhandled++;
  1208. }
  1209. if (inta & ~(priv->inta_mask)) {
  1210. IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
  1211. inta & ~priv->inta_mask);
  1212. }
  1213. /* Re-enable all interrupts */
  1214. /* only Re-enable if diabled by irq */
  1215. if (test_bit(STATUS_INT_ENABLED, &priv->status))
  1216. iwl_enable_interrupts(priv);
  1217. }
  1218. /******************************************************************************
  1219. *
  1220. * uCode download functions
  1221. *
  1222. ******************************************************************************/
  1223. static void iwl_dealloc_ucode_pci(struct iwl_priv *priv)
  1224. {
  1225. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code);
  1226. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data);
  1227. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
  1228. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init);
  1229. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data);
  1230. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot);
  1231. }
  1232. static void iwl_nic_start(struct iwl_priv *priv)
  1233. {
  1234. /* Remove all resets to allow NIC to operate */
  1235. iwl_write32(priv, CSR_RESET, 0);
  1236. }
  1237. static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context);
  1238. static int iwl_mac_setup_register(struct iwl_priv *priv);
  1239. static int __must_check iwl_request_firmware(struct iwl_priv *priv, bool first)
  1240. {
  1241. const char *name_pre = priv->cfg->fw_name_pre;
  1242. if (first)
  1243. priv->fw_index = priv->cfg->ucode_api_max;
  1244. else
  1245. priv->fw_index--;
  1246. if (priv->fw_index < priv->cfg->ucode_api_min) {
  1247. IWL_ERR(priv, "no suitable firmware found!\n");
  1248. return -ENOENT;
  1249. }
  1250. sprintf(priv->firmware_name, "%s%d%s",
  1251. name_pre, priv->fw_index, ".ucode");
  1252. IWL_DEBUG_INFO(priv, "attempting to load firmware '%s'\n",
  1253. priv->firmware_name);
  1254. return request_firmware_nowait(THIS_MODULE, 1, priv->firmware_name,
  1255. &priv->pci_dev->dev, GFP_KERNEL, priv,
  1256. iwl_ucode_callback);
  1257. }
  1258. /**
  1259. * iwl_ucode_callback - callback when firmware was loaded
  1260. *
  1261. * If loaded successfully, copies the firmware into buffers
  1262. * for the card to fetch (via DMA).
  1263. */
  1264. static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context)
  1265. {
  1266. struct iwl_priv *priv = context;
  1267. struct iwl_ucode_header *ucode;
  1268. const unsigned int api_max = priv->cfg->ucode_api_max;
  1269. const unsigned int api_min = priv->cfg->ucode_api_min;
  1270. u8 *src;
  1271. size_t len;
  1272. u32 api_ver, build;
  1273. u32 inst_size, data_size, init_size, init_data_size, boot_size;
  1274. int err;
  1275. u16 eeprom_ver;
  1276. if (!ucode_raw) {
  1277. IWL_ERR(priv, "request for firmware file '%s' failed.\n",
  1278. priv->firmware_name);
  1279. goto try_again;
  1280. }
  1281. IWL_DEBUG_INFO(priv, "Loaded firmware file '%s' (%zd bytes).\n",
  1282. priv->firmware_name, ucode_raw->size);
  1283. /* Make sure that we got at least the v1 header! */
  1284. if (ucode_raw->size < priv->cfg->ops->ucode->get_header_size(1)) {
  1285. IWL_ERR(priv, "File size way too small!\n");
  1286. goto try_again;
  1287. }
  1288. /* Data from ucode file: header followed by uCode images */
  1289. ucode = (struct iwl_ucode_header *)ucode_raw->data;
  1290. priv->ucode_ver = le32_to_cpu(ucode->ver);
  1291. api_ver = IWL_UCODE_API(priv->ucode_ver);
  1292. build = priv->cfg->ops->ucode->get_build(ucode, api_ver);
  1293. inst_size = priv->cfg->ops->ucode->get_inst_size(ucode, api_ver);
  1294. data_size = priv->cfg->ops->ucode->get_data_size(ucode, api_ver);
  1295. init_size = priv->cfg->ops->ucode->get_init_size(ucode, api_ver);
  1296. init_data_size =
  1297. priv->cfg->ops->ucode->get_init_data_size(ucode, api_ver);
  1298. boot_size = priv->cfg->ops->ucode->get_boot_size(ucode, api_ver);
  1299. src = priv->cfg->ops->ucode->get_data(ucode, api_ver);
  1300. /* api_ver should match the api version forming part of the
  1301. * firmware filename ... but we don't check for that and only rely
  1302. * on the API version read from firmware header from here on forward */
  1303. if (api_ver < api_min || api_ver > api_max) {
  1304. IWL_ERR(priv, "Driver unable to support your firmware API. "
  1305. "Driver supports v%u, firmware is v%u.\n",
  1306. api_max, api_ver);
  1307. goto try_again;
  1308. }
  1309. if (api_ver != api_max)
  1310. IWL_ERR(priv, "Firmware has old API version. Expected v%u, "
  1311. "got v%u. New firmware can be obtained "
  1312. "from http://www.intellinuxwireless.org.\n",
  1313. api_max, api_ver);
  1314. IWL_INFO(priv, "loaded firmware version %u.%u.%u.%u\n",
  1315. IWL_UCODE_MAJOR(priv->ucode_ver),
  1316. IWL_UCODE_MINOR(priv->ucode_ver),
  1317. IWL_UCODE_API(priv->ucode_ver),
  1318. IWL_UCODE_SERIAL(priv->ucode_ver));
  1319. snprintf(priv->hw->wiphy->fw_version,
  1320. sizeof(priv->hw->wiphy->fw_version),
  1321. "%u.%u.%u.%u",
  1322. IWL_UCODE_MAJOR(priv->ucode_ver),
  1323. IWL_UCODE_MINOR(priv->ucode_ver),
  1324. IWL_UCODE_API(priv->ucode_ver),
  1325. IWL_UCODE_SERIAL(priv->ucode_ver));
  1326. if (build)
  1327. IWL_DEBUG_INFO(priv, "Build %u\n", build);
  1328. eeprom_ver = iwl_eeprom_query16(priv, EEPROM_VERSION);
  1329. IWL_DEBUG_INFO(priv, "NVM Type: %s, version: 0x%x\n",
  1330. (priv->nvm_device_type == NVM_DEVICE_TYPE_OTP)
  1331. ? "OTP" : "EEPROM", eeprom_ver);
  1332. IWL_DEBUG_INFO(priv, "f/w package hdr ucode version raw = 0x%x\n",
  1333. priv->ucode_ver);
  1334. IWL_DEBUG_INFO(priv, "f/w package hdr runtime inst size = %u\n",
  1335. inst_size);
  1336. IWL_DEBUG_INFO(priv, "f/w package hdr runtime data size = %u\n",
  1337. data_size);
  1338. IWL_DEBUG_INFO(priv, "f/w package hdr init inst size = %u\n",
  1339. init_size);
  1340. IWL_DEBUG_INFO(priv, "f/w package hdr init data size = %u\n",
  1341. init_data_size);
  1342. IWL_DEBUG_INFO(priv, "f/w package hdr boot inst size = %u\n",
  1343. boot_size);
  1344. /*
  1345. * For any of the failures below (before allocating pci memory)
  1346. * we will try to load a version with a smaller API -- maybe the
  1347. * user just got a corrupted version of the latest API.
  1348. */
  1349. /* Verify size of file vs. image size info in file's header */
  1350. if (ucode_raw->size !=
  1351. priv->cfg->ops->ucode->get_header_size(api_ver) +
  1352. inst_size + data_size + init_size +
  1353. init_data_size + boot_size) {
  1354. IWL_DEBUG_INFO(priv,
  1355. "uCode file size %d does not match expected size\n",
  1356. (int)ucode_raw->size);
  1357. goto try_again;
  1358. }
  1359. /* Verify that uCode images will fit in card's SRAM */
  1360. if (inst_size > priv->hw_params.max_inst_size) {
  1361. IWL_DEBUG_INFO(priv, "uCode instr len %d too large to fit in\n",
  1362. inst_size);
  1363. goto try_again;
  1364. }
  1365. if (data_size > priv->hw_params.max_data_size) {
  1366. IWL_DEBUG_INFO(priv, "uCode data len %d too large to fit in\n",
  1367. data_size);
  1368. goto try_again;
  1369. }
  1370. if (init_size > priv->hw_params.max_inst_size) {
  1371. IWL_INFO(priv, "uCode init instr len %d too large to fit in\n",
  1372. init_size);
  1373. goto try_again;
  1374. }
  1375. if (init_data_size > priv->hw_params.max_data_size) {
  1376. IWL_INFO(priv, "uCode init data len %d too large to fit in\n",
  1377. init_data_size);
  1378. goto try_again;
  1379. }
  1380. if (boot_size > priv->hw_params.max_bsm_size) {
  1381. IWL_INFO(priv, "uCode boot instr len %d too large to fit in\n",
  1382. boot_size);
  1383. goto try_again;
  1384. }
  1385. /* Allocate ucode buffers for card's bus-master loading ... */
  1386. /* Runtime instructions and 2 copies of data:
  1387. * 1) unmodified from disk
  1388. * 2) backup cache for save/restore during power-downs */
  1389. priv->ucode_code.len = inst_size;
  1390. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code);
  1391. priv->ucode_data.len = data_size;
  1392. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data);
  1393. priv->ucode_data_backup.len = data_size;
  1394. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
  1395. if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr ||
  1396. !priv->ucode_data_backup.v_addr)
  1397. goto err_pci_alloc;
  1398. /* Initialization instructions and data */
  1399. if (init_size && init_data_size) {
  1400. priv->ucode_init.len = init_size;
  1401. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init);
  1402. priv->ucode_init_data.len = init_data_size;
  1403. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data);
  1404. if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr)
  1405. goto err_pci_alloc;
  1406. }
  1407. /* Bootstrap (instructions only, no data) */
  1408. if (boot_size) {
  1409. priv->ucode_boot.len = boot_size;
  1410. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot);
  1411. if (!priv->ucode_boot.v_addr)
  1412. goto err_pci_alloc;
  1413. }
  1414. /* Copy images into buffers for card's bus-master reads ... */
  1415. /* Runtime instructions (first block of data in file) */
  1416. len = inst_size;
  1417. IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode instr len %Zd\n", len);
  1418. memcpy(priv->ucode_code.v_addr, src, len);
  1419. src += len;
  1420. IWL_DEBUG_INFO(priv, "uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
  1421. priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr);
  1422. /* Runtime data (2nd block)
  1423. * NOTE: Copy into backup buffer will be done in iwl_up() */
  1424. len = data_size;
  1425. IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode data len %Zd\n", len);
  1426. memcpy(priv->ucode_data.v_addr, src, len);
  1427. memcpy(priv->ucode_data_backup.v_addr, src, len);
  1428. src += len;
  1429. /* Initialization instructions (3rd block) */
  1430. if (init_size) {
  1431. len = init_size;
  1432. IWL_DEBUG_INFO(priv, "Copying (but not loading) init instr len %Zd\n",
  1433. len);
  1434. memcpy(priv->ucode_init.v_addr, src, len);
  1435. src += len;
  1436. }
  1437. /* Initialization data (4th block) */
  1438. if (init_data_size) {
  1439. len = init_data_size;
  1440. IWL_DEBUG_INFO(priv, "Copying (but not loading) init data len %Zd\n",
  1441. len);
  1442. memcpy(priv->ucode_init_data.v_addr, src, len);
  1443. src += len;
  1444. }
  1445. /* Bootstrap instructions (5th block) */
  1446. len = boot_size;
  1447. IWL_DEBUG_INFO(priv, "Copying (but not loading) boot instr len %Zd\n", len);
  1448. memcpy(priv->ucode_boot.v_addr, src, len);
  1449. /**************************************************
  1450. * This is still part of probe() in a sense...
  1451. *
  1452. * 9. Setup and register with mac80211 and debugfs
  1453. **************************************************/
  1454. err = iwl_mac_setup_register(priv);
  1455. if (err)
  1456. goto out_unbind;
  1457. err = iwl_dbgfs_register(priv, DRV_NAME);
  1458. if (err)
  1459. IWL_ERR(priv, "failed to create debugfs files. Ignoring error: %d\n", err);
  1460. /* We have our copies now, allow OS release its copies */
  1461. release_firmware(ucode_raw);
  1462. return;
  1463. try_again:
  1464. /* try next, if any */
  1465. if (iwl_request_firmware(priv, false))
  1466. goto out_unbind;
  1467. release_firmware(ucode_raw);
  1468. return;
  1469. err_pci_alloc:
  1470. IWL_ERR(priv, "failed to allocate pci memory\n");
  1471. iwl_dealloc_ucode_pci(priv);
  1472. out_unbind:
  1473. device_release_driver(&priv->pci_dev->dev);
  1474. release_firmware(ucode_raw);
  1475. }
  1476. static const char *desc_lookup_text[] = {
  1477. "OK",
  1478. "FAIL",
  1479. "BAD_PARAM",
  1480. "BAD_CHECKSUM",
  1481. "NMI_INTERRUPT_WDG",
  1482. "SYSASSERT",
  1483. "FATAL_ERROR",
  1484. "BAD_COMMAND",
  1485. "HW_ERROR_TUNE_LOCK",
  1486. "HW_ERROR_TEMPERATURE",
  1487. "ILLEGAL_CHAN_FREQ",
  1488. "VCC_NOT_STABLE",
  1489. "FH_ERROR",
  1490. "NMI_INTERRUPT_HOST",
  1491. "NMI_INTERRUPT_ACTION_PT",
  1492. "NMI_INTERRUPT_UNKNOWN",
  1493. "UCODE_VERSION_MISMATCH",
  1494. "HW_ERROR_ABS_LOCK",
  1495. "HW_ERROR_CAL_LOCK_FAIL",
  1496. "NMI_INTERRUPT_INST_ACTION_PT",
  1497. "NMI_INTERRUPT_DATA_ACTION_PT",
  1498. "NMI_TRM_HW_ER",
  1499. "NMI_INTERRUPT_TRM",
  1500. "NMI_INTERRUPT_BREAK_POINT"
  1501. "DEBUG_0",
  1502. "DEBUG_1",
  1503. "DEBUG_2",
  1504. "DEBUG_3",
  1505. "ADVANCED SYSASSERT"
  1506. };
  1507. static const char *desc_lookup(int i)
  1508. {
  1509. int max = ARRAY_SIZE(desc_lookup_text) - 1;
  1510. if (i < 0 || i > max)
  1511. i = max;
  1512. return desc_lookup_text[i];
  1513. }
  1514. #define ERROR_START_OFFSET (1 * sizeof(u32))
  1515. #define ERROR_ELEM_SIZE (7 * sizeof(u32))
  1516. void iwl_dump_nic_error_log(struct iwl_priv *priv)
  1517. {
  1518. u32 data2, line;
  1519. u32 desc, time, count, base, data1;
  1520. u32 blink1, blink2, ilink1, ilink2;
  1521. if (priv->ucode_type == UCODE_INIT)
  1522. base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
  1523. else
  1524. base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
  1525. if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
  1526. IWL_ERR(priv,
  1527. "Not valid error log pointer 0x%08X for %s uCode\n",
  1528. base, (priv->ucode_type == UCODE_INIT) ? "Init" : "RT");
  1529. return;
  1530. }
  1531. count = iwl_read_targ_mem(priv, base);
  1532. if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
  1533. IWL_ERR(priv, "Start IWL Error Log Dump:\n");
  1534. IWL_ERR(priv, "Status: 0x%08lX, count: %d\n",
  1535. priv->status, count);
  1536. }
  1537. desc = iwl_read_targ_mem(priv, base + 1 * sizeof(u32));
  1538. blink1 = iwl_read_targ_mem(priv, base + 3 * sizeof(u32));
  1539. blink2 = iwl_read_targ_mem(priv, base + 4 * sizeof(u32));
  1540. ilink1 = iwl_read_targ_mem(priv, base + 5 * sizeof(u32));
  1541. ilink2 = iwl_read_targ_mem(priv, base + 6 * sizeof(u32));
  1542. data1 = iwl_read_targ_mem(priv, base + 7 * sizeof(u32));
  1543. data2 = iwl_read_targ_mem(priv, base + 8 * sizeof(u32));
  1544. line = iwl_read_targ_mem(priv, base + 9 * sizeof(u32));
  1545. time = iwl_read_targ_mem(priv, base + 11 * sizeof(u32));
  1546. trace_iwlwifi_dev_ucode_error(priv, desc, time, data1, data2, line,
  1547. blink1, blink2, ilink1, ilink2);
  1548. IWL_ERR(priv, "Desc Time "
  1549. "data1 data2 line\n");
  1550. IWL_ERR(priv, "%-28s (#%02d) %010u 0x%08X 0x%08X %u\n",
  1551. desc_lookup(desc), desc, time, data1, data2, line);
  1552. IWL_ERR(priv, "blink1 blink2 ilink1 ilink2\n");
  1553. IWL_ERR(priv, "0x%05X 0x%05X 0x%05X 0x%05X\n", blink1, blink2,
  1554. ilink1, ilink2);
  1555. }
  1556. #define EVENT_START_OFFSET (4 * sizeof(u32))
  1557. /**
  1558. * iwl_print_event_log - Dump error event log to syslog
  1559. *
  1560. */
  1561. static int iwl_print_event_log(struct iwl_priv *priv, u32 start_idx,
  1562. u32 num_events, u32 mode,
  1563. int pos, char **buf, size_t bufsz)
  1564. {
  1565. u32 i;
  1566. u32 base; /* SRAM byte address of event log header */
  1567. u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
  1568. u32 ptr; /* SRAM byte address of log data */
  1569. u32 ev, time, data; /* event log data */
  1570. unsigned long reg_flags;
  1571. if (num_events == 0)
  1572. return pos;
  1573. if (priv->ucode_type == UCODE_INIT)
  1574. base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
  1575. else
  1576. base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
  1577. if (mode == 0)
  1578. event_size = 2 * sizeof(u32);
  1579. else
  1580. event_size = 3 * sizeof(u32);
  1581. ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
  1582. /* Make sure device is powered up for SRAM reads */
  1583. spin_lock_irqsave(&priv->reg_lock, reg_flags);
  1584. iwl_grab_nic_access(priv);
  1585. /* Set starting address; reads will auto-increment */
  1586. _iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, ptr);
  1587. rmb();
  1588. /* "time" is actually "data" for mode 0 (no timestamp).
  1589. * place event id # at far right for easier visual parsing. */
  1590. for (i = 0; i < num_events; i++) {
  1591. ev = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  1592. time = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  1593. if (mode == 0) {
  1594. /* data, ev */
  1595. if (bufsz) {
  1596. pos += scnprintf(*buf + pos, bufsz - pos,
  1597. "EVT_LOG:0x%08x:%04u\n",
  1598. time, ev);
  1599. } else {
  1600. trace_iwlwifi_dev_ucode_event(priv, 0,
  1601. time, ev);
  1602. IWL_ERR(priv, "EVT_LOG:0x%08x:%04u\n",
  1603. time, ev);
  1604. }
  1605. } else {
  1606. data = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  1607. if (bufsz) {
  1608. pos += scnprintf(*buf + pos, bufsz - pos,
  1609. "EVT_LOGT:%010u:0x%08x:%04u\n",
  1610. time, data, ev);
  1611. } else {
  1612. IWL_ERR(priv, "EVT_LOGT:%010u:0x%08x:%04u\n",
  1613. time, data, ev);
  1614. trace_iwlwifi_dev_ucode_event(priv, time,
  1615. data, ev);
  1616. }
  1617. }
  1618. }
  1619. /* Allow device to power down */
  1620. iwl_release_nic_access(priv);
  1621. spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
  1622. return pos;
  1623. }
  1624. /**
  1625. * iwl_print_last_event_logs - Dump the newest # of event log to syslog
  1626. */
  1627. static int iwl_print_last_event_logs(struct iwl_priv *priv, u32 capacity,
  1628. u32 num_wraps, u32 next_entry,
  1629. u32 size, u32 mode,
  1630. int pos, char **buf, size_t bufsz)
  1631. {
  1632. /*
  1633. * display the newest DEFAULT_LOG_ENTRIES entries
  1634. * i.e the entries just before the next ont that uCode would fill.
  1635. */
  1636. if (num_wraps) {
  1637. if (next_entry < size) {
  1638. pos = iwl_print_event_log(priv,
  1639. capacity - (size - next_entry),
  1640. size - next_entry, mode,
  1641. pos, buf, bufsz);
  1642. pos = iwl_print_event_log(priv, 0,
  1643. next_entry, mode,
  1644. pos, buf, bufsz);
  1645. } else
  1646. pos = iwl_print_event_log(priv, next_entry - size,
  1647. size, mode, pos, buf, bufsz);
  1648. } else {
  1649. if (next_entry < size) {
  1650. pos = iwl_print_event_log(priv, 0, next_entry,
  1651. mode, pos, buf, bufsz);
  1652. } else {
  1653. pos = iwl_print_event_log(priv, next_entry - size,
  1654. size, mode, pos, buf, bufsz);
  1655. }
  1656. }
  1657. return pos;
  1658. }
  1659. /* For sanity check only. Actual size is determined by uCode, typ. 512 */
  1660. #define MAX_EVENT_LOG_SIZE (512)
  1661. #define DEFAULT_DUMP_EVENT_LOG_ENTRIES (20)
  1662. int iwl_dump_nic_event_log(struct iwl_priv *priv, bool full_log,
  1663. char **buf, bool display)
  1664. {
  1665. u32 base; /* SRAM byte address of event log header */
  1666. u32 capacity; /* event log capacity in # entries */
  1667. u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
  1668. u32 num_wraps; /* # times uCode wrapped to top of log */
  1669. u32 next_entry; /* index of next entry to be written by uCode */
  1670. u32 size; /* # entries that we'll print */
  1671. int pos = 0;
  1672. size_t bufsz = 0;
  1673. if (priv->ucode_type == UCODE_INIT)
  1674. base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
  1675. else
  1676. base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
  1677. if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
  1678. IWL_ERR(priv,
  1679. "Invalid event log pointer 0x%08X for %s uCode\n",
  1680. base, (priv->ucode_type == UCODE_INIT) ? "Init" : "RT");
  1681. return -EINVAL;
  1682. }
  1683. /* event log header */
  1684. capacity = iwl_read_targ_mem(priv, base);
  1685. mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
  1686. num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
  1687. next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
  1688. if (capacity > MAX_EVENT_LOG_SIZE) {
  1689. IWL_ERR(priv, "Log capacity %d is bogus, limit to %d entries\n",
  1690. capacity, MAX_EVENT_LOG_SIZE);
  1691. capacity = MAX_EVENT_LOG_SIZE;
  1692. }
  1693. if (next_entry > MAX_EVENT_LOG_SIZE) {
  1694. IWL_ERR(priv, "Log write index %d is bogus, limit to %d\n",
  1695. next_entry, MAX_EVENT_LOG_SIZE);
  1696. next_entry = MAX_EVENT_LOG_SIZE;
  1697. }
  1698. size = num_wraps ? capacity : next_entry;
  1699. /* bail out if nothing in log */
  1700. if (size == 0) {
  1701. IWL_ERR(priv, "Start IWL Event Log Dump: nothing in log\n");
  1702. return pos;
  1703. }
  1704. #ifdef CONFIG_IWLWIFI_DEBUG
  1705. if (!(iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) && !full_log)
  1706. size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
  1707. ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
  1708. #else
  1709. size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
  1710. ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
  1711. #endif
  1712. IWL_ERR(priv, "Start IWL Event Log Dump: display last %u entries\n",
  1713. size);
  1714. #ifdef CONFIG_IWLWIFI_DEBUG
  1715. if (display) {
  1716. if (full_log)
  1717. bufsz = capacity * 48;
  1718. else
  1719. bufsz = size * 48;
  1720. *buf = kmalloc(bufsz, GFP_KERNEL);
  1721. if (!*buf)
  1722. return -ENOMEM;
  1723. }
  1724. if ((iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) || full_log) {
  1725. /*
  1726. * if uCode has wrapped back to top of log,
  1727. * start at the oldest entry,
  1728. * i.e the next one that uCode would fill.
  1729. */
  1730. if (num_wraps)
  1731. pos = iwl_print_event_log(priv, next_entry,
  1732. capacity - next_entry, mode,
  1733. pos, buf, bufsz);
  1734. /* (then/else) start at top of log */
  1735. pos = iwl_print_event_log(priv, 0,
  1736. next_entry, mode, pos, buf, bufsz);
  1737. } else
  1738. pos = iwl_print_last_event_logs(priv, capacity, num_wraps,
  1739. next_entry, size, mode,
  1740. pos, buf, bufsz);
  1741. #else
  1742. pos = iwl_print_last_event_logs(priv, capacity, num_wraps,
  1743. next_entry, size, mode,
  1744. pos, buf, bufsz);
  1745. #endif
  1746. return pos;
  1747. }
  1748. /**
  1749. * iwl_alive_start - called after REPLY_ALIVE notification received
  1750. * from protocol/runtime uCode (initialization uCode's
  1751. * Alive gets handled by iwl_init_alive_start()).
  1752. */
  1753. static void iwl_alive_start(struct iwl_priv *priv)
  1754. {
  1755. int ret = 0;
  1756. IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
  1757. if (priv->card_alive.is_valid != UCODE_VALID_OK) {
  1758. /* We had an error bringing up the hardware, so take it
  1759. * all the way back down so we can try again */
  1760. IWL_DEBUG_INFO(priv, "Alive failed.\n");
  1761. goto restart;
  1762. }
  1763. /* Initialize uCode has loaded Runtime uCode ... verify inst image.
  1764. * This is a paranoid check, because we would not have gotten the
  1765. * "runtime" alive if code weren't properly loaded. */
  1766. if (iwl_verify_ucode(priv)) {
  1767. /* Runtime instruction load was bad;
  1768. * take it all the way back down so we can try again */
  1769. IWL_DEBUG_INFO(priv, "Bad runtime uCode load.\n");
  1770. goto restart;
  1771. }
  1772. iwl_clear_stations_table(priv);
  1773. ret = priv->cfg->ops->lib->alive_notify(priv);
  1774. if (ret) {
  1775. IWL_WARN(priv,
  1776. "Could not complete ALIVE transition [ntf]: %d\n", ret);
  1777. goto restart;
  1778. }
  1779. /* After the ALIVE response, we can send host commands to the uCode */
  1780. set_bit(STATUS_ALIVE, &priv->status);
  1781. if (iwl_is_rfkill(priv))
  1782. return;
  1783. ieee80211_wake_queues(priv->hw);
  1784. priv->active_rate = IWL_RATES_MASK;
  1785. /* Configure Tx antenna selection based on H/W config */
  1786. if (priv->cfg->ops->hcmd->set_tx_ant)
  1787. priv->cfg->ops->hcmd->set_tx_ant(priv, priv->cfg->valid_tx_ant);
  1788. if (iwl_is_associated(priv)) {
  1789. struct iwl_rxon_cmd *active_rxon =
  1790. (struct iwl_rxon_cmd *)&priv->active_rxon;
  1791. /* apply any changes in staging */
  1792. priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
  1793. active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  1794. } else {
  1795. /* Initialize our rx_config data */
  1796. iwl_connection_init_rx_config(priv, priv->iw_mode);
  1797. if (priv->cfg->ops->hcmd->set_rxon_chain)
  1798. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  1799. memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
  1800. }
  1801. /* Configure Bluetooth device coexistence support */
  1802. iwl_send_bt_config(priv);
  1803. iwl_reset_run_time_calib(priv);
  1804. /* Configure the adapter for unassociated operation */
  1805. iwlcore_commit_rxon(priv);
  1806. /* At this point, the NIC is initialized and operational */
  1807. iwl_rf_kill_ct_config(priv);
  1808. iwl_leds_init(priv);
  1809. IWL_DEBUG_INFO(priv, "ALIVE processing complete.\n");
  1810. set_bit(STATUS_READY, &priv->status);
  1811. wake_up_interruptible(&priv->wait_command_queue);
  1812. iwl_power_update_mode(priv, true);
  1813. if (test_and_clear_bit(STATUS_MODE_PENDING, &priv->status))
  1814. iwl_set_mode(priv, priv->iw_mode);
  1815. return;
  1816. restart:
  1817. queue_work(priv->workqueue, &priv->restart);
  1818. }
  1819. static void iwl_cancel_deferred_work(struct iwl_priv *priv);
  1820. static void __iwl_down(struct iwl_priv *priv)
  1821. {
  1822. unsigned long flags;
  1823. int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status);
  1824. IWL_DEBUG_INFO(priv, DRV_NAME " is going down\n");
  1825. if (!exit_pending)
  1826. set_bit(STATUS_EXIT_PENDING, &priv->status);
  1827. iwl_clear_stations_table(priv);
  1828. /* Unblock any waiting calls */
  1829. wake_up_interruptible_all(&priv->wait_command_queue);
  1830. /* Wipe out the EXIT_PENDING status bit if we are not actually
  1831. * exiting the module */
  1832. if (!exit_pending)
  1833. clear_bit(STATUS_EXIT_PENDING, &priv->status);
  1834. /* stop and reset the on-board processor */
  1835. iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
  1836. /* tell the device to stop sending interrupts */
  1837. spin_lock_irqsave(&priv->lock, flags);
  1838. iwl_disable_interrupts(priv);
  1839. spin_unlock_irqrestore(&priv->lock, flags);
  1840. iwl_synchronize_irq(priv);
  1841. if (priv->mac80211_registered)
  1842. ieee80211_stop_queues(priv->hw);
  1843. /* If we have not previously called iwl_init() then
  1844. * clear all bits but the RF Kill bit and return */
  1845. if (!iwl_is_init(priv)) {
  1846. priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) <<
  1847. STATUS_RF_KILL_HW |
  1848. test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
  1849. STATUS_GEO_CONFIGURED |
  1850. test_bit(STATUS_EXIT_PENDING, &priv->status) <<
  1851. STATUS_EXIT_PENDING;
  1852. goto exit;
  1853. }
  1854. /* ...otherwise clear out all the status bits but the RF Kill
  1855. * bit and continue taking the NIC down. */
  1856. priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
  1857. STATUS_RF_KILL_HW |
  1858. test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
  1859. STATUS_GEO_CONFIGURED |
  1860. test_bit(STATUS_FW_ERROR, &priv->status) <<
  1861. STATUS_FW_ERROR |
  1862. test_bit(STATUS_EXIT_PENDING, &priv->status) <<
  1863. STATUS_EXIT_PENDING;
  1864. /* device going down, Stop using ICT table */
  1865. iwl_disable_ict(priv);
  1866. iwl_txq_ctx_stop(priv);
  1867. iwl_rxq_stop(priv);
  1868. /* Power-down device's busmaster DMA clocks */
  1869. iwl_write_prph(priv, APMG_CLK_DIS_REG, APMG_CLK_VAL_DMA_CLK_RQT);
  1870. udelay(5);
  1871. /* Make sure (redundant) we've released our request to stay awake */
  1872. iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
  1873. /* Stop the device, and put it in low power state */
  1874. priv->cfg->ops->lib->apm_ops.stop(priv);
  1875. exit:
  1876. memset(&priv->card_alive, 0, sizeof(struct iwl_alive_resp));
  1877. if (priv->ibss_beacon)
  1878. dev_kfree_skb(priv->ibss_beacon);
  1879. priv->ibss_beacon = NULL;
  1880. /* clear out any free frames */
  1881. iwl_clear_free_frames(priv);
  1882. }
  1883. static void iwl_down(struct iwl_priv *priv)
  1884. {
  1885. mutex_lock(&priv->mutex);
  1886. __iwl_down(priv);
  1887. mutex_unlock(&priv->mutex);
  1888. iwl_cancel_deferred_work(priv);
  1889. }
  1890. #define HW_READY_TIMEOUT (50)
  1891. static int iwl_set_hw_ready(struct iwl_priv *priv)
  1892. {
  1893. int ret = 0;
  1894. iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
  1895. CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
  1896. /* See if we got it */
  1897. ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
  1898. CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
  1899. CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
  1900. HW_READY_TIMEOUT);
  1901. if (ret != -ETIMEDOUT)
  1902. priv->hw_ready = true;
  1903. else
  1904. priv->hw_ready = false;
  1905. IWL_DEBUG_INFO(priv, "hardware %s\n",
  1906. (priv->hw_ready == 1) ? "ready" : "not ready");
  1907. return ret;
  1908. }
  1909. static int iwl_prepare_card_hw(struct iwl_priv *priv)
  1910. {
  1911. int ret = 0;
  1912. IWL_DEBUG_INFO(priv, "iwl_prepare_card_hw enter \n");
  1913. ret = iwl_set_hw_ready(priv);
  1914. if (priv->hw_ready)
  1915. return ret;
  1916. /* If HW is not ready, prepare the conditions to check again */
  1917. iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
  1918. CSR_HW_IF_CONFIG_REG_PREPARE);
  1919. ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
  1920. ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE,
  1921. CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000);
  1922. /* HW should be ready by now, check again. */
  1923. if (ret != -ETIMEDOUT)
  1924. iwl_set_hw_ready(priv);
  1925. return ret;
  1926. }
  1927. #define MAX_HW_RESTARTS 5
  1928. static int __iwl_up(struct iwl_priv *priv)
  1929. {
  1930. int i;
  1931. int ret;
  1932. if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
  1933. IWL_WARN(priv, "Exit pending; will not bring the NIC up\n");
  1934. return -EIO;
  1935. }
  1936. if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) {
  1937. IWL_ERR(priv, "ucode not available for device bringup\n");
  1938. return -EIO;
  1939. }
  1940. iwl_prepare_card_hw(priv);
  1941. if (!priv->hw_ready) {
  1942. IWL_WARN(priv, "Exit HW not ready\n");
  1943. return -EIO;
  1944. }
  1945. /* If platform's RF_KILL switch is NOT set to KILL */
  1946. if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
  1947. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  1948. else
  1949. set_bit(STATUS_RF_KILL_HW, &priv->status);
  1950. if (iwl_is_rfkill(priv)) {
  1951. wiphy_rfkill_set_hw_state(priv->hw->wiphy, true);
  1952. iwl_enable_interrupts(priv);
  1953. IWL_WARN(priv, "Radio disabled by HW RF Kill switch\n");
  1954. return 0;
  1955. }
  1956. iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
  1957. ret = iwl_hw_nic_init(priv);
  1958. if (ret) {
  1959. IWL_ERR(priv, "Unable to init nic\n");
  1960. return ret;
  1961. }
  1962. /* make sure rfkill handshake bits are cleared */
  1963. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  1964. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
  1965. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  1966. /* clear (again), then enable host interrupts */
  1967. iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
  1968. iwl_enable_interrupts(priv);
  1969. /* really make sure rfkill handshake bits are cleared */
  1970. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  1971. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  1972. /* Copy original ucode data image from disk into backup cache.
  1973. * This will be used to initialize the on-board processor's
  1974. * data SRAM for a clean start when the runtime program first loads. */
  1975. memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr,
  1976. priv->ucode_data.len);
  1977. for (i = 0; i < MAX_HW_RESTARTS; i++) {
  1978. iwl_clear_stations_table(priv);
  1979. /* load bootstrap state machine,
  1980. * load bootstrap program into processor's memory,
  1981. * prepare to load the "initialize" uCode */
  1982. ret = priv->cfg->ops->lib->load_ucode(priv);
  1983. if (ret) {
  1984. IWL_ERR(priv, "Unable to set up bootstrap uCode: %d\n",
  1985. ret);
  1986. continue;
  1987. }
  1988. /* start card; "initialize" will load runtime ucode */
  1989. iwl_nic_start(priv);
  1990. IWL_DEBUG_INFO(priv, DRV_NAME " is coming up\n");
  1991. return 0;
  1992. }
  1993. set_bit(STATUS_EXIT_PENDING, &priv->status);
  1994. __iwl_down(priv);
  1995. clear_bit(STATUS_EXIT_PENDING, &priv->status);
  1996. /* tried to restart and config the device for as long as our
  1997. * patience could withstand */
  1998. IWL_ERR(priv, "Unable to initialize device after %d attempts.\n", i);
  1999. return -EIO;
  2000. }
  2001. /*****************************************************************************
  2002. *
  2003. * Workqueue callbacks
  2004. *
  2005. *****************************************************************************/
  2006. static void iwl_bg_init_alive_start(struct work_struct *data)
  2007. {
  2008. struct iwl_priv *priv =
  2009. container_of(data, struct iwl_priv, init_alive_start.work);
  2010. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2011. return;
  2012. mutex_lock(&priv->mutex);
  2013. priv->cfg->ops->lib->init_alive_start(priv);
  2014. mutex_unlock(&priv->mutex);
  2015. }
  2016. static void iwl_bg_alive_start(struct work_struct *data)
  2017. {
  2018. struct iwl_priv *priv =
  2019. container_of(data, struct iwl_priv, alive_start.work);
  2020. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2021. return;
  2022. /* enable dram interrupt */
  2023. iwl_reset_ict(priv);
  2024. mutex_lock(&priv->mutex);
  2025. iwl_alive_start(priv);
  2026. mutex_unlock(&priv->mutex);
  2027. }
  2028. static void iwl_bg_run_time_calib_work(struct work_struct *work)
  2029. {
  2030. struct iwl_priv *priv = container_of(work, struct iwl_priv,
  2031. run_time_calib_work);
  2032. mutex_lock(&priv->mutex);
  2033. if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
  2034. test_bit(STATUS_SCANNING, &priv->status)) {
  2035. mutex_unlock(&priv->mutex);
  2036. return;
  2037. }
  2038. if (priv->start_calib) {
  2039. iwl_chain_noise_calibration(priv, &priv->statistics);
  2040. iwl_sensitivity_calibration(priv, &priv->statistics);
  2041. }
  2042. mutex_unlock(&priv->mutex);
  2043. return;
  2044. }
  2045. static void iwl_bg_restart(struct work_struct *data)
  2046. {
  2047. struct iwl_priv *priv = container_of(data, struct iwl_priv, restart);
  2048. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2049. return;
  2050. if (test_and_clear_bit(STATUS_FW_ERROR, &priv->status)) {
  2051. mutex_lock(&priv->mutex);
  2052. priv->vif = NULL;
  2053. priv->is_open = 0;
  2054. mutex_unlock(&priv->mutex);
  2055. iwl_down(priv);
  2056. ieee80211_restart_hw(priv->hw);
  2057. } else {
  2058. iwl_down(priv);
  2059. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2060. return;
  2061. mutex_lock(&priv->mutex);
  2062. __iwl_up(priv);
  2063. mutex_unlock(&priv->mutex);
  2064. }
  2065. }
  2066. static void iwl_bg_rx_replenish(struct work_struct *data)
  2067. {
  2068. struct iwl_priv *priv =
  2069. container_of(data, struct iwl_priv, rx_replenish);
  2070. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2071. return;
  2072. mutex_lock(&priv->mutex);
  2073. iwl_rx_replenish(priv);
  2074. mutex_unlock(&priv->mutex);
  2075. }
  2076. #define IWL_DELAY_NEXT_SCAN (HZ*2)
  2077. void iwl_post_associate(struct iwl_priv *priv)
  2078. {
  2079. struct ieee80211_conf *conf = NULL;
  2080. int ret = 0;
  2081. unsigned long flags;
  2082. if (priv->iw_mode == NL80211_IFTYPE_AP) {
  2083. IWL_ERR(priv, "%s Should not be called in AP mode\n", __func__);
  2084. return;
  2085. }
  2086. IWL_DEBUG_ASSOC(priv, "Associated as %d to: %pM\n",
  2087. priv->assoc_id, priv->active_rxon.bssid_addr);
  2088. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2089. return;
  2090. if (!priv->vif || !priv->is_open)
  2091. return;
  2092. iwl_scan_cancel_timeout(priv, 200);
  2093. conf = ieee80211_get_hw_conf(priv->hw);
  2094. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  2095. iwlcore_commit_rxon(priv);
  2096. iwl_setup_rxon_timing(priv);
  2097. ret = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING,
  2098. sizeof(priv->rxon_timing), &priv->rxon_timing);
  2099. if (ret)
  2100. IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
  2101. "Attempting to continue.\n");
  2102. priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
  2103. iwl_set_rxon_ht(priv, &priv->current_ht_config);
  2104. if (priv->cfg->ops->hcmd->set_rxon_chain)
  2105. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  2106. priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
  2107. IWL_DEBUG_ASSOC(priv, "assoc id %d beacon interval %d\n",
  2108. priv->assoc_id, priv->beacon_int);
  2109. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
  2110. priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
  2111. else
  2112. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
  2113. if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
  2114. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
  2115. priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
  2116. else
  2117. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  2118. if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
  2119. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  2120. }
  2121. iwlcore_commit_rxon(priv);
  2122. switch (priv->iw_mode) {
  2123. case NL80211_IFTYPE_STATION:
  2124. break;
  2125. case NL80211_IFTYPE_ADHOC:
  2126. /* assume default assoc id */
  2127. priv->assoc_id = 1;
  2128. iwl_rxon_add_station(priv, priv->bssid, 0);
  2129. iwl_send_beacon_cmd(priv);
  2130. break;
  2131. default:
  2132. IWL_ERR(priv, "%s Should not be called in %d mode\n",
  2133. __func__, priv->iw_mode);
  2134. break;
  2135. }
  2136. if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
  2137. priv->assoc_station_added = 1;
  2138. spin_lock_irqsave(&priv->lock, flags);
  2139. iwl_activate_qos(priv, 0);
  2140. spin_unlock_irqrestore(&priv->lock, flags);
  2141. /* the chain noise calibration will enabled PM upon completion
  2142. * If chain noise has already been run, then we need to enable
  2143. * power management here */
  2144. if (priv->chain_noise_data.state == IWL_CHAIN_NOISE_DONE)
  2145. iwl_power_update_mode(priv, false);
  2146. /* Enable Rx differential gain and sensitivity calibrations */
  2147. iwl_chain_noise_reset(priv);
  2148. priv->start_calib = 1;
  2149. }
  2150. /*****************************************************************************
  2151. *
  2152. * mac80211 entry point functions
  2153. *
  2154. *****************************************************************************/
  2155. #define UCODE_READY_TIMEOUT (4 * HZ)
  2156. /*
  2157. * Not a mac80211 entry point function, but it fits in with all the
  2158. * other mac80211 functions grouped here.
  2159. */
  2160. static int iwl_mac_setup_register(struct iwl_priv *priv)
  2161. {
  2162. int ret;
  2163. struct ieee80211_hw *hw = priv->hw;
  2164. hw->rate_control_algorithm = "iwl-agn-rs";
  2165. /* Tell mac80211 our characteristics */
  2166. hw->flags = IEEE80211_HW_SIGNAL_DBM |
  2167. IEEE80211_HW_NOISE_DBM |
  2168. IEEE80211_HW_AMPDU_AGGREGATION |
  2169. IEEE80211_HW_SPECTRUM_MGMT;
  2170. if (!priv->cfg->broken_powersave)
  2171. hw->flags |= IEEE80211_HW_SUPPORTS_PS |
  2172. IEEE80211_HW_SUPPORTS_DYNAMIC_PS;
  2173. if (priv->cfg->sku & IWL_SKU_N)
  2174. hw->flags |= IEEE80211_HW_SUPPORTS_DYNAMIC_SMPS |
  2175. IEEE80211_HW_SUPPORTS_STATIC_SMPS;
  2176. hw->sta_data_size = sizeof(struct iwl_station_priv);
  2177. hw->wiphy->interface_modes =
  2178. BIT(NL80211_IFTYPE_STATION) |
  2179. BIT(NL80211_IFTYPE_ADHOC);
  2180. hw->wiphy->flags |= WIPHY_FLAG_STRICT_REGULATORY |
  2181. WIPHY_FLAG_DISABLE_BEACON_HINTS;
  2182. /*
  2183. * For now, disable PS by default because it affects
  2184. * RX performance significantly.
  2185. */
  2186. hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
  2187. hw->wiphy->max_scan_ssids = PROBE_OPTION_MAX + 1;
  2188. /* we create the 802.11 header and a zero-length SSID element */
  2189. hw->wiphy->max_scan_ie_len = IWL_MAX_PROBE_REQUEST - 24 - 2;
  2190. /* Default value; 4 EDCA QOS priorities */
  2191. hw->queues = 4;
  2192. hw->max_listen_interval = IWL_CONN_MAX_LISTEN_INTERVAL;
  2193. if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
  2194. priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
  2195. &priv->bands[IEEE80211_BAND_2GHZ];
  2196. if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
  2197. priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
  2198. &priv->bands[IEEE80211_BAND_5GHZ];
  2199. ret = ieee80211_register_hw(priv->hw);
  2200. if (ret) {
  2201. IWL_ERR(priv, "Failed to register hw (error %d)\n", ret);
  2202. return ret;
  2203. }
  2204. priv->mac80211_registered = 1;
  2205. return 0;
  2206. }
  2207. static int iwl_mac_start(struct ieee80211_hw *hw)
  2208. {
  2209. struct iwl_priv *priv = hw->priv;
  2210. int ret;
  2211. IWL_DEBUG_MAC80211(priv, "enter\n");
  2212. /* we should be verifying the device is ready to be opened */
  2213. mutex_lock(&priv->mutex);
  2214. ret = __iwl_up(priv);
  2215. mutex_unlock(&priv->mutex);
  2216. if (ret)
  2217. return ret;
  2218. if (iwl_is_rfkill(priv))
  2219. goto out;
  2220. IWL_DEBUG_INFO(priv, "Start UP work done.\n");
  2221. /* Wait for START_ALIVE from Run Time ucode. Otherwise callbacks from
  2222. * mac80211 will not be run successfully. */
  2223. ret = wait_event_interruptible_timeout(priv->wait_command_queue,
  2224. test_bit(STATUS_READY, &priv->status),
  2225. UCODE_READY_TIMEOUT);
  2226. if (!ret) {
  2227. if (!test_bit(STATUS_READY, &priv->status)) {
  2228. IWL_ERR(priv, "START_ALIVE timeout after %dms.\n",
  2229. jiffies_to_msecs(UCODE_READY_TIMEOUT));
  2230. return -ETIMEDOUT;
  2231. }
  2232. }
  2233. iwl_led_start(priv);
  2234. out:
  2235. priv->is_open = 1;
  2236. IWL_DEBUG_MAC80211(priv, "leave\n");
  2237. return 0;
  2238. }
  2239. static void iwl_mac_stop(struct ieee80211_hw *hw)
  2240. {
  2241. struct iwl_priv *priv = hw->priv;
  2242. IWL_DEBUG_MAC80211(priv, "enter\n");
  2243. if (!priv->is_open)
  2244. return;
  2245. priv->is_open = 0;
  2246. if (iwl_is_ready_rf(priv) || test_bit(STATUS_SCAN_HW, &priv->status)) {
  2247. /* stop mac, cancel any scan request and clear
  2248. * RXON_FILTER_ASSOC_MSK BIT
  2249. */
  2250. mutex_lock(&priv->mutex);
  2251. iwl_scan_cancel_timeout(priv, 100);
  2252. mutex_unlock(&priv->mutex);
  2253. }
  2254. iwl_down(priv);
  2255. flush_workqueue(priv->workqueue);
  2256. /* enable interrupts again in order to receive rfkill changes */
  2257. iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
  2258. iwl_enable_interrupts(priv);
  2259. IWL_DEBUG_MAC80211(priv, "leave\n");
  2260. }
  2261. static int iwl_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
  2262. {
  2263. struct iwl_priv *priv = hw->priv;
  2264. IWL_DEBUG_MACDUMP(priv, "enter\n");
  2265. IWL_DEBUG_TX(priv, "dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
  2266. ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
  2267. if (iwl_tx_skb(priv, skb))
  2268. dev_kfree_skb_any(skb);
  2269. IWL_DEBUG_MACDUMP(priv, "leave\n");
  2270. return NETDEV_TX_OK;
  2271. }
  2272. void iwl_config_ap(struct iwl_priv *priv)
  2273. {
  2274. int ret = 0;
  2275. unsigned long flags;
  2276. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2277. return;
  2278. /* The following should be done only at AP bring up */
  2279. if (!iwl_is_associated(priv)) {
  2280. /* RXON - unassoc (to set timing command) */
  2281. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  2282. iwlcore_commit_rxon(priv);
  2283. /* RXON Timing */
  2284. iwl_setup_rxon_timing(priv);
  2285. ret = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING,
  2286. sizeof(priv->rxon_timing), &priv->rxon_timing);
  2287. if (ret)
  2288. IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
  2289. "Attempting to continue.\n");
  2290. /* AP has all antennas */
  2291. priv->chain_noise_data.active_chains =
  2292. priv->hw_params.valid_rx_ant;
  2293. iwl_set_rxon_ht(priv, &priv->current_ht_config);
  2294. if (priv->cfg->ops->hcmd->set_rxon_chain)
  2295. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  2296. /* FIXME: what should be the assoc_id for AP? */
  2297. priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
  2298. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
  2299. priv->staging_rxon.flags |=
  2300. RXON_FLG_SHORT_PREAMBLE_MSK;
  2301. else
  2302. priv->staging_rxon.flags &=
  2303. ~RXON_FLG_SHORT_PREAMBLE_MSK;
  2304. if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
  2305. if (priv->assoc_capability &
  2306. WLAN_CAPABILITY_SHORT_SLOT_TIME)
  2307. priv->staging_rxon.flags |=
  2308. RXON_FLG_SHORT_SLOT_MSK;
  2309. else
  2310. priv->staging_rxon.flags &=
  2311. ~RXON_FLG_SHORT_SLOT_MSK;
  2312. if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
  2313. priv->staging_rxon.flags &=
  2314. ~RXON_FLG_SHORT_SLOT_MSK;
  2315. }
  2316. /* restore RXON assoc */
  2317. priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
  2318. iwlcore_commit_rxon(priv);
  2319. iwl_reset_qos(priv);
  2320. spin_lock_irqsave(&priv->lock, flags);
  2321. iwl_activate_qos(priv, 1);
  2322. spin_unlock_irqrestore(&priv->lock, flags);
  2323. iwl_add_bcast_station(priv);
  2324. }
  2325. iwl_send_beacon_cmd(priv);
  2326. /* FIXME - we need to add code here to detect a totally new
  2327. * configuration, reset the AP, unassoc, rxon timing, assoc,
  2328. * clear sta table, add BCAST sta... */
  2329. }
  2330. static void iwl_mac_update_tkip_key(struct ieee80211_hw *hw,
  2331. struct ieee80211_vif *vif,
  2332. struct ieee80211_key_conf *keyconf,
  2333. struct ieee80211_sta *sta,
  2334. u32 iv32, u16 *phase1key)
  2335. {
  2336. struct iwl_priv *priv = hw->priv;
  2337. IWL_DEBUG_MAC80211(priv, "enter\n");
  2338. iwl_update_tkip_key(priv, keyconf,
  2339. sta ? sta->addr : iwl_bcast_addr,
  2340. iv32, phase1key);
  2341. IWL_DEBUG_MAC80211(priv, "leave\n");
  2342. }
  2343. static int iwl_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
  2344. struct ieee80211_vif *vif,
  2345. struct ieee80211_sta *sta,
  2346. struct ieee80211_key_conf *key)
  2347. {
  2348. struct iwl_priv *priv = hw->priv;
  2349. const u8 *addr;
  2350. int ret;
  2351. u8 sta_id;
  2352. bool is_default_wep_key = false;
  2353. IWL_DEBUG_MAC80211(priv, "enter\n");
  2354. if (priv->cfg->mod_params->sw_crypto) {
  2355. IWL_DEBUG_MAC80211(priv, "leave - hwcrypto disabled\n");
  2356. return -EOPNOTSUPP;
  2357. }
  2358. addr = sta ? sta->addr : iwl_bcast_addr;
  2359. sta_id = iwl_find_station(priv, addr);
  2360. if (sta_id == IWL_INVALID_STATION) {
  2361. IWL_DEBUG_MAC80211(priv, "leave - %pM not in station map.\n",
  2362. addr);
  2363. return -EINVAL;
  2364. }
  2365. mutex_lock(&priv->mutex);
  2366. iwl_scan_cancel_timeout(priv, 100);
  2367. mutex_unlock(&priv->mutex);
  2368. /* If we are getting WEP group key and we didn't receive any key mapping
  2369. * so far, we are in legacy wep mode (group key only), otherwise we are
  2370. * in 1X mode.
  2371. * In legacy wep mode, we use another host command to the uCode */
  2372. if (key->alg == ALG_WEP && sta_id == priv->hw_params.bcast_sta_id &&
  2373. priv->iw_mode != NL80211_IFTYPE_AP) {
  2374. if (cmd == SET_KEY)
  2375. is_default_wep_key = !priv->key_mapping_key;
  2376. else
  2377. is_default_wep_key =
  2378. (key->hw_key_idx == HW_KEY_DEFAULT);
  2379. }
  2380. switch (cmd) {
  2381. case SET_KEY:
  2382. if (is_default_wep_key)
  2383. ret = iwl_set_default_wep_key(priv, key);
  2384. else
  2385. ret = iwl_set_dynamic_key(priv, key, sta_id);
  2386. IWL_DEBUG_MAC80211(priv, "enable hwcrypto key\n");
  2387. break;
  2388. case DISABLE_KEY:
  2389. if (is_default_wep_key)
  2390. ret = iwl_remove_default_wep_key(priv, key);
  2391. else
  2392. ret = iwl_remove_dynamic_key(priv, key, sta_id);
  2393. IWL_DEBUG_MAC80211(priv, "disable hwcrypto key\n");
  2394. break;
  2395. default:
  2396. ret = -EINVAL;
  2397. }
  2398. IWL_DEBUG_MAC80211(priv, "leave\n");
  2399. return ret;
  2400. }
  2401. static int iwl_mac_ampdu_action(struct ieee80211_hw *hw,
  2402. struct ieee80211_vif *vif,
  2403. enum ieee80211_ampdu_mlme_action action,
  2404. struct ieee80211_sta *sta, u16 tid, u16 *ssn)
  2405. {
  2406. struct iwl_priv *priv = hw->priv;
  2407. int ret;
  2408. IWL_DEBUG_HT(priv, "A-MPDU action on addr %pM tid %d\n",
  2409. sta->addr, tid);
  2410. if (!(priv->cfg->sku & IWL_SKU_N))
  2411. return -EACCES;
  2412. switch (action) {
  2413. case IEEE80211_AMPDU_RX_START:
  2414. IWL_DEBUG_HT(priv, "start Rx\n");
  2415. return iwl_sta_rx_agg_start(priv, sta->addr, tid, *ssn);
  2416. case IEEE80211_AMPDU_RX_STOP:
  2417. IWL_DEBUG_HT(priv, "stop Rx\n");
  2418. ret = iwl_sta_rx_agg_stop(priv, sta->addr, tid);
  2419. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2420. return 0;
  2421. else
  2422. return ret;
  2423. case IEEE80211_AMPDU_TX_START:
  2424. IWL_DEBUG_HT(priv, "start Tx\n");
  2425. return iwl_tx_agg_start(priv, sta->addr, tid, ssn);
  2426. case IEEE80211_AMPDU_TX_STOP:
  2427. IWL_DEBUG_HT(priv, "stop Tx\n");
  2428. ret = iwl_tx_agg_stop(priv, sta->addr, tid);
  2429. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2430. return 0;
  2431. else
  2432. return ret;
  2433. case IEEE80211_AMPDU_TX_OPERATIONAL:
  2434. /* do nothing */
  2435. return -EOPNOTSUPP;
  2436. default:
  2437. IWL_DEBUG_HT(priv, "unknown\n");
  2438. return -EINVAL;
  2439. break;
  2440. }
  2441. return 0;
  2442. }
  2443. static int iwl_mac_get_stats(struct ieee80211_hw *hw,
  2444. struct ieee80211_low_level_stats *stats)
  2445. {
  2446. struct iwl_priv *priv = hw->priv;
  2447. priv = hw->priv;
  2448. IWL_DEBUG_MAC80211(priv, "enter\n");
  2449. IWL_DEBUG_MAC80211(priv, "leave\n");
  2450. return 0;
  2451. }
  2452. static void iwl_mac_sta_notify(struct ieee80211_hw *hw,
  2453. struct ieee80211_vif *vif,
  2454. enum sta_notify_cmd cmd,
  2455. struct ieee80211_sta *sta)
  2456. {
  2457. struct iwl_priv *priv = hw->priv;
  2458. struct iwl_station_priv *sta_priv = (void *)sta->drv_priv;
  2459. int sta_id;
  2460. /*
  2461. * TODO: We really should use this callback to
  2462. * actually maintain the station table in
  2463. * the device.
  2464. */
  2465. switch (cmd) {
  2466. case STA_NOTIFY_ADD:
  2467. atomic_set(&sta_priv->pending_frames, 0);
  2468. if (vif->type == NL80211_IFTYPE_AP)
  2469. sta_priv->client = true;
  2470. break;
  2471. case STA_NOTIFY_SLEEP:
  2472. WARN_ON(!sta_priv->client);
  2473. sta_priv->asleep = true;
  2474. if (atomic_read(&sta_priv->pending_frames) > 0)
  2475. ieee80211_sta_block_awake(hw, sta, true);
  2476. break;
  2477. case STA_NOTIFY_AWAKE:
  2478. WARN_ON(!sta_priv->client);
  2479. if (!sta_priv->asleep)
  2480. break;
  2481. sta_priv->asleep = false;
  2482. sta_id = iwl_find_station(priv, sta->addr);
  2483. if (sta_id != IWL_INVALID_STATION)
  2484. iwl_sta_modify_ps_wake(priv, sta_id);
  2485. break;
  2486. default:
  2487. break;
  2488. }
  2489. }
  2490. /*****************************************************************************
  2491. *
  2492. * sysfs attributes
  2493. *
  2494. *****************************************************************************/
  2495. #ifdef CONFIG_IWLWIFI_DEBUG
  2496. /*
  2497. * The following adds a new attribute to the sysfs representation
  2498. * of this device driver (i.e. a new file in /sys/class/net/wlan0/device/)
  2499. * used for controlling the debug level.
  2500. *
  2501. * See the level definitions in iwl for details.
  2502. *
  2503. * The debug_level being managed using sysfs below is a per device debug
  2504. * level that is used instead of the global debug level if it (the per
  2505. * device debug level) is set.
  2506. */
  2507. static ssize_t show_debug_level(struct device *d,
  2508. struct device_attribute *attr, char *buf)
  2509. {
  2510. struct iwl_priv *priv = dev_get_drvdata(d);
  2511. return sprintf(buf, "0x%08X\n", iwl_get_debug_level(priv));
  2512. }
  2513. static ssize_t store_debug_level(struct device *d,
  2514. struct device_attribute *attr,
  2515. const char *buf, size_t count)
  2516. {
  2517. struct iwl_priv *priv = dev_get_drvdata(d);
  2518. unsigned long val;
  2519. int ret;
  2520. ret = strict_strtoul(buf, 0, &val);
  2521. if (ret)
  2522. IWL_ERR(priv, "%s is not in hex or decimal form.\n", buf);
  2523. else {
  2524. priv->debug_level = val;
  2525. if (iwl_alloc_traffic_mem(priv))
  2526. IWL_ERR(priv,
  2527. "Not enough memory to generate traffic log\n");
  2528. }
  2529. return strnlen(buf, count);
  2530. }
  2531. static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO,
  2532. show_debug_level, store_debug_level);
  2533. #endif /* CONFIG_IWLWIFI_DEBUG */
  2534. static ssize_t show_temperature(struct device *d,
  2535. struct device_attribute *attr, char *buf)
  2536. {
  2537. struct iwl_priv *priv = dev_get_drvdata(d);
  2538. if (!iwl_is_alive(priv))
  2539. return -EAGAIN;
  2540. return sprintf(buf, "%d\n", priv->temperature);
  2541. }
  2542. static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
  2543. static ssize_t show_tx_power(struct device *d,
  2544. struct device_attribute *attr, char *buf)
  2545. {
  2546. struct iwl_priv *priv = dev_get_drvdata(d);
  2547. if (!iwl_is_ready_rf(priv))
  2548. return sprintf(buf, "off\n");
  2549. else
  2550. return sprintf(buf, "%d\n", priv->tx_power_user_lmt);
  2551. }
  2552. static ssize_t store_tx_power(struct device *d,
  2553. struct device_attribute *attr,
  2554. const char *buf, size_t count)
  2555. {
  2556. struct iwl_priv *priv = dev_get_drvdata(d);
  2557. unsigned long val;
  2558. int ret;
  2559. ret = strict_strtoul(buf, 10, &val);
  2560. if (ret)
  2561. IWL_INFO(priv, "%s is not in decimal form.\n", buf);
  2562. else {
  2563. ret = iwl_set_tx_power(priv, val, false);
  2564. if (ret)
  2565. IWL_ERR(priv, "failed setting tx power (0x%d).\n",
  2566. ret);
  2567. else
  2568. ret = count;
  2569. }
  2570. return ret;
  2571. }
  2572. static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
  2573. static ssize_t show_flags(struct device *d,
  2574. struct device_attribute *attr, char *buf)
  2575. {
  2576. struct iwl_priv *priv = dev_get_drvdata(d);
  2577. return sprintf(buf, "0x%04X\n", priv->active_rxon.flags);
  2578. }
  2579. static ssize_t store_flags(struct device *d,
  2580. struct device_attribute *attr,
  2581. const char *buf, size_t count)
  2582. {
  2583. struct iwl_priv *priv = dev_get_drvdata(d);
  2584. unsigned long val;
  2585. u32 flags;
  2586. int ret = strict_strtoul(buf, 0, &val);
  2587. if (ret)
  2588. return ret;
  2589. flags = (u32)val;
  2590. mutex_lock(&priv->mutex);
  2591. if (le32_to_cpu(priv->staging_rxon.flags) != flags) {
  2592. /* Cancel any currently running scans... */
  2593. if (iwl_scan_cancel_timeout(priv, 100))
  2594. IWL_WARN(priv, "Could not cancel scan.\n");
  2595. else {
  2596. IWL_DEBUG_INFO(priv, "Commit rxon.flags = 0x%04X\n", flags);
  2597. priv->staging_rxon.flags = cpu_to_le32(flags);
  2598. iwlcore_commit_rxon(priv);
  2599. }
  2600. }
  2601. mutex_unlock(&priv->mutex);
  2602. return count;
  2603. }
  2604. static DEVICE_ATTR(flags, S_IWUSR | S_IRUGO, show_flags, store_flags);
  2605. static ssize_t show_filter_flags(struct device *d,
  2606. struct device_attribute *attr, char *buf)
  2607. {
  2608. struct iwl_priv *priv = dev_get_drvdata(d);
  2609. return sprintf(buf, "0x%04X\n",
  2610. le32_to_cpu(priv->active_rxon.filter_flags));
  2611. }
  2612. static ssize_t store_filter_flags(struct device *d,
  2613. struct device_attribute *attr,
  2614. const char *buf, size_t count)
  2615. {
  2616. struct iwl_priv *priv = dev_get_drvdata(d);
  2617. unsigned long val;
  2618. u32 filter_flags;
  2619. int ret = strict_strtoul(buf, 0, &val);
  2620. if (ret)
  2621. return ret;
  2622. filter_flags = (u32)val;
  2623. mutex_lock(&priv->mutex);
  2624. if (le32_to_cpu(priv->staging_rxon.filter_flags) != filter_flags) {
  2625. /* Cancel any currently running scans... */
  2626. if (iwl_scan_cancel_timeout(priv, 100))
  2627. IWL_WARN(priv, "Could not cancel scan.\n");
  2628. else {
  2629. IWL_DEBUG_INFO(priv, "Committing rxon.filter_flags = "
  2630. "0x%04X\n", filter_flags);
  2631. priv->staging_rxon.filter_flags =
  2632. cpu_to_le32(filter_flags);
  2633. iwlcore_commit_rxon(priv);
  2634. }
  2635. }
  2636. mutex_unlock(&priv->mutex);
  2637. return count;
  2638. }
  2639. static DEVICE_ATTR(filter_flags, S_IWUSR | S_IRUGO, show_filter_flags,
  2640. store_filter_flags);
  2641. static ssize_t show_statistics(struct device *d,
  2642. struct device_attribute *attr, char *buf)
  2643. {
  2644. struct iwl_priv *priv = dev_get_drvdata(d);
  2645. u32 size = sizeof(struct iwl_notif_statistics);
  2646. u32 len = 0, ofs = 0;
  2647. u8 *data = (u8 *)&priv->statistics;
  2648. int rc = 0;
  2649. if (!iwl_is_alive(priv))
  2650. return -EAGAIN;
  2651. mutex_lock(&priv->mutex);
  2652. rc = iwl_send_statistics_request(priv, CMD_SYNC, false);
  2653. mutex_unlock(&priv->mutex);
  2654. if (rc) {
  2655. len = sprintf(buf,
  2656. "Error sending statistics request: 0x%08X\n", rc);
  2657. return len;
  2658. }
  2659. while (size && (PAGE_SIZE - len)) {
  2660. hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
  2661. PAGE_SIZE - len, 1);
  2662. len = strlen(buf);
  2663. if (PAGE_SIZE - len)
  2664. buf[len++] = '\n';
  2665. ofs += 16;
  2666. size -= min(size, 16U);
  2667. }
  2668. return len;
  2669. }
  2670. static DEVICE_ATTR(statistics, S_IRUGO, show_statistics, NULL);
  2671. static ssize_t show_rts_ht_protection(struct device *d,
  2672. struct device_attribute *attr, char *buf)
  2673. {
  2674. struct iwl_priv *priv = dev_get_drvdata(d);
  2675. return sprintf(buf, "%s\n",
  2676. priv->cfg->use_rts_for_ht ? "RTS/CTS" : "CTS-to-self");
  2677. }
  2678. static ssize_t store_rts_ht_protection(struct device *d,
  2679. struct device_attribute *attr,
  2680. const char *buf, size_t count)
  2681. {
  2682. struct iwl_priv *priv = dev_get_drvdata(d);
  2683. unsigned long val;
  2684. int ret;
  2685. ret = strict_strtoul(buf, 10, &val);
  2686. if (ret)
  2687. IWL_INFO(priv, "Input is not in decimal form.\n");
  2688. else {
  2689. if (!iwl_is_associated(priv))
  2690. priv->cfg->use_rts_for_ht = val ? true : false;
  2691. else
  2692. IWL_ERR(priv, "Sta associated with AP - "
  2693. "Change protection mechanism is not allowed\n");
  2694. ret = count;
  2695. }
  2696. return ret;
  2697. }
  2698. static DEVICE_ATTR(rts_ht_protection, S_IWUSR | S_IRUGO,
  2699. show_rts_ht_protection, store_rts_ht_protection);
  2700. /*****************************************************************************
  2701. *
  2702. * driver setup and teardown
  2703. *
  2704. *****************************************************************************/
  2705. static void iwl_setup_deferred_work(struct iwl_priv *priv)
  2706. {
  2707. priv->workqueue = create_singlethread_workqueue(DRV_NAME);
  2708. init_waitqueue_head(&priv->wait_command_queue);
  2709. INIT_WORK(&priv->restart, iwl_bg_restart);
  2710. INIT_WORK(&priv->rx_replenish, iwl_bg_rx_replenish);
  2711. INIT_WORK(&priv->beacon_update, iwl_bg_beacon_update);
  2712. INIT_WORK(&priv->run_time_calib_work, iwl_bg_run_time_calib_work);
  2713. INIT_DELAYED_WORK(&priv->init_alive_start, iwl_bg_init_alive_start);
  2714. INIT_DELAYED_WORK(&priv->alive_start, iwl_bg_alive_start);
  2715. iwl_setup_scan_deferred_work(priv);
  2716. if (priv->cfg->ops->lib->setup_deferred_work)
  2717. priv->cfg->ops->lib->setup_deferred_work(priv);
  2718. init_timer(&priv->statistics_periodic);
  2719. priv->statistics_periodic.data = (unsigned long)priv;
  2720. priv->statistics_periodic.function = iwl_bg_statistics_periodic;
  2721. init_timer(&priv->ucode_trace);
  2722. priv->ucode_trace.data = (unsigned long)priv;
  2723. priv->ucode_trace.function = iwl_bg_ucode_trace;
  2724. if (!priv->cfg->use_isr_legacy)
  2725. tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
  2726. iwl_irq_tasklet, (unsigned long)priv);
  2727. else
  2728. tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
  2729. iwl_irq_tasklet_legacy, (unsigned long)priv);
  2730. }
  2731. static void iwl_cancel_deferred_work(struct iwl_priv *priv)
  2732. {
  2733. if (priv->cfg->ops->lib->cancel_deferred_work)
  2734. priv->cfg->ops->lib->cancel_deferred_work(priv);
  2735. cancel_delayed_work_sync(&priv->init_alive_start);
  2736. cancel_delayed_work(&priv->scan_check);
  2737. cancel_delayed_work(&priv->alive_start);
  2738. cancel_work_sync(&priv->beacon_update);
  2739. del_timer_sync(&priv->statistics_periodic);
  2740. del_timer_sync(&priv->ucode_trace);
  2741. }
  2742. static void iwl_init_hw_rates(struct iwl_priv *priv,
  2743. struct ieee80211_rate *rates)
  2744. {
  2745. int i;
  2746. for (i = 0; i < IWL_RATE_COUNT_LEGACY; i++) {
  2747. rates[i].bitrate = iwl_rates[i].ieee * 5;
  2748. rates[i].hw_value = i; /* Rate scaling will work on indexes */
  2749. rates[i].hw_value_short = i;
  2750. rates[i].flags = 0;
  2751. if ((i >= IWL_FIRST_CCK_RATE) && (i <= IWL_LAST_CCK_RATE)) {
  2752. /*
  2753. * If CCK != 1M then set short preamble rate flag.
  2754. */
  2755. rates[i].flags |=
  2756. (iwl_rates[i].plcp == IWL_RATE_1M_PLCP) ?
  2757. 0 : IEEE80211_RATE_SHORT_PREAMBLE;
  2758. }
  2759. }
  2760. }
  2761. static int iwl_init_drv(struct iwl_priv *priv)
  2762. {
  2763. int ret;
  2764. priv->ibss_beacon = NULL;
  2765. spin_lock_init(&priv->sta_lock);
  2766. spin_lock_init(&priv->hcmd_lock);
  2767. INIT_LIST_HEAD(&priv->free_frames);
  2768. mutex_init(&priv->mutex);
  2769. mutex_init(&priv->sync_cmd_mutex);
  2770. /* Clear the driver's (not device's) station table */
  2771. iwl_clear_stations_table(priv);
  2772. priv->ieee_channels = NULL;
  2773. priv->ieee_rates = NULL;
  2774. priv->band = IEEE80211_BAND_2GHZ;
  2775. priv->iw_mode = NL80211_IFTYPE_STATION;
  2776. priv->current_ht_config.smps = IEEE80211_SMPS_STATIC;
  2777. priv->missed_beacon_threshold = IWL_MISSED_BEACON_THRESHOLD_DEF;
  2778. /* initialize force reset */
  2779. priv->force_reset[IWL_RF_RESET].reset_duration =
  2780. IWL_DELAY_NEXT_FORCE_RF_RESET;
  2781. priv->force_reset[IWL_FW_RESET].reset_duration =
  2782. IWL_DELAY_NEXT_FORCE_FW_RELOAD;
  2783. /* Choose which receivers/antennas to use */
  2784. if (priv->cfg->ops->hcmd->set_rxon_chain)
  2785. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  2786. iwl_init_scan_params(priv);
  2787. iwl_reset_qos(priv);
  2788. priv->qos_data.qos_active = 0;
  2789. priv->qos_data.qos_cap.val = 0;
  2790. /* Set the tx_power_user_lmt to the lowest power level
  2791. * this value will get overwritten by channel max power avg
  2792. * from eeprom */
  2793. priv->tx_power_user_lmt = IWL_TX_POWER_TARGET_POWER_MIN;
  2794. ret = iwl_init_channel_map(priv);
  2795. if (ret) {
  2796. IWL_ERR(priv, "initializing regulatory failed: %d\n", ret);
  2797. goto err;
  2798. }
  2799. ret = iwlcore_init_geos(priv);
  2800. if (ret) {
  2801. IWL_ERR(priv, "initializing geos failed: %d\n", ret);
  2802. goto err_free_channel_map;
  2803. }
  2804. iwl_init_hw_rates(priv, priv->ieee_rates);
  2805. return 0;
  2806. err_free_channel_map:
  2807. iwl_free_channel_map(priv);
  2808. err:
  2809. return ret;
  2810. }
  2811. static void iwl_uninit_drv(struct iwl_priv *priv)
  2812. {
  2813. iwl_calib_free_results(priv);
  2814. iwlcore_free_geos(priv);
  2815. iwl_free_channel_map(priv);
  2816. kfree(priv->scan);
  2817. }
  2818. static struct attribute *iwl_sysfs_entries[] = {
  2819. &dev_attr_flags.attr,
  2820. &dev_attr_filter_flags.attr,
  2821. &dev_attr_statistics.attr,
  2822. &dev_attr_temperature.attr,
  2823. &dev_attr_tx_power.attr,
  2824. &dev_attr_rts_ht_protection.attr,
  2825. #ifdef CONFIG_IWLWIFI_DEBUG
  2826. &dev_attr_debug_level.attr,
  2827. #endif
  2828. NULL
  2829. };
  2830. static struct attribute_group iwl_attribute_group = {
  2831. .name = NULL, /* put in device directory */
  2832. .attrs = iwl_sysfs_entries,
  2833. };
  2834. static struct ieee80211_ops iwl_hw_ops = {
  2835. .tx = iwl_mac_tx,
  2836. .start = iwl_mac_start,
  2837. .stop = iwl_mac_stop,
  2838. .add_interface = iwl_mac_add_interface,
  2839. .remove_interface = iwl_mac_remove_interface,
  2840. .config = iwl_mac_config,
  2841. .configure_filter = iwl_configure_filter,
  2842. .set_key = iwl_mac_set_key,
  2843. .update_tkip_key = iwl_mac_update_tkip_key,
  2844. .get_stats = iwl_mac_get_stats,
  2845. .conf_tx = iwl_mac_conf_tx,
  2846. .reset_tsf = iwl_mac_reset_tsf,
  2847. .bss_info_changed = iwl_bss_info_changed,
  2848. .ampdu_action = iwl_mac_ampdu_action,
  2849. .hw_scan = iwl_mac_hw_scan,
  2850. .sta_notify = iwl_mac_sta_notify,
  2851. };
  2852. static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
  2853. {
  2854. int err = 0;
  2855. struct iwl_priv *priv;
  2856. struct ieee80211_hw *hw;
  2857. struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data);
  2858. unsigned long flags;
  2859. u16 pci_cmd;
  2860. /************************
  2861. * 1. Allocating HW data
  2862. ************************/
  2863. /* Disabling hardware scan means that mac80211 will perform scans
  2864. * "the hard way", rather than using device's scan. */
  2865. if (cfg->mod_params->disable_hw_scan) {
  2866. if (iwl_debug_level & IWL_DL_INFO)
  2867. dev_printk(KERN_DEBUG, &(pdev->dev),
  2868. "Disabling hw_scan\n");
  2869. iwl_hw_ops.hw_scan = NULL;
  2870. }
  2871. hw = iwl_alloc_all(cfg, &iwl_hw_ops);
  2872. if (!hw) {
  2873. err = -ENOMEM;
  2874. goto out;
  2875. }
  2876. priv = hw->priv;
  2877. /* At this point both hw and priv are allocated. */
  2878. SET_IEEE80211_DEV(hw, &pdev->dev);
  2879. IWL_DEBUG_INFO(priv, "*** LOAD DRIVER ***\n");
  2880. priv->cfg = cfg;
  2881. priv->pci_dev = pdev;
  2882. priv->inta_mask = CSR_INI_SET_MASK;
  2883. #ifdef CONFIG_IWLWIFI_DEBUG
  2884. atomic_set(&priv->restrict_refcnt, 0);
  2885. #endif
  2886. if (iwl_alloc_traffic_mem(priv))
  2887. IWL_ERR(priv, "Not enough memory to generate traffic log\n");
  2888. /**************************
  2889. * 2. Initializing PCI bus
  2890. **************************/
  2891. if (pci_enable_device(pdev)) {
  2892. err = -ENODEV;
  2893. goto out_ieee80211_free_hw;
  2894. }
  2895. pci_set_master(pdev);
  2896. err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
  2897. if (!err)
  2898. err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
  2899. if (err) {
  2900. err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
  2901. if (!err)
  2902. err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
  2903. /* both attempts failed: */
  2904. if (err) {
  2905. IWL_WARN(priv, "No suitable DMA available.\n");
  2906. goto out_pci_disable_device;
  2907. }
  2908. }
  2909. err = pci_request_regions(pdev, DRV_NAME);
  2910. if (err)
  2911. goto out_pci_disable_device;
  2912. pci_set_drvdata(pdev, priv);
  2913. /***********************
  2914. * 3. Read REV register
  2915. ***********************/
  2916. priv->hw_base = pci_iomap(pdev, 0, 0);
  2917. if (!priv->hw_base) {
  2918. err = -ENODEV;
  2919. goto out_pci_release_regions;
  2920. }
  2921. IWL_DEBUG_INFO(priv, "pci_resource_len = 0x%08llx\n",
  2922. (unsigned long long) pci_resource_len(pdev, 0));
  2923. IWL_DEBUG_INFO(priv, "pci_resource_base = %p\n", priv->hw_base);
  2924. /* these spin locks will be used in apm_ops.init and EEPROM access
  2925. * we should init now
  2926. */
  2927. spin_lock_init(&priv->reg_lock);
  2928. spin_lock_init(&priv->lock);
  2929. /*
  2930. * stop and reset the on-board processor just in case it is in a
  2931. * strange state ... like being left stranded by a primary kernel
  2932. * and this is now the kdump kernel trying to start up
  2933. */
  2934. iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
  2935. iwl_hw_detect(priv);
  2936. IWL_INFO(priv, "Detected Intel Wireless WiFi Link %s REV=0x%X\n",
  2937. priv->cfg->name, priv->hw_rev);
  2938. /* We disable the RETRY_TIMEOUT register (0x41) to keep
  2939. * PCI Tx retries from interfering with C3 CPU state */
  2940. pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
  2941. iwl_prepare_card_hw(priv);
  2942. if (!priv->hw_ready) {
  2943. IWL_WARN(priv, "Failed, HW not ready\n");
  2944. goto out_iounmap;
  2945. }
  2946. /*****************
  2947. * 4. Read EEPROM
  2948. *****************/
  2949. /* Read the EEPROM */
  2950. err = iwl_eeprom_init(priv);
  2951. if (err) {
  2952. IWL_ERR(priv, "Unable to init EEPROM\n");
  2953. goto out_iounmap;
  2954. }
  2955. err = iwl_eeprom_check_version(priv);
  2956. if (err)
  2957. goto out_free_eeprom;
  2958. /* extract MAC Address */
  2959. iwl_eeprom_get_mac(priv, priv->mac_addr);
  2960. IWL_DEBUG_INFO(priv, "MAC address: %pM\n", priv->mac_addr);
  2961. SET_IEEE80211_PERM_ADDR(priv->hw, priv->mac_addr);
  2962. /************************
  2963. * 5. Setup HW constants
  2964. ************************/
  2965. if (iwl_set_hw_params(priv)) {
  2966. IWL_ERR(priv, "failed to set hw parameters\n");
  2967. goto out_free_eeprom;
  2968. }
  2969. /*******************
  2970. * 6. Setup priv
  2971. *******************/
  2972. err = iwl_init_drv(priv);
  2973. if (err)
  2974. goto out_free_eeprom;
  2975. /* At this point both hw and priv are initialized. */
  2976. /********************
  2977. * 7. Setup services
  2978. ********************/
  2979. spin_lock_irqsave(&priv->lock, flags);
  2980. iwl_disable_interrupts(priv);
  2981. spin_unlock_irqrestore(&priv->lock, flags);
  2982. pci_enable_msi(priv->pci_dev);
  2983. iwl_alloc_isr_ict(priv);
  2984. err = request_irq(priv->pci_dev->irq, priv->cfg->ops->lib->isr,
  2985. IRQF_SHARED, DRV_NAME, priv);
  2986. if (err) {
  2987. IWL_ERR(priv, "Error allocating IRQ %d\n", priv->pci_dev->irq);
  2988. goto out_disable_msi;
  2989. }
  2990. err = sysfs_create_group(&pdev->dev.kobj, &iwl_attribute_group);
  2991. if (err) {
  2992. IWL_ERR(priv, "failed to create sysfs device attributes\n");
  2993. goto out_free_irq;
  2994. }
  2995. iwl_setup_deferred_work(priv);
  2996. iwl_setup_rx_handlers(priv);
  2997. /*********************************************
  2998. * 8. Enable interrupts and read RFKILL state
  2999. *********************************************/
  3000. /* enable interrupts if needed: hw bug w/a */
  3001. pci_read_config_word(priv->pci_dev, PCI_COMMAND, &pci_cmd);
  3002. if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
  3003. pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
  3004. pci_write_config_word(priv->pci_dev, PCI_COMMAND, pci_cmd);
  3005. }
  3006. iwl_enable_interrupts(priv);
  3007. /* If platform's RF_KILL switch is NOT set to KILL */
  3008. if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
  3009. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  3010. else
  3011. set_bit(STATUS_RF_KILL_HW, &priv->status);
  3012. wiphy_rfkill_set_hw_state(priv->hw->wiphy,
  3013. test_bit(STATUS_RF_KILL_HW, &priv->status));
  3014. iwl_power_initialize(priv);
  3015. iwl_tt_initialize(priv);
  3016. err = iwl_request_firmware(priv, true);
  3017. if (err)
  3018. goto out_remove_sysfs;
  3019. return 0;
  3020. out_remove_sysfs:
  3021. destroy_workqueue(priv->workqueue);
  3022. priv->workqueue = NULL;
  3023. sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group);
  3024. out_free_irq:
  3025. free_irq(priv->pci_dev->irq, priv);
  3026. iwl_free_isr_ict(priv);
  3027. out_disable_msi:
  3028. pci_disable_msi(priv->pci_dev);
  3029. iwl_uninit_drv(priv);
  3030. out_free_eeprom:
  3031. iwl_eeprom_free(priv);
  3032. out_iounmap:
  3033. pci_iounmap(pdev, priv->hw_base);
  3034. out_pci_release_regions:
  3035. pci_set_drvdata(pdev, NULL);
  3036. pci_release_regions(pdev);
  3037. out_pci_disable_device:
  3038. pci_disable_device(pdev);
  3039. out_ieee80211_free_hw:
  3040. iwl_free_traffic_mem(priv);
  3041. ieee80211_free_hw(priv->hw);
  3042. out:
  3043. return err;
  3044. }
  3045. static void __devexit iwl_pci_remove(struct pci_dev *pdev)
  3046. {
  3047. struct iwl_priv *priv = pci_get_drvdata(pdev);
  3048. unsigned long flags;
  3049. if (!priv)
  3050. return;
  3051. IWL_DEBUG_INFO(priv, "*** UNLOAD DRIVER ***\n");
  3052. iwl_dbgfs_unregister(priv);
  3053. sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group);
  3054. /* ieee80211_unregister_hw call wil cause iwl_mac_stop to
  3055. * to be called and iwl_down since we are removing the device
  3056. * we need to set STATUS_EXIT_PENDING bit.
  3057. */
  3058. set_bit(STATUS_EXIT_PENDING, &priv->status);
  3059. if (priv->mac80211_registered) {
  3060. ieee80211_unregister_hw(priv->hw);
  3061. priv->mac80211_registered = 0;
  3062. } else {
  3063. iwl_down(priv);
  3064. }
  3065. /*
  3066. * Make sure device is reset to low power before unloading driver.
  3067. * This may be redundant with iwl_down(), but there are paths to
  3068. * run iwl_down() without calling apm_ops.stop(), and there are
  3069. * paths to avoid running iwl_down() at all before leaving driver.
  3070. * This (inexpensive) call *makes sure* device is reset.
  3071. */
  3072. priv->cfg->ops->lib->apm_ops.stop(priv);
  3073. iwl_tt_exit(priv);
  3074. /* make sure we flush any pending irq or
  3075. * tasklet for the driver
  3076. */
  3077. spin_lock_irqsave(&priv->lock, flags);
  3078. iwl_disable_interrupts(priv);
  3079. spin_unlock_irqrestore(&priv->lock, flags);
  3080. iwl_synchronize_irq(priv);
  3081. iwl_dealloc_ucode_pci(priv);
  3082. if (priv->rxq.bd)
  3083. iwl_rx_queue_free(priv, &priv->rxq);
  3084. iwl_hw_txq_ctx_free(priv);
  3085. iwl_clear_stations_table(priv);
  3086. iwl_eeprom_free(priv);
  3087. /*netif_stop_queue(dev); */
  3088. flush_workqueue(priv->workqueue);
  3089. /* ieee80211_unregister_hw calls iwl_mac_stop, which flushes
  3090. * priv->workqueue... so we can't take down the workqueue
  3091. * until now... */
  3092. destroy_workqueue(priv->workqueue);
  3093. priv->workqueue = NULL;
  3094. iwl_free_traffic_mem(priv);
  3095. free_irq(priv->pci_dev->irq, priv);
  3096. pci_disable_msi(priv->pci_dev);
  3097. pci_iounmap(pdev, priv->hw_base);
  3098. pci_release_regions(pdev);
  3099. pci_disable_device(pdev);
  3100. pci_set_drvdata(pdev, NULL);
  3101. iwl_uninit_drv(priv);
  3102. iwl_free_isr_ict(priv);
  3103. if (priv->ibss_beacon)
  3104. dev_kfree_skb(priv->ibss_beacon);
  3105. ieee80211_free_hw(priv->hw);
  3106. }
  3107. /*****************************************************************************
  3108. *
  3109. * driver and module entry point
  3110. *
  3111. *****************************************************************************/
  3112. /* Hardware specific file defines the PCI IDs table for that hardware module */
  3113. static DEFINE_PCI_DEVICE_TABLE(iwl_hw_card_ids) = {
  3114. #ifdef CONFIG_IWL4965
  3115. {IWL_PCI_DEVICE(0x4229, PCI_ANY_ID, iwl4965_agn_cfg)},
  3116. {IWL_PCI_DEVICE(0x4230, PCI_ANY_ID, iwl4965_agn_cfg)},
  3117. #endif /* CONFIG_IWL4965 */
  3118. #ifdef CONFIG_IWL5000
  3119. /* 5100 Series WiFi */
  3120. {IWL_PCI_DEVICE(0x4232, 0x1201, iwl5100_agn_cfg)}, /* Mini Card */
  3121. {IWL_PCI_DEVICE(0x4232, 0x1301, iwl5100_agn_cfg)}, /* Half Mini Card */
  3122. {IWL_PCI_DEVICE(0x4232, 0x1204, iwl5100_agn_cfg)}, /* Mini Card */
  3123. {IWL_PCI_DEVICE(0x4232, 0x1304, iwl5100_agn_cfg)}, /* Half Mini Card */
  3124. {IWL_PCI_DEVICE(0x4232, 0x1205, iwl5100_bgn_cfg)}, /* Mini Card */
  3125. {IWL_PCI_DEVICE(0x4232, 0x1305, iwl5100_bgn_cfg)}, /* Half Mini Card */
  3126. {IWL_PCI_DEVICE(0x4232, 0x1206, iwl5100_abg_cfg)}, /* Mini Card */
  3127. {IWL_PCI_DEVICE(0x4232, 0x1306, iwl5100_abg_cfg)}, /* Half Mini Card */
  3128. {IWL_PCI_DEVICE(0x4232, 0x1221, iwl5100_agn_cfg)}, /* Mini Card */
  3129. {IWL_PCI_DEVICE(0x4232, 0x1321, iwl5100_agn_cfg)}, /* Half Mini Card */
  3130. {IWL_PCI_DEVICE(0x4232, 0x1224, iwl5100_agn_cfg)}, /* Mini Card */
  3131. {IWL_PCI_DEVICE(0x4232, 0x1324, iwl5100_agn_cfg)}, /* Half Mini Card */
  3132. {IWL_PCI_DEVICE(0x4232, 0x1225, iwl5100_bgn_cfg)}, /* Mini Card */
  3133. {IWL_PCI_DEVICE(0x4232, 0x1325, iwl5100_bgn_cfg)}, /* Half Mini Card */
  3134. {IWL_PCI_DEVICE(0x4232, 0x1226, iwl5100_abg_cfg)}, /* Mini Card */
  3135. {IWL_PCI_DEVICE(0x4232, 0x1326, iwl5100_abg_cfg)}, /* Half Mini Card */
  3136. {IWL_PCI_DEVICE(0x4237, 0x1211, iwl5100_agn_cfg)}, /* Mini Card */
  3137. {IWL_PCI_DEVICE(0x4237, 0x1311, iwl5100_agn_cfg)}, /* Half Mini Card */
  3138. {IWL_PCI_DEVICE(0x4237, 0x1214, iwl5100_agn_cfg)}, /* Mini Card */
  3139. {IWL_PCI_DEVICE(0x4237, 0x1314, iwl5100_agn_cfg)}, /* Half Mini Card */
  3140. {IWL_PCI_DEVICE(0x4237, 0x1215, iwl5100_bgn_cfg)}, /* Mini Card */
  3141. {IWL_PCI_DEVICE(0x4237, 0x1315, iwl5100_bgn_cfg)}, /* Half Mini Card */
  3142. {IWL_PCI_DEVICE(0x4237, 0x1216, iwl5100_abg_cfg)}, /* Mini Card */
  3143. {IWL_PCI_DEVICE(0x4237, 0x1316, iwl5100_abg_cfg)}, /* Half Mini Card */
  3144. /* 5300 Series WiFi */
  3145. {IWL_PCI_DEVICE(0x4235, 0x1021, iwl5300_agn_cfg)}, /* Mini Card */
  3146. {IWL_PCI_DEVICE(0x4235, 0x1121, iwl5300_agn_cfg)}, /* Half Mini Card */
  3147. {IWL_PCI_DEVICE(0x4235, 0x1024, iwl5300_agn_cfg)}, /* Mini Card */
  3148. {IWL_PCI_DEVICE(0x4235, 0x1124, iwl5300_agn_cfg)}, /* Half Mini Card */
  3149. {IWL_PCI_DEVICE(0x4235, 0x1001, iwl5300_agn_cfg)}, /* Mini Card */
  3150. {IWL_PCI_DEVICE(0x4235, 0x1101, iwl5300_agn_cfg)}, /* Half Mini Card */
  3151. {IWL_PCI_DEVICE(0x4235, 0x1004, iwl5300_agn_cfg)}, /* Mini Card */
  3152. {IWL_PCI_DEVICE(0x4235, 0x1104, iwl5300_agn_cfg)}, /* Half Mini Card */
  3153. {IWL_PCI_DEVICE(0x4236, 0x1011, iwl5300_agn_cfg)}, /* Mini Card */
  3154. {IWL_PCI_DEVICE(0x4236, 0x1111, iwl5300_agn_cfg)}, /* Half Mini Card */
  3155. {IWL_PCI_DEVICE(0x4236, 0x1014, iwl5300_agn_cfg)}, /* Mini Card */
  3156. {IWL_PCI_DEVICE(0x4236, 0x1114, iwl5300_agn_cfg)}, /* Half Mini Card */
  3157. /* 5350 Series WiFi/WiMax */
  3158. {IWL_PCI_DEVICE(0x423A, 0x1001, iwl5350_agn_cfg)}, /* Mini Card */
  3159. {IWL_PCI_DEVICE(0x423A, 0x1021, iwl5350_agn_cfg)}, /* Mini Card */
  3160. {IWL_PCI_DEVICE(0x423B, 0x1011, iwl5350_agn_cfg)}, /* Mini Card */
  3161. /* 5150 Series Wifi/WiMax */
  3162. {IWL_PCI_DEVICE(0x423C, 0x1201, iwl5150_agn_cfg)}, /* Mini Card */
  3163. {IWL_PCI_DEVICE(0x423C, 0x1301, iwl5150_agn_cfg)}, /* Half Mini Card */
  3164. {IWL_PCI_DEVICE(0x423C, 0x1206, iwl5150_abg_cfg)}, /* Mini Card */
  3165. {IWL_PCI_DEVICE(0x423C, 0x1306, iwl5150_abg_cfg)}, /* Half Mini Card */
  3166. {IWL_PCI_DEVICE(0x423C, 0x1221, iwl5150_agn_cfg)}, /* Mini Card */
  3167. {IWL_PCI_DEVICE(0x423C, 0x1321, iwl5150_agn_cfg)}, /* Half Mini Card */
  3168. {IWL_PCI_DEVICE(0x423D, 0x1211, iwl5150_agn_cfg)}, /* Mini Card */
  3169. {IWL_PCI_DEVICE(0x423D, 0x1311, iwl5150_agn_cfg)}, /* Half Mini Card */
  3170. {IWL_PCI_DEVICE(0x423D, 0x1216, iwl5150_abg_cfg)}, /* Mini Card */
  3171. {IWL_PCI_DEVICE(0x423D, 0x1316, iwl5150_abg_cfg)}, /* Half Mini Card */
  3172. /* 6x00 Series */
  3173. {IWL_PCI_DEVICE(0x422B, 0x1101, iwl6000_3agn_cfg)},
  3174. {IWL_PCI_DEVICE(0x422B, 0x1121, iwl6000_3agn_cfg)},
  3175. {IWL_PCI_DEVICE(0x422C, 0x1301, iwl6000i_2agn_cfg)},
  3176. {IWL_PCI_DEVICE(0x422C, 0x1306, iwl6000i_2abg_cfg)},
  3177. {IWL_PCI_DEVICE(0x422C, 0x1307, iwl6000i_2bg_cfg)},
  3178. {IWL_PCI_DEVICE(0x422C, 0x1321, iwl6000i_2agn_cfg)},
  3179. {IWL_PCI_DEVICE(0x422C, 0x1326, iwl6000i_2abg_cfg)},
  3180. {IWL_PCI_DEVICE(0x4238, 0x1111, iwl6000_3agn_cfg)},
  3181. {IWL_PCI_DEVICE(0x4239, 0x1311, iwl6000i_2agn_cfg)},
  3182. {IWL_PCI_DEVICE(0x4239, 0x1316, iwl6000i_2abg_cfg)},
  3183. /* 6x50 WiFi/WiMax Series */
  3184. {IWL_PCI_DEVICE(0x0087, 0x1301, iwl6050_2agn_cfg)},
  3185. {IWL_PCI_DEVICE(0x0087, 0x1306, iwl6050_2abg_cfg)},
  3186. {IWL_PCI_DEVICE(0x0087, 0x1321, iwl6050_2agn_cfg)},
  3187. {IWL_PCI_DEVICE(0x0087, 0x1326, iwl6050_2abg_cfg)},
  3188. {IWL_PCI_DEVICE(0x0089, 0x1311, iwl6050_2agn_cfg)},
  3189. {IWL_PCI_DEVICE(0x0089, 0x1316, iwl6050_2abg_cfg)},
  3190. /* 1000 Series WiFi */
  3191. {IWL_PCI_DEVICE(0x0083, 0x1205, iwl1000_bgn_cfg)},
  3192. {IWL_PCI_DEVICE(0x0083, 0x1305, iwl1000_bgn_cfg)},
  3193. {IWL_PCI_DEVICE(0x0083, 0x1225, iwl1000_bgn_cfg)},
  3194. {IWL_PCI_DEVICE(0x0083, 0x1325, iwl1000_bgn_cfg)},
  3195. {IWL_PCI_DEVICE(0x0084, 0x1215, iwl1000_bgn_cfg)},
  3196. {IWL_PCI_DEVICE(0x0084, 0x1315, iwl1000_bgn_cfg)},
  3197. {IWL_PCI_DEVICE(0x0083, 0x1206, iwl1000_bg_cfg)},
  3198. {IWL_PCI_DEVICE(0x0083, 0x1306, iwl1000_bg_cfg)},
  3199. {IWL_PCI_DEVICE(0x0083, 0x1226, iwl1000_bg_cfg)},
  3200. {IWL_PCI_DEVICE(0x0083, 0x1326, iwl1000_bg_cfg)},
  3201. {IWL_PCI_DEVICE(0x0084, 0x1216, iwl1000_bg_cfg)},
  3202. {IWL_PCI_DEVICE(0x0084, 0x1316, iwl1000_bg_cfg)},
  3203. #endif /* CONFIG_IWL5000 */
  3204. {0}
  3205. };
  3206. MODULE_DEVICE_TABLE(pci, iwl_hw_card_ids);
  3207. static struct pci_driver iwl_driver = {
  3208. .name = DRV_NAME,
  3209. .id_table = iwl_hw_card_ids,
  3210. .probe = iwl_pci_probe,
  3211. .remove = __devexit_p(iwl_pci_remove),
  3212. #ifdef CONFIG_PM
  3213. .suspend = iwl_pci_suspend,
  3214. .resume = iwl_pci_resume,
  3215. #endif
  3216. };
  3217. static int __init iwl_init(void)
  3218. {
  3219. int ret;
  3220. printk(KERN_INFO DRV_NAME ": " DRV_DESCRIPTION ", " DRV_VERSION "\n");
  3221. printk(KERN_INFO DRV_NAME ": " DRV_COPYRIGHT "\n");
  3222. ret = iwlagn_rate_control_register();
  3223. if (ret) {
  3224. printk(KERN_ERR DRV_NAME
  3225. "Unable to register rate control algorithm: %d\n", ret);
  3226. return ret;
  3227. }
  3228. ret = pci_register_driver(&iwl_driver);
  3229. if (ret) {
  3230. printk(KERN_ERR DRV_NAME "Unable to initialize PCI module\n");
  3231. goto error_register;
  3232. }
  3233. return ret;
  3234. error_register:
  3235. iwlagn_rate_control_unregister();
  3236. return ret;
  3237. }
  3238. static void __exit iwl_exit(void)
  3239. {
  3240. pci_unregister_driver(&iwl_driver);
  3241. iwlagn_rate_control_unregister();
  3242. }
  3243. module_exit(iwl_exit);
  3244. module_init(iwl_init);
  3245. #ifdef CONFIG_IWLWIFI_DEBUG
  3246. module_param_named(debug50, iwl_debug_level, uint, S_IRUGO);
  3247. MODULE_PARM_DESC(debug50, "50XX debug output mask (deprecated)");
  3248. module_param_named(debug, iwl_debug_level, uint, S_IRUGO | S_IWUSR);
  3249. MODULE_PARM_DESC(debug, "debug output mask");
  3250. #endif