qeth_core_main.c 128 KB

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  1. /*
  2. * drivers/s390/net/qeth_core_main.c
  3. *
  4. * Copyright IBM Corp. 2007, 2009
  5. * Author(s): Utz Bacher <utz.bacher@de.ibm.com>,
  6. * Frank Pavlic <fpavlic@de.ibm.com>,
  7. * Thomas Spatzier <tspat@de.ibm.com>,
  8. * Frank Blaschka <frank.blaschka@de.ibm.com>
  9. */
  10. #define KMSG_COMPONENT "qeth"
  11. #define pr_fmt(fmt) KMSG_COMPONENT ": " fmt
  12. #include <linux/module.h>
  13. #include <linux/moduleparam.h>
  14. #include <linux/string.h>
  15. #include <linux/errno.h>
  16. #include <linux/kernel.h>
  17. #include <linux/ip.h>
  18. #include <linux/tcp.h>
  19. #include <linux/mii.h>
  20. #include <linux/kthread.h>
  21. #include <asm/ebcdic.h>
  22. #include <asm/io.h>
  23. #include "qeth_core.h"
  24. struct qeth_dbf_info qeth_dbf[QETH_DBF_INFOS] = {
  25. /* define dbf - Name, Pages, Areas, Maxlen, Level, View, Handle */
  26. /* N P A M L V H */
  27. [QETH_DBF_SETUP] = {"qeth_setup",
  28. 8, 1, 8, 5, &debug_hex_ascii_view, NULL},
  29. [QETH_DBF_QERR] = {"qeth_qerr",
  30. 2, 1, 8, 2, &debug_hex_ascii_view, NULL},
  31. [QETH_DBF_TRACE] = {"qeth_trace",
  32. 4, 1, 8, 3, &debug_hex_ascii_view, NULL},
  33. [QETH_DBF_MSG] = {"qeth_msg",
  34. 8, 1, 128, 3, &debug_sprintf_view, NULL},
  35. [QETH_DBF_SENSE] = {"qeth_sense",
  36. 2, 1, 64, 2, &debug_hex_ascii_view, NULL},
  37. [QETH_DBF_MISC] = {"qeth_misc",
  38. 2, 1, 256, 2, &debug_hex_ascii_view, NULL},
  39. [QETH_DBF_CTRL] = {"qeth_control",
  40. 8, 1, QETH_DBF_CTRL_LEN, 5, &debug_hex_ascii_view, NULL},
  41. };
  42. EXPORT_SYMBOL_GPL(qeth_dbf);
  43. struct qeth_card_list_struct qeth_core_card_list;
  44. EXPORT_SYMBOL_GPL(qeth_core_card_list);
  45. struct kmem_cache *qeth_core_header_cache;
  46. EXPORT_SYMBOL_GPL(qeth_core_header_cache);
  47. static struct device *qeth_core_root_dev;
  48. static unsigned int known_devices[][10] = QETH_MODELLIST_ARRAY;
  49. static struct lock_class_key qdio_out_skb_queue_key;
  50. static void qeth_send_control_data_cb(struct qeth_channel *,
  51. struct qeth_cmd_buffer *);
  52. static int qeth_issue_next_read(struct qeth_card *);
  53. static struct qeth_cmd_buffer *qeth_get_buffer(struct qeth_channel *);
  54. static void qeth_setup_ccw(struct qeth_channel *, unsigned char *, __u32);
  55. static void qeth_free_buffer_pool(struct qeth_card *);
  56. static int qeth_qdio_establish(struct qeth_card *);
  57. static inline void __qeth_fill_buffer_frag(struct sk_buff *skb,
  58. struct qdio_buffer *buffer, int is_tso,
  59. int *next_element_to_fill)
  60. {
  61. struct skb_frag_struct *frag;
  62. int fragno;
  63. unsigned long addr;
  64. int element, cnt, dlen;
  65. fragno = skb_shinfo(skb)->nr_frags;
  66. element = *next_element_to_fill;
  67. dlen = 0;
  68. if (is_tso)
  69. buffer->element[element].flags =
  70. SBAL_FLAGS_MIDDLE_FRAG;
  71. else
  72. buffer->element[element].flags =
  73. SBAL_FLAGS_FIRST_FRAG;
  74. dlen = skb->len - skb->data_len;
  75. if (dlen) {
  76. buffer->element[element].addr = skb->data;
  77. buffer->element[element].length = dlen;
  78. element++;
  79. }
  80. for (cnt = 0; cnt < fragno; cnt++) {
  81. frag = &skb_shinfo(skb)->frags[cnt];
  82. addr = (page_to_pfn(frag->page) << PAGE_SHIFT) +
  83. frag->page_offset;
  84. buffer->element[element].addr = (char *)addr;
  85. buffer->element[element].length = frag->size;
  86. if (cnt < (fragno - 1))
  87. buffer->element[element].flags =
  88. SBAL_FLAGS_MIDDLE_FRAG;
  89. else
  90. buffer->element[element].flags =
  91. SBAL_FLAGS_LAST_FRAG;
  92. element++;
  93. }
  94. *next_element_to_fill = element;
  95. }
  96. static inline const char *qeth_get_cardname(struct qeth_card *card)
  97. {
  98. if (card->info.guestlan) {
  99. switch (card->info.type) {
  100. case QETH_CARD_TYPE_OSAE:
  101. return " Guest LAN QDIO";
  102. case QETH_CARD_TYPE_IQD:
  103. return " Guest LAN Hiper";
  104. default:
  105. return " unknown";
  106. }
  107. } else {
  108. switch (card->info.type) {
  109. case QETH_CARD_TYPE_OSAE:
  110. return " OSD Express";
  111. case QETH_CARD_TYPE_IQD:
  112. return " HiperSockets";
  113. case QETH_CARD_TYPE_OSN:
  114. return " OSN QDIO";
  115. default:
  116. return " unknown";
  117. }
  118. }
  119. return " n/a";
  120. }
  121. /* max length to be returned: 14 */
  122. const char *qeth_get_cardname_short(struct qeth_card *card)
  123. {
  124. if (card->info.guestlan) {
  125. switch (card->info.type) {
  126. case QETH_CARD_TYPE_OSAE:
  127. return "GuestLAN QDIO";
  128. case QETH_CARD_TYPE_IQD:
  129. return "GuestLAN Hiper";
  130. default:
  131. return "unknown";
  132. }
  133. } else {
  134. switch (card->info.type) {
  135. case QETH_CARD_TYPE_OSAE:
  136. switch (card->info.link_type) {
  137. case QETH_LINK_TYPE_FAST_ETH:
  138. return "OSD_100";
  139. case QETH_LINK_TYPE_HSTR:
  140. return "HSTR";
  141. case QETH_LINK_TYPE_GBIT_ETH:
  142. return "OSD_1000";
  143. case QETH_LINK_TYPE_10GBIT_ETH:
  144. return "OSD_10GIG";
  145. case QETH_LINK_TYPE_LANE_ETH100:
  146. return "OSD_FE_LANE";
  147. case QETH_LINK_TYPE_LANE_TR:
  148. return "OSD_TR_LANE";
  149. case QETH_LINK_TYPE_LANE_ETH1000:
  150. return "OSD_GbE_LANE";
  151. case QETH_LINK_TYPE_LANE:
  152. return "OSD_ATM_LANE";
  153. default:
  154. return "OSD_Express";
  155. }
  156. case QETH_CARD_TYPE_IQD:
  157. return "HiperSockets";
  158. case QETH_CARD_TYPE_OSN:
  159. return "OSN";
  160. default:
  161. return "unknown";
  162. }
  163. }
  164. return "n/a";
  165. }
  166. void qeth_set_allowed_threads(struct qeth_card *card, unsigned long threads,
  167. int clear_start_mask)
  168. {
  169. unsigned long flags;
  170. spin_lock_irqsave(&card->thread_mask_lock, flags);
  171. card->thread_allowed_mask = threads;
  172. if (clear_start_mask)
  173. card->thread_start_mask &= threads;
  174. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  175. wake_up(&card->wait_q);
  176. }
  177. EXPORT_SYMBOL_GPL(qeth_set_allowed_threads);
  178. int qeth_threads_running(struct qeth_card *card, unsigned long threads)
  179. {
  180. unsigned long flags;
  181. int rc = 0;
  182. spin_lock_irqsave(&card->thread_mask_lock, flags);
  183. rc = (card->thread_running_mask & threads);
  184. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  185. return rc;
  186. }
  187. EXPORT_SYMBOL_GPL(qeth_threads_running);
  188. int qeth_wait_for_threads(struct qeth_card *card, unsigned long threads)
  189. {
  190. return wait_event_interruptible(card->wait_q,
  191. qeth_threads_running(card, threads) == 0);
  192. }
  193. EXPORT_SYMBOL_GPL(qeth_wait_for_threads);
  194. void qeth_clear_working_pool_list(struct qeth_card *card)
  195. {
  196. struct qeth_buffer_pool_entry *pool_entry, *tmp;
  197. QETH_DBF_TEXT(TRACE, 5, "clwrklst");
  198. list_for_each_entry_safe(pool_entry, tmp,
  199. &card->qdio.in_buf_pool.entry_list, list){
  200. list_del(&pool_entry->list);
  201. }
  202. }
  203. EXPORT_SYMBOL_GPL(qeth_clear_working_pool_list);
  204. static int qeth_alloc_buffer_pool(struct qeth_card *card)
  205. {
  206. struct qeth_buffer_pool_entry *pool_entry;
  207. void *ptr;
  208. int i, j;
  209. QETH_DBF_TEXT(TRACE, 5, "alocpool");
  210. for (i = 0; i < card->qdio.init_pool.buf_count; ++i) {
  211. pool_entry = kmalloc(sizeof(*pool_entry), GFP_KERNEL);
  212. if (!pool_entry) {
  213. qeth_free_buffer_pool(card);
  214. return -ENOMEM;
  215. }
  216. for (j = 0; j < QETH_MAX_BUFFER_ELEMENTS(card); ++j) {
  217. ptr = (void *) __get_free_page(GFP_KERNEL);
  218. if (!ptr) {
  219. while (j > 0)
  220. free_page((unsigned long)
  221. pool_entry->elements[--j]);
  222. kfree(pool_entry);
  223. qeth_free_buffer_pool(card);
  224. return -ENOMEM;
  225. }
  226. pool_entry->elements[j] = ptr;
  227. }
  228. list_add(&pool_entry->init_list,
  229. &card->qdio.init_pool.entry_list);
  230. }
  231. return 0;
  232. }
  233. int qeth_realloc_buffer_pool(struct qeth_card *card, int bufcnt)
  234. {
  235. QETH_DBF_TEXT(TRACE, 2, "realcbp");
  236. if ((card->state != CARD_STATE_DOWN) &&
  237. (card->state != CARD_STATE_RECOVER))
  238. return -EPERM;
  239. /* TODO: steel/add buffers from/to a running card's buffer pool (?) */
  240. qeth_clear_working_pool_list(card);
  241. qeth_free_buffer_pool(card);
  242. card->qdio.in_buf_pool.buf_count = bufcnt;
  243. card->qdio.init_pool.buf_count = bufcnt;
  244. return qeth_alloc_buffer_pool(card);
  245. }
  246. EXPORT_SYMBOL_GPL(qeth_realloc_buffer_pool);
  247. static int qeth_issue_next_read(struct qeth_card *card)
  248. {
  249. int rc;
  250. struct qeth_cmd_buffer *iob;
  251. QETH_DBF_TEXT(TRACE, 5, "issnxrd");
  252. if (card->read.state != CH_STATE_UP)
  253. return -EIO;
  254. iob = qeth_get_buffer(&card->read);
  255. if (!iob) {
  256. dev_warn(&card->gdev->dev, "The qeth device driver "
  257. "failed to recover an error on the device\n");
  258. QETH_DBF_MESSAGE(2, "%s issue_next_read failed: no iob "
  259. "available\n", dev_name(&card->gdev->dev));
  260. return -ENOMEM;
  261. }
  262. qeth_setup_ccw(&card->read, iob->data, QETH_BUFSIZE);
  263. QETH_DBF_TEXT(TRACE, 6, "noirqpnd");
  264. rc = ccw_device_start(card->read.ccwdev, &card->read.ccw,
  265. (addr_t) iob, 0, 0);
  266. if (rc) {
  267. QETH_DBF_MESSAGE(2, "%s error in starting next read ccw! "
  268. "rc=%i\n", dev_name(&card->gdev->dev), rc);
  269. atomic_set(&card->read.irq_pending, 0);
  270. qeth_schedule_recovery(card);
  271. wake_up(&card->wait_q);
  272. }
  273. return rc;
  274. }
  275. static struct qeth_reply *qeth_alloc_reply(struct qeth_card *card)
  276. {
  277. struct qeth_reply *reply;
  278. reply = kzalloc(sizeof(struct qeth_reply), GFP_ATOMIC);
  279. if (reply) {
  280. atomic_set(&reply->refcnt, 1);
  281. atomic_set(&reply->received, 0);
  282. reply->card = card;
  283. };
  284. return reply;
  285. }
  286. static void qeth_get_reply(struct qeth_reply *reply)
  287. {
  288. WARN_ON(atomic_read(&reply->refcnt) <= 0);
  289. atomic_inc(&reply->refcnt);
  290. }
  291. static void qeth_put_reply(struct qeth_reply *reply)
  292. {
  293. WARN_ON(atomic_read(&reply->refcnt) <= 0);
  294. if (atomic_dec_and_test(&reply->refcnt))
  295. kfree(reply);
  296. }
  297. static void qeth_issue_ipa_msg(struct qeth_ipa_cmd *cmd, int rc,
  298. struct qeth_card *card)
  299. {
  300. char *ipa_name;
  301. int com = cmd->hdr.command;
  302. ipa_name = qeth_get_ipa_cmd_name(com);
  303. if (rc)
  304. QETH_DBF_MESSAGE(2, "IPA: %s(x%X) for %s returned x%X \"%s\"\n",
  305. ipa_name, com, QETH_CARD_IFNAME(card),
  306. rc, qeth_get_ipa_msg(rc));
  307. else
  308. QETH_DBF_MESSAGE(5, "IPA: %s(x%X) for %s succeeded\n",
  309. ipa_name, com, QETH_CARD_IFNAME(card));
  310. }
  311. static struct qeth_ipa_cmd *qeth_check_ipa_data(struct qeth_card *card,
  312. struct qeth_cmd_buffer *iob)
  313. {
  314. struct qeth_ipa_cmd *cmd = NULL;
  315. QETH_DBF_TEXT(TRACE, 5, "chkipad");
  316. if (IS_IPA(iob->data)) {
  317. cmd = (struct qeth_ipa_cmd *) PDU_ENCAPSULATION(iob->data);
  318. if (IS_IPA_REPLY(cmd)) {
  319. if (cmd->hdr.command != IPA_CMD_SETCCID &&
  320. cmd->hdr.command != IPA_CMD_DELCCID &&
  321. cmd->hdr.command != IPA_CMD_MODCCID &&
  322. cmd->hdr.command != IPA_CMD_SET_DIAG_ASS)
  323. qeth_issue_ipa_msg(cmd,
  324. cmd->hdr.return_code, card);
  325. return cmd;
  326. } else {
  327. switch (cmd->hdr.command) {
  328. case IPA_CMD_STOPLAN:
  329. dev_warn(&card->gdev->dev,
  330. "The link for interface %s on CHPID"
  331. " 0x%X failed\n",
  332. QETH_CARD_IFNAME(card),
  333. card->info.chpid);
  334. card->lan_online = 0;
  335. if (card->dev && netif_carrier_ok(card->dev))
  336. netif_carrier_off(card->dev);
  337. return NULL;
  338. case IPA_CMD_STARTLAN:
  339. dev_info(&card->gdev->dev,
  340. "The link for %s on CHPID 0x%X has"
  341. " been restored\n",
  342. QETH_CARD_IFNAME(card),
  343. card->info.chpid);
  344. netif_carrier_on(card->dev);
  345. card->lan_online = 1;
  346. qeth_schedule_recovery(card);
  347. return NULL;
  348. case IPA_CMD_MODCCID:
  349. return cmd;
  350. case IPA_CMD_REGISTER_LOCAL_ADDR:
  351. QETH_DBF_TEXT(TRACE, 3, "irla");
  352. break;
  353. case IPA_CMD_UNREGISTER_LOCAL_ADDR:
  354. QETH_DBF_TEXT(TRACE, 3, "urla");
  355. break;
  356. default:
  357. QETH_DBF_MESSAGE(2, "Received data is IPA "
  358. "but not a reply!\n");
  359. break;
  360. }
  361. }
  362. }
  363. return cmd;
  364. }
  365. void qeth_clear_ipacmd_list(struct qeth_card *card)
  366. {
  367. struct qeth_reply *reply, *r;
  368. unsigned long flags;
  369. QETH_DBF_TEXT(TRACE, 4, "clipalst");
  370. spin_lock_irqsave(&card->lock, flags);
  371. list_for_each_entry_safe(reply, r, &card->cmd_waiter_list, list) {
  372. qeth_get_reply(reply);
  373. reply->rc = -EIO;
  374. atomic_inc(&reply->received);
  375. list_del_init(&reply->list);
  376. wake_up(&reply->wait_q);
  377. qeth_put_reply(reply);
  378. }
  379. spin_unlock_irqrestore(&card->lock, flags);
  380. }
  381. EXPORT_SYMBOL_GPL(qeth_clear_ipacmd_list);
  382. static int qeth_check_idx_response(unsigned char *buffer)
  383. {
  384. if (!buffer)
  385. return 0;
  386. QETH_DBF_HEX(CTRL, 2, buffer, QETH_DBF_CTRL_LEN);
  387. if ((buffer[2] & 0xc0) == 0xc0) {
  388. QETH_DBF_MESSAGE(2, "received an IDX TERMINATE "
  389. "with cause code 0x%02x%s\n",
  390. buffer[4],
  391. ((buffer[4] == 0x22) ?
  392. " -- try another portname" : ""));
  393. QETH_DBF_TEXT(TRACE, 2, "ckidxres");
  394. QETH_DBF_TEXT(TRACE, 2, " idxterm");
  395. QETH_DBF_TEXT_(TRACE, 2, " rc%d", -EIO);
  396. return -EIO;
  397. }
  398. return 0;
  399. }
  400. static void qeth_setup_ccw(struct qeth_channel *channel, unsigned char *iob,
  401. __u32 len)
  402. {
  403. struct qeth_card *card;
  404. QETH_DBF_TEXT(TRACE, 4, "setupccw");
  405. card = CARD_FROM_CDEV(channel->ccwdev);
  406. if (channel == &card->read)
  407. memcpy(&channel->ccw, READ_CCW, sizeof(struct ccw1));
  408. else
  409. memcpy(&channel->ccw, WRITE_CCW, sizeof(struct ccw1));
  410. channel->ccw.count = len;
  411. channel->ccw.cda = (__u32) __pa(iob);
  412. }
  413. static struct qeth_cmd_buffer *__qeth_get_buffer(struct qeth_channel *channel)
  414. {
  415. __u8 index;
  416. QETH_DBF_TEXT(TRACE, 6, "getbuff");
  417. index = channel->io_buf_no;
  418. do {
  419. if (channel->iob[index].state == BUF_STATE_FREE) {
  420. channel->iob[index].state = BUF_STATE_LOCKED;
  421. channel->io_buf_no = (channel->io_buf_no + 1) %
  422. QETH_CMD_BUFFER_NO;
  423. memset(channel->iob[index].data, 0, QETH_BUFSIZE);
  424. return channel->iob + index;
  425. }
  426. index = (index + 1) % QETH_CMD_BUFFER_NO;
  427. } while (index != channel->io_buf_no);
  428. return NULL;
  429. }
  430. void qeth_release_buffer(struct qeth_channel *channel,
  431. struct qeth_cmd_buffer *iob)
  432. {
  433. unsigned long flags;
  434. QETH_DBF_TEXT(TRACE, 6, "relbuff");
  435. spin_lock_irqsave(&channel->iob_lock, flags);
  436. memset(iob->data, 0, QETH_BUFSIZE);
  437. iob->state = BUF_STATE_FREE;
  438. iob->callback = qeth_send_control_data_cb;
  439. iob->rc = 0;
  440. spin_unlock_irqrestore(&channel->iob_lock, flags);
  441. }
  442. EXPORT_SYMBOL_GPL(qeth_release_buffer);
  443. static struct qeth_cmd_buffer *qeth_get_buffer(struct qeth_channel *channel)
  444. {
  445. struct qeth_cmd_buffer *buffer = NULL;
  446. unsigned long flags;
  447. spin_lock_irqsave(&channel->iob_lock, flags);
  448. buffer = __qeth_get_buffer(channel);
  449. spin_unlock_irqrestore(&channel->iob_lock, flags);
  450. return buffer;
  451. }
  452. struct qeth_cmd_buffer *qeth_wait_for_buffer(struct qeth_channel *channel)
  453. {
  454. struct qeth_cmd_buffer *buffer;
  455. wait_event(channel->wait_q,
  456. ((buffer = qeth_get_buffer(channel)) != NULL));
  457. return buffer;
  458. }
  459. EXPORT_SYMBOL_GPL(qeth_wait_for_buffer);
  460. void qeth_clear_cmd_buffers(struct qeth_channel *channel)
  461. {
  462. int cnt;
  463. for (cnt = 0; cnt < QETH_CMD_BUFFER_NO; cnt++)
  464. qeth_release_buffer(channel, &channel->iob[cnt]);
  465. channel->buf_no = 0;
  466. channel->io_buf_no = 0;
  467. }
  468. EXPORT_SYMBOL_GPL(qeth_clear_cmd_buffers);
  469. static void qeth_send_control_data_cb(struct qeth_channel *channel,
  470. struct qeth_cmd_buffer *iob)
  471. {
  472. struct qeth_card *card;
  473. struct qeth_reply *reply, *r;
  474. struct qeth_ipa_cmd *cmd;
  475. unsigned long flags;
  476. int keep_reply;
  477. QETH_DBF_TEXT(TRACE, 4, "sndctlcb");
  478. card = CARD_FROM_CDEV(channel->ccwdev);
  479. if (qeth_check_idx_response(iob->data)) {
  480. qeth_clear_ipacmd_list(card);
  481. if (((iob->data[2] & 0xc0) == 0xc0) && iob->data[4] == 0xf6)
  482. dev_err(&card->gdev->dev,
  483. "The qeth device is not configured "
  484. "for the OSI layer required by z/VM\n");
  485. qeth_schedule_recovery(card);
  486. goto out;
  487. }
  488. cmd = qeth_check_ipa_data(card, iob);
  489. if ((cmd == NULL) && (card->state != CARD_STATE_DOWN))
  490. goto out;
  491. /*in case of OSN : check if cmd is set */
  492. if (card->info.type == QETH_CARD_TYPE_OSN &&
  493. cmd &&
  494. cmd->hdr.command != IPA_CMD_STARTLAN &&
  495. card->osn_info.assist_cb != NULL) {
  496. card->osn_info.assist_cb(card->dev, cmd);
  497. goto out;
  498. }
  499. spin_lock_irqsave(&card->lock, flags);
  500. list_for_each_entry_safe(reply, r, &card->cmd_waiter_list, list) {
  501. if ((reply->seqno == QETH_IDX_COMMAND_SEQNO) ||
  502. ((cmd) && (reply->seqno == cmd->hdr.seqno))) {
  503. qeth_get_reply(reply);
  504. list_del_init(&reply->list);
  505. spin_unlock_irqrestore(&card->lock, flags);
  506. keep_reply = 0;
  507. if (reply->callback != NULL) {
  508. if (cmd) {
  509. reply->offset = (__u16)((char *)cmd -
  510. (char *)iob->data);
  511. keep_reply = reply->callback(card,
  512. reply,
  513. (unsigned long)cmd);
  514. } else
  515. keep_reply = reply->callback(card,
  516. reply,
  517. (unsigned long)iob);
  518. }
  519. if (cmd)
  520. reply->rc = (u16) cmd->hdr.return_code;
  521. else if (iob->rc)
  522. reply->rc = iob->rc;
  523. if (keep_reply) {
  524. spin_lock_irqsave(&card->lock, flags);
  525. list_add_tail(&reply->list,
  526. &card->cmd_waiter_list);
  527. spin_unlock_irqrestore(&card->lock, flags);
  528. } else {
  529. atomic_inc(&reply->received);
  530. wake_up(&reply->wait_q);
  531. }
  532. qeth_put_reply(reply);
  533. goto out;
  534. }
  535. }
  536. spin_unlock_irqrestore(&card->lock, flags);
  537. out:
  538. memcpy(&card->seqno.pdu_hdr_ack,
  539. QETH_PDU_HEADER_SEQ_NO(iob->data),
  540. QETH_SEQ_NO_LENGTH);
  541. qeth_release_buffer(channel, iob);
  542. }
  543. static int qeth_setup_channel(struct qeth_channel *channel)
  544. {
  545. int cnt;
  546. QETH_DBF_TEXT(SETUP, 2, "setupch");
  547. for (cnt = 0; cnt < QETH_CMD_BUFFER_NO; cnt++) {
  548. channel->iob[cnt].data = (char *)
  549. kmalloc(QETH_BUFSIZE, GFP_DMA|GFP_KERNEL);
  550. if (channel->iob[cnt].data == NULL)
  551. break;
  552. channel->iob[cnt].state = BUF_STATE_FREE;
  553. channel->iob[cnt].channel = channel;
  554. channel->iob[cnt].callback = qeth_send_control_data_cb;
  555. channel->iob[cnt].rc = 0;
  556. }
  557. if (cnt < QETH_CMD_BUFFER_NO) {
  558. while (cnt-- > 0)
  559. kfree(channel->iob[cnt].data);
  560. return -ENOMEM;
  561. }
  562. channel->buf_no = 0;
  563. channel->io_buf_no = 0;
  564. atomic_set(&channel->irq_pending, 0);
  565. spin_lock_init(&channel->iob_lock);
  566. init_waitqueue_head(&channel->wait_q);
  567. return 0;
  568. }
  569. static int qeth_set_thread_start_bit(struct qeth_card *card,
  570. unsigned long thread)
  571. {
  572. unsigned long flags;
  573. spin_lock_irqsave(&card->thread_mask_lock, flags);
  574. if (!(card->thread_allowed_mask & thread) ||
  575. (card->thread_start_mask & thread)) {
  576. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  577. return -EPERM;
  578. }
  579. card->thread_start_mask |= thread;
  580. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  581. return 0;
  582. }
  583. void qeth_clear_thread_start_bit(struct qeth_card *card, unsigned long thread)
  584. {
  585. unsigned long flags;
  586. spin_lock_irqsave(&card->thread_mask_lock, flags);
  587. card->thread_start_mask &= ~thread;
  588. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  589. wake_up(&card->wait_q);
  590. }
  591. EXPORT_SYMBOL_GPL(qeth_clear_thread_start_bit);
  592. void qeth_clear_thread_running_bit(struct qeth_card *card, unsigned long thread)
  593. {
  594. unsigned long flags;
  595. spin_lock_irqsave(&card->thread_mask_lock, flags);
  596. card->thread_running_mask &= ~thread;
  597. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  598. wake_up(&card->wait_q);
  599. }
  600. EXPORT_SYMBOL_GPL(qeth_clear_thread_running_bit);
  601. static int __qeth_do_run_thread(struct qeth_card *card, unsigned long thread)
  602. {
  603. unsigned long flags;
  604. int rc = 0;
  605. spin_lock_irqsave(&card->thread_mask_lock, flags);
  606. if (card->thread_start_mask & thread) {
  607. if ((card->thread_allowed_mask & thread) &&
  608. !(card->thread_running_mask & thread)) {
  609. rc = 1;
  610. card->thread_start_mask &= ~thread;
  611. card->thread_running_mask |= thread;
  612. } else
  613. rc = -EPERM;
  614. }
  615. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  616. return rc;
  617. }
  618. int qeth_do_run_thread(struct qeth_card *card, unsigned long thread)
  619. {
  620. int rc = 0;
  621. wait_event(card->wait_q,
  622. (rc = __qeth_do_run_thread(card, thread)) >= 0);
  623. return rc;
  624. }
  625. EXPORT_SYMBOL_GPL(qeth_do_run_thread);
  626. void qeth_schedule_recovery(struct qeth_card *card)
  627. {
  628. QETH_DBF_TEXT(TRACE, 2, "startrec");
  629. if (qeth_set_thread_start_bit(card, QETH_RECOVER_THREAD) == 0)
  630. schedule_work(&card->kernel_thread_starter);
  631. }
  632. EXPORT_SYMBOL_GPL(qeth_schedule_recovery);
  633. static int qeth_get_problem(struct ccw_device *cdev, struct irb *irb)
  634. {
  635. int dstat, cstat;
  636. char *sense;
  637. sense = (char *) irb->ecw;
  638. cstat = irb->scsw.cmd.cstat;
  639. dstat = irb->scsw.cmd.dstat;
  640. if (cstat & (SCHN_STAT_CHN_CTRL_CHK | SCHN_STAT_INTF_CTRL_CHK |
  641. SCHN_STAT_CHN_DATA_CHK | SCHN_STAT_CHAIN_CHECK |
  642. SCHN_STAT_PROT_CHECK | SCHN_STAT_PROG_CHECK)) {
  643. QETH_DBF_TEXT(TRACE, 2, "CGENCHK");
  644. dev_warn(&cdev->dev, "The qeth device driver "
  645. "failed to recover an error on the device\n");
  646. QETH_DBF_MESSAGE(2, "%s check on device dstat=x%x, cstat=x%x ",
  647. dev_name(&cdev->dev), dstat, cstat);
  648. print_hex_dump(KERN_WARNING, "qeth: irb ", DUMP_PREFIX_OFFSET,
  649. 16, 1, irb, 64, 1);
  650. return 1;
  651. }
  652. if (dstat & DEV_STAT_UNIT_CHECK) {
  653. if (sense[SENSE_RESETTING_EVENT_BYTE] &
  654. SENSE_RESETTING_EVENT_FLAG) {
  655. QETH_DBF_TEXT(TRACE, 2, "REVIND");
  656. return 1;
  657. }
  658. if (sense[SENSE_COMMAND_REJECT_BYTE] &
  659. SENSE_COMMAND_REJECT_FLAG) {
  660. QETH_DBF_TEXT(TRACE, 2, "CMDREJi");
  661. return 1;
  662. }
  663. if ((sense[2] == 0xaf) && (sense[3] == 0xfe)) {
  664. QETH_DBF_TEXT(TRACE, 2, "AFFE");
  665. return 1;
  666. }
  667. if ((!sense[0]) && (!sense[1]) && (!sense[2]) && (!sense[3])) {
  668. QETH_DBF_TEXT(TRACE, 2, "ZEROSEN");
  669. return 0;
  670. }
  671. QETH_DBF_TEXT(TRACE, 2, "DGENCHK");
  672. return 1;
  673. }
  674. return 0;
  675. }
  676. static long __qeth_check_irb_error(struct ccw_device *cdev,
  677. unsigned long intparm, struct irb *irb)
  678. {
  679. if (!IS_ERR(irb))
  680. return 0;
  681. switch (PTR_ERR(irb)) {
  682. case -EIO:
  683. QETH_DBF_MESSAGE(2, "%s i/o-error on device\n",
  684. dev_name(&cdev->dev));
  685. QETH_DBF_TEXT(TRACE, 2, "ckirberr");
  686. QETH_DBF_TEXT_(TRACE, 2, " rc%d", -EIO);
  687. break;
  688. case -ETIMEDOUT:
  689. dev_warn(&cdev->dev, "A hardware operation timed out"
  690. " on the device\n");
  691. QETH_DBF_TEXT(TRACE, 2, "ckirberr");
  692. QETH_DBF_TEXT_(TRACE, 2, " rc%d", -ETIMEDOUT);
  693. if (intparm == QETH_RCD_PARM) {
  694. struct qeth_card *card = CARD_FROM_CDEV(cdev);
  695. if (card && (card->data.ccwdev == cdev)) {
  696. card->data.state = CH_STATE_DOWN;
  697. wake_up(&card->wait_q);
  698. }
  699. }
  700. break;
  701. default:
  702. QETH_DBF_MESSAGE(2, "%s unknown error %ld on device\n",
  703. dev_name(&cdev->dev), PTR_ERR(irb));
  704. QETH_DBF_TEXT(TRACE, 2, "ckirberr");
  705. QETH_DBF_TEXT(TRACE, 2, " rc???");
  706. }
  707. return PTR_ERR(irb);
  708. }
  709. static void qeth_irq(struct ccw_device *cdev, unsigned long intparm,
  710. struct irb *irb)
  711. {
  712. int rc;
  713. int cstat, dstat;
  714. struct qeth_cmd_buffer *buffer;
  715. struct qeth_channel *channel;
  716. struct qeth_card *card;
  717. struct qeth_cmd_buffer *iob;
  718. __u8 index;
  719. QETH_DBF_TEXT(TRACE, 5, "irq");
  720. if (__qeth_check_irb_error(cdev, intparm, irb))
  721. return;
  722. cstat = irb->scsw.cmd.cstat;
  723. dstat = irb->scsw.cmd.dstat;
  724. card = CARD_FROM_CDEV(cdev);
  725. if (!card)
  726. return;
  727. if (card->read.ccwdev == cdev) {
  728. channel = &card->read;
  729. QETH_DBF_TEXT(TRACE, 5, "read");
  730. } else if (card->write.ccwdev == cdev) {
  731. channel = &card->write;
  732. QETH_DBF_TEXT(TRACE, 5, "write");
  733. } else {
  734. channel = &card->data;
  735. QETH_DBF_TEXT(TRACE, 5, "data");
  736. }
  737. atomic_set(&channel->irq_pending, 0);
  738. if (irb->scsw.cmd.fctl & (SCSW_FCTL_CLEAR_FUNC))
  739. channel->state = CH_STATE_STOPPED;
  740. if (irb->scsw.cmd.fctl & (SCSW_FCTL_HALT_FUNC))
  741. channel->state = CH_STATE_HALTED;
  742. /*let's wake up immediately on data channel*/
  743. if ((channel == &card->data) && (intparm != 0) &&
  744. (intparm != QETH_RCD_PARM))
  745. goto out;
  746. if (intparm == QETH_CLEAR_CHANNEL_PARM) {
  747. QETH_DBF_TEXT(TRACE, 6, "clrchpar");
  748. /* we don't have to handle this further */
  749. intparm = 0;
  750. }
  751. if (intparm == QETH_HALT_CHANNEL_PARM) {
  752. QETH_DBF_TEXT(TRACE, 6, "hltchpar");
  753. /* we don't have to handle this further */
  754. intparm = 0;
  755. }
  756. if ((dstat & DEV_STAT_UNIT_EXCEP) ||
  757. (dstat & DEV_STAT_UNIT_CHECK) ||
  758. (cstat)) {
  759. if (irb->esw.esw0.erw.cons) {
  760. dev_warn(&channel->ccwdev->dev,
  761. "The qeth device driver failed to recover "
  762. "an error on the device\n");
  763. QETH_DBF_MESSAGE(2, "%s sense data available. cstat "
  764. "0x%X dstat 0x%X\n",
  765. dev_name(&channel->ccwdev->dev), cstat, dstat);
  766. print_hex_dump(KERN_WARNING, "qeth: irb ",
  767. DUMP_PREFIX_OFFSET, 16, 1, irb, 32, 1);
  768. print_hex_dump(KERN_WARNING, "qeth: sense data ",
  769. DUMP_PREFIX_OFFSET, 16, 1, irb->ecw, 32, 1);
  770. }
  771. if (intparm == QETH_RCD_PARM) {
  772. channel->state = CH_STATE_DOWN;
  773. goto out;
  774. }
  775. rc = qeth_get_problem(cdev, irb);
  776. if (rc) {
  777. qeth_clear_ipacmd_list(card);
  778. qeth_schedule_recovery(card);
  779. goto out;
  780. }
  781. }
  782. if (intparm == QETH_RCD_PARM) {
  783. channel->state = CH_STATE_RCD_DONE;
  784. goto out;
  785. }
  786. if (intparm) {
  787. buffer = (struct qeth_cmd_buffer *) __va((addr_t)intparm);
  788. buffer->state = BUF_STATE_PROCESSED;
  789. }
  790. if (channel == &card->data)
  791. return;
  792. if (channel == &card->read &&
  793. channel->state == CH_STATE_UP)
  794. qeth_issue_next_read(card);
  795. iob = channel->iob;
  796. index = channel->buf_no;
  797. while (iob[index].state == BUF_STATE_PROCESSED) {
  798. if (iob[index].callback != NULL)
  799. iob[index].callback(channel, iob + index);
  800. index = (index + 1) % QETH_CMD_BUFFER_NO;
  801. }
  802. channel->buf_no = index;
  803. out:
  804. wake_up(&card->wait_q);
  805. return;
  806. }
  807. static void __qeth_clear_output_buffer(struct qeth_qdio_out_q *queue,
  808. struct qeth_qdio_out_buffer *buf, unsigned int qeth_skip_skb)
  809. {
  810. int i;
  811. struct sk_buff *skb;
  812. /* is PCI flag set on buffer? */
  813. if (buf->buffer->element[0].flags & 0x40)
  814. atomic_dec(&queue->set_pci_flags_count);
  815. if (!qeth_skip_skb) {
  816. skb = skb_dequeue(&buf->skb_list);
  817. while (skb) {
  818. atomic_dec(&skb->users);
  819. dev_kfree_skb_any(skb);
  820. skb = skb_dequeue(&buf->skb_list);
  821. }
  822. }
  823. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(queue->card); ++i) {
  824. if (buf->buffer->element[i].addr && buf->is_header[i])
  825. kmem_cache_free(qeth_core_header_cache,
  826. buf->buffer->element[i].addr);
  827. buf->is_header[i] = 0;
  828. buf->buffer->element[i].length = 0;
  829. buf->buffer->element[i].addr = NULL;
  830. buf->buffer->element[i].flags = 0;
  831. }
  832. buf->buffer->element[15].flags = 0;
  833. buf->next_element_to_fill = 0;
  834. atomic_set(&buf->state, QETH_QDIO_BUF_EMPTY);
  835. }
  836. static void qeth_clear_output_buffer(struct qeth_qdio_out_q *queue,
  837. struct qeth_qdio_out_buffer *buf)
  838. {
  839. __qeth_clear_output_buffer(queue, buf, 0);
  840. }
  841. void qeth_clear_qdio_buffers(struct qeth_card *card)
  842. {
  843. int i, j;
  844. QETH_DBF_TEXT(TRACE, 2, "clearqdbf");
  845. /* clear outbound buffers to free skbs */
  846. for (i = 0; i < card->qdio.no_out_queues; ++i)
  847. if (card->qdio.out_qs[i]) {
  848. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j)
  849. qeth_clear_output_buffer(card->qdio.out_qs[i],
  850. &card->qdio.out_qs[i]->bufs[j]);
  851. }
  852. }
  853. EXPORT_SYMBOL_GPL(qeth_clear_qdio_buffers);
  854. static void qeth_free_buffer_pool(struct qeth_card *card)
  855. {
  856. struct qeth_buffer_pool_entry *pool_entry, *tmp;
  857. int i = 0;
  858. QETH_DBF_TEXT(TRACE, 5, "freepool");
  859. list_for_each_entry_safe(pool_entry, tmp,
  860. &card->qdio.init_pool.entry_list, init_list){
  861. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i)
  862. free_page((unsigned long)pool_entry->elements[i]);
  863. list_del(&pool_entry->init_list);
  864. kfree(pool_entry);
  865. }
  866. }
  867. static void qeth_free_qdio_buffers(struct qeth_card *card)
  868. {
  869. int i, j;
  870. QETH_DBF_TEXT(TRACE, 2, "freeqdbf");
  871. if (atomic_xchg(&card->qdio.state, QETH_QDIO_UNINITIALIZED) ==
  872. QETH_QDIO_UNINITIALIZED)
  873. return;
  874. kfree(card->qdio.in_q);
  875. card->qdio.in_q = NULL;
  876. /* inbound buffer pool */
  877. qeth_free_buffer_pool(card);
  878. /* free outbound qdio_qs */
  879. if (card->qdio.out_qs) {
  880. for (i = 0; i < card->qdio.no_out_queues; ++i) {
  881. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j)
  882. qeth_clear_output_buffer(card->qdio.out_qs[i],
  883. &card->qdio.out_qs[i]->bufs[j]);
  884. kfree(card->qdio.out_qs[i]);
  885. }
  886. kfree(card->qdio.out_qs);
  887. card->qdio.out_qs = NULL;
  888. }
  889. }
  890. static void qeth_clean_channel(struct qeth_channel *channel)
  891. {
  892. int cnt;
  893. QETH_DBF_TEXT(SETUP, 2, "freech");
  894. for (cnt = 0; cnt < QETH_CMD_BUFFER_NO; cnt++)
  895. kfree(channel->iob[cnt].data);
  896. }
  897. static int qeth_is_1920_device(struct qeth_card *card)
  898. {
  899. int single_queue = 0;
  900. struct ccw_device *ccwdev;
  901. struct channelPath_dsc {
  902. u8 flags;
  903. u8 lsn;
  904. u8 desc;
  905. u8 chpid;
  906. u8 swla;
  907. u8 zeroes;
  908. u8 chla;
  909. u8 chpp;
  910. } *chp_dsc;
  911. QETH_DBF_TEXT(SETUP, 2, "chk_1920");
  912. ccwdev = card->data.ccwdev;
  913. chp_dsc = (struct channelPath_dsc *)ccw_device_get_chp_desc(ccwdev, 0);
  914. if (chp_dsc != NULL) {
  915. /* CHPP field bit 6 == 1 -> single queue */
  916. single_queue = ((chp_dsc->chpp & 0x02) == 0x02);
  917. kfree(chp_dsc);
  918. }
  919. QETH_DBF_TEXT_(SETUP, 2, "rc:%x", single_queue);
  920. return single_queue;
  921. }
  922. static void qeth_init_qdio_info(struct qeth_card *card)
  923. {
  924. QETH_DBF_TEXT(SETUP, 4, "intqdinf");
  925. atomic_set(&card->qdio.state, QETH_QDIO_UNINITIALIZED);
  926. /* inbound */
  927. card->qdio.in_buf_size = QETH_IN_BUF_SIZE_DEFAULT;
  928. card->qdio.init_pool.buf_count = QETH_IN_BUF_COUNT_DEFAULT;
  929. card->qdio.in_buf_pool.buf_count = card->qdio.init_pool.buf_count;
  930. INIT_LIST_HEAD(&card->qdio.in_buf_pool.entry_list);
  931. INIT_LIST_HEAD(&card->qdio.init_pool.entry_list);
  932. }
  933. static void qeth_set_intial_options(struct qeth_card *card)
  934. {
  935. card->options.route4.type = NO_ROUTER;
  936. card->options.route6.type = NO_ROUTER;
  937. card->options.checksum_type = QETH_CHECKSUM_DEFAULT;
  938. card->options.broadcast_mode = QETH_TR_BROADCAST_ALLRINGS;
  939. card->options.macaddr_mode = QETH_TR_MACADDR_NONCANONICAL;
  940. card->options.fake_broadcast = 0;
  941. card->options.add_hhlen = DEFAULT_ADD_HHLEN;
  942. card->options.performance_stats = 0;
  943. card->options.rx_sg_cb = QETH_RX_SG_CB;
  944. card->options.isolation = ISOLATION_MODE_NONE;
  945. }
  946. static int qeth_do_start_thread(struct qeth_card *card, unsigned long thread)
  947. {
  948. unsigned long flags;
  949. int rc = 0;
  950. spin_lock_irqsave(&card->thread_mask_lock, flags);
  951. QETH_DBF_TEXT_(TRACE, 4, " %02x%02x%02x",
  952. (u8) card->thread_start_mask,
  953. (u8) card->thread_allowed_mask,
  954. (u8) card->thread_running_mask);
  955. rc = (card->thread_start_mask & thread);
  956. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  957. return rc;
  958. }
  959. static void qeth_start_kernel_thread(struct work_struct *work)
  960. {
  961. struct qeth_card *card = container_of(work, struct qeth_card,
  962. kernel_thread_starter);
  963. QETH_DBF_TEXT(TRACE , 2, "strthrd");
  964. if (card->read.state != CH_STATE_UP &&
  965. card->write.state != CH_STATE_UP)
  966. return;
  967. if (qeth_do_start_thread(card, QETH_RECOVER_THREAD))
  968. kthread_run(card->discipline.recover, (void *) card,
  969. "qeth_recover");
  970. }
  971. static int qeth_setup_card(struct qeth_card *card)
  972. {
  973. QETH_DBF_TEXT(SETUP, 2, "setupcrd");
  974. QETH_DBF_HEX(SETUP, 2, &card, sizeof(void *));
  975. card->read.state = CH_STATE_DOWN;
  976. card->write.state = CH_STATE_DOWN;
  977. card->data.state = CH_STATE_DOWN;
  978. card->state = CARD_STATE_DOWN;
  979. card->lan_online = 0;
  980. card->use_hard_stop = 0;
  981. card->dev = NULL;
  982. spin_lock_init(&card->vlanlock);
  983. spin_lock_init(&card->mclock);
  984. card->vlangrp = NULL;
  985. spin_lock_init(&card->lock);
  986. spin_lock_init(&card->ip_lock);
  987. spin_lock_init(&card->thread_mask_lock);
  988. card->thread_start_mask = 0;
  989. card->thread_allowed_mask = 0;
  990. card->thread_running_mask = 0;
  991. INIT_WORK(&card->kernel_thread_starter, qeth_start_kernel_thread);
  992. INIT_LIST_HEAD(&card->ip_list);
  993. INIT_LIST_HEAD(card->ip_tbd_list);
  994. INIT_LIST_HEAD(&card->cmd_waiter_list);
  995. init_waitqueue_head(&card->wait_q);
  996. /* intial options */
  997. qeth_set_intial_options(card);
  998. /* IP address takeover */
  999. INIT_LIST_HEAD(&card->ipato.entries);
  1000. card->ipato.enabled = 0;
  1001. card->ipato.invert4 = 0;
  1002. card->ipato.invert6 = 0;
  1003. if (card->info.type == QETH_CARD_TYPE_IQD)
  1004. card->options.checksum_type = NO_CHECKSUMMING;
  1005. /* init QDIO stuff */
  1006. qeth_init_qdio_info(card);
  1007. return 0;
  1008. }
  1009. static void qeth_core_sl_print(struct seq_file *m, struct service_level *slr)
  1010. {
  1011. struct qeth_card *card = container_of(slr, struct qeth_card,
  1012. qeth_service_level);
  1013. if (card->info.mcl_level[0])
  1014. seq_printf(m, "qeth: %s firmware level %s\n",
  1015. CARD_BUS_ID(card), card->info.mcl_level);
  1016. }
  1017. static struct qeth_card *qeth_alloc_card(void)
  1018. {
  1019. struct qeth_card *card;
  1020. QETH_DBF_TEXT(SETUP, 2, "alloccrd");
  1021. card = kzalloc(sizeof(struct qeth_card), GFP_DMA|GFP_KERNEL);
  1022. if (!card)
  1023. goto out;
  1024. QETH_DBF_HEX(SETUP, 2, &card, sizeof(void *));
  1025. card->ip_tbd_list = kmalloc(sizeof(struct list_head), GFP_KERNEL);
  1026. if (!card->ip_tbd_list) {
  1027. QETH_DBF_TEXT(SETUP, 0, "iptbdnom");
  1028. goto out_card;
  1029. }
  1030. if (qeth_setup_channel(&card->read))
  1031. goto out_ip;
  1032. if (qeth_setup_channel(&card->write))
  1033. goto out_channel;
  1034. card->options.layer2 = -1;
  1035. card->qeth_service_level.seq_print = qeth_core_sl_print;
  1036. register_service_level(&card->qeth_service_level);
  1037. return card;
  1038. out_channel:
  1039. qeth_clean_channel(&card->read);
  1040. out_ip:
  1041. kfree(card->ip_tbd_list);
  1042. out_card:
  1043. kfree(card);
  1044. out:
  1045. return NULL;
  1046. }
  1047. static int qeth_determine_card_type(struct qeth_card *card)
  1048. {
  1049. int i = 0;
  1050. QETH_DBF_TEXT(SETUP, 2, "detcdtyp");
  1051. card->qdio.do_prio_queueing = QETH_PRIOQ_DEFAULT;
  1052. card->qdio.default_out_queue = QETH_DEFAULT_QUEUE;
  1053. while (known_devices[i][4]) {
  1054. if ((CARD_RDEV(card)->id.dev_type == known_devices[i][2]) &&
  1055. (CARD_RDEV(card)->id.dev_model == known_devices[i][3])) {
  1056. card->info.type = known_devices[i][4];
  1057. card->qdio.no_out_queues = known_devices[i][8];
  1058. card->info.is_multicast_different = known_devices[i][9];
  1059. if (qeth_is_1920_device(card)) {
  1060. dev_info(&card->gdev->dev,
  1061. "Priority Queueing not supported\n");
  1062. card->qdio.no_out_queues = 1;
  1063. card->qdio.default_out_queue = 0;
  1064. }
  1065. return 0;
  1066. }
  1067. i++;
  1068. }
  1069. card->info.type = QETH_CARD_TYPE_UNKNOWN;
  1070. dev_err(&card->gdev->dev, "The adapter hardware is of an "
  1071. "unknown type\n");
  1072. return -ENOENT;
  1073. }
  1074. static int qeth_clear_channel(struct qeth_channel *channel)
  1075. {
  1076. unsigned long flags;
  1077. struct qeth_card *card;
  1078. int rc;
  1079. QETH_DBF_TEXT(TRACE, 3, "clearch");
  1080. card = CARD_FROM_CDEV(channel->ccwdev);
  1081. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1082. rc = ccw_device_clear(channel->ccwdev, QETH_CLEAR_CHANNEL_PARM);
  1083. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1084. if (rc)
  1085. return rc;
  1086. rc = wait_event_interruptible_timeout(card->wait_q,
  1087. channel->state == CH_STATE_STOPPED, QETH_TIMEOUT);
  1088. if (rc == -ERESTARTSYS)
  1089. return rc;
  1090. if (channel->state != CH_STATE_STOPPED)
  1091. return -ETIME;
  1092. channel->state = CH_STATE_DOWN;
  1093. return 0;
  1094. }
  1095. static int qeth_halt_channel(struct qeth_channel *channel)
  1096. {
  1097. unsigned long flags;
  1098. struct qeth_card *card;
  1099. int rc;
  1100. QETH_DBF_TEXT(TRACE, 3, "haltch");
  1101. card = CARD_FROM_CDEV(channel->ccwdev);
  1102. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1103. rc = ccw_device_halt(channel->ccwdev, QETH_HALT_CHANNEL_PARM);
  1104. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1105. if (rc)
  1106. return rc;
  1107. rc = wait_event_interruptible_timeout(card->wait_q,
  1108. channel->state == CH_STATE_HALTED, QETH_TIMEOUT);
  1109. if (rc == -ERESTARTSYS)
  1110. return rc;
  1111. if (channel->state != CH_STATE_HALTED)
  1112. return -ETIME;
  1113. return 0;
  1114. }
  1115. static int qeth_halt_channels(struct qeth_card *card)
  1116. {
  1117. int rc1 = 0, rc2 = 0, rc3 = 0;
  1118. QETH_DBF_TEXT(TRACE, 3, "haltchs");
  1119. rc1 = qeth_halt_channel(&card->read);
  1120. rc2 = qeth_halt_channel(&card->write);
  1121. rc3 = qeth_halt_channel(&card->data);
  1122. if (rc1)
  1123. return rc1;
  1124. if (rc2)
  1125. return rc2;
  1126. return rc3;
  1127. }
  1128. static int qeth_clear_channels(struct qeth_card *card)
  1129. {
  1130. int rc1 = 0, rc2 = 0, rc3 = 0;
  1131. QETH_DBF_TEXT(TRACE, 3, "clearchs");
  1132. rc1 = qeth_clear_channel(&card->read);
  1133. rc2 = qeth_clear_channel(&card->write);
  1134. rc3 = qeth_clear_channel(&card->data);
  1135. if (rc1)
  1136. return rc1;
  1137. if (rc2)
  1138. return rc2;
  1139. return rc3;
  1140. }
  1141. static int qeth_clear_halt_card(struct qeth_card *card, int halt)
  1142. {
  1143. int rc = 0;
  1144. QETH_DBF_TEXT(TRACE, 3, "clhacrd");
  1145. QETH_DBF_HEX(TRACE, 3, &card, sizeof(void *));
  1146. if (halt)
  1147. rc = qeth_halt_channels(card);
  1148. if (rc)
  1149. return rc;
  1150. return qeth_clear_channels(card);
  1151. }
  1152. int qeth_qdio_clear_card(struct qeth_card *card, int use_halt)
  1153. {
  1154. int rc = 0;
  1155. QETH_DBF_TEXT(TRACE, 3, "qdioclr");
  1156. switch (atomic_cmpxchg(&card->qdio.state, QETH_QDIO_ESTABLISHED,
  1157. QETH_QDIO_CLEANING)) {
  1158. case QETH_QDIO_ESTABLISHED:
  1159. if (card->info.type == QETH_CARD_TYPE_IQD)
  1160. rc = qdio_cleanup(CARD_DDEV(card),
  1161. QDIO_FLAG_CLEANUP_USING_HALT);
  1162. else
  1163. rc = qdio_cleanup(CARD_DDEV(card),
  1164. QDIO_FLAG_CLEANUP_USING_CLEAR);
  1165. if (rc)
  1166. QETH_DBF_TEXT_(TRACE, 3, "1err%d", rc);
  1167. atomic_set(&card->qdio.state, QETH_QDIO_ALLOCATED);
  1168. break;
  1169. case QETH_QDIO_CLEANING:
  1170. return rc;
  1171. default:
  1172. break;
  1173. }
  1174. rc = qeth_clear_halt_card(card, use_halt);
  1175. if (rc)
  1176. QETH_DBF_TEXT_(TRACE, 3, "2err%d", rc);
  1177. card->state = CARD_STATE_DOWN;
  1178. return rc;
  1179. }
  1180. EXPORT_SYMBOL_GPL(qeth_qdio_clear_card);
  1181. static int qeth_read_conf_data(struct qeth_card *card, void **buffer,
  1182. int *length)
  1183. {
  1184. struct ciw *ciw;
  1185. char *rcd_buf;
  1186. int ret;
  1187. struct qeth_channel *channel = &card->data;
  1188. unsigned long flags;
  1189. /*
  1190. * scan for RCD command in extended SenseID data
  1191. */
  1192. ciw = ccw_device_get_ciw(channel->ccwdev, CIW_TYPE_RCD);
  1193. if (!ciw || ciw->cmd == 0)
  1194. return -EOPNOTSUPP;
  1195. rcd_buf = kzalloc(ciw->count, GFP_KERNEL | GFP_DMA);
  1196. if (!rcd_buf)
  1197. return -ENOMEM;
  1198. channel->ccw.cmd_code = ciw->cmd;
  1199. channel->ccw.cda = (__u32) __pa(rcd_buf);
  1200. channel->ccw.count = ciw->count;
  1201. channel->ccw.flags = CCW_FLAG_SLI;
  1202. channel->state = CH_STATE_RCD;
  1203. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1204. ret = ccw_device_start_timeout(channel->ccwdev, &channel->ccw,
  1205. QETH_RCD_PARM, LPM_ANYPATH, 0,
  1206. QETH_RCD_TIMEOUT);
  1207. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1208. if (!ret)
  1209. wait_event(card->wait_q,
  1210. (channel->state == CH_STATE_RCD_DONE ||
  1211. channel->state == CH_STATE_DOWN));
  1212. if (channel->state == CH_STATE_DOWN)
  1213. ret = -EIO;
  1214. else
  1215. channel->state = CH_STATE_DOWN;
  1216. if (ret) {
  1217. kfree(rcd_buf);
  1218. *buffer = NULL;
  1219. *length = 0;
  1220. } else {
  1221. *length = ciw->count;
  1222. *buffer = rcd_buf;
  1223. }
  1224. return ret;
  1225. }
  1226. static int qeth_get_unitaddr(struct qeth_card *card)
  1227. {
  1228. int length;
  1229. char *prcd;
  1230. int rc;
  1231. QETH_DBF_TEXT(SETUP, 2, "getunit");
  1232. rc = qeth_read_conf_data(card, (void **) &prcd, &length);
  1233. if (rc) {
  1234. QETH_DBF_MESSAGE(2, "%s qeth_read_conf_data returned %i\n",
  1235. dev_name(&card->gdev->dev), rc);
  1236. return rc;
  1237. }
  1238. card->info.chpid = prcd[30];
  1239. card->info.unit_addr2 = prcd[31];
  1240. card->info.cula = prcd[63];
  1241. card->info.guestlan = ((prcd[0x10] == _ascebc['V']) &&
  1242. (prcd[0x11] == _ascebc['M']));
  1243. kfree(prcd);
  1244. return 0;
  1245. }
  1246. static void qeth_init_tokens(struct qeth_card *card)
  1247. {
  1248. card->token.issuer_rm_w = 0x00010103UL;
  1249. card->token.cm_filter_w = 0x00010108UL;
  1250. card->token.cm_connection_w = 0x0001010aUL;
  1251. card->token.ulp_filter_w = 0x0001010bUL;
  1252. card->token.ulp_connection_w = 0x0001010dUL;
  1253. }
  1254. static void qeth_init_func_level(struct qeth_card *card)
  1255. {
  1256. if (card->ipato.enabled) {
  1257. if (card->info.type == QETH_CARD_TYPE_IQD)
  1258. card->info.func_level =
  1259. QETH_IDX_FUNC_LEVEL_IQD_ENA_IPAT;
  1260. else
  1261. card->info.func_level =
  1262. QETH_IDX_FUNC_LEVEL_OSAE_ENA_IPAT;
  1263. } else {
  1264. if (card->info.type == QETH_CARD_TYPE_IQD)
  1265. /*FIXME:why do we have same values for dis and ena for
  1266. osae??? */
  1267. card->info.func_level =
  1268. QETH_IDX_FUNC_LEVEL_IQD_DIS_IPAT;
  1269. else
  1270. card->info.func_level =
  1271. QETH_IDX_FUNC_LEVEL_OSAE_DIS_IPAT;
  1272. }
  1273. }
  1274. static int qeth_idx_activate_get_answer(struct qeth_channel *channel,
  1275. void (*idx_reply_cb)(struct qeth_channel *,
  1276. struct qeth_cmd_buffer *))
  1277. {
  1278. struct qeth_cmd_buffer *iob;
  1279. unsigned long flags;
  1280. int rc;
  1281. struct qeth_card *card;
  1282. QETH_DBF_TEXT(SETUP, 2, "idxanswr");
  1283. card = CARD_FROM_CDEV(channel->ccwdev);
  1284. iob = qeth_get_buffer(channel);
  1285. iob->callback = idx_reply_cb;
  1286. memcpy(&channel->ccw, READ_CCW, sizeof(struct ccw1));
  1287. channel->ccw.count = QETH_BUFSIZE;
  1288. channel->ccw.cda = (__u32) __pa(iob->data);
  1289. wait_event(card->wait_q,
  1290. atomic_cmpxchg(&channel->irq_pending, 0, 1) == 0);
  1291. QETH_DBF_TEXT(SETUP, 6, "noirqpnd");
  1292. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1293. rc = ccw_device_start(channel->ccwdev,
  1294. &channel->ccw, (addr_t) iob, 0, 0);
  1295. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1296. if (rc) {
  1297. QETH_DBF_MESSAGE(2, "Error2 in activating channel rc=%d\n", rc);
  1298. QETH_DBF_TEXT_(SETUP, 2, "2err%d", rc);
  1299. atomic_set(&channel->irq_pending, 0);
  1300. wake_up(&card->wait_q);
  1301. return rc;
  1302. }
  1303. rc = wait_event_interruptible_timeout(card->wait_q,
  1304. channel->state == CH_STATE_UP, QETH_TIMEOUT);
  1305. if (rc == -ERESTARTSYS)
  1306. return rc;
  1307. if (channel->state != CH_STATE_UP) {
  1308. rc = -ETIME;
  1309. QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
  1310. qeth_clear_cmd_buffers(channel);
  1311. } else
  1312. rc = 0;
  1313. return rc;
  1314. }
  1315. static int qeth_idx_activate_channel(struct qeth_channel *channel,
  1316. void (*idx_reply_cb)(struct qeth_channel *,
  1317. struct qeth_cmd_buffer *))
  1318. {
  1319. struct qeth_card *card;
  1320. struct qeth_cmd_buffer *iob;
  1321. unsigned long flags;
  1322. __u16 temp;
  1323. __u8 tmp;
  1324. int rc;
  1325. struct ccw_dev_id temp_devid;
  1326. card = CARD_FROM_CDEV(channel->ccwdev);
  1327. QETH_DBF_TEXT(SETUP, 2, "idxactch");
  1328. iob = qeth_get_buffer(channel);
  1329. iob->callback = idx_reply_cb;
  1330. memcpy(&channel->ccw, WRITE_CCW, sizeof(struct ccw1));
  1331. channel->ccw.count = IDX_ACTIVATE_SIZE;
  1332. channel->ccw.cda = (__u32) __pa(iob->data);
  1333. if (channel == &card->write) {
  1334. memcpy(iob->data, IDX_ACTIVATE_WRITE, IDX_ACTIVATE_SIZE);
  1335. memcpy(QETH_TRANSPORT_HEADER_SEQ_NO(iob->data),
  1336. &card->seqno.trans_hdr, QETH_SEQ_NO_LENGTH);
  1337. card->seqno.trans_hdr++;
  1338. } else {
  1339. memcpy(iob->data, IDX_ACTIVATE_READ, IDX_ACTIVATE_SIZE);
  1340. memcpy(QETH_TRANSPORT_HEADER_SEQ_NO(iob->data),
  1341. &card->seqno.trans_hdr, QETH_SEQ_NO_LENGTH);
  1342. }
  1343. tmp = ((__u8)card->info.portno) | 0x80;
  1344. memcpy(QETH_IDX_ACT_PNO(iob->data), &tmp, 1);
  1345. memcpy(QETH_IDX_ACT_ISSUER_RM_TOKEN(iob->data),
  1346. &card->token.issuer_rm_w, QETH_MPC_TOKEN_LENGTH);
  1347. memcpy(QETH_IDX_ACT_FUNC_LEVEL(iob->data),
  1348. &card->info.func_level, sizeof(__u16));
  1349. ccw_device_get_id(CARD_DDEV(card), &temp_devid);
  1350. memcpy(QETH_IDX_ACT_QDIO_DEV_CUA(iob->data), &temp_devid.devno, 2);
  1351. temp = (card->info.cula << 8) + card->info.unit_addr2;
  1352. memcpy(QETH_IDX_ACT_QDIO_DEV_REALADDR(iob->data), &temp, 2);
  1353. wait_event(card->wait_q,
  1354. atomic_cmpxchg(&channel->irq_pending, 0, 1) == 0);
  1355. QETH_DBF_TEXT(SETUP, 6, "noirqpnd");
  1356. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1357. rc = ccw_device_start(channel->ccwdev,
  1358. &channel->ccw, (addr_t) iob, 0, 0);
  1359. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1360. if (rc) {
  1361. QETH_DBF_MESSAGE(2, "Error1 in activating channel. rc=%d\n",
  1362. rc);
  1363. QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
  1364. atomic_set(&channel->irq_pending, 0);
  1365. wake_up(&card->wait_q);
  1366. return rc;
  1367. }
  1368. rc = wait_event_interruptible_timeout(card->wait_q,
  1369. channel->state == CH_STATE_ACTIVATING, QETH_TIMEOUT);
  1370. if (rc == -ERESTARTSYS)
  1371. return rc;
  1372. if (channel->state != CH_STATE_ACTIVATING) {
  1373. dev_warn(&channel->ccwdev->dev, "The qeth device driver"
  1374. " failed to recover an error on the device\n");
  1375. QETH_DBF_MESSAGE(2, "%s IDX activate timed out\n",
  1376. dev_name(&channel->ccwdev->dev));
  1377. QETH_DBF_TEXT_(SETUP, 2, "2err%d", -ETIME);
  1378. qeth_clear_cmd_buffers(channel);
  1379. return -ETIME;
  1380. }
  1381. return qeth_idx_activate_get_answer(channel, idx_reply_cb);
  1382. }
  1383. static int qeth_peer_func_level(int level)
  1384. {
  1385. if ((level & 0xff) == 8)
  1386. return (level & 0xff) + 0x400;
  1387. if (((level >> 8) & 3) == 1)
  1388. return (level & 0xff) + 0x200;
  1389. return level;
  1390. }
  1391. static void qeth_idx_write_cb(struct qeth_channel *channel,
  1392. struct qeth_cmd_buffer *iob)
  1393. {
  1394. struct qeth_card *card;
  1395. __u16 temp;
  1396. QETH_DBF_TEXT(SETUP , 2, "idxwrcb");
  1397. if (channel->state == CH_STATE_DOWN) {
  1398. channel->state = CH_STATE_ACTIVATING;
  1399. goto out;
  1400. }
  1401. card = CARD_FROM_CDEV(channel->ccwdev);
  1402. if (!(QETH_IS_IDX_ACT_POS_REPLY(iob->data))) {
  1403. if (QETH_IDX_ACT_CAUSE_CODE(iob->data) == 0x19)
  1404. dev_err(&card->write.ccwdev->dev,
  1405. "The adapter is used exclusively by another "
  1406. "host\n");
  1407. else
  1408. QETH_DBF_MESSAGE(2, "%s IDX_ACTIVATE on write channel:"
  1409. " negative reply\n",
  1410. dev_name(&card->write.ccwdev->dev));
  1411. goto out;
  1412. }
  1413. memcpy(&temp, QETH_IDX_ACT_FUNC_LEVEL(iob->data), 2);
  1414. if ((temp & ~0x0100) != qeth_peer_func_level(card->info.func_level)) {
  1415. QETH_DBF_MESSAGE(2, "%s IDX_ACTIVATE on write channel: "
  1416. "function level mismatch (sent: 0x%x, received: "
  1417. "0x%x)\n", dev_name(&card->write.ccwdev->dev),
  1418. card->info.func_level, temp);
  1419. goto out;
  1420. }
  1421. channel->state = CH_STATE_UP;
  1422. out:
  1423. qeth_release_buffer(channel, iob);
  1424. }
  1425. static void qeth_idx_read_cb(struct qeth_channel *channel,
  1426. struct qeth_cmd_buffer *iob)
  1427. {
  1428. struct qeth_card *card;
  1429. __u16 temp;
  1430. QETH_DBF_TEXT(SETUP , 2, "idxrdcb");
  1431. if (channel->state == CH_STATE_DOWN) {
  1432. channel->state = CH_STATE_ACTIVATING;
  1433. goto out;
  1434. }
  1435. card = CARD_FROM_CDEV(channel->ccwdev);
  1436. if (qeth_check_idx_response(iob->data))
  1437. goto out;
  1438. if (!(QETH_IS_IDX_ACT_POS_REPLY(iob->data))) {
  1439. if (QETH_IDX_ACT_CAUSE_CODE(iob->data) == 0x19)
  1440. dev_err(&card->write.ccwdev->dev,
  1441. "The adapter is used exclusively by another "
  1442. "host\n");
  1443. else
  1444. QETH_DBF_MESSAGE(2, "%s IDX_ACTIVATE on read channel:"
  1445. " negative reply\n",
  1446. dev_name(&card->read.ccwdev->dev));
  1447. goto out;
  1448. }
  1449. /**
  1450. * temporary fix for microcode bug
  1451. * to revert it,replace OR by AND
  1452. */
  1453. if ((!QETH_IDX_NO_PORTNAME_REQUIRED(iob->data)) ||
  1454. (card->info.type == QETH_CARD_TYPE_OSAE))
  1455. card->info.portname_required = 1;
  1456. memcpy(&temp, QETH_IDX_ACT_FUNC_LEVEL(iob->data), 2);
  1457. if (temp != qeth_peer_func_level(card->info.func_level)) {
  1458. QETH_DBF_MESSAGE(2, "%s IDX_ACTIVATE on read channel: function "
  1459. "level mismatch (sent: 0x%x, received: 0x%x)\n",
  1460. dev_name(&card->read.ccwdev->dev),
  1461. card->info.func_level, temp);
  1462. goto out;
  1463. }
  1464. memcpy(&card->token.issuer_rm_r,
  1465. QETH_IDX_ACT_ISSUER_RM_TOKEN(iob->data),
  1466. QETH_MPC_TOKEN_LENGTH);
  1467. memcpy(&card->info.mcl_level[0],
  1468. QETH_IDX_REPLY_LEVEL(iob->data), QETH_MCL_LENGTH);
  1469. channel->state = CH_STATE_UP;
  1470. out:
  1471. qeth_release_buffer(channel, iob);
  1472. }
  1473. void qeth_prepare_control_data(struct qeth_card *card, int len,
  1474. struct qeth_cmd_buffer *iob)
  1475. {
  1476. qeth_setup_ccw(&card->write, iob->data, len);
  1477. iob->callback = qeth_release_buffer;
  1478. memcpy(QETH_TRANSPORT_HEADER_SEQ_NO(iob->data),
  1479. &card->seqno.trans_hdr, QETH_SEQ_NO_LENGTH);
  1480. card->seqno.trans_hdr++;
  1481. memcpy(QETH_PDU_HEADER_SEQ_NO(iob->data),
  1482. &card->seqno.pdu_hdr, QETH_SEQ_NO_LENGTH);
  1483. card->seqno.pdu_hdr++;
  1484. memcpy(QETH_PDU_HEADER_ACK_SEQ_NO(iob->data),
  1485. &card->seqno.pdu_hdr_ack, QETH_SEQ_NO_LENGTH);
  1486. QETH_DBF_HEX(CTRL, 2, iob->data, QETH_DBF_CTRL_LEN);
  1487. }
  1488. EXPORT_SYMBOL_GPL(qeth_prepare_control_data);
  1489. int qeth_send_control_data(struct qeth_card *card, int len,
  1490. struct qeth_cmd_buffer *iob,
  1491. int (*reply_cb)(struct qeth_card *, struct qeth_reply *,
  1492. unsigned long),
  1493. void *reply_param)
  1494. {
  1495. int rc;
  1496. unsigned long flags;
  1497. struct qeth_reply *reply = NULL;
  1498. unsigned long timeout, event_timeout;
  1499. struct qeth_ipa_cmd *cmd;
  1500. QETH_DBF_TEXT(TRACE, 2, "sendctl");
  1501. reply = qeth_alloc_reply(card);
  1502. if (!reply) {
  1503. return -ENOMEM;
  1504. }
  1505. reply->callback = reply_cb;
  1506. reply->param = reply_param;
  1507. if (card->state == CARD_STATE_DOWN)
  1508. reply->seqno = QETH_IDX_COMMAND_SEQNO;
  1509. else
  1510. reply->seqno = card->seqno.ipa++;
  1511. init_waitqueue_head(&reply->wait_q);
  1512. spin_lock_irqsave(&card->lock, flags);
  1513. list_add_tail(&reply->list, &card->cmd_waiter_list);
  1514. spin_unlock_irqrestore(&card->lock, flags);
  1515. QETH_DBF_HEX(CTRL, 2, iob->data, QETH_DBF_CTRL_LEN);
  1516. while (atomic_cmpxchg(&card->write.irq_pending, 0, 1)) ;
  1517. qeth_prepare_control_data(card, len, iob);
  1518. if (IS_IPA(iob->data))
  1519. event_timeout = QETH_IPA_TIMEOUT;
  1520. else
  1521. event_timeout = QETH_TIMEOUT;
  1522. timeout = jiffies + event_timeout;
  1523. QETH_DBF_TEXT(TRACE, 6, "noirqpnd");
  1524. spin_lock_irqsave(get_ccwdev_lock(card->write.ccwdev), flags);
  1525. rc = ccw_device_start(card->write.ccwdev, &card->write.ccw,
  1526. (addr_t) iob, 0, 0);
  1527. spin_unlock_irqrestore(get_ccwdev_lock(card->write.ccwdev), flags);
  1528. if (rc) {
  1529. QETH_DBF_MESSAGE(2, "%s qeth_send_control_data: "
  1530. "ccw_device_start rc = %i\n",
  1531. dev_name(&card->write.ccwdev->dev), rc);
  1532. QETH_DBF_TEXT_(TRACE, 2, " err%d", rc);
  1533. spin_lock_irqsave(&card->lock, flags);
  1534. list_del_init(&reply->list);
  1535. qeth_put_reply(reply);
  1536. spin_unlock_irqrestore(&card->lock, flags);
  1537. qeth_release_buffer(iob->channel, iob);
  1538. atomic_set(&card->write.irq_pending, 0);
  1539. wake_up(&card->wait_q);
  1540. return rc;
  1541. }
  1542. /* we have only one long running ipassist, since we can ensure
  1543. process context of this command we can sleep */
  1544. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  1545. if ((cmd->hdr.command == IPA_CMD_SETIP) &&
  1546. (cmd->hdr.prot_version == QETH_PROT_IPV4)) {
  1547. if (!wait_event_timeout(reply->wait_q,
  1548. atomic_read(&reply->received), event_timeout))
  1549. goto time_err;
  1550. } else {
  1551. while (!atomic_read(&reply->received)) {
  1552. if (time_after(jiffies, timeout))
  1553. goto time_err;
  1554. cpu_relax();
  1555. };
  1556. }
  1557. rc = reply->rc;
  1558. qeth_put_reply(reply);
  1559. return rc;
  1560. time_err:
  1561. spin_lock_irqsave(&reply->card->lock, flags);
  1562. list_del_init(&reply->list);
  1563. spin_unlock_irqrestore(&reply->card->lock, flags);
  1564. reply->rc = -ETIME;
  1565. atomic_inc(&reply->received);
  1566. wake_up(&reply->wait_q);
  1567. rc = reply->rc;
  1568. qeth_put_reply(reply);
  1569. return rc;
  1570. }
  1571. EXPORT_SYMBOL_GPL(qeth_send_control_data);
  1572. static int qeth_cm_enable_cb(struct qeth_card *card, struct qeth_reply *reply,
  1573. unsigned long data)
  1574. {
  1575. struct qeth_cmd_buffer *iob;
  1576. QETH_DBF_TEXT(SETUP, 2, "cmenblcb");
  1577. iob = (struct qeth_cmd_buffer *) data;
  1578. memcpy(&card->token.cm_filter_r,
  1579. QETH_CM_ENABLE_RESP_FILTER_TOKEN(iob->data),
  1580. QETH_MPC_TOKEN_LENGTH);
  1581. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  1582. return 0;
  1583. }
  1584. static int qeth_cm_enable(struct qeth_card *card)
  1585. {
  1586. int rc;
  1587. struct qeth_cmd_buffer *iob;
  1588. QETH_DBF_TEXT(SETUP, 2, "cmenable");
  1589. iob = qeth_wait_for_buffer(&card->write);
  1590. memcpy(iob->data, CM_ENABLE, CM_ENABLE_SIZE);
  1591. memcpy(QETH_CM_ENABLE_ISSUER_RM_TOKEN(iob->data),
  1592. &card->token.issuer_rm_r, QETH_MPC_TOKEN_LENGTH);
  1593. memcpy(QETH_CM_ENABLE_FILTER_TOKEN(iob->data),
  1594. &card->token.cm_filter_w, QETH_MPC_TOKEN_LENGTH);
  1595. rc = qeth_send_control_data(card, CM_ENABLE_SIZE, iob,
  1596. qeth_cm_enable_cb, NULL);
  1597. return rc;
  1598. }
  1599. static int qeth_cm_setup_cb(struct qeth_card *card, struct qeth_reply *reply,
  1600. unsigned long data)
  1601. {
  1602. struct qeth_cmd_buffer *iob;
  1603. QETH_DBF_TEXT(SETUP, 2, "cmsetpcb");
  1604. iob = (struct qeth_cmd_buffer *) data;
  1605. memcpy(&card->token.cm_connection_r,
  1606. QETH_CM_SETUP_RESP_DEST_ADDR(iob->data),
  1607. QETH_MPC_TOKEN_LENGTH);
  1608. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  1609. return 0;
  1610. }
  1611. static int qeth_cm_setup(struct qeth_card *card)
  1612. {
  1613. int rc;
  1614. struct qeth_cmd_buffer *iob;
  1615. QETH_DBF_TEXT(SETUP, 2, "cmsetup");
  1616. iob = qeth_wait_for_buffer(&card->write);
  1617. memcpy(iob->data, CM_SETUP, CM_SETUP_SIZE);
  1618. memcpy(QETH_CM_SETUP_DEST_ADDR(iob->data),
  1619. &card->token.issuer_rm_r, QETH_MPC_TOKEN_LENGTH);
  1620. memcpy(QETH_CM_SETUP_CONNECTION_TOKEN(iob->data),
  1621. &card->token.cm_connection_w, QETH_MPC_TOKEN_LENGTH);
  1622. memcpy(QETH_CM_SETUP_FILTER_TOKEN(iob->data),
  1623. &card->token.cm_filter_r, QETH_MPC_TOKEN_LENGTH);
  1624. rc = qeth_send_control_data(card, CM_SETUP_SIZE, iob,
  1625. qeth_cm_setup_cb, NULL);
  1626. return rc;
  1627. }
  1628. static inline int qeth_get_initial_mtu_for_card(struct qeth_card *card)
  1629. {
  1630. switch (card->info.type) {
  1631. case QETH_CARD_TYPE_UNKNOWN:
  1632. return 1500;
  1633. case QETH_CARD_TYPE_IQD:
  1634. return card->info.max_mtu;
  1635. case QETH_CARD_TYPE_OSAE:
  1636. switch (card->info.link_type) {
  1637. case QETH_LINK_TYPE_HSTR:
  1638. case QETH_LINK_TYPE_LANE_TR:
  1639. return 2000;
  1640. default:
  1641. return 1492;
  1642. }
  1643. default:
  1644. return 1500;
  1645. }
  1646. }
  1647. static inline int qeth_get_max_mtu_for_card(int cardtype)
  1648. {
  1649. switch (cardtype) {
  1650. case QETH_CARD_TYPE_UNKNOWN:
  1651. case QETH_CARD_TYPE_OSAE:
  1652. case QETH_CARD_TYPE_OSN:
  1653. return 61440;
  1654. case QETH_CARD_TYPE_IQD:
  1655. return 57344;
  1656. default:
  1657. return 1500;
  1658. }
  1659. }
  1660. static inline int qeth_get_mtu_out_of_mpc(int cardtype)
  1661. {
  1662. switch (cardtype) {
  1663. case QETH_CARD_TYPE_IQD:
  1664. return 1;
  1665. default:
  1666. return 0;
  1667. }
  1668. }
  1669. static inline int qeth_get_mtu_outof_framesize(int framesize)
  1670. {
  1671. switch (framesize) {
  1672. case 0x4000:
  1673. return 8192;
  1674. case 0x6000:
  1675. return 16384;
  1676. case 0xa000:
  1677. return 32768;
  1678. case 0xffff:
  1679. return 57344;
  1680. default:
  1681. return 0;
  1682. }
  1683. }
  1684. static inline int qeth_mtu_is_valid(struct qeth_card *card, int mtu)
  1685. {
  1686. switch (card->info.type) {
  1687. case QETH_CARD_TYPE_OSAE:
  1688. return ((mtu >= 576) && (mtu <= 61440));
  1689. case QETH_CARD_TYPE_IQD:
  1690. return ((mtu >= 576) &&
  1691. (mtu <= card->info.max_mtu + 4096 - 32));
  1692. case QETH_CARD_TYPE_OSN:
  1693. case QETH_CARD_TYPE_UNKNOWN:
  1694. default:
  1695. return 1;
  1696. }
  1697. }
  1698. static int qeth_ulp_enable_cb(struct qeth_card *card, struct qeth_reply *reply,
  1699. unsigned long data)
  1700. {
  1701. __u16 mtu, framesize;
  1702. __u16 len;
  1703. __u8 link_type;
  1704. struct qeth_cmd_buffer *iob;
  1705. QETH_DBF_TEXT(SETUP, 2, "ulpenacb");
  1706. iob = (struct qeth_cmd_buffer *) data;
  1707. memcpy(&card->token.ulp_filter_r,
  1708. QETH_ULP_ENABLE_RESP_FILTER_TOKEN(iob->data),
  1709. QETH_MPC_TOKEN_LENGTH);
  1710. if (qeth_get_mtu_out_of_mpc(card->info.type)) {
  1711. memcpy(&framesize, QETH_ULP_ENABLE_RESP_MAX_MTU(iob->data), 2);
  1712. mtu = qeth_get_mtu_outof_framesize(framesize);
  1713. if (!mtu) {
  1714. iob->rc = -EINVAL;
  1715. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  1716. return 0;
  1717. }
  1718. card->info.max_mtu = mtu;
  1719. card->info.initial_mtu = mtu;
  1720. card->qdio.in_buf_size = mtu + 2 * PAGE_SIZE;
  1721. } else {
  1722. card->info.initial_mtu = qeth_get_initial_mtu_for_card(card);
  1723. card->info.max_mtu = qeth_get_max_mtu_for_card(card->info.type);
  1724. card->qdio.in_buf_size = QETH_IN_BUF_SIZE_DEFAULT;
  1725. }
  1726. memcpy(&len, QETH_ULP_ENABLE_RESP_DIFINFO_LEN(iob->data), 2);
  1727. if (len >= QETH_MPC_DIFINFO_LEN_INDICATES_LINK_TYPE) {
  1728. memcpy(&link_type,
  1729. QETH_ULP_ENABLE_RESP_LINK_TYPE(iob->data), 1);
  1730. card->info.link_type = link_type;
  1731. } else
  1732. card->info.link_type = 0;
  1733. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  1734. return 0;
  1735. }
  1736. static int qeth_ulp_enable(struct qeth_card *card)
  1737. {
  1738. int rc;
  1739. char prot_type;
  1740. struct qeth_cmd_buffer *iob;
  1741. /*FIXME: trace view callbacks*/
  1742. QETH_DBF_TEXT(SETUP, 2, "ulpenabl");
  1743. iob = qeth_wait_for_buffer(&card->write);
  1744. memcpy(iob->data, ULP_ENABLE, ULP_ENABLE_SIZE);
  1745. *(QETH_ULP_ENABLE_LINKNUM(iob->data)) =
  1746. (__u8) card->info.portno;
  1747. if (card->options.layer2)
  1748. if (card->info.type == QETH_CARD_TYPE_OSN)
  1749. prot_type = QETH_PROT_OSN2;
  1750. else
  1751. prot_type = QETH_PROT_LAYER2;
  1752. else
  1753. prot_type = QETH_PROT_TCPIP;
  1754. memcpy(QETH_ULP_ENABLE_PROT_TYPE(iob->data), &prot_type, 1);
  1755. memcpy(QETH_ULP_ENABLE_DEST_ADDR(iob->data),
  1756. &card->token.cm_connection_r, QETH_MPC_TOKEN_LENGTH);
  1757. memcpy(QETH_ULP_ENABLE_FILTER_TOKEN(iob->data),
  1758. &card->token.ulp_filter_w, QETH_MPC_TOKEN_LENGTH);
  1759. memcpy(QETH_ULP_ENABLE_PORTNAME_AND_LL(iob->data),
  1760. card->info.portname, 9);
  1761. rc = qeth_send_control_data(card, ULP_ENABLE_SIZE, iob,
  1762. qeth_ulp_enable_cb, NULL);
  1763. return rc;
  1764. }
  1765. static int qeth_ulp_setup_cb(struct qeth_card *card, struct qeth_reply *reply,
  1766. unsigned long data)
  1767. {
  1768. struct qeth_cmd_buffer *iob;
  1769. QETH_DBF_TEXT(SETUP, 2, "ulpstpcb");
  1770. iob = (struct qeth_cmd_buffer *) data;
  1771. memcpy(&card->token.ulp_connection_r,
  1772. QETH_ULP_SETUP_RESP_CONNECTION_TOKEN(iob->data),
  1773. QETH_MPC_TOKEN_LENGTH);
  1774. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  1775. return 0;
  1776. }
  1777. static int qeth_ulp_setup(struct qeth_card *card)
  1778. {
  1779. int rc;
  1780. __u16 temp;
  1781. struct qeth_cmd_buffer *iob;
  1782. struct ccw_dev_id dev_id;
  1783. QETH_DBF_TEXT(SETUP, 2, "ulpsetup");
  1784. iob = qeth_wait_for_buffer(&card->write);
  1785. memcpy(iob->data, ULP_SETUP, ULP_SETUP_SIZE);
  1786. memcpy(QETH_ULP_SETUP_DEST_ADDR(iob->data),
  1787. &card->token.cm_connection_r, QETH_MPC_TOKEN_LENGTH);
  1788. memcpy(QETH_ULP_SETUP_CONNECTION_TOKEN(iob->data),
  1789. &card->token.ulp_connection_w, QETH_MPC_TOKEN_LENGTH);
  1790. memcpy(QETH_ULP_SETUP_FILTER_TOKEN(iob->data),
  1791. &card->token.ulp_filter_r, QETH_MPC_TOKEN_LENGTH);
  1792. ccw_device_get_id(CARD_DDEV(card), &dev_id);
  1793. memcpy(QETH_ULP_SETUP_CUA(iob->data), &dev_id.devno, 2);
  1794. temp = (card->info.cula << 8) + card->info.unit_addr2;
  1795. memcpy(QETH_ULP_SETUP_REAL_DEVADDR(iob->data), &temp, 2);
  1796. rc = qeth_send_control_data(card, ULP_SETUP_SIZE, iob,
  1797. qeth_ulp_setup_cb, NULL);
  1798. return rc;
  1799. }
  1800. static int qeth_alloc_qdio_buffers(struct qeth_card *card)
  1801. {
  1802. int i, j;
  1803. QETH_DBF_TEXT(SETUP, 2, "allcqdbf");
  1804. if (atomic_cmpxchg(&card->qdio.state, QETH_QDIO_UNINITIALIZED,
  1805. QETH_QDIO_ALLOCATED) != QETH_QDIO_UNINITIALIZED)
  1806. return 0;
  1807. card->qdio.in_q = kmalloc(sizeof(struct qeth_qdio_q),
  1808. GFP_KERNEL);
  1809. if (!card->qdio.in_q)
  1810. goto out_nomem;
  1811. QETH_DBF_TEXT(SETUP, 2, "inq");
  1812. QETH_DBF_HEX(SETUP, 2, &card->qdio.in_q, sizeof(void *));
  1813. memset(card->qdio.in_q, 0, sizeof(struct qeth_qdio_q));
  1814. /* give inbound qeth_qdio_buffers their qdio_buffers */
  1815. for (i = 0; i < QDIO_MAX_BUFFERS_PER_Q; ++i)
  1816. card->qdio.in_q->bufs[i].buffer =
  1817. &card->qdio.in_q->qdio_bufs[i];
  1818. /* inbound buffer pool */
  1819. if (qeth_alloc_buffer_pool(card))
  1820. goto out_freeinq;
  1821. /* outbound */
  1822. card->qdio.out_qs =
  1823. kmalloc(card->qdio.no_out_queues *
  1824. sizeof(struct qeth_qdio_out_q *), GFP_KERNEL);
  1825. if (!card->qdio.out_qs)
  1826. goto out_freepool;
  1827. for (i = 0; i < card->qdio.no_out_queues; ++i) {
  1828. card->qdio.out_qs[i] = kmalloc(sizeof(struct qeth_qdio_out_q),
  1829. GFP_KERNEL);
  1830. if (!card->qdio.out_qs[i])
  1831. goto out_freeoutq;
  1832. QETH_DBF_TEXT_(SETUP, 2, "outq %i", i);
  1833. QETH_DBF_HEX(SETUP, 2, &card->qdio.out_qs[i], sizeof(void *));
  1834. memset(card->qdio.out_qs[i], 0, sizeof(struct qeth_qdio_out_q));
  1835. card->qdio.out_qs[i]->queue_no = i;
  1836. /* give outbound qeth_qdio_buffers their qdio_buffers */
  1837. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j) {
  1838. card->qdio.out_qs[i]->bufs[j].buffer =
  1839. &card->qdio.out_qs[i]->qdio_bufs[j];
  1840. skb_queue_head_init(&card->qdio.out_qs[i]->bufs[j].
  1841. skb_list);
  1842. lockdep_set_class(
  1843. &card->qdio.out_qs[i]->bufs[j].skb_list.lock,
  1844. &qdio_out_skb_queue_key);
  1845. INIT_LIST_HEAD(&card->qdio.out_qs[i]->bufs[j].ctx_list);
  1846. }
  1847. }
  1848. return 0;
  1849. out_freeoutq:
  1850. while (i > 0)
  1851. kfree(card->qdio.out_qs[--i]);
  1852. kfree(card->qdio.out_qs);
  1853. card->qdio.out_qs = NULL;
  1854. out_freepool:
  1855. qeth_free_buffer_pool(card);
  1856. out_freeinq:
  1857. kfree(card->qdio.in_q);
  1858. card->qdio.in_q = NULL;
  1859. out_nomem:
  1860. atomic_set(&card->qdio.state, QETH_QDIO_UNINITIALIZED);
  1861. return -ENOMEM;
  1862. }
  1863. static void qeth_create_qib_param_field(struct qeth_card *card,
  1864. char *param_field)
  1865. {
  1866. param_field[0] = _ascebc['P'];
  1867. param_field[1] = _ascebc['C'];
  1868. param_field[2] = _ascebc['I'];
  1869. param_field[3] = _ascebc['T'];
  1870. *((unsigned int *) (&param_field[4])) = QETH_PCI_THRESHOLD_A(card);
  1871. *((unsigned int *) (&param_field[8])) = QETH_PCI_THRESHOLD_B(card);
  1872. *((unsigned int *) (&param_field[12])) = QETH_PCI_TIMER_VALUE(card);
  1873. }
  1874. static void qeth_create_qib_param_field_blkt(struct qeth_card *card,
  1875. char *param_field)
  1876. {
  1877. param_field[16] = _ascebc['B'];
  1878. param_field[17] = _ascebc['L'];
  1879. param_field[18] = _ascebc['K'];
  1880. param_field[19] = _ascebc['T'];
  1881. *((unsigned int *) (&param_field[20])) = card->info.blkt.time_total;
  1882. *((unsigned int *) (&param_field[24])) = card->info.blkt.inter_packet;
  1883. *((unsigned int *) (&param_field[28])) =
  1884. card->info.blkt.inter_packet_jumbo;
  1885. }
  1886. static int qeth_qdio_activate(struct qeth_card *card)
  1887. {
  1888. QETH_DBF_TEXT(SETUP, 3, "qdioact");
  1889. return qdio_activate(CARD_DDEV(card));
  1890. }
  1891. static int qeth_dm_act(struct qeth_card *card)
  1892. {
  1893. int rc;
  1894. struct qeth_cmd_buffer *iob;
  1895. QETH_DBF_TEXT(SETUP, 2, "dmact");
  1896. iob = qeth_wait_for_buffer(&card->write);
  1897. memcpy(iob->data, DM_ACT, DM_ACT_SIZE);
  1898. memcpy(QETH_DM_ACT_DEST_ADDR(iob->data),
  1899. &card->token.cm_connection_r, QETH_MPC_TOKEN_LENGTH);
  1900. memcpy(QETH_DM_ACT_CONNECTION_TOKEN(iob->data),
  1901. &card->token.ulp_connection_r, QETH_MPC_TOKEN_LENGTH);
  1902. rc = qeth_send_control_data(card, DM_ACT_SIZE, iob, NULL, NULL);
  1903. return rc;
  1904. }
  1905. static int qeth_mpc_initialize(struct qeth_card *card)
  1906. {
  1907. int rc;
  1908. QETH_DBF_TEXT(SETUP, 2, "mpcinit");
  1909. rc = qeth_issue_next_read(card);
  1910. if (rc) {
  1911. QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
  1912. return rc;
  1913. }
  1914. rc = qeth_cm_enable(card);
  1915. if (rc) {
  1916. QETH_DBF_TEXT_(SETUP, 2, "2err%d", rc);
  1917. goto out_qdio;
  1918. }
  1919. rc = qeth_cm_setup(card);
  1920. if (rc) {
  1921. QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
  1922. goto out_qdio;
  1923. }
  1924. rc = qeth_ulp_enable(card);
  1925. if (rc) {
  1926. QETH_DBF_TEXT_(SETUP, 2, "4err%d", rc);
  1927. goto out_qdio;
  1928. }
  1929. rc = qeth_ulp_setup(card);
  1930. if (rc) {
  1931. QETH_DBF_TEXT_(SETUP, 2, "5err%d", rc);
  1932. goto out_qdio;
  1933. }
  1934. rc = qeth_alloc_qdio_buffers(card);
  1935. if (rc) {
  1936. QETH_DBF_TEXT_(SETUP, 2, "5err%d", rc);
  1937. goto out_qdio;
  1938. }
  1939. rc = qeth_qdio_establish(card);
  1940. if (rc) {
  1941. QETH_DBF_TEXT_(SETUP, 2, "6err%d", rc);
  1942. qeth_free_qdio_buffers(card);
  1943. goto out_qdio;
  1944. }
  1945. rc = qeth_qdio_activate(card);
  1946. if (rc) {
  1947. QETH_DBF_TEXT_(SETUP, 2, "7err%d", rc);
  1948. goto out_qdio;
  1949. }
  1950. rc = qeth_dm_act(card);
  1951. if (rc) {
  1952. QETH_DBF_TEXT_(SETUP, 2, "8err%d", rc);
  1953. goto out_qdio;
  1954. }
  1955. return 0;
  1956. out_qdio:
  1957. qeth_qdio_clear_card(card, card->info.type != QETH_CARD_TYPE_IQD);
  1958. return rc;
  1959. }
  1960. static void qeth_print_status_with_portname(struct qeth_card *card)
  1961. {
  1962. char dbf_text[15];
  1963. int i;
  1964. sprintf(dbf_text, "%s", card->info.portname + 1);
  1965. for (i = 0; i < 8; i++)
  1966. dbf_text[i] =
  1967. (char) _ebcasc[(__u8) dbf_text[i]];
  1968. dbf_text[8] = 0;
  1969. dev_info(&card->gdev->dev, "Device is a%s card%s%s%s\n"
  1970. "with link type %s (portname: %s)\n",
  1971. qeth_get_cardname(card),
  1972. (card->info.mcl_level[0]) ? " (level: " : "",
  1973. (card->info.mcl_level[0]) ? card->info.mcl_level : "",
  1974. (card->info.mcl_level[0]) ? ")" : "",
  1975. qeth_get_cardname_short(card),
  1976. dbf_text);
  1977. }
  1978. static void qeth_print_status_no_portname(struct qeth_card *card)
  1979. {
  1980. if (card->info.portname[0])
  1981. dev_info(&card->gdev->dev, "Device is a%s "
  1982. "card%s%s%s\nwith link type %s "
  1983. "(no portname needed by interface).\n",
  1984. qeth_get_cardname(card),
  1985. (card->info.mcl_level[0]) ? " (level: " : "",
  1986. (card->info.mcl_level[0]) ? card->info.mcl_level : "",
  1987. (card->info.mcl_level[0]) ? ")" : "",
  1988. qeth_get_cardname_short(card));
  1989. else
  1990. dev_info(&card->gdev->dev, "Device is a%s "
  1991. "card%s%s%s\nwith link type %s.\n",
  1992. qeth_get_cardname(card),
  1993. (card->info.mcl_level[0]) ? " (level: " : "",
  1994. (card->info.mcl_level[0]) ? card->info.mcl_level : "",
  1995. (card->info.mcl_level[0]) ? ")" : "",
  1996. qeth_get_cardname_short(card));
  1997. }
  1998. void qeth_print_status_message(struct qeth_card *card)
  1999. {
  2000. switch (card->info.type) {
  2001. case QETH_CARD_TYPE_OSAE:
  2002. /* VM will use a non-zero first character
  2003. * to indicate a HiperSockets like reporting
  2004. * of the level OSA sets the first character to zero
  2005. * */
  2006. if (!card->info.mcl_level[0]) {
  2007. sprintf(card->info.mcl_level, "%02x%02x",
  2008. card->info.mcl_level[2],
  2009. card->info.mcl_level[3]);
  2010. card->info.mcl_level[QETH_MCL_LENGTH] = 0;
  2011. break;
  2012. }
  2013. /* fallthrough */
  2014. case QETH_CARD_TYPE_IQD:
  2015. if ((card->info.guestlan) ||
  2016. (card->info.mcl_level[0] & 0x80)) {
  2017. card->info.mcl_level[0] = (char) _ebcasc[(__u8)
  2018. card->info.mcl_level[0]];
  2019. card->info.mcl_level[1] = (char) _ebcasc[(__u8)
  2020. card->info.mcl_level[1]];
  2021. card->info.mcl_level[2] = (char) _ebcasc[(__u8)
  2022. card->info.mcl_level[2]];
  2023. card->info.mcl_level[3] = (char) _ebcasc[(__u8)
  2024. card->info.mcl_level[3]];
  2025. card->info.mcl_level[QETH_MCL_LENGTH] = 0;
  2026. }
  2027. break;
  2028. default:
  2029. memset(&card->info.mcl_level[0], 0, QETH_MCL_LENGTH + 1);
  2030. }
  2031. if (card->info.portname_required)
  2032. qeth_print_status_with_portname(card);
  2033. else
  2034. qeth_print_status_no_portname(card);
  2035. }
  2036. EXPORT_SYMBOL_GPL(qeth_print_status_message);
  2037. static void qeth_initialize_working_pool_list(struct qeth_card *card)
  2038. {
  2039. struct qeth_buffer_pool_entry *entry;
  2040. QETH_DBF_TEXT(TRACE, 5, "inwrklst");
  2041. list_for_each_entry(entry,
  2042. &card->qdio.init_pool.entry_list, init_list) {
  2043. qeth_put_buffer_pool_entry(card, entry);
  2044. }
  2045. }
  2046. static inline struct qeth_buffer_pool_entry *qeth_find_free_buffer_pool_entry(
  2047. struct qeth_card *card)
  2048. {
  2049. struct list_head *plh;
  2050. struct qeth_buffer_pool_entry *entry;
  2051. int i, free;
  2052. struct page *page;
  2053. if (list_empty(&card->qdio.in_buf_pool.entry_list))
  2054. return NULL;
  2055. list_for_each(plh, &card->qdio.in_buf_pool.entry_list) {
  2056. entry = list_entry(plh, struct qeth_buffer_pool_entry, list);
  2057. free = 1;
  2058. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i) {
  2059. if (page_count(virt_to_page(entry->elements[i])) > 1) {
  2060. free = 0;
  2061. break;
  2062. }
  2063. }
  2064. if (free) {
  2065. list_del_init(&entry->list);
  2066. return entry;
  2067. }
  2068. }
  2069. /* no free buffer in pool so take first one and swap pages */
  2070. entry = list_entry(card->qdio.in_buf_pool.entry_list.next,
  2071. struct qeth_buffer_pool_entry, list);
  2072. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i) {
  2073. if (page_count(virt_to_page(entry->elements[i])) > 1) {
  2074. page = alloc_page(GFP_ATOMIC);
  2075. if (!page) {
  2076. return NULL;
  2077. } else {
  2078. free_page((unsigned long)entry->elements[i]);
  2079. entry->elements[i] = page_address(page);
  2080. if (card->options.performance_stats)
  2081. card->perf_stats.sg_alloc_page_rx++;
  2082. }
  2083. }
  2084. }
  2085. list_del_init(&entry->list);
  2086. return entry;
  2087. }
  2088. static int qeth_init_input_buffer(struct qeth_card *card,
  2089. struct qeth_qdio_buffer *buf)
  2090. {
  2091. struct qeth_buffer_pool_entry *pool_entry;
  2092. int i;
  2093. pool_entry = qeth_find_free_buffer_pool_entry(card);
  2094. if (!pool_entry)
  2095. return 1;
  2096. /*
  2097. * since the buffer is accessed only from the input_tasklet
  2098. * there shouldn't be a need to synchronize; also, since we use
  2099. * the QETH_IN_BUF_REQUEUE_THRESHOLD we should never run out off
  2100. * buffers
  2101. */
  2102. buf->pool_entry = pool_entry;
  2103. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i) {
  2104. buf->buffer->element[i].length = PAGE_SIZE;
  2105. buf->buffer->element[i].addr = pool_entry->elements[i];
  2106. if (i == QETH_MAX_BUFFER_ELEMENTS(card) - 1)
  2107. buf->buffer->element[i].flags = SBAL_FLAGS_LAST_ENTRY;
  2108. else
  2109. buf->buffer->element[i].flags = 0;
  2110. }
  2111. return 0;
  2112. }
  2113. int qeth_init_qdio_queues(struct qeth_card *card)
  2114. {
  2115. int i, j;
  2116. int rc;
  2117. QETH_DBF_TEXT(SETUP, 2, "initqdqs");
  2118. /* inbound queue */
  2119. memset(card->qdio.in_q->qdio_bufs, 0,
  2120. QDIO_MAX_BUFFERS_PER_Q * sizeof(struct qdio_buffer));
  2121. qeth_initialize_working_pool_list(card);
  2122. /*give only as many buffers to hardware as we have buffer pool entries*/
  2123. for (i = 0; i < card->qdio.in_buf_pool.buf_count - 1; ++i)
  2124. qeth_init_input_buffer(card, &card->qdio.in_q->bufs[i]);
  2125. card->qdio.in_q->next_buf_to_init =
  2126. card->qdio.in_buf_pool.buf_count - 1;
  2127. rc = do_QDIO(CARD_DDEV(card), QDIO_FLAG_SYNC_INPUT, 0, 0,
  2128. card->qdio.in_buf_pool.buf_count - 1);
  2129. if (rc) {
  2130. QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
  2131. return rc;
  2132. }
  2133. /* outbound queue */
  2134. for (i = 0; i < card->qdio.no_out_queues; ++i) {
  2135. memset(card->qdio.out_qs[i]->qdio_bufs, 0,
  2136. QDIO_MAX_BUFFERS_PER_Q * sizeof(struct qdio_buffer));
  2137. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j) {
  2138. qeth_clear_output_buffer(card->qdio.out_qs[i],
  2139. &card->qdio.out_qs[i]->bufs[j]);
  2140. }
  2141. card->qdio.out_qs[i]->card = card;
  2142. card->qdio.out_qs[i]->next_buf_to_fill = 0;
  2143. card->qdio.out_qs[i]->do_pack = 0;
  2144. atomic_set(&card->qdio.out_qs[i]->used_buffers, 0);
  2145. atomic_set(&card->qdio.out_qs[i]->set_pci_flags_count, 0);
  2146. atomic_set(&card->qdio.out_qs[i]->state,
  2147. QETH_OUT_Q_UNLOCKED);
  2148. }
  2149. return 0;
  2150. }
  2151. EXPORT_SYMBOL_GPL(qeth_init_qdio_queues);
  2152. static inline __u8 qeth_get_ipa_adp_type(enum qeth_link_types link_type)
  2153. {
  2154. switch (link_type) {
  2155. case QETH_LINK_TYPE_HSTR:
  2156. return 2;
  2157. default:
  2158. return 1;
  2159. }
  2160. }
  2161. static void qeth_fill_ipacmd_header(struct qeth_card *card,
  2162. struct qeth_ipa_cmd *cmd, __u8 command,
  2163. enum qeth_prot_versions prot)
  2164. {
  2165. memset(cmd, 0, sizeof(struct qeth_ipa_cmd));
  2166. cmd->hdr.command = command;
  2167. cmd->hdr.initiator = IPA_CMD_INITIATOR_HOST;
  2168. cmd->hdr.seqno = card->seqno.ipa;
  2169. cmd->hdr.adapter_type = qeth_get_ipa_adp_type(card->info.link_type);
  2170. cmd->hdr.rel_adapter_no = (__u8) card->info.portno;
  2171. if (card->options.layer2)
  2172. cmd->hdr.prim_version_no = 2;
  2173. else
  2174. cmd->hdr.prim_version_no = 1;
  2175. cmd->hdr.param_count = 1;
  2176. cmd->hdr.prot_version = prot;
  2177. cmd->hdr.ipa_supported = 0;
  2178. cmd->hdr.ipa_enabled = 0;
  2179. }
  2180. struct qeth_cmd_buffer *qeth_get_ipacmd_buffer(struct qeth_card *card,
  2181. enum qeth_ipa_cmds ipacmd, enum qeth_prot_versions prot)
  2182. {
  2183. struct qeth_cmd_buffer *iob;
  2184. struct qeth_ipa_cmd *cmd;
  2185. iob = qeth_wait_for_buffer(&card->write);
  2186. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  2187. qeth_fill_ipacmd_header(card, cmd, ipacmd, prot);
  2188. return iob;
  2189. }
  2190. EXPORT_SYMBOL_GPL(qeth_get_ipacmd_buffer);
  2191. void qeth_prepare_ipa_cmd(struct qeth_card *card, struct qeth_cmd_buffer *iob,
  2192. char prot_type)
  2193. {
  2194. memcpy(iob->data, IPA_PDU_HEADER, IPA_PDU_HEADER_SIZE);
  2195. memcpy(QETH_IPA_CMD_PROT_TYPE(iob->data), &prot_type, 1);
  2196. memcpy(QETH_IPA_CMD_DEST_ADDR(iob->data),
  2197. &card->token.ulp_connection_r, QETH_MPC_TOKEN_LENGTH);
  2198. }
  2199. EXPORT_SYMBOL_GPL(qeth_prepare_ipa_cmd);
  2200. int qeth_send_ipa_cmd(struct qeth_card *card, struct qeth_cmd_buffer *iob,
  2201. int (*reply_cb)(struct qeth_card *, struct qeth_reply*,
  2202. unsigned long),
  2203. void *reply_param)
  2204. {
  2205. int rc;
  2206. char prot_type;
  2207. QETH_DBF_TEXT(TRACE, 4, "sendipa");
  2208. if (card->options.layer2)
  2209. if (card->info.type == QETH_CARD_TYPE_OSN)
  2210. prot_type = QETH_PROT_OSN2;
  2211. else
  2212. prot_type = QETH_PROT_LAYER2;
  2213. else
  2214. prot_type = QETH_PROT_TCPIP;
  2215. qeth_prepare_ipa_cmd(card, iob, prot_type);
  2216. rc = qeth_send_control_data(card, IPA_CMD_LENGTH,
  2217. iob, reply_cb, reply_param);
  2218. return rc;
  2219. }
  2220. EXPORT_SYMBOL_GPL(qeth_send_ipa_cmd);
  2221. static int qeth_send_startstoplan(struct qeth_card *card,
  2222. enum qeth_ipa_cmds ipacmd, enum qeth_prot_versions prot)
  2223. {
  2224. int rc;
  2225. struct qeth_cmd_buffer *iob;
  2226. iob = qeth_get_ipacmd_buffer(card, ipacmd, prot);
  2227. rc = qeth_send_ipa_cmd(card, iob, NULL, NULL);
  2228. return rc;
  2229. }
  2230. int qeth_send_startlan(struct qeth_card *card)
  2231. {
  2232. int rc;
  2233. QETH_DBF_TEXT(SETUP, 2, "strtlan");
  2234. rc = qeth_send_startstoplan(card, IPA_CMD_STARTLAN, 0);
  2235. return rc;
  2236. }
  2237. EXPORT_SYMBOL_GPL(qeth_send_startlan);
  2238. int qeth_send_stoplan(struct qeth_card *card)
  2239. {
  2240. int rc = 0;
  2241. /*
  2242. * TODO: according to the IPA format document page 14,
  2243. * TCP/IP (we!) never issue a STOPLAN
  2244. * is this right ?!?
  2245. */
  2246. QETH_DBF_TEXT(SETUP, 2, "stoplan");
  2247. rc = qeth_send_startstoplan(card, IPA_CMD_STOPLAN, 0);
  2248. return rc;
  2249. }
  2250. EXPORT_SYMBOL_GPL(qeth_send_stoplan);
  2251. int qeth_default_setadapterparms_cb(struct qeth_card *card,
  2252. struct qeth_reply *reply, unsigned long data)
  2253. {
  2254. struct qeth_ipa_cmd *cmd;
  2255. QETH_DBF_TEXT(TRACE, 4, "defadpcb");
  2256. cmd = (struct qeth_ipa_cmd *) data;
  2257. if (cmd->hdr.return_code == 0)
  2258. cmd->hdr.return_code =
  2259. cmd->data.setadapterparms.hdr.return_code;
  2260. return 0;
  2261. }
  2262. EXPORT_SYMBOL_GPL(qeth_default_setadapterparms_cb);
  2263. static int qeth_query_setadapterparms_cb(struct qeth_card *card,
  2264. struct qeth_reply *reply, unsigned long data)
  2265. {
  2266. struct qeth_ipa_cmd *cmd;
  2267. QETH_DBF_TEXT(TRACE, 3, "quyadpcb");
  2268. cmd = (struct qeth_ipa_cmd *) data;
  2269. if (cmd->data.setadapterparms.data.query_cmds_supp.lan_type & 0x7f)
  2270. card->info.link_type =
  2271. cmd->data.setadapterparms.data.query_cmds_supp.lan_type;
  2272. card->options.adp.supported_funcs =
  2273. cmd->data.setadapterparms.data.query_cmds_supp.supported_cmds;
  2274. return qeth_default_setadapterparms_cb(card, reply, (unsigned long)cmd);
  2275. }
  2276. struct qeth_cmd_buffer *qeth_get_adapter_cmd(struct qeth_card *card,
  2277. __u32 command, __u32 cmdlen)
  2278. {
  2279. struct qeth_cmd_buffer *iob;
  2280. struct qeth_ipa_cmd *cmd;
  2281. iob = qeth_get_ipacmd_buffer(card, IPA_CMD_SETADAPTERPARMS,
  2282. QETH_PROT_IPV4);
  2283. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  2284. cmd->data.setadapterparms.hdr.cmdlength = cmdlen;
  2285. cmd->data.setadapterparms.hdr.command_code = command;
  2286. cmd->data.setadapterparms.hdr.used_total = 1;
  2287. cmd->data.setadapterparms.hdr.seq_no = 1;
  2288. return iob;
  2289. }
  2290. EXPORT_SYMBOL_GPL(qeth_get_adapter_cmd);
  2291. int qeth_query_setadapterparms(struct qeth_card *card)
  2292. {
  2293. int rc;
  2294. struct qeth_cmd_buffer *iob;
  2295. QETH_DBF_TEXT(TRACE, 3, "queryadp");
  2296. iob = qeth_get_adapter_cmd(card, IPA_SETADP_QUERY_COMMANDS_SUPPORTED,
  2297. sizeof(struct qeth_ipacmd_setadpparms));
  2298. rc = qeth_send_ipa_cmd(card, iob, qeth_query_setadapterparms_cb, NULL);
  2299. return rc;
  2300. }
  2301. EXPORT_SYMBOL_GPL(qeth_query_setadapterparms);
  2302. int qeth_check_qdio_errors(struct qeth_card *card, struct qdio_buffer *buf,
  2303. unsigned int qdio_error, const char *dbftext)
  2304. {
  2305. if (qdio_error) {
  2306. QETH_DBF_TEXT(TRACE, 2, dbftext);
  2307. QETH_DBF_TEXT(QERR, 2, dbftext);
  2308. QETH_DBF_TEXT_(QERR, 2, " F15=%02X",
  2309. buf->element[15].flags & 0xff);
  2310. QETH_DBF_TEXT_(QERR, 2, " F14=%02X",
  2311. buf->element[14].flags & 0xff);
  2312. QETH_DBF_TEXT_(QERR, 2, " qerr=%X", qdio_error);
  2313. if ((buf->element[15].flags & 0xff) == 0x12) {
  2314. card->stats.rx_dropped++;
  2315. return 0;
  2316. } else
  2317. return 1;
  2318. }
  2319. return 0;
  2320. }
  2321. EXPORT_SYMBOL_GPL(qeth_check_qdio_errors);
  2322. void qeth_queue_input_buffer(struct qeth_card *card, int index)
  2323. {
  2324. struct qeth_qdio_q *queue = card->qdio.in_q;
  2325. int count;
  2326. int i;
  2327. int rc;
  2328. int newcount = 0;
  2329. count = (index < queue->next_buf_to_init)?
  2330. card->qdio.in_buf_pool.buf_count -
  2331. (queue->next_buf_to_init - index) :
  2332. card->qdio.in_buf_pool.buf_count -
  2333. (queue->next_buf_to_init + QDIO_MAX_BUFFERS_PER_Q - index);
  2334. /* only requeue at a certain threshold to avoid SIGAs */
  2335. if (count >= QETH_IN_BUF_REQUEUE_THRESHOLD(card)) {
  2336. for (i = queue->next_buf_to_init;
  2337. i < queue->next_buf_to_init + count; ++i) {
  2338. if (qeth_init_input_buffer(card,
  2339. &queue->bufs[i % QDIO_MAX_BUFFERS_PER_Q])) {
  2340. break;
  2341. } else {
  2342. newcount++;
  2343. }
  2344. }
  2345. if (newcount < count) {
  2346. /* we are in memory shortage so we switch back to
  2347. traditional skb allocation and drop packages */
  2348. atomic_set(&card->force_alloc_skb, 3);
  2349. count = newcount;
  2350. } else {
  2351. atomic_add_unless(&card->force_alloc_skb, -1, 0);
  2352. }
  2353. /*
  2354. * according to old code it should be avoided to requeue all
  2355. * 128 buffers in order to benefit from PCI avoidance.
  2356. * this function keeps at least one buffer (the buffer at
  2357. * 'index') un-requeued -> this buffer is the first buffer that
  2358. * will be requeued the next time
  2359. */
  2360. if (card->options.performance_stats) {
  2361. card->perf_stats.inbound_do_qdio_cnt++;
  2362. card->perf_stats.inbound_do_qdio_start_time =
  2363. qeth_get_micros();
  2364. }
  2365. rc = do_QDIO(CARD_DDEV(card), QDIO_FLAG_SYNC_INPUT, 0,
  2366. queue->next_buf_to_init, count);
  2367. if (card->options.performance_stats)
  2368. card->perf_stats.inbound_do_qdio_time +=
  2369. qeth_get_micros() -
  2370. card->perf_stats.inbound_do_qdio_start_time;
  2371. if (rc) {
  2372. dev_warn(&card->gdev->dev,
  2373. "QDIO reported an error, rc=%i\n", rc);
  2374. QETH_DBF_TEXT(TRACE, 2, "qinberr");
  2375. QETH_DBF_TEXT_(TRACE, 2, "%s", CARD_BUS_ID(card));
  2376. }
  2377. queue->next_buf_to_init = (queue->next_buf_to_init + count) %
  2378. QDIO_MAX_BUFFERS_PER_Q;
  2379. }
  2380. }
  2381. EXPORT_SYMBOL_GPL(qeth_queue_input_buffer);
  2382. static int qeth_handle_send_error(struct qeth_card *card,
  2383. struct qeth_qdio_out_buffer *buffer, unsigned int qdio_err)
  2384. {
  2385. int sbalf15 = buffer->buffer->element[15].flags & 0xff;
  2386. QETH_DBF_TEXT(TRACE, 6, "hdsnderr");
  2387. if (card->info.type == QETH_CARD_TYPE_IQD) {
  2388. if (sbalf15 == 0) {
  2389. qdio_err = 0;
  2390. } else {
  2391. qdio_err = 1;
  2392. }
  2393. }
  2394. qeth_check_qdio_errors(card, buffer->buffer, qdio_err, "qouterr");
  2395. if (!qdio_err)
  2396. return QETH_SEND_ERROR_NONE;
  2397. if ((sbalf15 >= 15) && (sbalf15 <= 31))
  2398. return QETH_SEND_ERROR_RETRY;
  2399. QETH_DBF_TEXT(TRACE, 1, "lnkfail");
  2400. QETH_DBF_TEXT_(TRACE, 1, "%s", CARD_BUS_ID(card));
  2401. QETH_DBF_TEXT_(TRACE, 1, "%04x %02x",
  2402. (u16)qdio_err, (u8)sbalf15);
  2403. return QETH_SEND_ERROR_LINK_FAILURE;
  2404. }
  2405. /*
  2406. * Switched to packing state if the number of used buffers on a queue
  2407. * reaches a certain limit.
  2408. */
  2409. static void qeth_switch_to_packing_if_needed(struct qeth_qdio_out_q *queue)
  2410. {
  2411. if (!queue->do_pack) {
  2412. if (atomic_read(&queue->used_buffers)
  2413. >= QETH_HIGH_WATERMARK_PACK){
  2414. /* switch non-PACKING -> PACKING */
  2415. QETH_DBF_TEXT(TRACE, 6, "np->pack");
  2416. if (queue->card->options.performance_stats)
  2417. queue->card->perf_stats.sc_dp_p++;
  2418. queue->do_pack = 1;
  2419. }
  2420. }
  2421. }
  2422. /*
  2423. * Switches from packing to non-packing mode. If there is a packing
  2424. * buffer on the queue this buffer will be prepared to be flushed.
  2425. * In that case 1 is returned to inform the caller. If no buffer
  2426. * has to be flushed, zero is returned.
  2427. */
  2428. static int qeth_switch_to_nonpacking_if_needed(struct qeth_qdio_out_q *queue)
  2429. {
  2430. struct qeth_qdio_out_buffer *buffer;
  2431. int flush_count = 0;
  2432. if (queue->do_pack) {
  2433. if (atomic_read(&queue->used_buffers)
  2434. <= QETH_LOW_WATERMARK_PACK) {
  2435. /* switch PACKING -> non-PACKING */
  2436. QETH_DBF_TEXT(TRACE, 6, "pack->np");
  2437. if (queue->card->options.performance_stats)
  2438. queue->card->perf_stats.sc_p_dp++;
  2439. queue->do_pack = 0;
  2440. /* flush packing buffers */
  2441. buffer = &queue->bufs[queue->next_buf_to_fill];
  2442. if ((atomic_read(&buffer->state) ==
  2443. QETH_QDIO_BUF_EMPTY) &&
  2444. (buffer->next_element_to_fill > 0)) {
  2445. atomic_set(&buffer->state,
  2446. QETH_QDIO_BUF_PRIMED);
  2447. flush_count++;
  2448. queue->next_buf_to_fill =
  2449. (queue->next_buf_to_fill + 1) %
  2450. QDIO_MAX_BUFFERS_PER_Q;
  2451. }
  2452. }
  2453. }
  2454. return flush_count;
  2455. }
  2456. /*
  2457. * Called to flush a packing buffer if no more pci flags are on the queue.
  2458. * Checks if there is a packing buffer and prepares it to be flushed.
  2459. * In that case returns 1, otherwise zero.
  2460. */
  2461. static int qeth_flush_buffers_on_no_pci(struct qeth_qdio_out_q *queue)
  2462. {
  2463. struct qeth_qdio_out_buffer *buffer;
  2464. buffer = &queue->bufs[queue->next_buf_to_fill];
  2465. if ((atomic_read(&buffer->state) == QETH_QDIO_BUF_EMPTY) &&
  2466. (buffer->next_element_to_fill > 0)) {
  2467. /* it's a packing buffer */
  2468. atomic_set(&buffer->state, QETH_QDIO_BUF_PRIMED);
  2469. queue->next_buf_to_fill =
  2470. (queue->next_buf_to_fill + 1) % QDIO_MAX_BUFFERS_PER_Q;
  2471. return 1;
  2472. }
  2473. return 0;
  2474. }
  2475. static void qeth_flush_buffers(struct qeth_qdio_out_q *queue, int index,
  2476. int count)
  2477. {
  2478. struct qeth_qdio_out_buffer *buf;
  2479. int rc;
  2480. int i;
  2481. unsigned int qdio_flags;
  2482. for (i = index; i < index + count; ++i) {
  2483. buf = &queue->bufs[i % QDIO_MAX_BUFFERS_PER_Q];
  2484. buf->buffer->element[buf->next_element_to_fill - 1].flags |=
  2485. SBAL_FLAGS_LAST_ENTRY;
  2486. if (queue->card->info.type == QETH_CARD_TYPE_IQD)
  2487. continue;
  2488. if (!queue->do_pack) {
  2489. if ((atomic_read(&queue->used_buffers) >=
  2490. (QETH_HIGH_WATERMARK_PACK -
  2491. QETH_WATERMARK_PACK_FUZZ)) &&
  2492. !atomic_read(&queue->set_pci_flags_count)) {
  2493. /* it's likely that we'll go to packing
  2494. * mode soon */
  2495. atomic_inc(&queue->set_pci_flags_count);
  2496. buf->buffer->element[0].flags |= 0x40;
  2497. }
  2498. } else {
  2499. if (!atomic_read(&queue->set_pci_flags_count)) {
  2500. /*
  2501. * there's no outstanding PCI any more, so we
  2502. * have to request a PCI to be sure the the PCI
  2503. * will wake at some time in the future then we
  2504. * can flush packed buffers that might still be
  2505. * hanging around, which can happen if no
  2506. * further send was requested by the stack
  2507. */
  2508. atomic_inc(&queue->set_pci_flags_count);
  2509. buf->buffer->element[0].flags |= 0x40;
  2510. }
  2511. }
  2512. }
  2513. queue->sync_iqdio_error = 0;
  2514. queue->card->dev->trans_start = jiffies;
  2515. if (queue->card->options.performance_stats) {
  2516. queue->card->perf_stats.outbound_do_qdio_cnt++;
  2517. queue->card->perf_stats.outbound_do_qdio_start_time =
  2518. qeth_get_micros();
  2519. }
  2520. qdio_flags = QDIO_FLAG_SYNC_OUTPUT;
  2521. if (atomic_read(&queue->set_pci_flags_count))
  2522. qdio_flags |= QDIO_FLAG_PCI_OUT;
  2523. rc = do_QDIO(CARD_DDEV(queue->card), qdio_flags,
  2524. queue->queue_no, index, count);
  2525. if (queue->card->options.performance_stats)
  2526. queue->card->perf_stats.outbound_do_qdio_time +=
  2527. qeth_get_micros() -
  2528. queue->card->perf_stats.outbound_do_qdio_start_time;
  2529. if (rc > 0) {
  2530. if (!(rc & QDIO_ERROR_SIGA_BUSY))
  2531. queue->sync_iqdio_error = rc & 3;
  2532. }
  2533. if (rc) {
  2534. queue->card->stats.tx_errors += count;
  2535. /* ignore temporary SIGA errors without busy condition */
  2536. if (rc == QDIO_ERROR_SIGA_TARGET)
  2537. return;
  2538. QETH_DBF_TEXT(TRACE, 2, "flushbuf");
  2539. QETH_DBF_TEXT_(TRACE, 2, " err%d", rc);
  2540. QETH_DBF_TEXT_(TRACE, 2, "%s", CARD_DDEV_ID(queue->card));
  2541. /* this must not happen under normal circumstances. if it
  2542. * happens something is really wrong -> recover */
  2543. qeth_schedule_recovery(queue->card);
  2544. return;
  2545. }
  2546. atomic_add(count, &queue->used_buffers);
  2547. if (queue->card->options.performance_stats)
  2548. queue->card->perf_stats.bufs_sent += count;
  2549. }
  2550. static void qeth_check_outbound_queue(struct qeth_qdio_out_q *queue)
  2551. {
  2552. int index;
  2553. int flush_cnt = 0;
  2554. int q_was_packing = 0;
  2555. /*
  2556. * check if weed have to switch to non-packing mode or if
  2557. * we have to get a pci flag out on the queue
  2558. */
  2559. if ((atomic_read(&queue->used_buffers) <= QETH_LOW_WATERMARK_PACK) ||
  2560. !atomic_read(&queue->set_pci_flags_count)) {
  2561. if (atomic_xchg(&queue->state, QETH_OUT_Q_LOCKED_FLUSH) ==
  2562. QETH_OUT_Q_UNLOCKED) {
  2563. /*
  2564. * If we get in here, there was no action in
  2565. * do_send_packet. So, we check if there is a
  2566. * packing buffer to be flushed here.
  2567. */
  2568. netif_stop_queue(queue->card->dev);
  2569. index = queue->next_buf_to_fill;
  2570. q_was_packing = queue->do_pack;
  2571. /* queue->do_pack may change */
  2572. barrier();
  2573. flush_cnt += qeth_switch_to_nonpacking_if_needed(queue);
  2574. if (!flush_cnt &&
  2575. !atomic_read(&queue->set_pci_flags_count))
  2576. flush_cnt +=
  2577. qeth_flush_buffers_on_no_pci(queue);
  2578. if (queue->card->options.performance_stats &&
  2579. q_was_packing)
  2580. queue->card->perf_stats.bufs_sent_pack +=
  2581. flush_cnt;
  2582. if (flush_cnt)
  2583. qeth_flush_buffers(queue, index, flush_cnt);
  2584. atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED);
  2585. }
  2586. }
  2587. }
  2588. void qeth_qdio_output_handler(struct ccw_device *ccwdev,
  2589. unsigned int qdio_error, int __queue, int first_element,
  2590. int count, unsigned long card_ptr)
  2591. {
  2592. struct qeth_card *card = (struct qeth_card *) card_ptr;
  2593. struct qeth_qdio_out_q *queue = card->qdio.out_qs[__queue];
  2594. struct qeth_qdio_out_buffer *buffer;
  2595. int i;
  2596. unsigned qeth_send_err;
  2597. QETH_DBF_TEXT(TRACE, 6, "qdouhdl");
  2598. if (qdio_error & QDIO_ERROR_ACTIVATE_CHECK_CONDITION) {
  2599. QETH_DBF_TEXT(TRACE, 2, "achkcond");
  2600. QETH_DBF_TEXT_(TRACE, 2, "%s", CARD_BUS_ID(card));
  2601. netif_stop_queue(card->dev);
  2602. qeth_schedule_recovery(card);
  2603. return;
  2604. }
  2605. if (card->options.performance_stats) {
  2606. card->perf_stats.outbound_handler_cnt++;
  2607. card->perf_stats.outbound_handler_start_time =
  2608. qeth_get_micros();
  2609. }
  2610. for (i = first_element; i < (first_element + count); ++i) {
  2611. buffer = &queue->bufs[i % QDIO_MAX_BUFFERS_PER_Q];
  2612. qeth_send_err = qeth_handle_send_error(card, buffer, qdio_error);
  2613. __qeth_clear_output_buffer(queue, buffer,
  2614. (qeth_send_err == QETH_SEND_ERROR_RETRY) ? 1 : 0);
  2615. }
  2616. atomic_sub(count, &queue->used_buffers);
  2617. /* check if we need to do something on this outbound queue */
  2618. if (card->info.type != QETH_CARD_TYPE_IQD)
  2619. qeth_check_outbound_queue(queue);
  2620. netif_wake_queue(queue->card->dev);
  2621. if (card->options.performance_stats)
  2622. card->perf_stats.outbound_handler_time += qeth_get_micros() -
  2623. card->perf_stats.outbound_handler_start_time;
  2624. }
  2625. EXPORT_SYMBOL_GPL(qeth_qdio_output_handler);
  2626. int qeth_get_priority_queue(struct qeth_card *card, struct sk_buff *skb,
  2627. int ipv, int cast_type)
  2628. {
  2629. if (!ipv && (card->info.type == QETH_CARD_TYPE_OSAE))
  2630. return card->qdio.default_out_queue;
  2631. switch (card->qdio.no_out_queues) {
  2632. case 4:
  2633. if (cast_type && card->info.is_multicast_different)
  2634. return card->info.is_multicast_different &
  2635. (card->qdio.no_out_queues - 1);
  2636. if (card->qdio.do_prio_queueing && (ipv == 4)) {
  2637. const u8 tos = ip_hdr(skb)->tos;
  2638. if (card->qdio.do_prio_queueing ==
  2639. QETH_PRIO_Q_ING_TOS) {
  2640. if (tos & IP_TOS_NOTIMPORTANT)
  2641. return 3;
  2642. if (tos & IP_TOS_HIGHRELIABILITY)
  2643. return 2;
  2644. if (tos & IP_TOS_HIGHTHROUGHPUT)
  2645. return 1;
  2646. if (tos & IP_TOS_LOWDELAY)
  2647. return 0;
  2648. }
  2649. if (card->qdio.do_prio_queueing ==
  2650. QETH_PRIO_Q_ING_PREC)
  2651. return 3 - (tos >> 6);
  2652. } else if (card->qdio.do_prio_queueing && (ipv == 6)) {
  2653. /* TODO: IPv6!!! */
  2654. }
  2655. return card->qdio.default_out_queue;
  2656. case 1: /* fallthrough for single-out-queue 1920-device */
  2657. default:
  2658. return card->qdio.default_out_queue;
  2659. }
  2660. }
  2661. EXPORT_SYMBOL_GPL(qeth_get_priority_queue);
  2662. int qeth_get_elements_no(struct qeth_card *card, void *hdr,
  2663. struct sk_buff *skb, int elems)
  2664. {
  2665. int elements_needed = 0;
  2666. if (skb_shinfo(skb)->nr_frags > 0)
  2667. elements_needed = (skb_shinfo(skb)->nr_frags + 1);
  2668. if (elements_needed == 0)
  2669. elements_needed = 1 + (((((unsigned long) skb->data) %
  2670. PAGE_SIZE) + skb->len) >> PAGE_SHIFT);
  2671. if ((elements_needed + elems) > QETH_MAX_BUFFER_ELEMENTS(card)) {
  2672. QETH_DBF_MESSAGE(2, "Invalid size of IP packet "
  2673. "(Number=%d / Length=%d). Discarded.\n",
  2674. (elements_needed+elems), skb->len);
  2675. return 0;
  2676. }
  2677. return elements_needed;
  2678. }
  2679. EXPORT_SYMBOL_GPL(qeth_get_elements_no);
  2680. static inline void __qeth_fill_buffer(struct sk_buff *skb,
  2681. struct qdio_buffer *buffer, int is_tso, int *next_element_to_fill,
  2682. int offset)
  2683. {
  2684. int length = skb->len;
  2685. int length_here;
  2686. int element;
  2687. char *data;
  2688. int first_lap ;
  2689. element = *next_element_to_fill;
  2690. data = skb->data;
  2691. first_lap = (is_tso == 0 ? 1 : 0);
  2692. if (offset >= 0) {
  2693. data = skb->data + offset;
  2694. length -= offset;
  2695. first_lap = 0;
  2696. }
  2697. while (length > 0) {
  2698. /* length_here is the remaining amount of data in this page */
  2699. length_here = PAGE_SIZE - ((unsigned long) data % PAGE_SIZE);
  2700. if (length < length_here)
  2701. length_here = length;
  2702. buffer->element[element].addr = data;
  2703. buffer->element[element].length = length_here;
  2704. length -= length_here;
  2705. if (!length) {
  2706. if (first_lap)
  2707. buffer->element[element].flags = 0;
  2708. else
  2709. buffer->element[element].flags =
  2710. SBAL_FLAGS_LAST_FRAG;
  2711. } else {
  2712. if (first_lap)
  2713. buffer->element[element].flags =
  2714. SBAL_FLAGS_FIRST_FRAG;
  2715. else
  2716. buffer->element[element].flags =
  2717. SBAL_FLAGS_MIDDLE_FRAG;
  2718. }
  2719. data += length_here;
  2720. element++;
  2721. first_lap = 0;
  2722. }
  2723. *next_element_to_fill = element;
  2724. }
  2725. static inline int qeth_fill_buffer(struct qeth_qdio_out_q *queue,
  2726. struct qeth_qdio_out_buffer *buf, struct sk_buff *skb,
  2727. struct qeth_hdr *hdr, int offset, int hd_len)
  2728. {
  2729. struct qdio_buffer *buffer;
  2730. int flush_cnt = 0, hdr_len, large_send = 0;
  2731. buffer = buf->buffer;
  2732. atomic_inc(&skb->users);
  2733. skb_queue_tail(&buf->skb_list, skb);
  2734. /*check first on TSO ....*/
  2735. if (hdr->hdr.l3.id == QETH_HEADER_TYPE_TSO) {
  2736. int element = buf->next_element_to_fill;
  2737. hdr_len = sizeof(struct qeth_hdr_tso) +
  2738. ((struct qeth_hdr_tso *)hdr)->ext.dg_hdr_len;
  2739. /*fill first buffer entry only with header information */
  2740. buffer->element[element].addr = skb->data;
  2741. buffer->element[element].length = hdr_len;
  2742. buffer->element[element].flags = SBAL_FLAGS_FIRST_FRAG;
  2743. buf->next_element_to_fill++;
  2744. skb->data += hdr_len;
  2745. skb->len -= hdr_len;
  2746. large_send = 1;
  2747. }
  2748. if (offset >= 0) {
  2749. int element = buf->next_element_to_fill;
  2750. buffer->element[element].addr = hdr;
  2751. buffer->element[element].length = sizeof(struct qeth_hdr) +
  2752. hd_len;
  2753. buffer->element[element].flags = SBAL_FLAGS_FIRST_FRAG;
  2754. buf->is_header[element] = 1;
  2755. buf->next_element_to_fill++;
  2756. }
  2757. if (skb_shinfo(skb)->nr_frags == 0)
  2758. __qeth_fill_buffer(skb, buffer, large_send,
  2759. (int *)&buf->next_element_to_fill, offset);
  2760. else
  2761. __qeth_fill_buffer_frag(skb, buffer, large_send,
  2762. (int *)&buf->next_element_to_fill);
  2763. if (!queue->do_pack) {
  2764. QETH_DBF_TEXT(TRACE, 6, "fillbfnp");
  2765. /* set state to PRIMED -> will be flushed */
  2766. atomic_set(&buf->state, QETH_QDIO_BUF_PRIMED);
  2767. flush_cnt = 1;
  2768. } else {
  2769. QETH_DBF_TEXT(TRACE, 6, "fillbfpa");
  2770. if (queue->card->options.performance_stats)
  2771. queue->card->perf_stats.skbs_sent_pack++;
  2772. if (buf->next_element_to_fill >=
  2773. QETH_MAX_BUFFER_ELEMENTS(queue->card)) {
  2774. /*
  2775. * packed buffer if full -> set state PRIMED
  2776. * -> will be flushed
  2777. */
  2778. atomic_set(&buf->state, QETH_QDIO_BUF_PRIMED);
  2779. flush_cnt = 1;
  2780. }
  2781. }
  2782. return flush_cnt;
  2783. }
  2784. int qeth_do_send_packet_fast(struct qeth_card *card,
  2785. struct qeth_qdio_out_q *queue, struct sk_buff *skb,
  2786. struct qeth_hdr *hdr, int elements_needed,
  2787. int offset, int hd_len)
  2788. {
  2789. struct qeth_qdio_out_buffer *buffer;
  2790. struct sk_buff *skb1;
  2791. struct qeth_skb_data *retry_ctrl;
  2792. int index;
  2793. int rc;
  2794. /* spin until we get the queue ... */
  2795. while (atomic_cmpxchg(&queue->state, QETH_OUT_Q_UNLOCKED,
  2796. QETH_OUT_Q_LOCKED) != QETH_OUT_Q_UNLOCKED);
  2797. /* ... now we've got the queue */
  2798. index = queue->next_buf_to_fill;
  2799. buffer = &queue->bufs[queue->next_buf_to_fill];
  2800. /*
  2801. * check if buffer is empty to make sure that we do not 'overtake'
  2802. * ourselves and try to fill a buffer that is already primed
  2803. */
  2804. if (atomic_read(&buffer->state) != QETH_QDIO_BUF_EMPTY)
  2805. goto out;
  2806. queue->next_buf_to_fill = (queue->next_buf_to_fill + 1) %
  2807. QDIO_MAX_BUFFERS_PER_Q;
  2808. atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED);
  2809. qeth_fill_buffer(queue, buffer, skb, hdr, offset, hd_len);
  2810. qeth_flush_buffers(queue, index, 1);
  2811. if (queue->sync_iqdio_error == 2) {
  2812. skb1 = skb_dequeue(&buffer->skb_list);
  2813. while (skb1) {
  2814. atomic_dec(&skb1->users);
  2815. skb1 = skb_dequeue(&buffer->skb_list);
  2816. }
  2817. retry_ctrl = (struct qeth_skb_data *) &skb->cb[16];
  2818. if (retry_ctrl->magic != QETH_SKB_MAGIC) {
  2819. retry_ctrl->magic = QETH_SKB_MAGIC;
  2820. retry_ctrl->count = 0;
  2821. }
  2822. if (retry_ctrl->count < QETH_SIGA_CC2_RETRIES) {
  2823. retry_ctrl->count++;
  2824. rc = dev_queue_xmit(skb);
  2825. } else {
  2826. dev_kfree_skb_any(skb);
  2827. QETH_DBF_TEXT(QERR, 2, "qrdrop");
  2828. }
  2829. }
  2830. return 0;
  2831. out:
  2832. atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED);
  2833. return -EBUSY;
  2834. }
  2835. EXPORT_SYMBOL_GPL(qeth_do_send_packet_fast);
  2836. int qeth_do_send_packet(struct qeth_card *card, struct qeth_qdio_out_q *queue,
  2837. struct sk_buff *skb, struct qeth_hdr *hdr,
  2838. int elements_needed)
  2839. {
  2840. struct qeth_qdio_out_buffer *buffer;
  2841. int start_index;
  2842. int flush_count = 0;
  2843. int do_pack = 0;
  2844. int tmp;
  2845. int rc = 0;
  2846. /* spin until we get the queue ... */
  2847. while (atomic_cmpxchg(&queue->state, QETH_OUT_Q_UNLOCKED,
  2848. QETH_OUT_Q_LOCKED) != QETH_OUT_Q_UNLOCKED);
  2849. start_index = queue->next_buf_to_fill;
  2850. buffer = &queue->bufs[queue->next_buf_to_fill];
  2851. /*
  2852. * check if buffer is empty to make sure that we do not 'overtake'
  2853. * ourselves and try to fill a buffer that is already primed
  2854. */
  2855. if (atomic_read(&buffer->state) != QETH_QDIO_BUF_EMPTY) {
  2856. atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED);
  2857. return -EBUSY;
  2858. }
  2859. /* check if we need to switch packing state of this queue */
  2860. qeth_switch_to_packing_if_needed(queue);
  2861. if (queue->do_pack) {
  2862. do_pack = 1;
  2863. /* does packet fit in current buffer? */
  2864. if ((QETH_MAX_BUFFER_ELEMENTS(card) -
  2865. buffer->next_element_to_fill) < elements_needed) {
  2866. /* ... no -> set state PRIMED */
  2867. atomic_set(&buffer->state, QETH_QDIO_BUF_PRIMED);
  2868. flush_count++;
  2869. queue->next_buf_to_fill =
  2870. (queue->next_buf_to_fill + 1) %
  2871. QDIO_MAX_BUFFERS_PER_Q;
  2872. buffer = &queue->bufs[queue->next_buf_to_fill];
  2873. /* we did a step forward, so check buffer state
  2874. * again */
  2875. if (atomic_read(&buffer->state) !=
  2876. QETH_QDIO_BUF_EMPTY) {
  2877. qeth_flush_buffers(queue, start_index,
  2878. flush_count);
  2879. atomic_set(&queue->state,
  2880. QETH_OUT_Q_UNLOCKED);
  2881. return -EBUSY;
  2882. }
  2883. }
  2884. }
  2885. tmp = qeth_fill_buffer(queue, buffer, skb, hdr, -1, 0);
  2886. queue->next_buf_to_fill = (queue->next_buf_to_fill + tmp) %
  2887. QDIO_MAX_BUFFERS_PER_Q;
  2888. flush_count += tmp;
  2889. if (flush_count)
  2890. qeth_flush_buffers(queue, start_index, flush_count);
  2891. else if (!atomic_read(&queue->set_pci_flags_count))
  2892. atomic_xchg(&queue->state, QETH_OUT_Q_LOCKED_FLUSH);
  2893. /*
  2894. * queue->state will go from LOCKED -> UNLOCKED or from
  2895. * LOCKED_FLUSH -> LOCKED if output_handler wanted to 'notify' us
  2896. * (switch packing state or flush buffer to get another pci flag out).
  2897. * In that case we will enter this loop
  2898. */
  2899. while (atomic_dec_return(&queue->state)) {
  2900. flush_count = 0;
  2901. start_index = queue->next_buf_to_fill;
  2902. /* check if we can go back to non-packing state */
  2903. flush_count += qeth_switch_to_nonpacking_if_needed(queue);
  2904. /*
  2905. * check if we need to flush a packing buffer to get a pci
  2906. * flag out on the queue
  2907. */
  2908. if (!flush_count && !atomic_read(&queue->set_pci_flags_count))
  2909. flush_count += qeth_flush_buffers_on_no_pci(queue);
  2910. if (flush_count)
  2911. qeth_flush_buffers(queue, start_index, flush_count);
  2912. }
  2913. /* at this point the queue is UNLOCKED again */
  2914. if (queue->card->options.performance_stats && do_pack)
  2915. queue->card->perf_stats.bufs_sent_pack += flush_count;
  2916. return rc;
  2917. }
  2918. EXPORT_SYMBOL_GPL(qeth_do_send_packet);
  2919. static int qeth_setadp_promisc_mode_cb(struct qeth_card *card,
  2920. struct qeth_reply *reply, unsigned long data)
  2921. {
  2922. struct qeth_ipa_cmd *cmd;
  2923. struct qeth_ipacmd_setadpparms *setparms;
  2924. QETH_DBF_TEXT(TRACE, 4, "prmadpcb");
  2925. cmd = (struct qeth_ipa_cmd *) data;
  2926. setparms = &(cmd->data.setadapterparms);
  2927. qeth_default_setadapterparms_cb(card, reply, (unsigned long)cmd);
  2928. if (cmd->hdr.return_code) {
  2929. QETH_DBF_TEXT_(TRACE, 4, "prmrc%2.2x", cmd->hdr.return_code);
  2930. setparms->data.mode = SET_PROMISC_MODE_OFF;
  2931. }
  2932. card->info.promisc_mode = setparms->data.mode;
  2933. return 0;
  2934. }
  2935. void qeth_setadp_promisc_mode(struct qeth_card *card)
  2936. {
  2937. enum qeth_ipa_promisc_modes mode;
  2938. struct net_device *dev = card->dev;
  2939. struct qeth_cmd_buffer *iob;
  2940. struct qeth_ipa_cmd *cmd;
  2941. QETH_DBF_TEXT(TRACE, 4, "setprom");
  2942. if (((dev->flags & IFF_PROMISC) &&
  2943. (card->info.promisc_mode == SET_PROMISC_MODE_ON)) ||
  2944. (!(dev->flags & IFF_PROMISC) &&
  2945. (card->info.promisc_mode == SET_PROMISC_MODE_OFF)))
  2946. return;
  2947. mode = SET_PROMISC_MODE_OFF;
  2948. if (dev->flags & IFF_PROMISC)
  2949. mode = SET_PROMISC_MODE_ON;
  2950. QETH_DBF_TEXT_(TRACE, 4, "mode:%x", mode);
  2951. iob = qeth_get_adapter_cmd(card, IPA_SETADP_SET_PROMISC_MODE,
  2952. sizeof(struct qeth_ipacmd_setadpparms));
  2953. cmd = (struct qeth_ipa_cmd *)(iob->data + IPA_PDU_HEADER_SIZE);
  2954. cmd->data.setadapterparms.data.mode = mode;
  2955. qeth_send_ipa_cmd(card, iob, qeth_setadp_promisc_mode_cb, NULL);
  2956. }
  2957. EXPORT_SYMBOL_GPL(qeth_setadp_promisc_mode);
  2958. int qeth_change_mtu(struct net_device *dev, int new_mtu)
  2959. {
  2960. struct qeth_card *card;
  2961. char dbf_text[15];
  2962. card = dev->ml_priv;
  2963. QETH_DBF_TEXT(TRACE, 4, "chgmtu");
  2964. sprintf(dbf_text, "%8x", new_mtu);
  2965. QETH_DBF_TEXT(TRACE, 4, dbf_text);
  2966. if (new_mtu < 64)
  2967. return -EINVAL;
  2968. if (new_mtu > 65535)
  2969. return -EINVAL;
  2970. if ((!qeth_is_supported(card, IPA_IP_FRAGMENTATION)) &&
  2971. (!qeth_mtu_is_valid(card, new_mtu)))
  2972. return -EINVAL;
  2973. dev->mtu = new_mtu;
  2974. return 0;
  2975. }
  2976. EXPORT_SYMBOL_GPL(qeth_change_mtu);
  2977. struct net_device_stats *qeth_get_stats(struct net_device *dev)
  2978. {
  2979. struct qeth_card *card;
  2980. card = dev->ml_priv;
  2981. QETH_DBF_TEXT(TRACE, 5, "getstat");
  2982. return &card->stats;
  2983. }
  2984. EXPORT_SYMBOL_GPL(qeth_get_stats);
  2985. static int qeth_setadpparms_change_macaddr_cb(struct qeth_card *card,
  2986. struct qeth_reply *reply, unsigned long data)
  2987. {
  2988. struct qeth_ipa_cmd *cmd;
  2989. QETH_DBF_TEXT(TRACE, 4, "chgmaccb");
  2990. cmd = (struct qeth_ipa_cmd *) data;
  2991. if (!card->options.layer2 ||
  2992. !(card->info.mac_bits & QETH_LAYER2_MAC_READ)) {
  2993. memcpy(card->dev->dev_addr,
  2994. &cmd->data.setadapterparms.data.change_addr.addr,
  2995. OSA_ADDR_LEN);
  2996. card->info.mac_bits |= QETH_LAYER2_MAC_READ;
  2997. }
  2998. qeth_default_setadapterparms_cb(card, reply, (unsigned long) cmd);
  2999. return 0;
  3000. }
  3001. int qeth_setadpparms_change_macaddr(struct qeth_card *card)
  3002. {
  3003. int rc;
  3004. struct qeth_cmd_buffer *iob;
  3005. struct qeth_ipa_cmd *cmd;
  3006. QETH_DBF_TEXT(TRACE, 4, "chgmac");
  3007. iob = qeth_get_adapter_cmd(card, IPA_SETADP_ALTER_MAC_ADDRESS,
  3008. sizeof(struct qeth_ipacmd_setadpparms));
  3009. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  3010. cmd->data.setadapterparms.data.change_addr.cmd = CHANGE_ADDR_READ_MAC;
  3011. cmd->data.setadapterparms.data.change_addr.addr_size = OSA_ADDR_LEN;
  3012. memcpy(&cmd->data.setadapterparms.data.change_addr.addr,
  3013. card->dev->dev_addr, OSA_ADDR_LEN);
  3014. rc = qeth_send_ipa_cmd(card, iob, qeth_setadpparms_change_macaddr_cb,
  3015. NULL);
  3016. return rc;
  3017. }
  3018. EXPORT_SYMBOL_GPL(qeth_setadpparms_change_macaddr);
  3019. static int qeth_setadpparms_set_access_ctrl_cb(struct qeth_card *card,
  3020. struct qeth_reply *reply, unsigned long data)
  3021. {
  3022. struct qeth_ipa_cmd *cmd;
  3023. struct qeth_set_access_ctrl *access_ctrl_req;
  3024. int rc;
  3025. QETH_DBF_TEXT(TRACE, 4, "setaccb");
  3026. cmd = (struct qeth_ipa_cmd *) data;
  3027. access_ctrl_req = &cmd->data.setadapterparms.data.set_access_ctrl;
  3028. QETH_DBF_TEXT_(SETUP, 2, "setaccb");
  3029. QETH_DBF_TEXT_(SETUP, 2, "%s", card->gdev->dev.kobj.name);
  3030. QETH_DBF_TEXT_(SETUP, 2, "rc=%d",
  3031. cmd->data.setadapterparms.hdr.return_code);
  3032. switch (cmd->data.setadapterparms.hdr.return_code) {
  3033. case SET_ACCESS_CTRL_RC_SUCCESS:
  3034. case SET_ACCESS_CTRL_RC_ALREADY_NOT_ISOLATED:
  3035. case SET_ACCESS_CTRL_RC_ALREADY_ISOLATED:
  3036. {
  3037. card->options.isolation = access_ctrl_req->subcmd_code;
  3038. if (card->options.isolation == ISOLATION_MODE_NONE) {
  3039. dev_info(&card->gdev->dev,
  3040. "QDIO data connection isolation is deactivated\n");
  3041. } else {
  3042. dev_info(&card->gdev->dev,
  3043. "QDIO data connection isolation is activated\n");
  3044. }
  3045. QETH_DBF_MESSAGE(3, "OK:SET_ACCESS_CTRL(%s, %d)==%d\n",
  3046. card->gdev->dev.kobj.name,
  3047. access_ctrl_req->subcmd_code,
  3048. cmd->data.setadapterparms.hdr.return_code);
  3049. rc = 0;
  3050. break;
  3051. }
  3052. case SET_ACCESS_CTRL_RC_NOT_SUPPORTED:
  3053. {
  3054. QETH_DBF_MESSAGE(3, "ERR:SET_ACCESS_CTRL(%s,%d)==%d\n",
  3055. card->gdev->dev.kobj.name,
  3056. access_ctrl_req->subcmd_code,
  3057. cmd->data.setadapterparms.hdr.return_code);
  3058. dev_err(&card->gdev->dev, "Adapter does not "
  3059. "support QDIO data connection isolation\n");
  3060. /* ensure isolation mode is "none" */
  3061. card->options.isolation = ISOLATION_MODE_NONE;
  3062. rc = -EOPNOTSUPP;
  3063. break;
  3064. }
  3065. case SET_ACCESS_CTRL_RC_NONE_SHARED_ADAPTER:
  3066. {
  3067. QETH_DBF_MESSAGE(3, "ERR:SET_ACCESS_MODE(%s,%d)==%d\n",
  3068. card->gdev->dev.kobj.name,
  3069. access_ctrl_req->subcmd_code,
  3070. cmd->data.setadapterparms.hdr.return_code);
  3071. dev_err(&card->gdev->dev,
  3072. "Adapter is dedicated. "
  3073. "QDIO data connection isolation not supported\n");
  3074. /* ensure isolation mode is "none" */
  3075. card->options.isolation = ISOLATION_MODE_NONE;
  3076. rc = -EOPNOTSUPP;
  3077. break;
  3078. }
  3079. case SET_ACCESS_CTRL_RC_ACTIVE_CHECKSUM_OFF:
  3080. {
  3081. QETH_DBF_MESSAGE(3, "ERR:SET_ACCESS_MODE(%s,%d)==%d\n",
  3082. card->gdev->dev.kobj.name,
  3083. access_ctrl_req->subcmd_code,
  3084. cmd->data.setadapterparms.hdr.return_code);
  3085. dev_err(&card->gdev->dev,
  3086. "TSO does not permit QDIO data connection isolation\n");
  3087. /* ensure isolation mode is "none" */
  3088. card->options.isolation = ISOLATION_MODE_NONE;
  3089. rc = -EPERM;
  3090. break;
  3091. }
  3092. default:
  3093. {
  3094. /* this should never happen */
  3095. QETH_DBF_MESSAGE(3, "ERR:SET_ACCESS_MODE(%s,%d)==%d"
  3096. "==UNKNOWN\n",
  3097. card->gdev->dev.kobj.name,
  3098. access_ctrl_req->subcmd_code,
  3099. cmd->data.setadapterparms.hdr.return_code);
  3100. /* ensure isolation mode is "none" */
  3101. card->options.isolation = ISOLATION_MODE_NONE;
  3102. rc = 0;
  3103. break;
  3104. }
  3105. }
  3106. qeth_default_setadapterparms_cb(card, reply, (unsigned long) cmd);
  3107. return rc;
  3108. }
  3109. static int qeth_setadpparms_set_access_ctrl(struct qeth_card *card,
  3110. enum qeth_ipa_isolation_modes isolation)
  3111. {
  3112. int rc;
  3113. struct qeth_cmd_buffer *iob;
  3114. struct qeth_ipa_cmd *cmd;
  3115. struct qeth_set_access_ctrl *access_ctrl_req;
  3116. QETH_DBF_TEXT(TRACE, 4, "setacctl");
  3117. QETH_DBF_TEXT_(SETUP, 2, "setacctl");
  3118. QETH_DBF_TEXT_(SETUP, 2, "%s", card->gdev->dev.kobj.name);
  3119. iob = qeth_get_adapter_cmd(card, IPA_SETADP_SET_ACCESS_CONTROL,
  3120. sizeof(struct qeth_ipacmd_setadpparms_hdr) +
  3121. sizeof(struct qeth_set_access_ctrl));
  3122. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  3123. access_ctrl_req = &cmd->data.setadapterparms.data.set_access_ctrl;
  3124. access_ctrl_req->subcmd_code = isolation;
  3125. rc = qeth_send_ipa_cmd(card, iob, qeth_setadpparms_set_access_ctrl_cb,
  3126. NULL);
  3127. QETH_DBF_TEXT_(SETUP, 2, "rc=%d", rc);
  3128. return rc;
  3129. }
  3130. int qeth_set_access_ctrl_online(struct qeth_card *card)
  3131. {
  3132. int rc = 0;
  3133. QETH_DBF_TEXT(TRACE, 4, "setactlo");
  3134. if (card->info.type == QETH_CARD_TYPE_OSAE &&
  3135. qeth_adp_supported(card, IPA_SETADP_SET_ACCESS_CONTROL)) {
  3136. rc = qeth_setadpparms_set_access_ctrl(card,
  3137. card->options.isolation);
  3138. if (rc) {
  3139. QETH_DBF_MESSAGE(3,
  3140. "IPA(SET_ACCESS_CTRL,%s,%d) sent failed",
  3141. card->gdev->dev.kobj.name,
  3142. rc);
  3143. }
  3144. } else if (card->options.isolation != ISOLATION_MODE_NONE) {
  3145. card->options.isolation = ISOLATION_MODE_NONE;
  3146. dev_err(&card->gdev->dev, "Adapter does not "
  3147. "support QDIO data connection isolation\n");
  3148. rc = -EOPNOTSUPP;
  3149. }
  3150. return rc;
  3151. }
  3152. EXPORT_SYMBOL_GPL(qeth_set_access_ctrl_online);
  3153. void qeth_tx_timeout(struct net_device *dev)
  3154. {
  3155. struct qeth_card *card;
  3156. QETH_DBF_TEXT(TRACE, 4, "txtimeo");
  3157. card = dev->ml_priv;
  3158. card->stats.tx_errors++;
  3159. qeth_schedule_recovery(card);
  3160. }
  3161. EXPORT_SYMBOL_GPL(qeth_tx_timeout);
  3162. int qeth_mdio_read(struct net_device *dev, int phy_id, int regnum)
  3163. {
  3164. struct qeth_card *card = dev->ml_priv;
  3165. int rc = 0;
  3166. switch (regnum) {
  3167. case MII_BMCR: /* Basic mode control register */
  3168. rc = BMCR_FULLDPLX;
  3169. if ((card->info.link_type != QETH_LINK_TYPE_GBIT_ETH) &&
  3170. (card->info.link_type != QETH_LINK_TYPE_OSN) &&
  3171. (card->info.link_type != QETH_LINK_TYPE_10GBIT_ETH))
  3172. rc |= BMCR_SPEED100;
  3173. break;
  3174. case MII_BMSR: /* Basic mode status register */
  3175. rc = BMSR_ERCAP | BMSR_ANEGCOMPLETE | BMSR_LSTATUS |
  3176. BMSR_10HALF | BMSR_10FULL | BMSR_100HALF | BMSR_100FULL |
  3177. BMSR_100BASE4;
  3178. break;
  3179. case MII_PHYSID1: /* PHYS ID 1 */
  3180. rc = (dev->dev_addr[0] << 16) | (dev->dev_addr[1] << 8) |
  3181. dev->dev_addr[2];
  3182. rc = (rc >> 5) & 0xFFFF;
  3183. break;
  3184. case MII_PHYSID2: /* PHYS ID 2 */
  3185. rc = (dev->dev_addr[2] << 10) & 0xFFFF;
  3186. break;
  3187. case MII_ADVERTISE: /* Advertisement control reg */
  3188. rc = ADVERTISE_ALL;
  3189. break;
  3190. case MII_LPA: /* Link partner ability reg */
  3191. rc = LPA_10HALF | LPA_10FULL | LPA_100HALF | LPA_100FULL |
  3192. LPA_100BASE4 | LPA_LPACK;
  3193. break;
  3194. case MII_EXPANSION: /* Expansion register */
  3195. break;
  3196. case MII_DCOUNTER: /* disconnect counter */
  3197. break;
  3198. case MII_FCSCOUNTER: /* false carrier counter */
  3199. break;
  3200. case MII_NWAYTEST: /* N-way auto-neg test register */
  3201. break;
  3202. case MII_RERRCOUNTER: /* rx error counter */
  3203. rc = card->stats.rx_errors;
  3204. break;
  3205. case MII_SREVISION: /* silicon revision */
  3206. break;
  3207. case MII_RESV1: /* reserved 1 */
  3208. break;
  3209. case MII_LBRERROR: /* loopback, rx, bypass error */
  3210. break;
  3211. case MII_PHYADDR: /* physical address */
  3212. break;
  3213. case MII_RESV2: /* reserved 2 */
  3214. break;
  3215. case MII_TPISTATUS: /* TPI status for 10mbps */
  3216. break;
  3217. case MII_NCONFIG: /* network interface config */
  3218. break;
  3219. default:
  3220. break;
  3221. }
  3222. return rc;
  3223. }
  3224. EXPORT_SYMBOL_GPL(qeth_mdio_read);
  3225. static int qeth_send_ipa_snmp_cmd(struct qeth_card *card,
  3226. struct qeth_cmd_buffer *iob, int len,
  3227. int (*reply_cb)(struct qeth_card *, struct qeth_reply *,
  3228. unsigned long),
  3229. void *reply_param)
  3230. {
  3231. u16 s1, s2;
  3232. QETH_DBF_TEXT(TRACE, 4, "sendsnmp");
  3233. memcpy(iob->data, IPA_PDU_HEADER, IPA_PDU_HEADER_SIZE);
  3234. memcpy(QETH_IPA_CMD_DEST_ADDR(iob->data),
  3235. &card->token.ulp_connection_r, QETH_MPC_TOKEN_LENGTH);
  3236. /* adjust PDU length fields in IPA_PDU_HEADER */
  3237. s1 = (u32) IPA_PDU_HEADER_SIZE + len;
  3238. s2 = (u32) len;
  3239. memcpy(QETH_IPA_PDU_LEN_TOTAL(iob->data), &s1, 2);
  3240. memcpy(QETH_IPA_PDU_LEN_PDU1(iob->data), &s2, 2);
  3241. memcpy(QETH_IPA_PDU_LEN_PDU2(iob->data), &s2, 2);
  3242. memcpy(QETH_IPA_PDU_LEN_PDU3(iob->data), &s2, 2);
  3243. return qeth_send_control_data(card, IPA_PDU_HEADER_SIZE + len, iob,
  3244. reply_cb, reply_param);
  3245. }
  3246. static int qeth_snmp_command_cb(struct qeth_card *card,
  3247. struct qeth_reply *reply, unsigned long sdata)
  3248. {
  3249. struct qeth_ipa_cmd *cmd;
  3250. struct qeth_arp_query_info *qinfo;
  3251. struct qeth_snmp_cmd *snmp;
  3252. unsigned char *data;
  3253. __u16 data_len;
  3254. QETH_DBF_TEXT(TRACE, 3, "snpcmdcb");
  3255. cmd = (struct qeth_ipa_cmd *) sdata;
  3256. data = (unsigned char *)((char *)cmd - reply->offset);
  3257. qinfo = (struct qeth_arp_query_info *) reply->param;
  3258. snmp = &cmd->data.setadapterparms.data.snmp;
  3259. if (cmd->hdr.return_code) {
  3260. QETH_DBF_TEXT_(TRACE, 4, "scer1%i", cmd->hdr.return_code);
  3261. return 0;
  3262. }
  3263. if (cmd->data.setadapterparms.hdr.return_code) {
  3264. cmd->hdr.return_code =
  3265. cmd->data.setadapterparms.hdr.return_code;
  3266. QETH_DBF_TEXT_(TRACE, 4, "scer2%i", cmd->hdr.return_code);
  3267. return 0;
  3268. }
  3269. data_len = *((__u16 *)QETH_IPA_PDU_LEN_PDU1(data));
  3270. if (cmd->data.setadapterparms.hdr.seq_no == 1)
  3271. data_len -= (__u16)((char *)&snmp->data - (char *)cmd);
  3272. else
  3273. data_len -= (__u16)((char *)&snmp->request - (char *)cmd);
  3274. /* check if there is enough room in userspace */
  3275. if ((qinfo->udata_len - qinfo->udata_offset) < data_len) {
  3276. QETH_DBF_TEXT_(TRACE, 4, "scer3%i", -ENOMEM);
  3277. cmd->hdr.return_code = -ENOMEM;
  3278. return 0;
  3279. }
  3280. QETH_DBF_TEXT_(TRACE, 4, "snore%i",
  3281. cmd->data.setadapterparms.hdr.used_total);
  3282. QETH_DBF_TEXT_(TRACE, 4, "sseqn%i",
  3283. cmd->data.setadapterparms.hdr.seq_no);
  3284. /*copy entries to user buffer*/
  3285. if (cmd->data.setadapterparms.hdr.seq_no == 1) {
  3286. memcpy(qinfo->udata + qinfo->udata_offset,
  3287. (char *)snmp,
  3288. data_len + offsetof(struct qeth_snmp_cmd, data));
  3289. qinfo->udata_offset += offsetof(struct qeth_snmp_cmd, data);
  3290. } else {
  3291. memcpy(qinfo->udata + qinfo->udata_offset,
  3292. (char *)&snmp->request, data_len);
  3293. }
  3294. qinfo->udata_offset += data_len;
  3295. /* check if all replies received ... */
  3296. QETH_DBF_TEXT_(TRACE, 4, "srtot%i",
  3297. cmd->data.setadapterparms.hdr.used_total);
  3298. QETH_DBF_TEXT_(TRACE, 4, "srseq%i",
  3299. cmd->data.setadapterparms.hdr.seq_no);
  3300. if (cmd->data.setadapterparms.hdr.seq_no <
  3301. cmd->data.setadapterparms.hdr.used_total)
  3302. return 1;
  3303. return 0;
  3304. }
  3305. int qeth_snmp_command(struct qeth_card *card, char __user *udata)
  3306. {
  3307. struct qeth_cmd_buffer *iob;
  3308. struct qeth_ipa_cmd *cmd;
  3309. struct qeth_snmp_ureq *ureq;
  3310. int req_len;
  3311. struct qeth_arp_query_info qinfo = {0, };
  3312. int rc = 0;
  3313. QETH_DBF_TEXT(TRACE, 3, "snmpcmd");
  3314. if (card->info.guestlan)
  3315. return -EOPNOTSUPP;
  3316. if ((!qeth_adp_supported(card, IPA_SETADP_SET_SNMP_CONTROL)) &&
  3317. (!card->options.layer2)) {
  3318. return -EOPNOTSUPP;
  3319. }
  3320. /* skip 4 bytes (data_len struct member) to get req_len */
  3321. if (copy_from_user(&req_len, udata + sizeof(int), sizeof(int)))
  3322. return -EFAULT;
  3323. ureq = kmalloc(req_len+sizeof(struct qeth_snmp_ureq_hdr), GFP_KERNEL);
  3324. if (!ureq) {
  3325. QETH_DBF_TEXT(TRACE, 2, "snmpnome");
  3326. return -ENOMEM;
  3327. }
  3328. if (copy_from_user(ureq, udata,
  3329. req_len + sizeof(struct qeth_snmp_ureq_hdr))) {
  3330. kfree(ureq);
  3331. return -EFAULT;
  3332. }
  3333. qinfo.udata_len = ureq->hdr.data_len;
  3334. qinfo.udata = kzalloc(qinfo.udata_len, GFP_KERNEL);
  3335. if (!qinfo.udata) {
  3336. kfree(ureq);
  3337. return -ENOMEM;
  3338. }
  3339. qinfo.udata_offset = sizeof(struct qeth_snmp_ureq_hdr);
  3340. iob = qeth_get_adapter_cmd(card, IPA_SETADP_SET_SNMP_CONTROL,
  3341. QETH_SNMP_SETADP_CMDLENGTH + req_len);
  3342. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  3343. memcpy(&cmd->data.setadapterparms.data.snmp, &ureq->cmd, req_len);
  3344. rc = qeth_send_ipa_snmp_cmd(card, iob, QETH_SETADP_BASE_LEN + req_len,
  3345. qeth_snmp_command_cb, (void *)&qinfo);
  3346. if (rc)
  3347. QETH_DBF_MESSAGE(2, "SNMP command failed on %s: (0x%x)\n",
  3348. QETH_CARD_IFNAME(card), rc);
  3349. else {
  3350. if (copy_to_user(udata, qinfo.udata, qinfo.udata_len))
  3351. rc = -EFAULT;
  3352. }
  3353. kfree(ureq);
  3354. kfree(qinfo.udata);
  3355. return rc;
  3356. }
  3357. EXPORT_SYMBOL_GPL(qeth_snmp_command);
  3358. static inline int qeth_get_qdio_q_format(struct qeth_card *card)
  3359. {
  3360. switch (card->info.type) {
  3361. case QETH_CARD_TYPE_IQD:
  3362. return 2;
  3363. default:
  3364. return 0;
  3365. }
  3366. }
  3367. static int qeth_qdio_establish(struct qeth_card *card)
  3368. {
  3369. struct qdio_initialize init_data;
  3370. char *qib_param_field;
  3371. struct qdio_buffer **in_sbal_ptrs;
  3372. struct qdio_buffer **out_sbal_ptrs;
  3373. int i, j, k;
  3374. int rc = 0;
  3375. QETH_DBF_TEXT(SETUP, 2, "qdioest");
  3376. qib_param_field = kzalloc(QDIO_MAX_BUFFERS_PER_Q * sizeof(char),
  3377. GFP_KERNEL);
  3378. if (!qib_param_field)
  3379. return -ENOMEM;
  3380. qeth_create_qib_param_field(card, qib_param_field);
  3381. qeth_create_qib_param_field_blkt(card, qib_param_field);
  3382. in_sbal_ptrs = kmalloc(QDIO_MAX_BUFFERS_PER_Q * sizeof(void *),
  3383. GFP_KERNEL);
  3384. if (!in_sbal_ptrs) {
  3385. kfree(qib_param_field);
  3386. return -ENOMEM;
  3387. }
  3388. for (i = 0; i < QDIO_MAX_BUFFERS_PER_Q; ++i)
  3389. in_sbal_ptrs[i] = (struct qdio_buffer *)
  3390. virt_to_phys(card->qdio.in_q->bufs[i].buffer);
  3391. out_sbal_ptrs =
  3392. kmalloc(card->qdio.no_out_queues * QDIO_MAX_BUFFERS_PER_Q *
  3393. sizeof(void *), GFP_KERNEL);
  3394. if (!out_sbal_ptrs) {
  3395. kfree(in_sbal_ptrs);
  3396. kfree(qib_param_field);
  3397. return -ENOMEM;
  3398. }
  3399. for (i = 0, k = 0; i < card->qdio.no_out_queues; ++i)
  3400. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j, ++k) {
  3401. out_sbal_ptrs[k] = (struct qdio_buffer *)virt_to_phys(
  3402. card->qdio.out_qs[i]->bufs[j].buffer);
  3403. }
  3404. memset(&init_data, 0, sizeof(struct qdio_initialize));
  3405. init_data.cdev = CARD_DDEV(card);
  3406. init_data.q_format = qeth_get_qdio_q_format(card);
  3407. init_data.qib_param_field_format = 0;
  3408. init_data.qib_param_field = qib_param_field;
  3409. init_data.no_input_qs = 1;
  3410. init_data.no_output_qs = card->qdio.no_out_queues;
  3411. init_data.input_handler = card->discipline.input_handler;
  3412. init_data.output_handler = card->discipline.output_handler;
  3413. init_data.int_parm = (unsigned long) card;
  3414. init_data.flags = QDIO_INBOUND_0COPY_SBALS |
  3415. QDIO_OUTBOUND_0COPY_SBALS |
  3416. QDIO_USE_OUTBOUND_PCIS;
  3417. init_data.input_sbal_addr_array = (void **) in_sbal_ptrs;
  3418. init_data.output_sbal_addr_array = (void **) out_sbal_ptrs;
  3419. if (atomic_cmpxchg(&card->qdio.state, QETH_QDIO_ALLOCATED,
  3420. QETH_QDIO_ESTABLISHED) == QETH_QDIO_ALLOCATED) {
  3421. rc = qdio_initialize(&init_data);
  3422. if (rc)
  3423. atomic_set(&card->qdio.state, QETH_QDIO_ALLOCATED);
  3424. }
  3425. kfree(out_sbal_ptrs);
  3426. kfree(in_sbal_ptrs);
  3427. kfree(qib_param_field);
  3428. return rc;
  3429. }
  3430. static void qeth_core_free_card(struct qeth_card *card)
  3431. {
  3432. QETH_DBF_TEXT(SETUP, 2, "freecrd");
  3433. QETH_DBF_HEX(SETUP, 2, &card, sizeof(void *));
  3434. qeth_clean_channel(&card->read);
  3435. qeth_clean_channel(&card->write);
  3436. if (card->dev)
  3437. free_netdev(card->dev);
  3438. kfree(card->ip_tbd_list);
  3439. qeth_free_qdio_buffers(card);
  3440. unregister_service_level(&card->qeth_service_level);
  3441. kfree(card);
  3442. }
  3443. static struct ccw_device_id qeth_ids[] = {
  3444. {CCW_DEVICE(0x1731, 0x01), .driver_info = QETH_CARD_TYPE_OSAE},
  3445. {CCW_DEVICE(0x1731, 0x05), .driver_info = QETH_CARD_TYPE_IQD},
  3446. {CCW_DEVICE(0x1731, 0x06), .driver_info = QETH_CARD_TYPE_OSN},
  3447. {},
  3448. };
  3449. MODULE_DEVICE_TABLE(ccw, qeth_ids);
  3450. static struct ccw_driver qeth_ccw_driver = {
  3451. .name = "qeth",
  3452. .ids = qeth_ids,
  3453. .probe = ccwgroup_probe_ccwdev,
  3454. .remove = ccwgroup_remove_ccwdev,
  3455. };
  3456. static int qeth_core_driver_group(const char *buf, struct device *root_dev,
  3457. unsigned long driver_id)
  3458. {
  3459. return ccwgroup_create_from_string(root_dev, driver_id,
  3460. &qeth_ccw_driver, 3, buf);
  3461. }
  3462. int qeth_core_hardsetup_card(struct qeth_card *card)
  3463. {
  3464. int retries = 0;
  3465. int rc;
  3466. QETH_DBF_TEXT(SETUP, 2, "hrdsetup");
  3467. atomic_set(&card->force_alloc_skb, 0);
  3468. retry:
  3469. if (retries)
  3470. QETH_DBF_MESSAGE(2, "%s Retrying to do IDX activates.\n",
  3471. dev_name(&card->gdev->dev));
  3472. ccw_device_set_offline(CARD_DDEV(card));
  3473. ccw_device_set_offline(CARD_WDEV(card));
  3474. ccw_device_set_offline(CARD_RDEV(card));
  3475. rc = ccw_device_set_online(CARD_RDEV(card));
  3476. if (rc)
  3477. goto retriable;
  3478. rc = ccw_device_set_online(CARD_WDEV(card));
  3479. if (rc)
  3480. goto retriable;
  3481. rc = ccw_device_set_online(CARD_DDEV(card));
  3482. if (rc)
  3483. goto retriable;
  3484. rc = qeth_qdio_clear_card(card, card->info.type != QETH_CARD_TYPE_IQD);
  3485. retriable:
  3486. if (rc == -ERESTARTSYS) {
  3487. QETH_DBF_TEXT(SETUP, 2, "break1");
  3488. return rc;
  3489. } else if (rc) {
  3490. QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
  3491. if (++retries > 3)
  3492. goto out;
  3493. else
  3494. goto retry;
  3495. }
  3496. qeth_init_tokens(card);
  3497. qeth_init_func_level(card);
  3498. rc = qeth_idx_activate_channel(&card->read, qeth_idx_read_cb);
  3499. if (rc == -ERESTARTSYS) {
  3500. QETH_DBF_TEXT(SETUP, 2, "break2");
  3501. return rc;
  3502. } else if (rc) {
  3503. QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
  3504. if (--retries < 0)
  3505. goto out;
  3506. else
  3507. goto retry;
  3508. }
  3509. rc = qeth_idx_activate_channel(&card->write, qeth_idx_write_cb);
  3510. if (rc == -ERESTARTSYS) {
  3511. QETH_DBF_TEXT(SETUP, 2, "break3");
  3512. return rc;
  3513. } else if (rc) {
  3514. QETH_DBF_TEXT_(SETUP, 2, "4err%d", rc);
  3515. if (--retries < 0)
  3516. goto out;
  3517. else
  3518. goto retry;
  3519. }
  3520. rc = qeth_mpc_initialize(card);
  3521. if (rc) {
  3522. QETH_DBF_TEXT_(SETUP, 2, "5err%d", rc);
  3523. goto out;
  3524. }
  3525. return 0;
  3526. out:
  3527. dev_warn(&card->gdev->dev, "The qeth device driver failed to recover "
  3528. "an error on the device\n");
  3529. QETH_DBF_MESSAGE(2, "%s Initialization in hardsetup failed! rc=%d\n",
  3530. dev_name(&card->gdev->dev), rc);
  3531. return rc;
  3532. }
  3533. EXPORT_SYMBOL_GPL(qeth_core_hardsetup_card);
  3534. static inline int qeth_create_skb_frag(struct qdio_buffer_element *element,
  3535. struct sk_buff **pskb, int offset, int *pfrag, int data_len)
  3536. {
  3537. struct page *page = virt_to_page(element->addr);
  3538. if (*pskb == NULL) {
  3539. /* the upper protocol layers assume that there is data in the
  3540. * skb itself. Copy a small amount (64 bytes) to make them
  3541. * happy. */
  3542. *pskb = dev_alloc_skb(64 + ETH_HLEN);
  3543. if (!(*pskb))
  3544. return -ENOMEM;
  3545. skb_reserve(*pskb, ETH_HLEN);
  3546. if (data_len <= 64) {
  3547. memcpy(skb_put(*pskb, data_len), element->addr + offset,
  3548. data_len);
  3549. } else {
  3550. get_page(page);
  3551. memcpy(skb_put(*pskb, 64), element->addr + offset, 64);
  3552. skb_fill_page_desc(*pskb, *pfrag, page, offset + 64,
  3553. data_len - 64);
  3554. (*pskb)->data_len += data_len - 64;
  3555. (*pskb)->len += data_len - 64;
  3556. (*pskb)->truesize += data_len - 64;
  3557. (*pfrag)++;
  3558. }
  3559. } else {
  3560. get_page(page);
  3561. skb_fill_page_desc(*pskb, *pfrag, page, offset, data_len);
  3562. (*pskb)->data_len += data_len;
  3563. (*pskb)->len += data_len;
  3564. (*pskb)->truesize += data_len;
  3565. (*pfrag)++;
  3566. }
  3567. return 0;
  3568. }
  3569. struct sk_buff *qeth_core_get_next_skb(struct qeth_card *card,
  3570. struct qdio_buffer *buffer,
  3571. struct qdio_buffer_element **__element, int *__offset,
  3572. struct qeth_hdr **hdr)
  3573. {
  3574. struct qdio_buffer_element *element = *__element;
  3575. int offset = *__offset;
  3576. struct sk_buff *skb = NULL;
  3577. int skb_len = 0;
  3578. void *data_ptr;
  3579. int data_len;
  3580. int headroom = 0;
  3581. int use_rx_sg = 0;
  3582. int frag = 0;
  3583. /* qeth_hdr must not cross element boundaries */
  3584. if (element->length < offset + sizeof(struct qeth_hdr)) {
  3585. if (qeth_is_last_sbale(element))
  3586. return NULL;
  3587. element++;
  3588. offset = 0;
  3589. if (element->length < sizeof(struct qeth_hdr))
  3590. return NULL;
  3591. }
  3592. *hdr = element->addr + offset;
  3593. offset += sizeof(struct qeth_hdr);
  3594. switch ((*hdr)->hdr.l2.id) {
  3595. case QETH_HEADER_TYPE_LAYER2:
  3596. skb_len = (*hdr)->hdr.l2.pkt_length;
  3597. break;
  3598. case QETH_HEADER_TYPE_LAYER3:
  3599. skb_len = (*hdr)->hdr.l3.length;
  3600. if ((card->info.link_type == QETH_LINK_TYPE_LANE_TR) ||
  3601. (card->info.link_type == QETH_LINK_TYPE_HSTR))
  3602. headroom = TR_HLEN;
  3603. else
  3604. headroom = ETH_HLEN;
  3605. break;
  3606. case QETH_HEADER_TYPE_OSN:
  3607. skb_len = (*hdr)->hdr.osn.pdu_length;
  3608. headroom = sizeof(struct qeth_hdr);
  3609. break;
  3610. default:
  3611. break;
  3612. }
  3613. if (!skb_len)
  3614. return NULL;
  3615. if ((skb_len >= card->options.rx_sg_cb) &&
  3616. (!(card->info.type == QETH_CARD_TYPE_OSN)) &&
  3617. (!atomic_read(&card->force_alloc_skb))) {
  3618. use_rx_sg = 1;
  3619. } else {
  3620. skb = dev_alloc_skb(skb_len + headroom);
  3621. if (!skb)
  3622. goto no_mem;
  3623. if (headroom)
  3624. skb_reserve(skb, headroom);
  3625. }
  3626. data_ptr = element->addr + offset;
  3627. while (skb_len) {
  3628. data_len = min(skb_len, (int)(element->length - offset));
  3629. if (data_len) {
  3630. if (use_rx_sg) {
  3631. if (qeth_create_skb_frag(element, &skb, offset,
  3632. &frag, data_len))
  3633. goto no_mem;
  3634. } else {
  3635. memcpy(skb_put(skb, data_len), data_ptr,
  3636. data_len);
  3637. }
  3638. }
  3639. skb_len -= data_len;
  3640. if (skb_len) {
  3641. if (qeth_is_last_sbale(element)) {
  3642. QETH_DBF_TEXT(TRACE, 4, "unexeob");
  3643. QETH_DBF_TEXT_(TRACE, 4, "%s",
  3644. CARD_BUS_ID(card));
  3645. QETH_DBF_TEXT(QERR, 2, "unexeob");
  3646. QETH_DBF_TEXT_(QERR, 2, "%s",
  3647. CARD_BUS_ID(card));
  3648. QETH_DBF_HEX(MISC, 4, buffer, sizeof(*buffer));
  3649. dev_kfree_skb_any(skb);
  3650. card->stats.rx_errors++;
  3651. return NULL;
  3652. }
  3653. element++;
  3654. offset = 0;
  3655. data_ptr = element->addr;
  3656. } else {
  3657. offset += data_len;
  3658. }
  3659. }
  3660. *__element = element;
  3661. *__offset = offset;
  3662. if (use_rx_sg && card->options.performance_stats) {
  3663. card->perf_stats.sg_skbs_rx++;
  3664. card->perf_stats.sg_frags_rx += skb_shinfo(skb)->nr_frags;
  3665. }
  3666. return skb;
  3667. no_mem:
  3668. if (net_ratelimit()) {
  3669. QETH_DBF_TEXT(TRACE, 2, "noskbmem");
  3670. QETH_DBF_TEXT_(TRACE, 2, "%s", CARD_BUS_ID(card));
  3671. }
  3672. card->stats.rx_dropped++;
  3673. return NULL;
  3674. }
  3675. EXPORT_SYMBOL_GPL(qeth_core_get_next_skb);
  3676. static void qeth_unregister_dbf_views(void)
  3677. {
  3678. int x;
  3679. for (x = 0; x < QETH_DBF_INFOS; x++) {
  3680. debug_unregister(qeth_dbf[x].id);
  3681. qeth_dbf[x].id = NULL;
  3682. }
  3683. }
  3684. void qeth_dbf_longtext(enum qeth_dbf_names dbf_nix, int level, char *fmt, ...)
  3685. {
  3686. char dbf_txt_buf[32];
  3687. va_list args;
  3688. if (level > (qeth_dbf[dbf_nix].id)->level)
  3689. return;
  3690. va_start(args, fmt);
  3691. vsnprintf(dbf_txt_buf, sizeof(dbf_txt_buf), fmt, args);
  3692. va_end(args);
  3693. debug_text_event(qeth_dbf[dbf_nix].id, level, dbf_txt_buf);
  3694. }
  3695. EXPORT_SYMBOL_GPL(qeth_dbf_longtext);
  3696. static int qeth_register_dbf_views(void)
  3697. {
  3698. int ret;
  3699. int x;
  3700. for (x = 0; x < QETH_DBF_INFOS; x++) {
  3701. /* register the areas */
  3702. qeth_dbf[x].id = debug_register(qeth_dbf[x].name,
  3703. qeth_dbf[x].pages,
  3704. qeth_dbf[x].areas,
  3705. qeth_dbf[x].len);
  3706. if (qeth_dbf[x].id == NULL) {
  3707. qeth_unregister_dbf_views();
  3708. return -ENOMEM;
  3709. }
  3710. /* register a view */
  3711. ret = debug_register_view(qeth_dbf[x].id, qeth_dbf[x].view);
  3712. if (ret) {
  3713. qeth_unregister_dbf_views();
  3714. return ret;
  3715. }
  3716. /* set a passing level */
  3717. debug_set_level(qeth_dbf[x].id, qeth_dbf[x].level);
  3718. }
  3719. return 0;
  3720. }
  3721. int qeth_core_load_discipline(struct qeth_card *card,
  3722. enum qeth_discipline_id discipline)
  3723. {
  3724. int rc = 0;
  3725. switch (discipline) {
  3726. case QETH_DISCIPLINE_LAYER3:
  3727. card->discipline.ccwgdriver = try_then_request_module(
  3728. symbol_get(qeth_l3_ccwgroup_driver),
  3729. "qeth_l3");
  3730. break;
  3731. case QETH_DISCIPLINE_LAYER2:
  3732. card->discipline.ccwgdriver = try_then_request_module(
  3733. symbol_get(qeth_l2_ccwgroup_driver),
  3734. "qeth_l2");
  3735. break;
  3736. }
  3737. if (!card->discipline.ccwgdriver) {
  3738. dev_err(&card->gdev->dev, "There is no kernel module to "
  3739. "support discipline %d\n", discipline);
  3740. rc = -EINVAL;
  3741. }
  3742. return rc;
  3743. }
  3744. void qeth_core_free_discipline(struct qeth_card *card)
  3745. {
  3746. if (card->options.layer2)
  3747. symbol_put(qeth_l2_ccwgroup_driver);
  3748. else
  3749. symbol_put(qeth_l3_ccwgroup_driver);
  3750. card->discipline.ccwgdriver = NULL;
  3751. }
  3752. static void qeth_determine_capabilities(struct qeth_card *card)
  3753. {
  3754. int rc;
  3755. QETH_DBF_TEXT(SETUP, 2, "detcapab");
  3756. rc = ccw_device_set_online(CARD_DDEV(card));
  3757. if (rc) {
  3758. QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
  3759. goto out;
  3760. }
  3761. rc = qeth_get_unitaddr(card);
  3762. if (rc) {
  3763. QETH_DBF_TEXT_(SETUP, 2, "5err%d", rc);
  3764. goto out_offline;
  3765. }
  3766. rc = qdio_get_ssqd_desc(CARD_DDEV(card), &card->ssqd);
  3767. if (rc)
  3768. QETH_DBF_TEXT_(SETUP, 2, "6err%d", rc);
  3769. out_offline:
  3770. ccw_device_set_offline(CARD_DDEV(card));
  3771. out:
  3772. return;
  3773. }
  3774. static int qeth_core_probe_device(struct ccwgroup_device *gdev)
  3775. {
  3776. struct qeth_card *card;
  3777. struct device *dev;
  3778. int rc;
  3779. unsigned long flags;
  3780. QETH_DBF_TEXT(SETUP, 2, "probedev");
  3781. dev = &gdev->dev;
  3782. if (!get_device(dev))
  3783. return -ENODEV;
  3784. QETH_DBF_TEXT_(SETUP, 2, "%s", dev_name(&gdev->dev));
  3785. card = qeth_alloc_card();
  3786. if (!card) {
  3787. QETH_DBF_TEXT_(SETUP, 2, "1err%d", -ENOMEM);
  3788. rc = -ENOMEM;
  3789. goto err_dev;
  3790. }
  3791. card->read.ccwdev = gdev->cdev[0];
  3792. card->write.ccwdev = gdev->cdev[1];
  3793. card->data.ccwdev = gdev->cdev[2];
  3794. dev_set_drvdata(&gdev->dev, card);
  3795. card->gdev = gdev;
  3796. gdev->cdev[0]->handler = qeth_irq;
  3797. gdev->cdev[1]->handler = qeth_irq;
  3798. gdev->cdev[2]->handler = qeth_irq;
  3799. rc = qeth_determine_card_type(card);
  3800. if (rc) {
  3801. QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
  3802. goto err_card;
  3803. }
  3804. rc = qeth_setup_card(card);
  3805. if (rc) {
  3806. QETH_DBF_TEXT_(SETUP, 2, "2err%d", rc);
  3807. goto err_card;
  3808. }
  3809. if (card->info.type == QETH_CARD_TYPE_OSN) {
  3810. rc = qeth_core_create_osn_attributes(dev);
  3811. if (rc)
  3812. goto err_card;
  3813. rc = qeth_core_load_discipline(card, QETH_DISCIPLINE_LAYER2);
  3814. if (rc) {
  3815. qeth_core_remove_osn_attributes(dev);
  3816. goto err_card;
  3817. }
  3818. rc = card->discipline.ccwgdriver->probe(card->gdev);
  3819. if (rc) {
  3820. qeth_core_free_discipline(card);
  3821. qeth_core_remove_osn_attributes(dev);
  3822. goto err_card;
  3823. }
  3824. } else {
  3825. rc = qeth_core_create_device_attributes(dev);
  3826. if (rc)
  3827. goto err_card;
  3828. }
  3829. write_lock_irqsave(&qeth_core_card_list.rwlock, flags);
  3830. list_add_tail(&card->list, &qeth_core_card_list.list);
  3831. write_unlock_irqrestore(&qeth_core_card_list.rwlock, flags);
  3832. qeth_determine_capabilities(card);
  3833. return 0;
  3834. err_card:
  3835. qeth_core_free_card(card);
  3836. err_dev:
  3837. put_device(dev);
  3838. return rc;
  3839. }
  3840. static void qeth_core_remove_device(struct ccwgroup_device *gdev)
  3841. {
  3842. unsigned long flags;
  3843. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  3844. QETH_DBF_TEXT(SETUP, 2, "removedv");
  3845. if (card->discipline.ccwgdriver) {
  3846. card->discipline.ccwgdriver->remove(gdev);
  3847. qeth_core_free_discipline(card);
  3848. }
  3849. if (card->info.type == QETH_CARD_TYPE_OSN) {
  3850. qeth_core_remove_osn_attributes(&gdev->dev);
  3851. } else {
  3852. qeth_core_remove_device_attributes(&gdev->dev);
  3853. }
  3854. write_lock_irqsave(&qeth_core_card_list.rwlock, flags);
  3855. list_del(&card->list);
  3856. write_unlock_irqrestore(&qeth_core_card_list.rwlock, flags);
  3857. qeth_core_free_card(card);
  3858. dev_set_drvdata(&gdev->dev, NULL);
  3859. put_device(&gdev->dev);
  3860. return;
  3861. }
  3862. static int qeth_core_set_online(struct ccwgroup_device *gdev)
  3863. {
  3864. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  3865. int rc = 0;
  3866. int def_discipline;
  3867. if (!card->discipline.ccwgdriver) {
  3868. if (card->info.type == QETH_CARD_TYPE_IQD)
  3869. def_discipline = QETH_DISCIPLINE_LAYER3;
  3870. else
  3871. def_discipline = QETH_DISCIPLINE_LAYER2;
  3872. rc = qeth_core_load_discipline(card, def_discipline);
  3873. if (rc)
  3874. goto err;
  3875. rc = card->discipline.ccwgdriver->probe(card->gdev);
  3876. if (rc)
  3877. goto err;
  3878. }
  3879. rc = card->discipline.ccwgdriver->set_online(gdev);
  3880. err:
  3881. return rc;
  3882. }
  3883. static int qeth_core_set_offline(struct ccwgroup_device *gdev)
  3884. {
  3885. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  3886. return card->discipline.ccwgdriver->set_offline(gdev);
  3887. }
  3888. static void qeth_core_shutdown(struct ccwgroup_device *gdev)
  3889. {
  3890. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  3891. if (card->discipline.ccwgdriver &&
  3892. card->discipline.ccwgdriver->shutdown)
  3893. card->discipline.ccwgdriver->shutdown(gdev);
  3894. }
  3895. static int qeth_core_prepare(struct ccwgroup_device *gdev)
  3896. {
  3897. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  3898. if (card->discipline.ccwgdriver &&
  3899. card->discipline.ccwgdriver->prepare)
  3900. return card->discipline.ccwgdriver->prepare(gdev);
  3901. return 0;
  3902. }
  3903. static void qeth_core_complete(struct ccwgroup_device *gdev)
  3904. {
  3905. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  3906. if (card->discipline.ccwgdriver &&
  3907. card->discipline.ccwgdriver->complete)
  3908. card->discipline.ccwgdriver->complete(gdev);
  3909. }
  3910. static int qeth_core_freeze(struct ccwgroup_device *gdev)
  3911. {
  3912. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  3913. if (card->discipline.ccwgdriver &&
  3914. card->discipline.ccwgdriver->freeze)
  3915. return card->discipline.ccwgdriver->freeze(gdev);
  3916. return 0;
  3917. }
  3918. static int qeth_core_thaw(struct ccwgroup_device *gdev)
  3919. {
  3920. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  3921. if (card->discipline.ccwgdriver &&
  3922. card->discipline.ccwgdriver->thaw)
  3923. return card->discipline.ccwgdriver->thaw(gdev);
  3924. return 0;
  3925. }
  3926. static int qeth_core_restore(struct ccwgroup_device *gdev)
  3927. {
  3928. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  3929. if (card->discipline.ccwgdriver &&
  3930. card->discipline.ccwgdriver->restore)
  3931. return card->discipline.ccwgdriver->restore(gdev);
  3932. return 0;
  3933. }
  3934. static struct ccwgroup_driver qeth_core_ccwgroup_driver = {
  3935. .owner = THIS_MODULE,
  3936. .name = "qeth",
  3937. .driver_id = 0xD8C5E3C8,
  3938. .probe = qeth_core_probe_device,
  3939. .remove = qeth_core_remove_device,
  3940. .set_online = qeth_core_set_online,
  3941. .set_offline = qeth_core_set_offline,
  3942. .shutdown = qeth_core_shutdown,
  3943. .prepare = qeth_core_prepare,
  3944. .complete = qeth_core_complete,
  3945. .freeze = qeth_core_freeze,
  3946. .thaw = qeth_core_thaw,
  3947. .restore = qeth_core_restore,
  3948. };
  3949. static ssize_t
  3950. qeth_core_driver_group_store(struct device_driver *ddrv, const char *buf,
  3951. size_t count)
  3952. {
  3953. int err;
  3954. err = qeth_core_driver_group(buf, qeth_core_root_dev,
  3955. qeth_core_ccwgroup_driver.driver_id);
  3956. if (err)
  3957. return err;
  3958. else
  3959. return count;
  3960. }
  3961. static DRIVER_ATTR(group, 0200, NULL, qeth_core_driver_group_store);
  3962. static struct {
  3963. const char str[ETH_GSTRING_LEN];
  3964. } qeth_ethtool_stats_keys[] = {
  3965. /* 0 */{"rx skbs"},
  3966. {"rx buffers"},
  3967. {"tx skbs"},
  3968. {"tx buffers"},
  3969. {"tx skbs no packing"},
  3970. {"tx buffers no packing"},
  3971. {"tx skbs packing"},
  3972. {"tx buffers packing"},
  3973. {"tx sg skbs"},
  3974. {"tx sg frags"},
  3975. /* 10 */{"rx sg skbs"},
  3976. {"rx sg frags"},
  3977. {"rx sg page allocs"},
  3978. {"tx large kbytes"},
  3979. {"tx large count"},
  3980. {"tx pk state ch n->p"},
  3981. {"tx pk state ch p->n"},
  3982. {"tx pk watermark low"},
  3983. {"tx pk watermark high"},
  3984. {"queue 0 buffer usage"},
  3985. /* 20 */{"queue 1 buffer usage"},
  3986. {"queue 2 buffer usage"},
  3987. {"queue 3 buffer usage"},
  3988. {"rx handler time"},
  3989. {"rx handler count"},
  3990. {"rx do_QDIO time"},
  3991. {"rx do_QDIO count"},
  3992. {"tx handler time"},
  3993. {"tx handler count"},
  3994. {"tx time"},
  3995. /* 30 */{"tx count"},
  3996. {"tx do_QDIO time"},
  3997. {"tx do_QDIO count"},
  3998. {"tx csum"},
  3999. {"tx lin"},
  4000. };
  4001. int qeth_core_get_sset_count(struct net_device *dev, int stringset)
  4002. {
  4003. switch (stringset) {
  4004. case ETH_SS_STATS:
  4005. return (sizeof(qeth_ethtool_stats_keys) / ETH_GSTRING_LEN);
  4006. default:
  4007. return -EINVAL;
  4008. }
  4009. }
  4010. EXPORT_SYMBOL_GPL(qeth_core_get_sset_count);
  4011. void qeth_core_get_ethtool_stats(struct net_device *dev,
  4012. struct ethtool_stats *stats, u64 *data)
  4013. {
  4014. struct qeth_card *card = dev->ml_priv;
  4015. data[0] = card->stats.rx_packets -
  4016. card->perf_stats.initial_rx_packets;
  4017. data[1] = card->perf_stats.bufs_rec;
  4018. data[2] = card->stats.tx_packets -
  4019. card->perf_stats.initial_tx_packets;
  4020. data[3] = card->perf_stats.bufs_sent;
  4021. data[4] = card->stats.tx_packets - card->perf_stats.initial_tx_packets
  4022. - card->perf_stats.skbs_sent_pack;
  4023. data[5] = card->perf_stats.bufs_sent - card->perf_stats.bufs_sent_pack;
  4024. data[6] = card->perf_stats.skbs_sent_pack;
  4025. data[7] = card->perf_stats.bufs_sent_pack;
  4026. data[8] = card->perf_stats.sg_skbs_sent;
  4027. data[9] = card->perf_stats.sg_frags_sent;
  4028. data[10] = card->perf_stats.sg_skbs_rx;
  4029. data[11] = card->perf_stats.sg_frags_rx;
  4030. data[12] = card->perf_stats.sg_alloc_page_rx;
  4031. data[13] = (card->perf_stats.large_send_bytes >> 10);
  4032. data[14] = card->perf_stats.large_send_cnt;
  4033. data[15] = card->perf_stats.sc_dp_p;
  4034. data[16] = card->perf_stats.sc_p_dp;
  4035. data[17] = QETH_LOW_WATERMARK_PACK;
  4036. data[18] = QETH_HIGH_WATERMARK_PACK;
  4037. data[19] = atomic_read(&card->qdio.out_qs[0]->used_buffers);
  4038. data[20] = (card->qdio.no_out_queues > 1) ?
  4039. atomic_read(&card->qdio.out_qs[1]->used_buffers) : 0;
  4040. data[21] = (card->qdio.no_out_queues > 2) ?
  4041. atomic_read(&card->qdio.out_qs[2]->used_buffers) : 0;
  4042. data[22] = (card->qdio.no_out_queues > 3) ?
  4043. atomic_read(&card->qdio.out_qs[3]->used_buffers) : 0;
  4044. data[23] = card->perf_stats.inbound_time;
  4045. data[24] = card->perf_stats.inbound_cnt;
  4046. data[25] = card->perf_stats.inbound_do_qdio_time;
  4047. data[26] = card->perf_stats.inbound_do_qdio_cnt;
  4048. data[27] = card->perf_stats.outbound_handler_time;
  4049. data[28] = card->perf_stats.outbound_handler_cnt;
  4050. data[29] = card->perf_stats.outbound_time;
  4051. data[30] = card->perf_stats.outbound_cnt;
  4052. data[31] = card->perf_stats.outbound_do_qdio_time;
  4053. data[32] = card->perf_stats.outbound_do_qdio_cnt;
  4054. data[33] = card->perf_stats.tx_csum;
  4055. data[34] = card->perf_stats.tx_lin;
  4056. }
  4057. EXPORT_SYMBOL_GPL(qeth_core_get_ethtool_stats);
  4058. void qeth_core_get_strings(struct net_device *dev, u32 stringset, u8 *data)
  4059. {
  4060. switch (stringset) {
  4061. case ETH_SS_STATS:
  4062. memcpy(data, &qeth_ethtool_stats_keys,
  4063. sizeof(qeth_ethtool_stats_keys));
  4064. break;
  4065. default:
  4066. WARN_ON(1);
  4067. break;
  4068. }
  4069. }
  4070. EXPORT_SYMBOL_GPL(qeth_core_get_strings);
  4071. void qeth_core_get_drvinfo(struct net_device *dev,
  4072. struct ethtool_drvinfo *info)
  4073. {
  4074. struct qeth_card *card = dev->ml_priv;
  4075. if (card->options.layer2)
  4076. strcpy(info->driver, "qeth_l2");
  4077. else
  4078. strcpy(info->driver, "qeth_l3");
  4079. strcpy(info->version, "1.0");
  4080. strcpy(info->fw_version, card->info.mcl_level);
  4081. sprintf(info->bus_info, "%s/%s/%s",
  4082. CARD_RDEV_ID(card),
  4083. CARD_WDEV_ID(card),
  4084. CARD_DDEV_ID(card));
  4085. }
  4086. EXPORT_SYMBOL_GPL(qeth_core_get_drvinfo);
  4087. int qeth_core_ethtool_get_settings(struct net_device *netdev,
  4088. struct ethtool_cmd *ecmd)
  4089. {
  4090. struct qeth_card *card = netdev->ml_priv;
  4091. enum qeth_link_types link_type;
  4092. if ((card->info.type == QETH_CARD_TYPE_IQD) || (card->info.guestlan))
  4093. link_type = QETH_LINK_TYPE_10GBIT_ETH;
  4094. else
  4095. link_type = card->info.link_type;
  4096. ecmd->transceiver = XCVR_INTERNAL;
  4097. ecmd->supported = SUPPORTED_Autoneg;
  4098. ecmd->advertising = ADVERTISED_Autoneg;
  4099. ecmd->duplex = DUPLEX_FULL;
  4100. ecmd->autoneg = AUTONEG_ENABLE;
  4101. switch (link_type) {
  4102. case QETH_LINK_TYPE_FAST_ETH:
  4103. case QETH_LINK_TYPE_LANE_ETH100:
  4104. ecmd->supported |= SUPPORTED_10baseT_Half |
  4105. SUPPORTED_10baseT_Full |
  4106. SUPPORTED_100baseT_Half |
  4107. SUPPORTED_100baseT_Full |
  4108. SUPPORTED_TP;
  4109. ecmd->advertising |= ADVERTISED_10baseT_Half |
  4110. ADVERTISED_10baseT_Full |
  4111. ADVERTISED_100baseT_Half |
  4112. ADVERTISED_100baseT_Full |
  4113. ADVERTISED_TP;
  4114. ecmd->speed = SPEED_100;
  4115. ecmd->port = PORT_TP;
  4116. break;
  4117. case QETH_LINK_TYPE_GBIT_ETH:
  4118. case QETH_LINK_TYPE_LANE_ETH1000:
  4119. ecmd->supported |= SUPPORTED_10baseT_Half |
  4120. SUPPORTED_10baseT_Full |
  4121. SUPPORTED_100baseT_Half |
  4122. SUPPORTED_100baseT_Full |
  4123. SUPPORTED_1000baseT_Half |
  4124. SUPPORTED_1000baseT_Full |
  4125. SUPPORTED_FIBRE;
  4126. ecmd->advertising |= ADVERTISED_10baseT_Half |
  4127. ADVERTISED_10baseT_Full |
  4128. ADVERTISED_100baseT_Half |
  4129. ADVERTISED_100baseT_Full |
  4130. ADVERTISED_1000baseT_Half |
  4131. ADVERTISED_1000baseT_Full |
  4132. ADVERTISED_FIBRE;
  4133. ecmd->speed = SPEED_1000;
  4134. ecmd->port = PORT_FIBRE;
  4135. break;
  4136. case QETH_LINK_TYPE_10GBIT_ETH:
  4137. ecmd->supported |= SUPPORTED_10baseT_Half |
  4138. SUPPORTED_10baseT_Full |
  4139. SUPPORTED_100baseT_Half |
  4140. SUPPORTED_100baseT_Full |
  4141. SUPPORTED_1000baseT_Half |
  4142. SUPPORTED_1000baseT_Full |
  4143. SUPPORTED_10000baseT_Full |
  4144. SUPPORTED_FIBRE;
  4145. ecmd->advertising |= ADVERTISED_10baseT_Half |
  4146. ADVERTISED_10baseT_Full |
  4147. ADVERTISED_100baseT_Half |
  4148. ADVERTISED_100baseT_Full |
  4149. ADVERTISED_1000baseT_Half |
  4150. ADVERTISED_1000baseT_Full |
  4151. ADVERTISED_10000baseT_Full |
  4152. ADVERTISED_FIBRE;
  4153. ecmd->speed = SPEED_10000;
  4154. ecmd->port = PORT_FIBRE;
  4155. break;
  4156. default:
  4157. ecmd->supported |= SUPPORTED_10baseT_Half |
  4158. SUPPORTED_10baseT_Full |
  4159. SUPPORTED_TP;
  4160. ecmd->advertising |= ADVERTISED_10baseT_Half |
  4161. ADVERTISED_10baseT_Full |
  4162. ADVERTISED_TP;
  4163. ecmd->speed = SPEED_10;
  4164. ecmd->port = PORT_TP;
  4165. }
  4166. return 0;
  4167. }
  4168. EXPORT_SYMBOL_GPL(qeth_core_ethtool_get_settings);
  4169. static int __init qeth_core_init(void)
  4170. {
  4171. int rc;
  4172. pr_info("loading core functions\n");
  4173. INIT_LIST_HEAD(&qeth_core_card_list.list);
  4174. rwlock_init(&qeth_core_card_list.rwlock);
  4175. rc = qeth_register_dbf_views();
  4176. if (rc)
  4177. goto out_err;
  4178. rc = ccw_driver_register(&qeth_ccw_driver);
  4179. if (rc)
  4180. goto ccw_err;
  4181. rc = ccwgroup_driver_register(&qeth_core_ccwgroup_driver);
  4182. if (rc)
  4183. goto ccwgroup_err;
  4184. rc = driver_create_file(&qeth_core_ccwgroup_driver.driver,
  4185. &driver_attr_group);
  4186. if (rc)
  4187. goto driver_err;
  4188. qeth_core_root_dev = root_device_register("qeth");
  4189. rc = IS_ERR(qeth_core_root_dev) ? PTR_ERR(qeth_core_root_dev) : 0;
  4190. if (rc)
  4191. goto register_err;
  4192. qeth_core_header_cache = kmem_cache_create("qeth_hdr",
  4193. sizeof(struct qeth_hdr) + ETH_HLEN, 64, 0, NULL);
  4194. if (!qeth_core_header_cache) {
  4195. rc = -ENOMEM;
  4196. goto slab_err;
  4197. }
  4198. return 0;
  4199. slab_err:
  4200. root_device_unregister(qeth_core_root_dev);
  4201. register_err:
  4202. driver_remove_file(&qeth_core_ccwgroup_driver.driver,
  4203. &driver_attr_group);
  4204. driver_err:
  4205. ccwgroup_driver_unregister(&qeth_core_ccwgroup_driver);
  4206. ccwgroup_err:
  4207. ccw_driver_unregister(&qeth_ccw_driver);
  4208. ccw_err:
  4209. QETH_DBF_MESSAGE(2, "Initialization failed with code %d\n", rc);
  4210. qeth_unregister_dbf_views();
  4211. out_err:
  4212. pr_err("Initializing the qeth device driver failed\n");
  4213. return rc;
  4214. }
  4215. static void __exit qeth_core_exit(void)
  4216. {
  4217. root_device_unregister(qeth_core_root_dev);
  4218. driver_remove_file(&qeth_core_ccwgroup_driver.driver,
  4219. &driver_attr_group);
  4220. ccwgroup_driver_unregister(&qeth_core_ccwgroup_driver);
  4221. ccw_driver_unregister(&qeth_ccw_driver);
  4222. kmem_cache_destroy(qeth_core_header_cache);
  4223. qeth_unregister_dbf_views();
  4224. pr_info("core functions removed\n");
  4225. }
  4226. module_init(qeth_core_init);
  4227. module_exit(qeth_core_exit);
  4228. MODULE_AUTHOR("Frank Blaschka <frank.blaschka@de.ibm.com>");
  4229. MODULE_DESCRIPTION("qeth core functions");
  4230. MODULE_LICENSE("GPL");