netxen_nic_niu.c 23 KB

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  1. /*
  2. * Copyright (C) 2003 - 2006 NetXen, Inc.
  3. * All rights reserved.
  4. *
  5. * This program is free software; you can redistribute it and/or
  6. * modify it under the terms of the GNU General Public License
  7. * as published by the Free Software Foundation; either version 2
  8. * of the License, or (at your option) any later version.
  9. *
  10. * This program is distributed in the hope that it will be useful, but
  11. * WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, write to the Free Software
  17. * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
  18. * MA 02111-1307, USA.
  19. *
  20. * The full GNU General Public License is included in this distribution
  21. * in the file called LICENSE.
  22. *
  23. * Contact Information:
  24. * info@netxen.com
  25. * NetXen,
  26. * 3965 Freedom Circle, Fourth floor,
  27. * Santa Clara, CA 95054
  28. *
  29. *
  30. * Provides access to the Network Interface Unit h/w block.
  31. *
  32. */
  33. #include "netxen_nic.h"
  34. #define NETXEN_GB_MAC_SOFT_RESET 0x80000000
  35. #define NETXEN_GB_MAC_RESET_PROT_BLK 0x000F0000
  36. #define NETXEN_GB_MAC_ENABLE_TX_RX 0x00000005
  37. #define NETXEN_GB_MAC_PAUSED_FRMS 0x00000020
  38. static long phy_lock_timeout = 100000000;
  39. static inline int phy_lock(struct netxen_adapter *adapter)
  40. {
  41. int i;
  42. int done = 0, timeout = 0;
  43. while (!done) {
  44. done =
  45. readl(pci_base_offset
  46. (adapter, NETXEN_PCIE_REG(PCIE_SEM3_LOCK)));
  47. if (done == 1)
  48. break;
  49. if (timeout >= phy_lock_timeout) {
  50. return -1;
  51. }
  52. timeout++;
  53. if (!in_atomic())
  54. schedule();
  55. else {
  56. for (i = 0; i < 20; i++)
  57. cpu_relax();
  58. }
  59. }
  60. writel(PHY_LOCK_DRIVER,
  61. NETXEN_CRB_NORMALIZE(adapter, NETXEN_PHY_LOCK_ID));
  62. return 0;
  63. }
  64. static inline int phy_unlock(struct netxen_adapter *adapter)
  65. {
  66. readl(pci_base_offset(adapter, NETXEN_PCIE_REG(PCIE_SEM3_UNLOCK)));
  67. return 0;
  68. }
  69. /*
  70. * netxen_niu_gbe_phy_read - read a register from the GbE PHY via
  71. * mii management interface.
  72. *
  73. * Note: The MII management interface goes through port 0.
  74. * Individual phys are addressed as follows:
  75. * @param phy [15:8] phy id
  76. * @param reg [7:0] register number
  77. *
  78. * @returns 0 on success
  79. * -1 on error
  80. *
  81. */
  82. int netxen_niu_gbe_phy_read(struct netxen_adapter *adapter, long phy,
  83. long reg, __u32 * readval)
  84. {
  85. long timeout = 0;
  86. long result = 0;
  87. long restore = 0;
  88. __u32 address;
  89. __u32 command;
  90. __u32 status;
  91. __u32 mac_cfg0;
  92. if (phy_lock(adapter) != 0) {
  93. return -1;
  94. }
  95. /*
  96. * MII mgmt all goes through port 0 MAC interface,
  97. * so it cannot be in reset
  98. */
  99. if (netxen_nic_hw_read_wx(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(0),
  100. &mac_cfg0, 4))
  101. return -EIO;
  102. if (netxen_gb_get_soft_reset(mac_cfg0)) {
  103. __u32 temp;
  104. temp = 0;
  105. netxen_gb_tx_reset_pb(temp);
  106. netxen_gb_rx_reset_pb(temp);
  107. netxen_gb_tx_reset_mac(temp);
  108. netxen_gb_rx_reset_mac(temp);
  109. if (netxen_nic_hw_write_wx(adapter,
  110. NETXEN_NIU_GB_MAC_CONFIG_0(0),
  111. &temp, 4))
  112. return -EIO;
  113. restore = 1;
  114. }
  115. address = 0;
  116. netxen_gb_mii_mgmt_reg_addr(address, reg);
  117. netxen_gb_mii_mgmt_phy_addr(address, phy);
  118. if (netxen_nic_hw_write_wx(adapter, NETXEN_NIU_GB_MII_MGMT_ADDR(0),
  119. &address, 4))
  120. return -EIO;
  121. command = 0; /* turn off any prior activity */
  122. if (netxen_nic_hw_write_wx(adapter, NETXEN_NIU_GB_MII_MGMT_COMMAND(0),
  123. &command, 4))
  124. return -EIO;
  125. /* send read command */
  126. netxen_gb_mii_mgmt_set_read_cycle(command);
  127. if (netxen_nic_hw_write_wx(adapter, NETXEN_NIU_GB_MII_MGMT_COMMAND(0),
  128. &command, 4))
  129. return -EIO;
  130. status = 0;
  131. do {
  132. if (netxen_nic_hw_read_wx(adapter,
  133. NETXEN_NIU_GB_MII_MGMT_INDICATE(0),
  134. &status, 4))
  135. return -EIO;
  136. timeout++;
  137. } while ((netxen_get_gb_mii_mgmt_busy(status)
  138. || netxen_get_gb_mii_mgmt_notvalid(status))
  139. && (timeout++ < NETXEN_NIU_PHY_WAITMAX));
  140. if (timeout < NETXEN_NIU_PHY_WAITMAX) {
  141. if (netxen_nic_hw_read_wx(adapter,
  142. NETXEN_NIU_GB_MII_MGMT_STATUS(0),
  143. readval, 4))
  144. return -EIO;
  145. result = 0;
  146. } else
  147. result = -1;
  148. if (restore)
  149. if (netxen_nic_hw_write_wx(adapter,
  150. NETXEN_NIU_GB_MAC_CONFIG_0(0),
  151. &mac_cfg0, 4))
  152. return -EIO;
  153. phy_unlock(adapter);
  154. return result;
  155. }
  156. /*
  157. * netxen_niu_gbe_phy_write - write a register to the GbE PHY via
  158. * mii management interface.
  159. *
  160. * Note: The MII management interface goes through port 0.
  161. * Individual phys are addressed as follows:
  162. * @param phy [15:8] phy id
  163. * @param reg [7:0] register number
  164. *
  165. * @returns 0 on success
  166. * -1 on error
  167. *
  168. */
  169. int netxen_niu_gbe_phy_write(struct netxen_adapter *adapter,
  170. long phy, long reg, __u32 val)
  171. {
  172. long timeout = 0;
  173. long result = 0;
  174. long restore = 0;
  175. __u32 address;
  176. __u32 command;
  177. __u32 status;
  178. __u32 mac_cfg0;
  179. /*
  180. * MII mgmt all goes through port 0 MAC interface, so it
  181. * cannot be in reset
  182. */
  183. if (netxen_nic_hw_read_wx(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(0),
  184. &mac_cfg0, 4))
  185. return -EIO;
  186. if (netxen_gb_get_soft_reset(mac_cfg0)) {
  187. __u32 temp;
  188. temp = 0;
  189. netxen_gb_tx_reset_pb(temp);
  190. netxen_gb_rx_reset_pb(temp);
  191. netxen_gb_tx_reset_mac(temp);
  192. netxen_gb_rx_reset_mac(temp);
  193. if (netxen_nic_hw_write_wx(adapter,
  194. NETXEN_NIU_GB_MAC_CONFIG_0(0),
  195. &temp, 4))
  196. return -EIO;
  197. restore = 1;
  198. }
  199. command = 0; /* turn off any prior activity */
  200. if (netxen_nic_hw_write_wx(adapter, NETXEN_NIU_GB_MII_MGMT_COMMAND(0),
  201. &command, 4))
  202. return -EIO;
  203. address = 0;
  204. netxen_gb_mii_mgmt_reg_addr(address, reg);
  205. netxen_gb_mii_mgmt_phy_addr(address, phy);
  206. if (netxen_nic_hw_write_wx(adapter, NETXEN_NIU_GB_MII_MGMT_ADDR(0),
  207. &address, 4))
  208. return -EIO;
  209. if (netxen_nic_hw_write_wx(adapter, NETXEN_NIU_GB_MII_MGMT_CTRL(0),
  210. &val, 4))
  211. return -EIO;
  212. status = 0;
  213. do {
  214. if (netxen_nic_hw_read_wx(adapter,
  215. NETXEN_NIU_GB_MII_MGMT_INDICATE(0),
  216. &status, 4))
  217. return -EIO;
  218. timeout++;
  219. } while ((netxen_get_gb_mii_mgmt_busy(status))
  220. && (timeout++ < NETXEN_NIU_PHY_WAITMAX));
  221. if (timeout < NETXEN_NIU_PHY_WAITMAX)
  222. result = 0;
  223. else
  224. result = -EIO;
  225. /* restore the state of port 0 MAC in case we tampered with it */
  226. if (restore)
  227. if (netxen_nic_hw_write_wx(adapter,
  228. NETXEN_NIU_GB_MAC_CONFIG_0(0),
  229. &mac_cfg0, 4))
  230. return -EIO;
  231. return result;
  232. }
  233. int netxen_niu_xgbe_enable_phy_interrupts(struct netxen_adapter *adapter,
  234. int port)
  235. {
  236. netxen_crb_writelit_adapter(adapter, NETXEN_NIU_INT_MASK, 0x3f);
  237. return 0;
  238. }
  239. int netxen_niu_gbe_enable_phy_interrupts(struct netxen_adapter *adapter,
  240. int port)
  241. {
  242. int result = 0;
  243. __u32 enable = 0;
  244. netxen_set_phy_int_link_status_changed(enable);
  245. netxen_set_phy_int_autoneg_completed(enable);
  246. netxen_set_phy_int_speed_changed(enable);
  247. if (0 !=
  248. netxen_niu_gbe_phy_write(adapter, port,
  249. NETXEN_NIU_GB_MII_MGMT_ADDR_INT_ENABLE,
  250. enable))
  251. result = -EIO;
  252. return result;
  253. }
  254. int netxen_niu_xgbe_disable_phy_interrupts(struct netxen_adapter *adapter,
  255. int port)
  256. {
  257. netxen_crb_writelit_adapter(adapter, NETXEN_NIU_INT_MASK, 0x7f);
  258. return 0;
  259. }
  260. int netxen_niu_gbe_disable_phy_interrupts(struct netxen_adapter *adapter,
  261. int port)
  262. {
  263. int result = 0;
  264. if (0 !=
  265. netxen_niu_gbe_phy_write(adapter, port,
  266. NETXEN_NIU_GB_MII_MGMT_ADDR_INT_ENABLE, 0))
  267. result = -EIO;
  268. return result;
  269. }
  270. int netxen_niu_xgbe_clear_phy_interrupts(struct netxen_adapter *adapter,
  271. int port)
  272. {
  273. netxen_crb_writelit_adapter(adapter, NETXEN_NIU_ACTIVE_INT, -1);
  274. return 0;
  275. }
  276. int netxen_niu_gbe_clear_phy_interrupts(struct netxen_adapter *adapter,
  277. int port)
  278. {
  279. int result = 0;
  280. if (0 !=
  281. netxen_niu_gbe_phy_write(adapter, port,
  282. NETXEN_NIU_GB_MII_MGMT_ADDR_INT_STATUS,
  283. -EIO))
  284. result = -EIO;
  285. return result;
  286. }
  287. /*
  288. * netxen_niu_gbe_set_mii_mode- Set 10/100 Mbit Mode for GbE MAC
  289. *
  290. */
  291. void netxen_niu_gbe_set_mii_mode(struct netxen_adapter *adapter,
  292. int port, long enable)
  293. {
  294. netxen_crb_writelit_adapter(adapter, NETXEN_NIU_MODE, 0x2);
  295. netxen_crb_writelit_adapter(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(port),
  296. 0x80000000);
  297. netxen_crb_writelit_adapter(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(port),
  298. 0x0000f0025);
  299. netxen_crb_writelit_adapter(adapter, NETXEN_NIU_GB_MAC_CONFIG_1(port),
  300. 0xf1ff);
  301. netxen_crb_writelit_adapter(adapter,
  302. NETXEN_NIU_GB0_GMII_MODE + (port << 3), 0);
  303. netxen_crb_writelit_adapter(adapter,
  304. NETXEN_NIU_GB0_MII_MODE + (port << 3), 1);
  305. netxen_crb_writelit_adapter(adapter,
  306. (NETXEN_NIU_GB0_HALF_DUPLEX + port * 4), 0);
  307. netxen_crb_writelit_adapter(adapter,
  308. NETXEN_NIU_GB_MII_MGMT_CONFIG(port), 0x7);
  309. if (enable) {
  310. /*
  311. * Do NOT enable flow control until a suitable solution for
  312. * shutting down pause frames is found.
  313. */
  314. netxen_crb_writelit_adapter(adapter,
  315. NETXEN_NIU_GB_MAC_CONFIG_0(port),
  316. 0x5);
  317. }
  318. if (netxen_niu_gbe_enable_phy_interrupts(adapter, port))
  319. printk(KERN_ERR PFX "ERROR enabling PHY interrupts\n");
  320. if (netxen_niu_gbe_clear_phy_interrupts(adapter, port))
  321. printk(KERN_ERR PFX "ERROR clearing PHY interrupts\n");
  322. }
  323. /*
  324. * netxen_niu_gbe_set_gmii_mode- Set GbE Mode for GbE MAC
  325. */
  326. void netxen_niu_gbe_set_gmii_mode(struct netxen_adapter *adapter,
  327. int port, long enable)
  328. {
  329. netxen_crb_writelit_adapter(adapter, NETXEN_NIU_MODE, 0x2);
  330. netxen_crb_writelit_adapter(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(port),
  331. 0x80000000);
  332. netxen_crb_writelit_adapter(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(port),
  333. 0x0000f0025);
  334. netxen_crb_writelit_adapter(adapter, NETXEN_NIU_GB_MAC_CONFIG_1(port),
  335. 0xf2ff);
  336. netxen_crb_writelit_adapter(adapter,
  337. NETXEN_NIU_GB0_MII_MODE + (port << 3), 0);
  338. netxen_crb_writelit_adapter(adapter,
  339. NETXEN_NIU_GB0_GMII_MODE + (port << 3), 1);
  340. netxen_crb_writelit_adapter(adapter,
  341. (NETXEN_NIU_GB0_HALF_DUPLEX + port * 4), 0);
  342. netxen_crb_writelit_adapter(adapter,
  343. NETXEN_NIU_GB_MII_MGMT_CONFIG(port), 0x7);
  344. if (enable) {
  345. /*
  346. * Do NOT enable flow control until a suitable solution for
  347. * shutting down pause frames is found.
  348. */
  349. netxen_crb_writelit_adapter(adapter,
  350. NETXEN_NIU_GB_MAC_CONFIG_0(port),
  351. 0x5);
  352. }
  353. if (netxen_niu_gbe_enable_phy_interrupts(adapter, port))
  354. printk(KERN_ERR PFX "ERROR enabling PHY interrupts\n");
  355. if (netxen_niu_gbe_clear_phy_interrupts(adapter, port))
  356. printk(KERN_ERR PFX "ERROR clearing PHY interrupts\n");
  357. }
  358. int netxen_niu_gbe_init_port(struct netxen_adapter *adapter, int port)
  359. {
  360. int result = 0;
  361. __u32 status;
  362. if (adapter->disable_phy_interrupts)
  363. adapter->disable_phy_interrupts(adapter, port);
  364. mdelay(2);
  365. if (0 ==
  366. netxen_niu_gbe_phy_read(adapter, port,
  367. NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_STATUS,
  368. &status)) {
  369. if (netxen_get_phy_link(status)) {
  370. if (netxen_get_phy_speed(status) == 2) {
  371. netxen_niu_gbe_set_gmii_mode(adapter, port, 1);
  372. } else if ((netxen_get_phy_speed(status) == 1)
  373. || (netxen_get_phy_speed(status) == 0)) {
  374. netxen_niu_gbe_set_mii_mode(adapter, port, 1);
  375. } else {
  376. result = -1;
  377. }
  378. } else {
  379. /*
  380. * We don't have link. Cable must be unconnected.
  381. * Enable phy interrupts so we take action when
  382. * plugged in.
  383. */
  384. netxen_crb_writelit_adapter(adapter,
  385. NETXEN_NIU_GB_MAC_CONFIG_0
  386. (port),
  387. NETXEN_GB_MAC_SOFT_RESET);
  388. netxen_crb_writelit_adapter(adapter,
  389. NETXEN_NIU_GB_MAC_CONFIG_0
  390. (port),
  391. NETXEN_GB_MAC_RESET_PROT_BLK
  392. | NETXEN_GB_MAC_ENABLE_TX_RX
  393. |
  394. NETXEN_GB_MAC_PAUSED_FRMS);
  395. if (netxen_niu_gbe_clear_phy_interrupts(adapter, port))
  396. printk(KERN_ERR PFX
  397. "ERROR clearing PHY interrupts\n");
  398. if (netxen_niu_gbe_enable_phy_interrupts(adapter, port))
  399. printk(KERN_ERR PFX
  400. "ERROR enabling PHY interrupts\n");
  401. if (netxen_niu_gbe_clear_phy_interrupts(adapter, port))
  402. printk(KERN_ERR PFX
  403. "ERROR clearing PHY interrupts\n");
  404. result = -1;
  405. }
  406. } else {
  407. result = -EIO;
  408. }
  409. return result;
  410. }
  411. int netxen_niu_xg_init_port(struct netxen_adapter *adapter, int port)
  412. {
  413. long reg = 0, ret = 0;
  414. if (adapter->ahw.boardcfg.board_type == NETXEN_BRDTYPE_P2_SB31_10G_IMEZ) {
  415. netxen_crb_writelit_adapter(adapter,
  416. NETXEN_NIU_XG1_CONFIG_0, 0x5);
  417. /* XXX hack for Mez cards: both ports in promisc mode */
  418. netxen_nic_hw_read_wx(adapter,
  419. NETXEN_NIU_XGE_CONFIG_1, &reg, 4);
  420. reg = (reg | 0x2000UL);
  421. netxen_crb_writelit_adapter(adapter,
  422. NETXEN_NIU_XGE_CONFIG_1, reg);
  423. reg = 0;
  424. netxen_nic_hw_read_wx(adapter,
  425. NETXEN_NIU_XG1_CONFIG_1, &reg, 4);
  426. reg = (reg | 0x2000UL);
  427. netxen_crb_writelit_adapter(adapter,
  428. NETXEN_NIU_XG1_CONFIG_1, reg);
  429. }
  430. return ret;
  431. }
  432. /*
  433. * netxen_niu_gbe_handle_phy_interrupt - Handles GbE PHY interrupts
  434. * @param enable 0 means don't enable the port
  435. * 1 means enable (or re-enable) the port
  436. */
  437. int netxen_niu_gbe_handle_phy_interrupt(struct netxen_adapter *adapter,
  438. int port, long enable)
  439. {
  440. int result = 0;
  441. __u32 int_src;
  442. printk(KERN_INFO PFX "NETXEN: Handling PHY interrupt on port %d"
  443. " (device enable = %d)\n", (int)port, (int)enable);
  444. /*
  445. * The read of the PHY INT status will clear the pending
  446. * interrupt status
  447. */
  448. if (netxen_niu_gbe_phy_read(adapter, port,
  449. NETXEN_NIU_GB_MII_MGMT_ADDR_INT_STATUS,
  450. &int_src) != 0)
  451. result = -EINVAL;
  452. else {
  453. printk(KERN_INFO PFX "PHY Interrupt source = 0x%x \n", int_src);
  454. if (netxen_get_phy_int_jabber(int_src))
  455. printk(KERN_INFO PFX "jabber Interrupt ");
  456. if (netxen_get_phy_int_polarity_changed(int_src))
  457. printk(KERN_INFO PFX "polarity changed ");
  458. if (netxen_get_phy_int_energy_detect(int_src))
  459. printk(KERN_INFO PFX "energy detect \n");
  460. if (netxen_get_phy_int_downshift(int_src))
  461. printk(KERN_INFO PFX "downshift \n");
  462. if (netxen_get_phy_int_mdi_xover_changed(int_src))
  463. printk(KERN_INFO PFX "mdi_xover_changed ");
  464. if (netxen_get_phy_int_fifo_over_underflow(int_src))
  465. printk(KERN_INFO PFX "fifo_over_underflow ");
  466. if (netxen_get_phy_int_false_carrier(int_src))
  467. printk(KERN_INFO PFX "false_carrier ");
  468. if (netxen_get_phy_int_symbol_error(int_src))
  469. printk(KERN_INFO PFX "symbol_error ");
  470. if (netxen_get_phy_int_autoneg_completed(int_src))
  471. printk(KERN_INFO PFX "autoneg_completed ");
  472. if (netxen_get_phy_int_page_received(int_src))
  473. printk(KERN_INFO PFX "page_received ");
  474. if (netxen_get_phy_int_duplex_changed(int_src))
  475. printk(KERN_INFO PFX "duplex_changed ");
  476. if (netxen_get_phy_int_autoneg_error(int_src))
  477. printk(KERN_INFO PFX "autoneg_error ");
  478. if ((netxen_get_phy_int_speed_changed(int_src))
  479. || (netxen_get_phy_int_link_status_changed(int_src))) {
  480. __u32 status;
  481. printk(KERN_INFO PFX
  482. "speed_changed or link status changed");
  483. if (netxen_niu_gbe_phy_read
  484. (adapter, port,
  485. NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_STATUS,
  486. &status) == 0) {
  487. if (netxen_get_phy_speed(status) == 2) {
  488. printk
  489. (KERN_INFO PFX "Link speed changed"
  490. " to 1000 Mbps\n");
  491. netxen_niu_gbe_set_gmii_mode(adapter,
  492. port,
  493. enable);
  494. } else if (netxen_get_phy_speed(status) == 1) {
  495. printk
  496. (KERN_INFO PFX "Link speed changed"
  497. " to 100 Mbps\n");
  498. netxen_niu_gbe_set_mii_mode(adapter,
  499. port,
  500. enable);
  501. } else if (netxen_get_phy_speed(status) == 0) {
  502. printk
  503. (KERN_INFO PFX "Link speed changed"
  504. " to 10 Mbps\n");
  505. netxen_niu_gbe_set_mii_mode(adapter,
  506. port,
  507. enable);
  508. } else {
  509. printk(KERN_ERR PFX "ERROR reading"
  510. "PHY status. Illegal speed.\n");
  511. result = -1;
  512. }
  513. } else {
  514. printk(KERN_ERR PFX
  515. "ERROR reading PHY status.\n");
  516. result = -1;
  517. }
  518. }
  519. printk(KERN_INFO "\n");
  520. }
  521. return result;
  522. }
  523. /*
  524. * Return the current station MAC address.
  525. * Note that the passed-in value must already be in network byte order.
  526. */
  527. int netxen_niu_macaddr_get(struct netxen_adapter *adapter,
  528. int phy, netxen_ethernet_macaddr_t * addr)
  529. {
  530. u32 stationhigh;
  531. u32 stationlow;
  532. u8 val[8];
  533. if (addr == NULL)
  534. return -EINVAL;
  535. if ((phy < 0) || (phy > 3))
  536. return -EINVAL;
  537. if (netxen_nic_hw_read_wx(adapter, NETXEN_NIU_GB_STATION_ADDR_0(phy),
  538. &stationhigh, 4))
  539. return -EIO;
  540. if (netxen_nic_hw_read_wx(adapter, NETXEN_NIU_GB_STATION_ADDR_1(phy),
  541. &stationlow, 4))
  542. return -EIO;
  543. ((__le32 *)val)[1] = cpu_to_le32(stationhigh);
  544. ((__le32 *)val)[0] = cpu_to_le32(stationlow);
  545. memcpy(addr, val + 2, 6);
  546. return 0;
  547. }
  548. /*
  549. * Set the station MAC address.
  550. * Note that the passed-in value must already be in network byte order.
  551. */
  552. int netxen_niu_macaddr_set(struct netxen_port *port,
  553. netxen_ethernet_macaddr_t addr)
  554. {
  555. u8 temp[4];
  556. u32 val;
  557. struct netxen_adapter *adapter = port->adapter;
  558. int phy = port->portnum;
  559. unsigned char mac_addr[6];
  560. int i;
  561. for (i = 0; i < 10; i++) {
  562. temp[0] = temp[1] = 0;
  563. memcpy(temp + 2, addr, 2);
  564. val = le32_to_cpu(*(__le32 *)temp);
  565. if (netxen_nic_hw_write_wx
  566. (adapter, NETXEN_NIU_GB_STATION_ADDR_1(phy), &val, 4))
  567. return -EIO;
  568. memcpy(temp, ((u8 *) addr) + 2, sizeof(__le32));
  569. val = le32_to_cpu(*(__le32 *)temp);
  570. if (netxen_nic_hw_write_wx
  571. (adapter, NETXEN_NIU_GB_STATION_ADDR_0(phy), &val, 4))
  572. return -2;
  573. netxen_niu_macaddr_get(adapter, phy,
  574. (netxen_ethernet_macaddr_t *) mac_addr);
  575. if (memcmp(mac_addr, addr, 6) == 0)
  576. break;
  577. }
  578. if (i == 10) {
  579. printk(KERN_ERR "%s: cannot set Mac addr for %s\n",
  580. netxen_nic_driver_name, port->netdev->name);
  581. printk(KERN_ERR "MAC address set: "
  582. "%02x:%02x:%02x:%02x:%02x:%02x.\n",
  583. addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]);
  584. printk(KERN_ERR "MAC address get: "
  585. "%02x:%02x:%02x:%02x:%02x:%02x.\n",
  586. mac_addr[0],
  587. mac_addr[1],
  588. mac_addr[2], mac_addr[3], mac_addr[4], mac_addr[5]);
  589. }
  590. return 0;
  591. }
  592. /* Enable a GbE interface */
  593. int netxen_niu_enable_gbe_port(struct netxen_adapter *adapter,
  594. int port, netxen_niu_gbe_ifmode_t mode)
  595. {
  596. __u32 mac_cfg0;
  597. __u32 mac_cfg1;
  598. __u32 mii_cfg;
  599. if ((port < 0) || (port > NETXEN_NIU_MAX_GBE_PORTS))
  600. return -EINVAL;
  601. mac_cfg0 = 0;
  602. netxen_gb_soft_reset(mac_cfg0);
  603. if (netxen_nic_hw_write_wx(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(port),
  604. &mac_cfg0, 4))
  605. return -EIO;
  606. mac_cfg0 = 0;
  607. netxen_gb_enable_tx(mac_cfg0);
  608. netxen_gb_enable_rx(mac_cfg0);
  609. netxen_gb_unset_rx_flowctl(mac_cfg0);
  610. netxen_gb_tx_reset_pb(mac_cfg0);
  611. netxen_gb_rx_reset_pb(mac_cfg0);
  612. netxen_gb_tx_reset_mac(mac_cfg0);
  613. netxen_gb_rx_reset_mac(mac_cfg0);
  614. if (netxen_nic_hw_write_wx(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(port),
  615. &mac_cfg0, 4))
  616. return -EIO;
  617. mac_cfg1 = 0;
  618. netxen_gb_set_preamblelen(mac_cfg1, 0xf);
  619. netxen_gb_set_duplex(mac_cfg1);
  620. netxen_gb_set_crc_enable(mac_cfg1);
  621. netxen_gb_set_padshort(mac_cfg1);
  622. netxen_gb_set_checklength(mac_cfg1);
  623. netxen_gb_set_hugeframes(mac_cfg1);
  624. if (mode == NETXEN_NIU_10_100_MB) {
  625. netxen_gb_set_intfmode(mac_cfg1, 1);
  626. if (netxen_nic_hw_write_wx(adapter,
  627. NETXEN_NIU_GB_MAC_CONFIG_1(port),
  628. &mac_cfg1, 4))
  629. return -EIO;
  630. /* set mii mode */
  631. netxen_crb_writelit_adapter(adapter, NETXEN_NIU_GB0_GMII_MODE +
  632. (port << 3), 0);
  633. netxen_crb_writelit_adapter(adapter, NETXEN_NIU_GB0_MII_MODE +
  634. (port << 3), 1);
  635. } else if (mode == NETXEN_NIU_1000_MB) {
  636. netxen_gb_set_intfmode(mac_cfg1, 2);
  637. if (netxen_nic_hw_write_wx(adapter,
  638. NETXEN_NIU_GB_MAC_CONFIG_1(port),
  639. &mac_cfg1, 4))
  640. return -EIO;
  641. /* set gmii mode */
  642. netxen_crb_writelit_adapter(adapter, NETXEN_NIU_GB0_MII_MODE +
  643. (port << 3), 0);
  644. netxen_crb_writelit_adapter(adapter, NETXEN_NIU_GB0_GMII_MODE +
  645. (port << 3), 1);
  646. }
  647. mii_cfg = 0;
  648. netxen_gb_set_mii_mgmt_clockselect(mii_cfg, 7);
  649. if (netxen_nic_hw_write_wx(adapter, NETXEN_NIU_GB_MII_MGMT_CONFIG(port),
  650. &mii_cfg, 4))
  651. return -EIO;
  652. mac_cfg0 = 0;
  653. netxen_gb_enable_tx(mac_cfg0);
  654. netxen_gb_enable_rx(mac_cfg0);
  655. netxen_gb_unset_rx_flowctl(mac_cfg0);
  656. netxen_gb_unset_tx_flowctl(mac_cfg0);
  657. if (netxen_nic_hw_write_wx(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(port),
  658. &mac_cfg0, 4))
  659. return -EIO;
  660. return 0;
  661. }
  662. /* Disable a GbE interface */
  663. int netxen_niu_disable_gbe_port(struct netxen_adapter *adapter, int port)
  664. {
  665. __u32 mac_cfg0;
  666. if ((port < 0) || (port > NETXEN_NIU_MAX_GBE_PORTS))
  667. return -EINVAL;
  668. mac_cfg0 = 0;
  669. netxen_gb_soft_reset(mac_cfg0);
  670. if (netxen_nic_hw_write_wx(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(port),
  671. &mac_cfg0, 4))
  672. return -EIO;
  673. return 0;
  674. }
  675. /* Disable an XG interface */
  676. int netxen_niu_disable_xg_port(struct netxen_adapter *adapter, int port)
  677. {
  678. __u32 mac_cfg;
  679. if (port != 0)
  680. return -EINVAL;
  681. mac_cfg = 0;
  682. netxen_xg_soft_reset(mac_cfg);
  683. if (netxen_nic_hw_write_wx(adapter, NETXEN_NIU_XGE_CONFIG_0,
  684. &mac_cfg, 4))
  685. return -EIO;
  686. return 0;
  687. }
  688. /* Set promiscuous mode for a GbE interface */
  689. int netxen_niu_set_promiscuous_mode(struct netxen_adapter *adapter, int port,
  690. netxen_niu_prom_mode_t mode)
  691. {
  692. __u32 reg;
  693. if ((port < 0) || (port > NETXEN_NIU_MAX_GBE_PORTS))
  694. return -EINVAL;
  695. /* save previous contents */
  696. if (netxen_nic_hw_read_wx(adapter, NETXEN_NIU_GB_DROP_WRONGADDR,
  697. &reg, 4))
  698. return -EIO;
  699. if (mode == NETXEN_NIU_PROMISC_MODE) {
  700. switch (port) {
  701. case 0:
  702. netxen_clear_gb_drop_gb0(reg);
  703. break;
  704. case 1:
  705. netxen_clear_gb_drop_gb1(reg);
  706. break;
  707. case 2:
  708. netxen_clear_gb_drop_gb2(reg);
  709. break;
  710. case 3:
  711. netxen_clear_gb_drop_gb3(reg);
  712. break;
  713. default:
  714. return -EIO;
  715. }
  716. } else {
  717. switch (port) {
  718. case 0:
  719. netxen_set_gb_drop_gb0(reg);
  720. break;
  721. case 1:
  722. netxen_set_gb_drop_gb1(reg);
  723. break;
  724. case 2:
  725. netxen_set_gb_drop_gb2(reg);
  726. break;
  727. case 3:
  728. netxen_set_gb_drop_gb3(reg);
  729. break;
  730. default:
  731. return -EIO;
  732. }
  733. }
  734. if (netxen_nic_hw_write_wx(adapter, NETXEN_NIU_GB_DROP_WRONGADDR,
  735. &reg, 4))
  736. return -EIO;
  737. return 0;
  738. }
  739. /*
  740. * Set the MAC address for an XG port
  741. * Note that the passed-in value must already be in network byte order.
  742. */
  743. int netxen_niu_xg_macaddr_set(struct netxen_port *port,
  744. netxen_ethernet_macaddr_t addr)
  745. {
  746. u8 temp[4];
  747. u32 val;
  748. struct netxen_adapter *adapter = port->adapter;
  749. temp[0] = temp[1] = 0;
  750. memcpy(temp + 2, addr, 2);
  751. val = le32_to_cpu(*(__le32 *)temp);
  752. if (netxen_nic_hw_write_wx(adapter, NETXEN_NIU_XGE_STATION_ADDR_0_1,
  753. &val, 4))
  754. return -EIO;
  755. memcpy(&temp, ((u8 *) addr) + 2, sizeof(__le32));
  756. val = le32_to_cpu(*(__le32 *)temp);
  757. if (netxen_nic_hw_write_wx(adapter, NETXEN_NIU_XGE_STATION_ADDR_0_HI,
  758. &val, 4))
  759. return -EIO;
  760. return 0;
  761. }
  762. /*
  763. * Return the current station MAC address.
  764. * Note that the passed-in value must already be in network byte order.
  765. */
  766. int netxen_niu_xg_macaddr_get(struct netxen_adapter *adapter, int phy,
  767. netxen_ethernet_macaddr_t * addr)
  768. {
  769. u32 stationhigh;
  770. u32 stationlow;
  771. u8 val[8];
  772. if (addr == NULL)
  773. return -EINVAL;
  774. if (phy != 0)
  775. return -EINVAL;
  776. if (netxen_nic_hw_read_wx(adapter, NETXEN_NIU_XGE_STATION_ADDR_0_HI,
  777. &stationhigh, 4))
  778. return -EIO;
  779. if (netxen_nic_hw_read_wx(adapter, NETXEN_NIU_XGE_STATION_ADDR_0_1,
  780. &stationlow, 4))
  781. return -EIO;
  782. ((__le32 *)val)[1] = cpu_to_le32(stationhigh);
  783. ((__le32 *)val)[0] = cpu_to_le32(stationlow);
  784. memcpy(addr, val + 2, 6);
  785. return 0;
  786. }
  787. int netxen_niu_xg_set_promiscuous_mode(struct netxen_adapter *adapter,
  788. int port, netxen_niu_prom_mode_t mode)
  789. {
  790. __u32 reg;
  791. if ((port < 0) || (port > NETXEN_NIU_MAX_GBE_PORTS))
  792. return -EINVAL;
  793. if (netxen_nic_hw_read_wx(adapter, NETXEN_NIU_XGE_CONFIG_1, &reg, 4))
  794. return -EIO;
  795. if (mode == NETXEN_NIU_PROMISC_MODE)
  796. reg = (reg | 0x2000UL);
  797. else
  798. reg = (reg & ~0x2000UL);
  799. netxen_crb_writelit_adapter(adapter, NETXEN_NIU_XGE_CONFIG_1, reg);
  800. return 0;
  801. }