netxen_nic_init.c 40 KB

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  1. /*
  2. * Copyright (C) 2003 - 2006 NetXen, Inc.
  3. * All rights reserved.
  4. *
  5. * This program is free software; you can redistribute it and/or
  6. * modify it under the terms of the GNU General Public License
  7. * as published by the Free Software Foundation; either version 2
  8. * of the License, or (at your option) any later version.
  9. *
  10. * This program is distributed in the hope that it will be useful, but
  11. * WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, write to the Free Software
  17. * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
  18. * MA 02111-1307, USA.
  19. *
  20. * The full GNU General Public License is included in this distribution
  21. * in the file called LICENSE.
  22. *
  23. * Contact Information:
  24. * info@netxen.com
  25. * NetXen,
  26. * 3965 Freedom Circle, Fourth floor,
  27. * Santa Clara, CA 95054
  28. *
  29. *
  30. * Source file for NIC routines to initialize the Phantom Hardware
  31. *
  32. */
  33. #include <linux/netdevice.h>
  34. #include <linux/delay.h>
  35. #include "netxen_nic.h"
  36. #include "netxen_nic_hw.h"
  37. #include "netxen_nic_phan_reg.h"
  38. struct crb_addr_pair {
  39. long addr;
  40. long data;
  41. };
  42. #define NETXEN_MAX_CRB_XFORM 60
  43. static unsigned int crb_addr_xform[NETXEN_MAX_CRB_XFORM];
  44. #define NETXEN_ADDR_ERROR ((unsigned long ) 0xffffffff )
  45. #define crb_addr_transform(name) \
  46. crb_addr_xform[NETXEN_HW_PX_MAP_CRB_##name] = \
  47. NETXEN_HW_CRB_HUB_AGT_ADR_##name << 20
  48. #define NETXEN_NIC_XDMA_RESET 0x8000ff
  49. static inline void
  50. netxen_nic_locked_write_reg(struct netxen_adapter *adapter,
  51. unsigned long off, int *data)
  52. {
  53. void __iomem *addr = pci_base_offset(adapter, off);
  54. writel(*data, addr);
  55. }
  56. static void crb_addr_transform_setup(void)
  57. {
  58. crb_addr_transform(XDMA);
  59. crb_addr_transform(TIMR);
  60. crb_addr_transform(SRE);
  61. crb_addr_transform(SQN3);
  62. crb_addr_transform(SQN2);
  63. crb_addr_transform(SQN1);
  64. crb_addr_transform(SQN0);
  65. crb_addr_transform(SQS3);
  66. crb_addr_transform(SQS2);
  67. crb_addr_transform(SQS1);
  68. crb_addr_transform(SQS0);
  69. crb_addr_transform(RPMX7);
  70. crb_addr_transform(RPMX6);
  71. crb_addr_transform(RPMX5);
  72. crb_addr_transform(RPMX4);
  73. crb_addr_transform(RPMX3);
  74. crb_addr_transform(RPMX2);
  75. crb_addr_transform(RPMX1);
  76. crb_addr_transform(RPMX0);
  77. crb_addr_transform(ROMUSB);
  78. crb_addr_transform(SN);
  79. crb_addr_transform(QMN);
  80. crb_addr_transform(QMS);
  81. crb_addr_transform(PGNI);
  82. crb_addr_transform(PGND);
  83. crb_addr_transform(PGN3);
  84. crb_addr_transform(PGN2);
  85. crb_addr_transform(PGN1);
  86. crb_addr_transform(PGN0);
  87. crb_addr_transform(PGSI);
  88. crb_addr_transform(PGSD);
  89. crb_addr_transform(PGS3);
  90. crb_addr_transform(PGS2);
  91. crb_addr_transform(PGS1);
  92. crb_addr_transform(PGS0);
  93. crb_addr_transform(PS);
  94. crb_addr_transform(PH);
  95. crb_addr_transform(NIU);
  96. crb_addr_transform(I2Q);
  97. crb_addr_transform(EG);
  98. crb_addr_transform(MN);
  99. crb_addr_transform(MS);
  100. crb_addr_transform(CAS2);
  101. crb_addr_transform(CAS1);
  102. crb_addr_transform(CAS0);
  103. crb_addr_transform(CAM);
  104. crb_addr_transform(C2C1);
  105. crb_addr_transform(C2C0);
  106. crb_addr_transform(SMB);
  107. }
  108. int netxen_init_firmware(struct netxen_adapter *adapter)
  109. {
  110. u32 state = 0, loops = 0, err = 0;
  111. /* Window 1 call */
  112. state = readl(NETXEN_CRB_NORMALIZE(adapter, CRB_CMDPEG_STATE));
  113. if (state == PHAN_INITIALIZE_ACK)
  114. return 0;
  115. while (state != PHAN_INITIALIZE_COMPLETE && loops < 2000) {
  116. udelay(100);
  117. /* Window 1 call */
  118. state = readl(NETXEN_CRB_NORMALIZE(adapter, CRB_CMDPEG_STATE));
  119. loops++;
  120. }
  121. if (loops >= 2000) {
  122. printk(KERN_ERR "Cmd Peg initialization not complete:%x.\n",
  123. state);
  124. err = -EIO;
  125. return err;
  126. }
  127. /* Window 1 call */
  128. writel(MPORT_SINGLE_FUNCTION_MODE,
  129. NETXEN_CRB_NORMALIZE(adapter, CRB_MPORT_MODE));
  130. writel(PHAN_INITIALIZE_ACK,
  131. NETXEN_CRB_NORMALIZE(adapter, CRB_CMDPEG_STATE));
  132. return err;
  133. }
  134. #define NETXEN_ADDR_LIMIT 0xffffffffULL
  135. void *netxen_alloc(struct pci_dev *pdev, size_t sz, dma_addr_t * ptr,
  136. struct pci_dev **used_dev)
  137. {
  138. void *addr;
  139. addr = pci_alloc_consistent(pdev, sz, ptr);
  140. if ((unsigned long long)(*ptr) < NETXEN_ADDR_LIMIT) {
  141. *used_dev = pdev;
  142. return addr;
  143. }
  144. pci_free_consistent(pdev, sz, addr, *ptr);
  145. addr = pci_alloc_consistent(NULL, sz, ptr);
  146. *used_dev = NULL;
  147. return addr;
  148. }
  149. void netxen_initialize_adapter_sw(struct netxen_adapter *adapter)
  150. {
  151. int ctxid, ring;
  152. u32 i;
  153. u32 num_rx_bufs = 0;
  154. struct netxen_rcv_desc_ctx *rcv_desc;
  155. DPRINTK(INFO, "initializing some queues: %p\n", adapter);
  156. for (ctxid = 0; ctxid < MAX_RCV_CTX; ++ctxid) {
  157. for (ring = 0; ring < NUM_RCV_DESC_RINGS; ring++) {
  158. struct netxen_rx_buffer *rx_buf;
  159. rcv_desc = &adapter->recv_ctx[ctxid].rcv_desc[ring];
  160. rcv_desc->rcv_free = rcv_desc->max_rx_desc_count;
  161. rcv_desc->begin_alloc = 0;
  162. rx_buf = rcv_desc->rx_buf_arr;
  163. num_rx_bufs = rcv_desc->max_rx_desc_count;
  164. /*
  165. * Now go through all of them, set reference handles
  166. * and put them in the queues.
  167. */
  168. for (i = 0; i < num_rx_bufs; i++) {
  169. rx_buf->ref_handle = i;
  170. rx_buf->state = NETXEN_BUFFER_FREE;
  171. DPRINTK(INFO, "Rx buf:ctx%d i(%d) rx_buf:"
  172. "%p\n", ctxid, i, rx_buf);
  173. rx_buf++;
  174. }
  175. }
  176. }
  177. }
  178. void netxen_initialize_adapter_hw(struct netxen_adapter *adapter)
  179. {
  180. int ports = 0;
  181. struct netxen_board_info *board_info = &(adapter->ahw.boardcfg);
  182. if (netxen_nic_get_board_info(adapter) != 0)
  183. printk("%s: Error getting board config info.\n",
  184. netxen_nic_driver_name);
  185. get_brd_port_by_type(board_info->board_type, &ports);
  186. if (ports == 0)
  187. printk(KERN_ERR "%s: Unknown board type\n",
  188. netxen_nic_driver_name);
  189. adapter->ahw.max_ports = ports;
  190. }
  191. void netxen_initialize_adapter_ops(struct netxen_adapter *adapter)
  192. {
  193. switch (adapter->ahw.board_type) {
  194. case NETXEN_NIC_GBE:
  195. adapter->enable_phy_interrupts =
  196. netxen_niu_gbe_enable_phy_interrupts;
  197. adapter->disable_phy_interrupts =
  198. netxen_niu_gbe_disable_phy_interrupts;
  199. adapter->handle_phy_intr = netxen_nic_gbe_handle_phy_intr;
  200. adapter->macaddr_set = netxen_niu_macaddr_set;
  201. adapter->set_mtu = netxen_nic_set_mtu_gb;
  202. adapter->set_promisc = netxen_niu_set_promiscuous_mode;
  203. adapter->unset_promisc = netxen_niu_set_promiscuous_mode;
  204. adapter->phy_read = netxen_niu_gbe_phy_read;
  205. adapter->phy_write = netxen_niu_gbe_phy_write;
  206. adapter->init_port = netxen_niu_gbe_init_port;
  207. adapter->init_niu = netxen_nic_init_niu_gb;
  208. adapter->stop_port = netxen_niu_disable_gbe_port;
  209. break;
  210. case NETXEN_NIC_XGBE:
  211. adapter->enable_phy_interrupts =
  212. netxen_niu_xgbe_enable_phy_interrupts;
  213. adapter->disable_phy_interrupts =
  214. netxen_niu_xgbe_disable_phy_interrupts;
  215. adapter->handle_phy_intr = netxen_nic_xgbe_handle_phy_intr;
  216. adapter->macaddr_set = netxen_niu_xg_macaddr_set;
  217. adapter->set_mtu = netxen_nic_set_mtu_xgb;
  218. adapter->init_port = netxen_niu_xg_init_port;
  219. adapter->set_promisc = netxen_niu_xg_set_promiscuous_mode;
  220. adapter->unset_promisc = netxen_niu_xg_set_promiscuous_mode;
  221. adapter->stop_port = netxen_niu_disable_xg_port;
  222. break;
  223. default:
  224. break;
  225. }
  226. }
  227. /*
  228. * netxen_decode_crb_addr(0 - utility to translate from internal Phantom CRB
  229. * address to external PCI CRB address.
  230. */
  231. unsigned long netxen_decode_crb_addr(unsigned long addr)
  232. {
  233. int i;
  234. unsigned long base_addr, offset, pci_base;
  235. crb_addr_transform_setup();
  236. pci_base = NETXEN_ADDR_ERROR;
  237. base_addr = addr & 0xfff00000;
  238. offset = addr & 0x000fffff;
  239. for (i = 0; i < NETXEN_MAX_CRB_XFORM; i++) {
  240. if (crb_addr_xform[i] == base_addr) {
  241. pci_base = i << 20;
  242. break;
  243. }
  244. }
  245. if (pci_base == NETXEN_ADDR_ERROR)
  246. return pci_base;
  247. else
  248. return (pci_base + offset);
  249. }
  250. static long rom_max_timeout = 10000;
  251. static long rom_lock_timeout = 1000000;
  252. static long rom_write_timeout = 700;
  253. static inline int rom_lock(struct netxen_adapter *adapter)
  254. {
  255. int iter;
  256. u32 done = 0;
  257. int timeout = 0;
  258. while (!done) {
  259. /* acquire semaphore2 from PCI HW block */
  260. netxen_nic_read_w0(adapter, NETXEN_PCIE_REG(PCIE_SEM2_LOCK),
  261. &done);
  262. if (done == 1)
  263. break;
  264. if (timeout >= rom_lock_timeout)
  265. return -EIO;
  266. timeout++;
  267. /*
  268. * Yield CPU
  269. */
  270. if (!in_atomic())
  271. schedule();
  272. else {
  273. for (iter = 0; iter < 20; iter++)
  274. cpu_relax(); /*This a nop instr on i386 */
  275. }
  276. }
  277. netxen_nic_reg_write(adapter, NETXEN_ROM_LOCK_ID, ROM_LOCK_DRIVER);
  278. return 0;
  279. }
  280. int netxen_wait_rom_done(struct netxen_adapter *adapter)
  281. {
  282. long timeout = 0;
  283. long done = 0;
  284. while (done == 0) {
  285. done = netxen_nic_reg_read(adapter, NETXEN_ROMUSB_GLB_STATUS);
  286. done &= 2;
  287. timeout++;
  288. if (timeout >= rom_max_timeout) {
  289. printk("Timeout reached waiting for rom done");
  290. return -EIO;
  291. }
  292. }
  293. return 0;
  294. }
  295. static inline int netxen_rom_wren(struct netxen_adapter *adapter)
  296. {
  297. /* Set write enable latch in ROM status register */
  298. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 0);
  299. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_INSTR_OPCODE,
  300. M25P_INSTR_WREN);
  301. if (netxen_wait_rom_done(adapter)) {
  302. return -1;
  303. }
  304. return 0;
  305. }
  306. static inline unsigned int netxen_rdcrbreg(struct netxen_adapter *adapter,
  307. unsigned int addr)
  308. {
  309. unsigned int data = 0xdeaddead;
  310. data = netxen_nic_reg_read(adapter, addr);
  311. return data;
  312. }
  313. static inline int netxen_do_rom_rdsr(struct netxen_adapter *adapter)
  314. {
  315. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_INSTR_OPCODE,
  316. M25P_INSTR_RDSR);
  317. if (netxen_wait_rom_done(adapter)) {
  318. return -1;
  319. }
  320. return netxen_rdcrbreg(adapter, NETXEN_ROMUSB_ROM_RDATA);
  321. }
  322. static inline void netxen_rom_unlock(struct netxen_adapter *adapter)
  323. {
  324. u32 val;
  325. /* release semaphore2 */
  326. netxen_nic_read_w0(adapter, NETXEN_PCIE_REG(PCIE_SEM2_UNLOCK), &val);
  327. }
  328. int netxen_rom_wip_poll(struct netxen_adapter *adapter)
  329. {
  330. long timeout = 0;
  331. long wip = 1;
  332. int val;
  333. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 0);
  334. while (wip != 0) {
  335. val = netxen_do_rom_rdsr(adapter);
  336. wip = val & 1;
  337. timeout++;
  338. if (timeout > rom_max_timeout) {
  339. return -1;
  340. }
  341. }
  342. return 0;
  343. }
  344. static inline int do_rom_fast_write(struct netxen_adapter *adapter, int addr,
  345. int data)
  346. {
  347. if (netxen_rom_wren(adapter)) {
  348. return -1;
  349. }
  350. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_WDATA, data);
  351. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ADDRESS, addr);
  352. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 3);
  353. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_INSTR_OPCODE,
  354. M25P_INSTR_PP);
  355. if (netxen_wait_rom_done(adapter)) {
  356. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 0);
  357. return -1;
  358. }
  359. return netxen_rom_wip_poll(adapter);
  360. }
  361. static inline int
  362. do_rom_fast_read(struct netxen_adapter *adapter, int addr, int *valp)
  363. {
  364. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ADDRESS, addr);
  365. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 3);
  366. udelay(70); /* prevent bursting on CRB */
  367. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
  368. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_INSTR_OPCODE, 0xb);
  369. if (netxen_wait_rom_done(adapter)) {
  370. printk("Error waiting for rom done\n");
  371. return -EIO;
  372. }
  373. /* reset abyte_cnt and dummy_byte_cnt */
  374. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 0);
  375. udelay(70); /* prevent bursting on CRB */
  376. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
  377. *valp = netxen_nic_reg_read(adapter, NETXEN_ROMUSB_ROM_RDATA);
  378. return 0;
  379. }
  380. static inline int
  381. do_rom_fast_read_words(struct netxen_adapter *adapter, int addr,
  382. u8 *bytes, size_t size)
  383. {
  384. int addridx;
  385. int ret = 0;
  386. for (addridx = addr; addridx < (addr + size); addridx += 4) {
  387. ret = do_rom_fast_read(adapter, addridx, (int *)bytes);
  388. if (ret != 0)
  389. break;
  390. bytes += 4;
  391. }
  392. return ret;
  393. }
  394. int
  395. netxen_rom_fast_read_words(struct netxen_adapter *adapter, int addr,
  396. u8 *bytes, size_t size)
  397. {
  398. int ret;
  399. ret = rom_lock(adapter);
  400. if (ret < 0)
  401. return ret;
  402. ret = do_rom_fast_read_words(adapter, addr, bytes, size);
  403. netxen_rom_unlock(adapter);
  404. return ret;
  405. }
  406. int netxen_rom_fast_read(struct netxen_adapter *adapter, int addr, int *valp)
  407. {
  408. int ret;
  409. if (rom_lock(adapter) != 0)
  410. return -EIO;
  411. ret = do_rom_fast_read(adapter, addr, valp);
  412. netxen_rom_unlock(adapter);
  413. return ret;
  414. }
  415. int netxen_rom_fast_write(struct netxen_adapter *adapter, int addr, int data)
  416. {
  417. int ret = 0;
  418. if (rom_lock(adapter) != 0) {
  419. return -1;
  420. }
  421. ret = do_rom_fast_write(adapter, addr, data);
  422. netxen_rom_unlock(adapter);
  423. return ret;
  424. }
  425. static inline int do_rom_fast_write_words(struct netxen_adapter *adapter,
  426. int addr, u8 *bytes, size_t size)
  427. {
  428. int addridx = addr;
  429. int ret = 0;
  430. while (addridx < (addr + size)) {
  431. int last_attempt = 0;
  432. int timeout = 0;
  433. int data;
  434. data = *(u32*)bytes;
  435. ret = do_rom_fast_write(adapter, addridx, data);
  436. if (ret < 0)
  437. return ret;
  438. while(1) {
  439. int data1;
  440. do_rom_fast_read(adapter, addridx, &data1);
  441. if (data1 == data)
  442. break;
  443. if (timeout++ >= rom_write_timeout) {
  444. if (last_attempt++ < 4) {
  445. ret = do_rom_fast_write(adapter,
  446. addridx, data);
  447. if (ret < 0)
  448. return ret;
  449. }
  450. else {
  451. printk(KERN_INFO "Data write did not "
  452. "succeed at address 0x%x\n", addridx);
  453. break;
  454. }
  455. }
  456. }
  457. bytes += 4;
  458. addridx += 4;
  459. }
  460. return ret;
  461. }
  462. int netxen_rom_fast_write_words(struct netxen_adapter *adapter, int addr,
  463. u8 *bytes, size_t size)
  464. {
  465. int ret = 0;
  466. ret = rom_lock(adapter);
  467. if (ret < 0)
  468. return ret;
  469. ret = do_rom_fast_write_words(adapter, addr, bytes, size);
  470. netxen_rom_unlock(adapter);
  471. return ret;
  472. }
  473. int netxen_rom_wrsr(struct netxen_adapter *adapter, int data)
  474. {
  475. int ret;
  476. ret = netxen_rom_wren(adapter);
  477. if (ret < 0)
  478. return ret;
  479. netxen_crb_writelit_adapter(adapter, NETXEN_ROMUSB_ROM_WDATA, data);
  480. netxen_crb_writelit_adapter(adapter,
  481. NETXEN_ROMUSB_ROM_INSTR_OPCODE, 0x1);
  482. ret = netxen_wait_rom_done(adapter);
  483. if (ret < 0)
  484. return ret;
  485. return netxen_rom_wip_poll(adapter);
  486. }
  487. int netxen_rom_rdsr(struct netxen_adapter *adapter)
  488. {
  489. int ret;
  490. ret = rom_lock(adapter);
  491. if (ret < 0)
  492. return ret;
  493. ret = netxen_do_rom_rdsr(adapter);
  494. netxen_rom_unlock(adapter);
  495. return ret;
  496. }
  497. int netxen_backup_crbinit(struct netxen_adapter *adapter)
  498. {
  499. int ret = FLASH_SUCCESS;
  500. int val;
  501. char *buffer = kmalloc(FLASH_SECTOR_SIZE, GFP_KERNEL);
  502. if (!buffer)
  503. return -ENOMEM;
  504. /* unlock sector 63 */
  505. val = netxen_rom_rdsr(adapter);
  506. val = val & 0xe3;
  507. ret = netxen_rom_wrsr(adapter, val);
  508. if (ret != FLASH_SUCCESS)
  509. goto out_kfree;
  510. ret = netxen_rom_wip_poll(adapter);
  511. if (ret != FLASH_SUCCESS)
  512. goto out_kfree;
  513. /* copy sector 0 to sector 63 */
  514. ret = netxen_rom_fast_read_words(adapter, CRBINIT_START,
  515. buffer, FLASH_SECTOR_SIZE);
  516. if (ret != FLASH_SUCCESS)
  517. goto out_kfree;
  518. ret = netxen_rom_fast_write_words(adapter, FIXED_START,
  519. buffer, FLASH_SECTOR_SIZE);
  520. if (ret != FLASH_SUCCESS)
  521. goto out_kfree;
  522. /* lock sector 63 */
  523. val = netxen_rom_rdsr(adapter);
  524. if (!(val & 0x8)) {
  525. val |= (0x1 << 2);
  526. /* lock sector 63 */
  527. if (netxen_rom_wrsr(adapter, val) == 0) {
  528. ret = netxen_rom_wip_poll(adapter);
  529. if (ret != FLASH_SUCCESS)
  530. goto out_kfree;
  531. /* lock SR writes */
  532. ret = netxen_rom_wip_poll(adapter);
  533. if (ret != FLASH_SUCCESS)
  534. goto out_kfree;
  535. }
  536. }
  537. out_kfree:
  538. kfree(buffer);
  539. return ret;
  540. }
  541. int netxen_do_rom_se(struct netxen_adapter *adapter, int addr)
  542. {
  543. netxen_rom_wren(adapter);
  544. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ADDRESS, addr);
  545. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 3);
  546. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_INSTR_OPCODE,
  547. M25P_INSTR_SE);
  548. if (netxen_wait_rom_done(adapter)) {
  549. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 0);
  550. return -1;
  551. }
  552. return netxen_rom_wip_poll(adapter);
  553. }
  554. void check_erased_flash(struct netxen_adapter *adapter, int addr)
  555. {
  556. int i;
  557. int val;
  558. int count = 0, erased_errors = 0;
  559. int range;
  560. range = (addr == USER_START) ? FIXED_START : addr + FLASH_SECTOR_SIZE;
  561. for (i = addr; i < range; i += 4) {
  562. netxen_rom_fast_read(adapter, i, &val);
  563. if (val != 0xffffffff)
  564. erased_errors++;
  565. count++;
  566. }
  567. if (erased_errors)
  568. printk(KERN_INFO "0x%x out of 0x%x words fail to be erased "
  569. "for sector address: %x\n", erased_errors, count, addr);
  570. }
  571. int netxen_rom_se(struct netxen_adapter *adapter, int addr)
  572. {
  573. int ret = 0;
  574. if (rom_lock(adapter) != 0) {
  575. return -1;
  576. }
  577. ret = netxen_do_rom_se(adapter, addr);
  578. netxen_rom_unlock(adapter);
  579. msleep(30);
  580. check_erased_flash(adapter, addr);
  581. return ret;
  582. }
  583. int
  584. netxen_flash_erase_sections(struct netxen_adapter *adapter, int start, int end)
  585. {
  586. int ret = FLASH_SUCCESS;
  587. int i;
  588. for (i = start; i < end; i++) {
  589. ret = netxen_rom_se(adapter, i * FLASH_SECTOR_SIZE);
  590. if (ret)
  591. break;
  592. ret = netxen_rom_wip_poll(adapter);
  593. if (ret < 0)
  594. return ret;
  595. }
  596. return ret;
  597. }
  598. int
  599. netxen_flash_erase_secondary(struct netxen_adapter *adapter)
  600. {
  601. int ret = FLASH_SUCCESS;
  602. int start, end;
  603. start = SECONDARY_START / FLASH_SECTOR_SIZE;
  604. end = USER_START / FLASH_SECTOR_SIZE;
  605. ret = netxen_flash_erase_sections(adapter, start, end);
  606. return ret;
  607. }
  608. int
  609. netxen_flash_erase_primary(struct netxen_adapter *adapter)
  610. {
  611. int ret = FLASH_SUCCESS;
  612. int start, end;
  613. start = PRIMARY_START / FLASH_SECTOR_SIZE;
  614. end = SECONDARY_START / FLASH_SECTOR_SIZE;
  615. ret = netxen_flash_erase_sections(adapter, start, end);
  616. return ret;
  617. }
  618. int netxen_flash_unlock(struct netxen_adapter *adapter)
  619. {
  620. int ret = 0;
  621. ret = netxen_rom_wrsr(adapter, 0);
  622. if (ret < 0)
  623. return ret;
  624. ret = netxen_rom_wren(adapter);
  625. if (ret < 0)
  626. return ret;
  627. return ret;
  628. }
  629. #define NETXEN_BOARDTYPE 0x4008
  630. #define NETXEN_BOARDNUM 0x400c
  631. #define NETXEN_CHIPNUM 0x4010
  632. #define NETXEN_ROMBUS_RESET 0xFFFFFFFF
  633. #define NETXEN_ROM_FIRST_BARRIER 0x800000000ULL
  634. #define NETXEN_ROM_FOUND_INIT 0x400
  635. int netxen_pinit_from_rom(struct netxen_adapter *adapter, int verbose)
  636. {
  637. int addr, val, status;
  638. int n, i;
  639. int init_delay = 0;
  640. struct crb_addr_pair *buf;
  641. unsigned long off;
  642. /* resetall */
  643. status = netxen_nic_get_board_info(adapter);
  644. if (status)
  645. printk("%s: netxen_pinit_from_rom: Error getting board info\n",
  646. netxen_nic_driver_name);
  647. netxen_crb_writelit_adapter(adapter, NETXEN_ROMUSB_GLB_SW_RESET,
  648. NETXEN_ROMBUS_RESET);
  649. if (verbose) {
  650. int val;
  651. if (netxen_rom_fast_read(adapter, NETXEN_BOARDTYPE, &val) == 0)
  652. printk("P2 ROM board type: 0x%08x\n", val);
  653. else
  654. printk("Could not read board type\n");
  655. if (netxen_rom_fast_read(adapter, NETXEN_BOARDNUM, &val) == 0)
  656. printk("P2 ROM board num: 0x%08x\n", val);
  657. else
  658. printk("Could not read board number\n");
  659. if (netxen_rom_fast_read(adapter, NETXEN_CHIPNUM, &val) == 0)
  660. printk("P2 ROM chip num: 0x%08x\n", val);
  661. else
  662. printk("Could not read chip number\n");
  663. }
  664. if (netxen_rom_fast_read(adapter, 0, &n) == 0
  665. && (n & NETXEN_ROM_FIRST_BARRIER)) {
  666. n &= ~NETXEN_ROM_ROUNDUP;
  667. if (n < NETXEN_ROM_FOUND_INIT) {
  668. if (verbose)
  669. printk("%s: %d CRB init values found"
  670. " in ROM.\n", netxen_nic_driver_name, n);
  671. } else {
  672. printk("%s:n=0x%x Error! NetXen card flash not"
  673. " initialized.\n", __FUNCTION__, n);
  674. return -EIO;
  675. }
  676. buf = kcalloc(n, sizeof(struct crb_addr_pair), GFP_KERNEL);
  677. if (buf == NULL) {
  678. printk("%s: netxen_pinit_from_rom: Unable to calloc "
  679. "memory.\n", netxen_nic_driver_name);
  680. return -ENOMEM;
  681. }
  682. for (i = 0; i < n; i++) {
  683. if (netxen_rom_fast_read(adapter, 8 * i + 4, &val) != 0
  684. || netxen_rom_fast_read(adapter, 8 * i + 8,
  685. &addr) != 0)
  686. return -EIO;
  687. buf[i].addr = addr;
  688. buf[i].data = val;
  689. if (verbose)
  690. printk("%s: PCI: 0x%08x == 0x%08x\n",
  691. netxen_nic_driver_name, (unsigned int)
  692. netxen_decode_crb_addr((unsigned long)
  693. addr), val);
  694. }
  695. for (i = 0; i < n; i++) {
  696. off = netxen_decode_crb_addr((unsigned long)buf[i].addr);
  697. if (off == NETXEN_ADDR_ERROR) {
  698. printk(KERN_ERR"CRB init value out of range %lx\n",
  699. buf[i].addr);
  700. continue;
  701. }
  702. off += NETXEN_PCI_CRBSPACE;
  703. /* skipping cold reboot MAGIC */
  704. if (off == NETXEN_CAM_RAM(0x1fc))
  705. continue;
  706. /* After writing this register, HW needs time for CRB */
  707. /* to quiet down (else crb_window returns 0xffffffff) */
  708. if (off == NETXEN_ROMUSB_GLB_SW_RESET) {
  709. init_delay = 1;
  710. /* hold xdma in reset also */
  711. buf[i].data = NETXEN_NIC_XDMA_RESET;
  712. }
  713. if (ADDR_IN_WINDOW1(off)) {
  714. writel(buf[i].data,
  715. NETXEN_CRB_NORMALIZE(adapter, off));
  716. } else {
  717. netxen_nic_pci_change_crbwindow(adapter, 0);
  718. writel(buf[i].data,
  719. pci_base_offset(adapter, off));
  720. netxen_nic_pci_change_crbwindow(adapter, 1);
  721. }
  722. if (init_delay == 1) {
  723. ssleep(1);
  724. init_delay = 0;
  725. }
  726. msleep(1);
  727. }
  728. kfree(buf);
  729. /* disable_peg_cache_all */
  730. /* unreset_net_cache */
  731. netxen_nic_hw_read_wx(adapter, NETXEN_ROMUSB_GLB_SW_RESET, &val,
  732. 4);
  733. netxen_crb_writelit_adapter(adapter, NETXEN_ROMUSB_GLB_SW_RESET,
  734. (val & 0xffffff0f));
  735. /* p2dn replyCount */
  736. netxen_crb_writelit_adapter(adapter,
  737. NETXEN_CRB_PEG_NET_D + 0xec, 0x1e);
  738. /* disable_peg_cache 0 */
  739. netxen_crb_writelit_adapter(adapter,
  740. NETXEN_CRB_PEG_NET_D + 0x4c, 8);
  741. /* disable_peg_cache 1 */
  742. netxen_crb_writelit_adapter(adapter,
  743. NETXEN_CRB_PEG_NET_I + 0x4c, 8);
  744. /* peg_clr_all */
  745. /* peg_clr 0 */
  746. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_0 + 0x8,
  747. 0);
  748. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_0 + 0xc,
  749. 0);
  750. /* peg_clr 1 */
  751. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_1 + 0x8,
  752. 0);
  753. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_1 + 0xc,
  754. 0);
  755. /* peg_clr 2 */
  756. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_2 + 0x8,
  757. 0);
  758. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_2 + 0xc,
  759. 0);
  760. /* peg_clr 3 */
  761. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_3 + 0x8,
  762. 0);
  763. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_3 + 0xc,
  764. 0);
  765. }
  766. return 0;
  767. }
  768. int netxen_initialize_adapter_offload(struct netxen_adapter *adapter)
  769. {
  770. uint64_t addr;
  771. uint32_t hi;
  772. uint32_t lo;
  773. adapter->dummy_dma.addr =
  774. pci_alloc_consistent(adapter->ahw.pdev,
  775. NETXEN_HOST_DUMMY_DMA_SIZE,
  776. &adapter->dummy_dma.phys_addr);
  777. if (adapter->dummy_dma.addr == NULL) {
  778. printk("%s: ERROR: Could not allocate dummy DMA memory\n",
  779. __FUNCTION__);
  780. return -ENOMEM;
  781. }
  782. addr = (uint64_t) adapter->dummy_dma.phys_addr;
  783. hi = (addr >> 32) & 0xffffffff;
  784. lo = addr & 0xffffffff;
  785. writel(hi, NETXEN_CRB_NORMALIZE(adapter, CRB_HOST_DUMMY_BUF_ADDR_HI));
  786. writel(lo, NETXEN_CRB_NORMALIZE(adapter, CRB_HOST_DUMMY_BUF_ADDR_LO));
  787. return 0;
  788. }
  789. void netxen_free_adapter_offload(struct netxen_adapter *adapter)
  790. {
  791. if (adapter->dummy_dma.addr) {
  792. pci_free_consistent(adapter->ahw.pdev,
  793. NETXEN_HOST_DUMMY_DMA_SIZE,
  794. adapter->dummy_dma.addr,
  795. adapter->dummy_dma.phys_addr);
  796. adapter->dummy_dma.addr = NULL;
  797. }
  798. }
  799. void netxen_phantom_init(struct netxen_adapter *adapter, int pegtune_val)
  800. {
  801. u32 val = 0;
  802. int loops = 0;
  803. if (!pegtune_val) {
  804. val = readl(NETXEN_CRB_NORMALIZE(adapter, CRB_CMDPEG_STATE));
  805. while (val != PHAN_INITIALIZE_COMPLETE && loops < 200000) {
  806. udelay(100);
  807. schedule();
  808. val =
  809. readl(NETXEN_CRB_NORMALIZE
  810. (adapter, CRB_CMDPEG_STATE));
  811. loops++;
  812. }
  813. if (val != PHAN_INITIALIZE_COMPLETE)
  814. printk("WARNING: Initial boot wait loop failed...\n");
  815. }
  816. }
  817. int netxen_nic_rx_has_work(struct netxen_adapter *adapter)
  818. {
  819. int ctx;
  820. for (ctx = 0; ctx < MAX_RCV_CTX; ++ctx) {
  821. struct netxen_recv_context *recv_ctx =
  822. &(adapter->recv_ctx[ctx]);
  823. u32 consumer;
  824. struct status_desc *desc_head;
  825. struct status_desc *desc;
  826. consumer = recv_ctx->status_rx_consumer;
  827. desc_head = recv_ctx->rcv_status_desc_head;
  828. desc = &desc_head[consumer];
  829. if (netxen_get_sts_owner(desc) & STATUS_OWNER_HOST)
  830. return 1;
  831. }
  832. return 0;
  833. }
  834. static inline int netxen_nic_check_temp(struct netxen_adapter *adapter)
  835. {
  836. int port_num;
  837. struct netxen_port *port;
  838. struct net_device *netdev;
  839. uint32_t temp, temp_state, temp_val;
  840. int rv = 0;
  841. temp = readl(NETXEN_CRB_NORMALIZE(adapter, CRB_TEMP_STATE));
  842. temp_state = nx_get_temp_state(temp);
  843. temp_val = nx_get_temp_val(temp);
  844. if (temp_state == NX_TEMP_PANIC) {
  845. printk(KERN_ALERT
  846. "%s: Device temperature %d degrees C exceeds"
  847. " maximum allowed. Hardware has been shut down.\n",
  848. netxen_nic_driver_name, temp_val);
  849. for (port_num = 0; port_num < adapter->ahw.max_ports;
  850. port_num++) {
  851. port = adapter->port[port_num];
  852. netdev = port->netdev;
  853. netif_carrier_off(netdev);
  854. netif_stop_queue(netdev);
  855. }
  856. rv = 1;
  857. } else if (temp_state == NX_TEMP_WARN) {
  858. if (adapter->temp == NX_TEMP_NORMAL) {
  859. printk(KERN_ALERT
  860. "%s: Device temperature %d degrees C "
  861. "exceeds operating range."
  862. " Immediate action needed.\n",
  863. netxen_nic_driver_name, temp_val);
  864. }
  865. } else {
  866. if (adapter->temp == NX_TEMP_WARN) {
  867. printk(KERN_INFO
  868. "%s: Device temperature is now %d degrees C"
  869. " in normal range.\n", netxen_nic_driver_name,
  870. temp_val);
  871. }
  872. }
  873. adapter->temp = temp_state;
  874. return rv;
  875. }
  876. void netxen_watchdog_task(struct work_struct *work)
  877. {
  878. int port_num;
  879. struct netxen_port *port;
  880. struct net_device *netdev;
  881. struct netxen_adapter *adapter =
  882. container_of(work, struct netxen_adapter, watchdog_task);
  883. if (netxen_nic_check_temp(adapter))
  884. return;
  885. for (port_num = 0; port_num < adapter->ahw.max_ports; port_num++) {
  886. port = adapter->port[port_num];
  887. netdev = port->netdev;
  888. if ((netif_running(netdev)) && !netif_carrier_ok(netdev)) {
  889. printk(KERN_INFO "%s port %d, %s carrier is now ok\n",
  890. netxen_nic_driver_name, port_num, netdev->name);
  891. netif_carrier_on(netdev);
  892. }
  893. if (netif_queue_stopped(netdev))
  894. netif_wake_queue(netdev);
  895. }
  896. if (adapter->handle_phy_intr)
  897. adapter->handle_phy_intr(adapter);
  898. mod_timer(&adapter->watchdog_timer, jiffies + 2 * HZ);
  899. }
  900. /*
  901. * netxen_process_rcv() send the received packet to the protocol stack.
  902. * and if the number of receives exceeds RX_BUFFERS_REFILL, then we
  903. * invoke the routine to send more rx buffers to the Phantom...
  904. */
  905. void
  906. netxen_process_rcv(struct netxen_adapter *adapter, int ctxid,
  907. struct status_desc *desc)
  908. {
  909. struct netxen_port *port = adapter->port[netxen_get_sts_port(desc)];
  910. struct pci_dev *pdev = port->pdev;
  911. struct net_device *netdev = port->netdev;
  912. int index = netxen_get_sts_refhandle(desc);
  913. struct netxen_recv_context *recv_ctx = &(adapter->recv_ctx[ctxid]);
  914. struct netxen_rx_buffer *buffer;
  915. struct sk_buff *skb;
  916. u32 length = netxen_get_sts_totallength(desc);
  917. u32 desc_ctx;
  918. struct netxen_rcv_desc_ctx *rcv_desc;
  919. int ret;
  920. desc_ctx = netxen_get_sts_type(desc);
  921. if (unlikely(desc_ctx >= NUM_RCV_DESC_RINGS)) {
  922. printk("%s: %s Bad Rcv descriptor ring\n",
  923. netxen_nic_driver_name, netdev->name);
  924. return;
  925. }
  926. rcv_desc = &recv_ctx->rcv_desc[desc_ctx];
  927. if (unlikely(index > rcv_desc->max_rx_desc_count)) {
  928. DPRINTK(ERR, "Got a buffer index:%x Max is %x\n",
  929. index, rcv_desc->max_rx_desc_count);
  930. return;
  931. }
  932. buffer = &rcv_desc->rx_buf_arr[index];
  933. if (desc_ctx == RCV_DESC_LRO_CTXID) {
  934. buffer->lro_current_frags++;
  935. if (netxen_get_sts_desc_lro_last_frag(desc)) {
  936. buffer->lro_expected_frags =
  937. netxen_get_sts_desc_lro_cnt(desc);
  938. buffer->lro_length = length;
  939. }
  940. if (buffer->lro_current_frags != buffer->lro_expected_frags) {
  941. if (buffer->lro_expected_frags != 0) {
  942. printk("LRO: (refhandle:%x) recv frag."
  943. "wait for last. flags: %x expected:%d"
  944. "have:%d\n", index,
  945. netxen_get_sts_desc_lro_last_frag(desc),
  946. buffer->lro_expected_frags,
  947. buffer->lro_current_frags);
  948. }
  949. return;
  950. }
  951. }
  952. pci_unmap_single(pdev, buffer->dma, rcv_desc->dma_size,
  953. PCI_DMA_FROMDEVICE);
  954. skb = (struct sk_buff *)buffer->skb;
  955. if (likely(netxen_get_sts_status(desc) == STATUS_CKSUM_OK)) {
  956. port->stats.csummed++;
  957. skb->ip_summed = CHECKSUM_UNNECESSARY;
  958. }
  959. skb->dev = netdev;
  960. if (desc_ctx == RCV_DESC_LRO_CTXID) {
  961. /* True length was only available on the last pkt */
  962. skb_put(skb, buffer->lro_length);
  963. } else {
  964. skb_put(skb, length);
  965. }
  966. skb->protocol = eth_type_trans(skb, netdev);
  967. ret = netif_receive_skb(skb);
  968. /*
  969. * RH: Do we need these stats on a regular basis. Can we get it from
  970. * Linux stats.
  971. */
  972. switch (ret) {
  973. case NET_RX_SUCCESS:
  974. port->stats.uphappy++;
  975. break;
  976. case NET_RX_CN_LOW:
  977. port->stats.uplcong++;
  978. break;
  979. case NET_RX_CN_MOD:
  980. port->stats.upmcong++;
  981. break;
  982. case NET_RX_CN_HIGH:
  983. port->stats.uphcong++;
  984. break;
  985. case NET_RX_DROP:
  986. port->stats.updropped++;
  987. break;
  988. default:
  989. port->stats.updunno++;
  990. break;
  991. }
  992. netdev->last_rx = jiffies;
  993. rcv_desc->rcv_free++;
  994. rcv_desc->rcv_pending--;
  995. /*
  996. * We just consumed one buffer so post a buffer.
  997. */
  998. adapter->stats.post_called++;
  999. buffer->skb = NULL;
  1000. buffer->state = NETXEN_BUFFER_FREE;
  1001. buffer->lro_current_frags = 0;
  1002. buffer->lro_expected_frags = 0;
  1003. port->stats.no_rcv++;
  1004. port->stats.rxbytes += length;
  1005. }
  1006. /* Process Receive status ring */
  1007. u32 netxen_process_rcv_ring(struct netxen_adapter *adapter, int ctxid, int max)
  1008. {
  1009. struct netxen_recv_context *recv_ctx = &(adapter->recv_ctx[ctxid]);
  1010. struct status_desc *desc_head = recv_ctx->rcv_status_desc_head;
  1011. struct status_desc *desc; /* used to read status desc here */
  1012. u32 consumer = recv_ctx->status_rx_consumer;
  1013. u32 producer = 0;
  1014. int count = 0, ring;
  1015. DPRINTK(INFO, "procesing receive\n");
  1016. /*
  1017. * we assume in this case that there is only one port and that is
  1018. * port #1...changes need to be done in firmware to indicate port
  1019. * number as part of the descriptor. This way we will be able to get
  1020. * the netdev which is associated with that device.
  1021. */
  1022. while (count < max) {
  1023. desc = &desc_head[consumer];
  1024. if (!(netxen_get_sts_owner(desc) & STATUS_OWNER_HOST)) {
  1025. DPRINTK(ERR, "desc %p ownedby %x\n", desc,
  1026. netxen_get_sts_owner(desc));
  1027. break;
  1028. }
  1029. netxen_process_rcv(adapter, ctxid, desc);
  1030. netxen_clear_sts_owner(desc);
  1031. netxen_set_sts_owner(desc, STATUS_OWNER_PHANTOM);
  1032. consumer = (consumer + 1) & (adapter->max_rx_desc_count - 1);
  1033. count++;
  1034. }
  1035. if (count) {
  1036. for (ring = 0; ring < NUM_RCV_DESC_RINGS; ring++) {
  1037. netxen_post_rx_buffers_nodb(adapter, ctxid, ring);
  1038. }
  1039. }
  1040. /* update the consumer index in phantom */
  1041. if (count) {
  1042. adapter->stats.process_rcv++;
  1043. recv_ctx->status_rx_consumer = consumer;
  1044. recv_ctx->status_rx_producer = producer;
  1045. /* Window = 1 */
  1046. writel(consumer,
  1047. NETXEN_CRB_NORMALIZE(adapter,
  1048. recv_crb_registers[ctxid].
  1049. crb_rcv_status_consumer));
  1050. }
  1051. return count;
  1052. }
  1053. /* Process Command status ring */
  1054. int netxen_process_cmd_ring(unsigned long data)
  1055. {
  1056. u32 last_consumer;
  1057. u32 consumer;
  1058. struct netxen_adapter *adapter = (struct netxen_adapter *)data;
  1059. int count1 = 0;
  1060. int count2 = 0;
  1061. struct netxen_cmd_buffer *buffer;
  1062. struct netxen_port *port; /* port #1 */
  1063. struct netxen_port *nport;
  1064. struct pci_dev *pdev;
  1065. struct netxen_skb_frag *frag;
  1066. u32 i;
  1067. struct sk_buff *skb = NULL;
  1068. int p;
  1069. int done;
  1070. spin_lock(&adapter->tx_lock);
  1071. last_consumer = adapter->last_cmd_consumer;
  1072. DPRINTK(INFO, "procesing xmit complete\n");
  1073. /* we assume in this case that there is only one port and that is
  1074. * port #1...changes need to be done in firmware to indicate port
  1075. * number as part of the descriptor. This way we will be able to get
  1076. * the netdev which is associated with that device.
  1077. */
  1078. consumer = *(adapter->cmd_consumer);
  1079. if (last_consumer == consumer) { /* Ring is empty */
  1080. DPRINTK(INFO, "last_consumer %d == consumer %d\n",
  1081. last_consumer, consumer);
  1082. spin_unlock(&adapter->tx_lock);
  1083. return 1;
  1084. }
  1085. adapter->proc_cmd_buf_counter++;
  1086. adapter->stats.process_xmit++;
  1087. /*
  1088. * Not needed - does not seem to be used anywhere.
  1089. * adapter->cmd_consumer = consumer;
  1090. */
  1091. spin_unlock(&adapter->tx_lock);
  1092. while ((last_consumer != consumer) && (count1 < MAX_STATUS_HANDLE)) {
  1093. buffer = &adapter->cmd_buf_arr[last_consumer];
  1094. port = adapter->port[buffer->port];
  1095. pdev = port->pdev;
  1096. frag = &buffer->frag_array[0];
  1097. skb = buffer->skb;
  1098. if (skb && (cmpxchg(&buffer->skb, skb, 0) == skb)) {
  1099. pci_unmap_single(pdev, frag->dma, frag->length,
  1100. PCI_DMA_TODEVICE);
  1101. for (i = 1; i < buffer->frag_count; i++) {
  1102. DPRINTK(INFO, "getting fragment no %d\n", i);
  1103. frag++; /* Get the next frag */
  1104. pci_unmap_page(pdev, frag->dma, frag->length,
  1105. PCI_DMA_TODEVICE);
  1106. }
  1107. port->stats.skbfreed++;
  1108. dev_kfree_skb_any(skb);
  1109. skb = NULL;
  1110. } else if (adapter->proc_cmd_buf_counter == 1) {
  1111. port->stats.txnullskb++;
  1112. }
  1113. if (unlikely(netif_queue_stopped(port->netdev)
  1114. && netif_carrier_ok(port->netdev))
  1115. && ((jiffies - port->netdev->trans_start) >
  1116. port->netdev->watchdog_timeo)) {
  1117. SCHEDULE_WORK(&port->tx_timeout_task);
  1118. }
  1119. last_consumer = get_next_index(last_consumer,
  1120. adapter->max_tx_desc_count);
  1121. count1++;
  1122. }
  1123. adapter->stats.noxmitdone += count1;
  1124. count2 = 0;
  1125. spin_lock(&adapter->tx_lock);
  1126. if ((--adapter->proc_cmd_buf_counter) == 0) {
  1127. adapter->last_cmd_consumer = last_consumer;
  1128. while ((adapter->last_cmd_consumer != consumer)
  1129. && (count2 < MAX_STATUS_HANDLE)) {
  1130. buffer =
  1131. &adapter->cmd_buf_arr[adapter->last_cmd_consumer];
  1132. count2++;
  1133. if (buffer->skb)
  1134. break;
  1135. else
  1136. adapter->last_cmd_consumer =
  1137. get_next_index(adapter->last_cmd_consumer,
  1138. adapter->max_tx_desc_count);
  1139. }
  1140. }
  1141. if (count1 || count2) {
  1142. for (p = 0; p < adapter->ahw.max_ports; p++) {
  1143. nport = adapter->port[p];
  1144. if (netif_queue_stopped(nport->netdev)
  1145. && (nport->flags & NETXEN_NETDEV_STATUS)) {
  1146. netif_wake_queue(nport->netdev);
  1147. nport->flags &= ~NETXEN_NETDEV_STATUS;
  1148. }
  1149. }
  1150. }
  1151. /*
  1152. * If everything is freed up to consumer then check if the ring is full
  1153. * If the ring is full then check if more needs to be freed and
  1154. * schedule the call back again.
  1155. *
  1156. * This happens when there are 2 CPUs. One could be freeing and the
  1157. * other filling it. If the ring is full when we get out of here and
  1158. * the card has already interrupted the host then the host can miss the
  1159. * interrupt.
  1160. *
  1161. * There is still a possible race condition and the host could miss an
  1162. * interrupt. The card has to take care of this.
  1163. */
  1164. if (adapter->last_cmd_consumer == consumer &&
  1165. (((adapter->cmd_producer + 1) %
  1166. adapter->max_tx_desc_count) == adapter->last_cmd_consumer)) {
  1167. consumer = *(adapter->cmd_consumer);
  1168. }
  1169. done = (adapter->last_cmd_consumer == consumer);
  1170. spin_unlock(&adapter->tx_lock);
  1171. DPRINTK(INFO, "last consumer is %d in %s\n", last_consumer,
  1172. __FUNCTION__);
  1173. return (done);
  1174. }
  1175. /*
  1176. * netxen_post_rx_buffers puts buffer in the Phantom memory
  1177. */
  1178. void netxen_post_rx_buffers(struct netxen_adapter *adapter, u32 ctx, u32 ringid)
  1179. {
  1180. struct pci_dev *pdev = adapter->ahw.pdev;
  1181. struct sk_buff *skb;
  1182. struct netxen_recv_context *recv_ctx = &(adapter->recv_ctx[ctx]);
  1183. struct netxen_rcv_desc_ctx *rcv_desc = NULL;
  1184. uint producer;
  1185. struct rcv_desc *pdesc;
  1186. struct netxen_rx_buffer *buffer;
  1187. int count = 0;
  1188. int index = 0;
  1189. netxen_ctx_msg msg = 0;
  1190. dma_addr_t dma;
  1191. adapter->stats.post_called++;
  1192. rcv_desc = &recv_ctx->rcv_desc[ringid];
  1193. producer = rcv_desc->producer;
  1194. index = rcv_desc->begin_alloc;
  1195. buffer = &rcv_desc->rx_buf_arr[index];
  1196. /* We can start writing rx descriptors into the phantom memory. */
  1197. while (buffer->state == NETXEN_BUFFER_FREE) {
  1198. skb = dev_alloc_skb(rcv_desc->skb_size);
  1199. if (unlikely(!skb)) {
  1200. /*
  1201. * TODO
  1202. * We need to schedule the posting of buffers to the pegs.
  1203. */
  1204. rcv_desc->begin_alloc = index;
  1205. DPRINTK(ERR, "netxen_post_rx_buffers: "
  1206. " allocated only %d buffers\n", count);
  1207. break;
  1208. }
  1209. count++; /* now there should be no failure */
  1210. pdesc = &rcv_desc->desc_head[producer];
  1211. #if defined(XGB_DEBUG)
  1212. *(unsigned long *)(skb->head) = 0xc0debabe;
  1213. if (skb_is_nonlinear(skb)) {
  1214. printk("Allocated SKB @%p is nonlinear\n");
  1215. }
  1216. #endif
  1217. skb_reserve(skb, 2);
  1218. /* This will be setup when we receive the
  1219. * buffer after it has been filled FSL TBD TBD
  1220. * skb->dev = netdev;
  1221. */
  1222. dma = pci_map_single(pdev, skb->data, rcv_desc->dma_size,
  1223. PCI_DMA_FROMDEVICE);
  1224. pdesc->addr_buffer = cpu_to_le64(dma);
  1225. buffer->skb = skb;
  1226. buffer->state = NETXEN_BUFFER_BUSY;
  1227. buffer->dma = dma;
  1228. /* make a rcv descriptor */
  1229. pdesc->reference_handle = cpu_to_le16(buffer->ref_handle);
  1230. pdesc->buffer_length = cpu_to_le32(rcv_desc->dma_size);
  1231. DPRINTK(INFO, "done writing descripter\n");
  1232. producer =
  1233. get_next_index(producer, rcv_desc->max_rx_desc_count);
  1234. index = get_next_index(index, rcv_desc->max_rx_desc_count);
  1235. buffer = &rcv_desc->rx_buf_arr[index];
  1236. }
  1237. /* if we did allocate buffers, then write the count to Phantom */
  1238. if (count) {
  1239. rcv_desc->begin_alloc = index;
  1240. rcv_desc->rcv_pending += count;
  1241. adapter->stats.lastposted = count;
  1242. adapter->stats.posted += count;
  1243. rcv_desc->producer = producer;
  1244. if (rcv_desc->rcv_free >= 32) {
  1245. rcv_desc->rcv_free = 0;
  1246. /* Window = 1 */
  1247. writel((producer - 1) &
  1248. (rcv_desc->max_rx_desc_count - 1),
  1249. NETXEN_CRB_NORMALIZE(adapter,
  1250. recv_crb_registers[0].
  1251. rcv_desc_crb[ringid].
  1252. crb_rcv_producer_offset));
  1253. /*
  1254. * Write a doorbell msg to tell phanmon of change in
  1255. * receive ring producer
  1256. */
  1257. netxen_set_msg_peg_id(msg, NETXEN_RCV_PEG_DB_ID);
  1258. netxen_set_msg_privid(msg);
  1259. netxen_set_msg_count(msg,
  1260. ((producer -
  1261. 1) & (rcv_desc->
  1262. max_rx_desc_count - 1)));
  1263. netxen_set_msg_ctxid(msg, 0);
  1264. netxen_set_msg_opcode(msg, NETXEN_RCV_PRODUCER(ringid));
  1265. writel(msg,
  1266. DB_NORMALIZE(adapter,
  1267. NETXEN_RCV_PRODUCER_OFFSET));
  1268. }
  1269. }
  1270. }
  1271. void netxen_post_rx_buffers_nodb(struct netxen_adapter *adapter, uint32_t ctx,
  1272. uint32_t ringid)
  1273. {
  1274. struct pci_dev *pdev = adapter->ahw.pdev;
  1275. struct sk_buff *skb;
  1276. struct netxen_recv_context *recv_ctx = &(adapter->recv_ctx[ctx]);
  1277. struct netxen_rcv_desc_ctx *rcv_desc = NULL;
  1278. u32 producer;
  1279. struct rcv_desc *pdesc;
  1280. struct netxen_rx_buffer *buffer;
  1281. int count = 0;
  1282. int index = 0;
  1283. adapter->stats.post_called++;
  1284. rcv_desc = &recv_ctx->rcv_desc[ringid];
  1285. producer = rcv_desc->producer;
  1286. index = rcv_desc->begin_alloc;
  1287. buffer = &rcv_desc->rx_buf_arr[index];
  1288. /* We can start writing rx descriptors into the phantom memory. */
  1289. while (buffer->state == NETXEN_BUFFER_FREE) {
  1290. skb = dev_alloc_skb(rcv_desc->skb_size);
  1291. if (unlikely(!skb)) {
  1292. /*
  1293. * We need to schedule the posting of buffers to the pegs.
  1294. */
  1295. rcv_desc->begin_alloc = index;
  1296. DPRINTK(ERR, "netxen_post_rx_buffers_nodb: "
  1297. " allocated only %d buffers\n", count);
  1298. break;
  1299. }
  1300. count++; /* now there should be no failure */
  1301. pdesc = &rcv_desc->desc_head[producer];
  1302. skb_reserve(skb, 2);
  1303. /*
  1304. * This will be setup when we receive the
  1305. * buffer after it has been filled
  1306. * skb->dev = netdev;
  1307. */
  1308. buffer->skb = skb;
  1309. buffer->state = NETXEN_BUFFER_BUSY;
  1310. buffer->dma = pci_map_single(pdev, skb->data,
  1311. rcv_desc->dma_size,
  1312. PCI_DMA_FROMDEVICE);
  1313. /* make a rcv descriptor */
  1314. pdesc->reference_handle = cpu_to_le16(buffer->ref_handle);
  1315. pdesc->buffer_length = cpu_to_le32(rcv_desc->dma_size);
  1316. pdesc->addr_buffer = cpu_to_le64(buffer->dma);
  1317. DPRINTK(INFO, "done writing descripter\n");
  1318. producer =
  1319. get_next_index(producer, rcv_desc->max_rx_desc_count);
  1320. index = get_next_index(index, rcv_desc->max_rx_desc_count);
  1321. buffer = &rcv_desc->rx_buf_arr[index];
  1322. }
  1323. /* if we did allocate buffers, then write the count to Phantom */
  1324. if (count) {
  1325. rcv_desc->begin_alloc = index;
  1326. rcv_desc->rcv_pending += count;
  1327. adapter->stats.lastposted = count;
  1328. adapter->stats.posted += count;
  1329. rcv_desc->producer = producer;
  1330. if (rcv_desc->rcv_free >= 32) {
  1331. rcv_desc->rcv_free = 0;
  1332. /* Window = 1 */
  1333. writel((producer - 1) &
  1334. (rcv_desc->max_rx_desc_count - 1),
  1335. NETXEN_CRB_NORMALIZE(adapter,
  1336. recv_crb_registers[0].
  1337. rcv_desc_crb[ringid].
  1338. crb_rcv_producer_offset));
  1339. wmb();
  1340. }
  1341. }
  1342. }
  1343. int netxen_nic_tx_has_work(struct netxen_adapter *adapter)
  1344. {
  1345. if (find_diff_among(adapter->last_cmd_consumer,
  1346. adapter->cmd_producer,
  1347. adapter->max_tx_desc_count) > 0)
  1348. return 1;
  1349. return 0;
  1350. }
  1351. void netxen_nic_clear_stats(struct netxen_adapter *adapter)
  1352. {
  1353. struct netxen_port *port;
  1354. int port_num;
  1355. memset(&adapter->stats, 0, sizeof(adapter->stats));
  1356. for (port_num = 0; port_num < adapter->ahw.max_ports; port_num++) {
  1357. port = adapter->port[port_num];
  1358. memset(&port->stats, 0, sizeof(port->stats));
  1359. }
  1360. }