macb.c 29 KB

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  1. /*
  2. * Atmel MACB Ethernet Controller driver
  3. *
  4. * Copyright (C) 2004-2006 Atmel Corporation
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. */
  10. #include <linux/clk.h>
  11. #include <linux/module.h>
  12. #include <linux/moduleparam.h>
  13. #include <linux/kernel.h>
  14. #include <linux/types.h>
  15. #include <linux/slab.h>
  16. #include <linux/init.h>
  17. #include <linux/netdevice.h>
  18. #include <linux/etherdevice.h>
  19. #include <linux/mii.h>
  20. #include <linux/mutex.h>
  21. #include <linux/dma-mapping.h>
  22. #include <linux/ethtool.h>
  23. #include <linux/platform_device.h>
  24. #include <asm/arch/board.h>
  25. #include "macb.h"
  26. #define to_net_dev(class) container_of(class, struct net_device, class_dev)
  27. #define RX_BUFFER_SIZE 128
  28. #define RX_RING_SIZE 512
  29. #define RX_RING_BYTES (sizeof(struct dma_desc) * RX_RING_SIZE)
  30. /* Make the IP header word-aligned (the ethernet header is 14 bytes) */
  31. #define RX_OFFSET 2
  32. #define TX_RING_SIZE 128
  33. #define DEF_TX_RING_PENDING (TX_RING_SIZE - 1)
  34. #define TX_RING_BYTES (sizeof(struct dma_desc) * TX_RING_SIZE)
  35. #define TX_RING_GAP(bp) \
  36. (TX_RING_SIZE - (bp)->tx_pending)
  37. #define TX_BUFFS_AVAIL(bp) \
  38. (((bp)->tx_tail <= (bp)->tx_head) ? \
  39. (bp)->tx_tail + (bp)->tx_pending - (bp)->tx_head : \
  40. (bp)->tx_tail - (bp)->tx_head - TX_RING_GAP(bp))
  41. #define NEXT_TX(n) (((n) + 1) & (TX_RING_SIZE - 1))
  42. #define NEXT_RX(n) (((n) + 1) & (RX_RING_SIZE - 1))
  43. /* minimum number of free TX descriptors before waking up TX process */
  44. #define MACB_TX_WAKEUP_THRESH (TX_RING_SIZE / 4)
  45. #define MACB_RX_INT_FLAGS (MACB_BIT(RCOMP) | MACB_BIT(RXUBR) \
  46. | MACB_BIT(ISR_ROVR))
  47. static void __macb_set_hwaddr(struct macb *bp)
  48. {
  49. u32 bottom;
  50. u16 top;
  51. bottom = cpu_to_le32(*((u32 *)bp->dev->dev_addr));
  52. macb_writel(bp, SA1B, bottom);
  53. top = cpu_to_le16(*((u16 *)(bp->dev->dev_addr + 4)));
  54. macb_writel(bp, SA1T, top);
  55. }
  56. static void __init macb_get_hwaddr(struct macb *bp)
  57. {
  58. u32 bottom;
  59. u16 top;
  60. u8 addr[6];
  61. bottom = macb_readl(bp, SA1B);
  62. top = macb_readl(bp, SA1T);
  63. addr[0] = bottom & 0xff;
  64. addr[1] = (bottom >> 8) & 0xff;
  65. addr[2] = (bottom >> 16) & 0xff;
  66. addr[3] = (bottom >> 24) & 0xff;
  67. addr[4] = top & 0xff;
  68. addr[5] = (top >> 8) & 0xff;
  69. if (is_valid_ether_addr(addr))
  70. memcpy(bp->dev->dev_addr, addr, sizeof(addr));
  71. }
  72. static void macb_enable_mdio(struct macb *bp)
  73. {
  74. unsigned long flags;
  75. u32 reg;
  76. spin_lock_irqsave(&bp->lock, flags);
  77. reg = macb_readl(bp, NCR);
  78. reg |= MACB_BIT(MPE);
  79. macb_writel(bp, NCR, reg);
  80. macb_writel(bp, IER, MACB_BIT(MFD));
  81. spin_unlock_irqrestore(&bp->lock, flags);
  82. }
  83. static void macb_disable_mdio(struct macb *bp)
  84. {
  85. unsigned long flags;
  86. u32 reg;
  87. spin_lock_irqsave(&bp->lock, flags);
  88. reg = macb_readl(bp, NCR);
  89. reg &= ~MACB_BIT(MPE);
  90. macb_writel(bp, NCR, reg);
  91. macb_writel(bp, IDR, MACB_BIT(MFD));
  92. spin_unlock_irqrestore(&bp->lock, flags);
  93. }
  94. static int macb_mdio_read(struct net_device *dev, int phy_id, int location)
  95. {
  96. struct macb *bp = netdev_priv(dev);
  97. int value;
  98. mutex_lock(&bp->mdio_mutex);
  99. macb_enable_mdio(bp);
  100. macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_SOF)
  101. | MACB_BF(RW, MACB_MAN_READ)
  102. | MACB_BF(PHYA, phy_id)
  103. | MACB_BF(REGA, location)
  104. | MACB_BF(CODE, MACB_MAN_CODE)));
  105. wait_for_completion(&bp->mdio_complete);
  106. value = MACB_BFEXT(DATA, macb_readl(bp, MAN));
  107. macb_disable_mdio(bp);
  108. mutex_unlock(&bp->mdio_mutex);
  109. return value;
  110. }
  111. static void macb_mdio_write(struct net_device *dev, int phy_id,
  112. int location, int val)
  113. {
  114. struct macb *bp = netdev_priv(dev);
  115. dev_dbg(&bp->pdev->dev, "mdio_write %02x:%02x <- %04x\n",
  116. phy_id, location, val);
  117. mutex_lock(&bp->mdio_mutex);
  118. macb_enable_mdio(bp);
  119. macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_SOF)
  120. | MACB_BF(RW, MACB_MAN_WRITE)
  121. | MACB_BF(PHYA, phy_id)
  122. | MACB_BF(REGA, location)
  123. | MACB_BF(CODE, MACB_MAN_CODE)
  124. | MACB_BF(DATA, val)));
  125. wait_for_completion(&bp->mdio_complete);
  126. macb_disable_mdio(bp);
  127. mutex_unlock(&bp->mdio_mutex);
  128. }
  129. static int macb_phy_probe(struct macb *bp)
  130. {
  131. int phy_address;
  132. u16 phyid1, phyid2;
  133. for (phy_address = 0; phy_address < 32; phy_address++) {
  134. phyid1 = macb_mdio_read(bp->dev, phy_address, MII_PHYSID1);
  135. phyid2 = macb_mdio_read(bp->dev, phy_address, MII_PHYSID2);
  136. if (phyid1 != 0xffff && phyid1 != 0x0000
  137. && phyid2 != 0xffff && phyid2 != 0x0000)
  138. break;
  139. }
  140. if (phy_address == 32)
  141. return -ENODEV;
  142. dev_info(&bp->pdev->dev,
  143. "detected PHY at address %d (ID %04x:%04x)\n",
  144. phy_address, phyid1, phyid2);
  145. bp->mii.phy_id = phy_address;
  146. return 0;
  147. }
  148. static void macb_set_media(struct macb *bp, int media)
  149. {
  150. u32 reg;
  151. spin_lock_irq(&bp->lock);
  152. reg = macb_readl(bp, NCFGR);
  153. reg &= ~(MACB_BIT(SPD) | MACB_BIT(FD));
  154. if (media & (ADVERTISE_100HALF | ADVERTISE_100FULL))
  155. reg |= MACB_BIT(SPD);
  156. if (media & ADVERTISE_FULL)
  157. reg |= MACB_BIT(FD);
  158. macb_writel(bp, NCFGR, reg);
  159. spin_unlock_irq(&bp->lock);
  160. }
  161. static void macb_check_media(struct macb *bp, int ok_to_print, int init_media)
  162. {
  163. struct mii_if_info *mii = &bp->mii;
  164. unsigned int old_carrier, new_carrier;
  165. int advertise, lpa, media, duplex;
  166. /* if forced media, go no further */
  167. if (mii->force_media)
  168. return;
  169. /* check current and old link status */
  170. old_carrier = netif_carrier_ok(mii->dev) ? 1 : 0;
  171. new_carrier = (unsigned int) mii_link_ok(mii);
  172. /* if carrier state did not change, assume nothing else did */
  173. if (!init_media && old_carrier == new_carrier)
  174. return;
  175. /* no carrier, nothing much to do */
  176. if (!new_carrier) {
  177. netif_carrier_off(mii->dev);
  178. printk(KERN_INFO "%s: link down\n", mii->dev->name);
  179. return;
  180. }
  181. /*
  182. * we have carrier, see who's on the other end
  183. */
  184. netif_carrier_on(mii->dev);
  185. /* get MII advertise and LPA values */
  186. if (!init_media && mii->advertising) {
  187. advertise = mii->advertising;
  188. } else {
  189. advertise = mii->mdio_read(mii->dev, mii->phy_id, MII_ADVERTISE);
  190. mii->advertising = advertise;
  191. }
  192. lpa = mii->mdio_read(mii->dev, mii->phy_id, MII_LPA);
  193. /* figure out media and duplex from advertise and LPA values */
  194. media = mii_nway_result(lpa & advertise);
  195. duplex = (media & ADVERTISE_FULL) ? 1 : 0;
  196. if (ok_to_print)
  197. printk(KERN_INFO "%s: link up, %sMbps, %s-duplex, lpa 0x%04X\n",
  198. mii->dev->name,
  199. media & (ADVERTISE_100FULL | ADVERTISE_100HALF) ? "100" : "10",
  200. duplex ? "full" : "half", lpa);
  201. mii->full_duplex = duplex;
  202. /* Let the MAC know about the new link state */
  203. macb_set_media(bp, media);
  204. }
  205. static void macb_update_stats(struct macb *bp)
  206. {
  207. u32 __iomem *reg = bp->regs + MACB_PFR;
  208. u32 *p = &bp->hw_stats.rx_pause_frames;
  209. u32 *end = &bp->hw_stats.tx_pause_frames + 1;
  210. WARN_ON((unsigned long)(end - p - 1) != (MACB_TPF - MACB_PFR) / 4);
  211. for(; p < end; p++, reg++)
  212. *p += __raw_readl(reg);
  213. }
  214. static void macb_periodic_task(struct work_struct *work)
  215. {
  216. struct macb *bp = container_of(work, struct macb, periodic_task.work);
  217. macb_update_stats(bp);
  218. macb_check_media(bp, 1, 0);
  219. schedule_delayed_work(&bp->periodic_task, HZ);
  220. }
  221. static void macb_tx(struct macb *bp)
  222. {
  223. unsigned int tail;
  224. unsigned int head;
  225. u32 status;
  226. status = macb_readl(bp, TSR);
  227. macb_writel(bp, TSR, status);
  228. dev_dbg(&bp->pdev->dev, "macb_tx status = %02lx\n",
  229. (unsigned long)status);
  230. if (status & MACB_BIT(UND)) {
  231. printk(KERN_ERR "%s: TX underrun, resetting buffers\n",
  232. bp->dev->name);
  233. bp->tx_head = bp->tx_tail = 0;
  234. }
  235. if (!(status & MACB_BIT(COMP)))
  236. /*
  237. * This may happen when a buffer becomes complete
  238. * between reading the ISR and scanning the
  239. * descriptors. Nothing to worry about.
  240. */
  241. return;
  242. head = bp->tx_head;
  243. for (tail = bp->tx_tail; tail != head; tail = NEXT_TX(tail)) {
  244. struct ring_info *rp = &bp->tx_skb[tail];
  245. struct sk_buff *skb = rp->skb;
  246. u32 bufstat;
  247. BUG_ON(skb == NULL);
  248. rmb();
  249. bufstat = bp->tx_ring[tail].ctrl;
  250. if (!(bufstat & MACB_BIT(TX_USED)))
  251. break;
  252. dev_dbg(&bp->pdev->dev, "skb %u (data %p) TX complete\n",
  253. tail, skb->data);
  254. dma_unmap_single(&bp->pdev->dev, rp->mapping, skb->len,
  255. DMA_TO_DEVICE);
  256. bp->stats.tx_packets++;
  257. bp->stats.tx_bytes += skb->len;
  258. rp->skb = NULL;
  259. dev_kfree_skb_irq(skb);
  260. }
  261. bp->tx_tail = tail;
  262. if (netif_queue_stopped(bp->dev) &&
  263. TX_BUFFS_AVAIL(bp) > MACB_TX_WAKEUP_THRESH)
  264. netif_wake_queue(bp->dev);
  265. }
  266. static int macb_rx_frame(struct macb *bp, unsigned int first_frag,
  267. unsigned int last_frag)
  268. {
  269. unsigned int len;
  270. unsigned int frag;
  271. unsigned int offset = 0;
  272. struct sk_buff *skb;
  273. len = MACB_BFEXT(RX_FRMLEN, bp->rx_ring[last_frag].ctrl);
  274. dev_dbg(&bp->pdev->dev, "macb_rx_frame frags %u - %u (len %u)\n",
  275. first_frag, last_frag, len);
  276. skb = dev_alloc_skb(len + RX_OFFSET);
  277. if (!skb) {
  278. bp->stats.rx_dropped++;
  279. for (frag = first_frag; ; frag = NEXT_RX(frag)) {
  280. bp->rx_ring[frag].addr &= ~MACB_BIT(RX_USED);
  281. if (frag == last_frag)
  282. break;
  283. }
  284. wmb();
  285. return 1;
  286. }
  287. skb_reserve(skb, RX_OFFSET);
  288. skb->dev = bp->dev;
  289. skb->ip_summed = CHECKSUM_NONE;
  290. skb_put(skb, len);
  291. for (frag = first_frag; ; frag = NEXT_RX(frag)) {
  292. unsigned int frag_len = RX_BUFFER_SIZE;
  293. if (offset + frag_len > len) {
  294. BUG_ON(frag != last_frag);
  295. frag_len = len - offset;
  296. }
  297. memcpy(skb->data + offset,
  298. bp->rx_buffers + (RX_BUFFER_SIZE * frag),
  299. frag_len);
  300. offset += RX_BUFFER_SIZE;
  301. bp->rx_ring[frag].addr &= ~MACB_BIT(RX_USED);
  302. wmb();
  303. if (frag == last_frag)
  304. break;
  305. }
  306. skb->protocol = eth_type_trans(skb, bp->dev);
  307. bp->stats.rx_packets++;
  308. bp->stats.rx_bytes += len;
  309. bp->dev->last_rx = jiffies;
  310. dev_dbg(&bp->pdev->dev, "received skb of length %u, csum: %08x\n",
  311. skb->len, skb->csum);
  312. netif_receive_skb(skb);
  313. return 0;
  314. }
  315. /* Mark DMA descriptors from begin up to and not including end as unused */
  316. static void discard_partial_frame(struct macb *bp, unsigned int begin,
  317. unsigned int end)
  318. {
  319. unsigned int frag;
  320. for (frag = begin; frag != end; frag = NEXT_RX(frag))
  321. bp->rx_ring[frag].addr &= ~MACB_BIT(RX_USED);
  322. wmb();
  323. /*
  324. * When this happens, the hardware stats registers for
  325. * whatever caused this is updated, so we don't have to record
  326. * anything.
  327. */
  328. }
  329. static int macb_rx(struct macb *bp, int budget)
  330. {
  331. int received = 0;
  332. unsigned int tail = bp->rx_tail;
  333. int first_frag = -1;
  334. for (; budget > 0; tail = NEXT_RX(tail)) {
  335. u32 addr, ctrl;
  336. rmb();
  337. addr = bp->rx_ring[tail].addr;
  338. ctrl = bp->rx_ring[tail].ctrl;
  339. if (!(addr & MACB_BIT(RX_USED)))
  340. break;
  341. if (ctrl & MACB_BIT(RX_SOF)) {
  342. if (first_frag != -1)
  343. discard_partial_frame(bp, first_frag, tail);
  344. first_frag = tail;
  345. }
  346. if (ctrl & MACB_BIT(RX_EOF)) {
  347. int dropped;
  348. BUG_ON(first_frag == -1);
  349. dropped = macb_rx_frame(bp, first_frag, tail);
  350. first_frag = -1;
  351. if (!dropped) {
  352. received++;
  353. budget--;
  354. }
  355. }
  356. }
  357. if (first_frag != -1)
  358. bp->rx_tail = first_frag;
  359. else
  360. bp->rx_tail = tail;
  361. return received;
  362. }
  363. static int macb_poll(struct net_device *dev, int *budget)
  364. {
  365. struct macb *bp = netdev_priv(dev);
  366. int orig_budget, work_done, retval = 0;
  367. u32 status;
  368. status = macb_readl(bp, RSR);
  369. macb_writel(bp, RSR, status);
  370. if (!status) {
  371. /*
  372. * This may happen if an interrupt was pending before
  373. * this function was called last time, and no packets
  374. * have been received since.
  375. */
  376. netif_rx_complete(dev);
  377. goto out;
  378. }
  379. dev_dbg(&bp->pdev->dev, "poll: status = %08lx, budget = %d\n",
  380. (unsigned long)status, *budget);
  381. if (!(status & MACB_BIT(REC))) {
  382. dev_warn(&bp->pdev->dev,
  383. "No RX buffers complete, status = %02lx\n",
  384. (unsigned long)status);
  385. netif_rx_complete(dev);
  386. goto out;
  387. }
  388. orig_budget = *budget;
  389. if (orig_budget > dev->quota)
  390. orig_budget = dev->quota;
  391. work_done = macb_rx(bp, orig_budget);
  392. if (work_done < orig_budget) {
  393. netif_rx_complete(dev);
  394. retval = 0;
  395. } else {
  396. retval = 1;
  397. }
  398. /*
  399. * We've done what we can to clean the buffers. Make sure we
  400. * get notified when new packets arrive.
  401. */
  402. out:
  403. macb_writel(bp, IER, MACB_RX_INT_FLAGS);
  404. /* TODO: Handle errors */
  405. return retval;
  406. }
  407. static irqreturn_t macb_interrupt(int irq, void *dev_id)
  408. {
  409. struct net_device *dev = dev_id;
  410. struct macb *bp = netdev_priv(dev);
  411. u32 status;
  412. status = macb_readl(bp, ISR);
  413. if (unlikely(!status))
  414. return IRQ_NONE;
  415. spin_lock(&bp->lock);
  416. while (status) {
  417. if (status & MACB_BIT(MFD))
  418. complete(&bp->mdio_complete);
  419. /* close possible race with dev_close */
  420. if (unlikely(!netif_running(dev))) {
  421. macb_writel(bp, IDR, ~0UL);
  422. break;
  423. }
  424. if (status & MACB_RX_INT_FLAGS) {
  425. if (netif_rx_schedule_prep(dev)) {
  426. /*
  427. * There's no point taking any more interrupts
  428. * until we have processed the buffers
  429. */
  430. macb_writel(bp, IDR, MACB_RX_INT_FLAGS);
  431. dev_dbg(&bp->pdev->dev, "scheduling RX softirq\n");
  432. __netif_rx_schedule(dev);
  433. }
  434. }
  435. if (status & (MACB_BIT(TCOMP) | MACB_BIT(ISR_TUND)))
  436. macb_tx(bp);
  437. /*
  438. * Link change detection isn't possible with RMII, so we'll
  439. * add that if/when we get our hands on a full-blown MII PHY.
  440. */
  441. if (status & MACB_BIT(HRESP)) {
  442. /*
  443. * TODO: Reset the hardware, and maybe move the printk
  444. * to a lower-priority context as well (work queue?)
  445. */
  446. printk(KERN_ERR "%s: DMA bus error: HRESP not OK\n",
  447. dev->name);
  448. }
  449. status = macb_readl(bp, ISR);
  450. }
  451. spin_unlock(&bp->lock);
  452. return IRQ_HANDLED;
  453. }
  454. static int macb_start_xmit(struct sk_buff *skb, struct net_device *dev)
  455. {
  456. struct macb *bp = netdev_priv(dev);
  457. dma_addr_t mapping;
  458. unsigned int len, entry;
  459. u32 ctrl;
  460. #ifdef DEBUG
  461. int i;
  462. dev_dbg(&bp->pdev->dev,
  463. "start_xmit: len %u head %p data %p tail %p end %p\n",
  464. skb->len, skb->head, skb->data, skb->tail, skb->end);
  465. dev_dbg(&bp->pdev->dev,
  466. "data:");
  467. for (i = 0; i < 16; i++)
  468. printk(" %02x", (unsigned int)skb->data[i]);
  469. printk("\n");
  470. #endif
  471. len = skb->len;
  472. spin_lock_irq(&bp->lock);
  473. /* This is a hard error, log it. */
  474. if (TX_BUFFS_AVAIL(bp) < 1) {
  475. netif_stop_queue(dev);
  476. spin_unlock_irq(&bp->lock);
  477. dev_err(&bp->pdev->dev,
  478. "BUG! Tx Ring full when queue awake!\n");
  479. dev_dbg(&bp->pdev->dev, "tx_head = %u, tx_tail = %u\n",
  480. bp->tx_head, bp->tx_tail);
  481. return 1;
  482. }
  483. entry = bp->tx_head;
  484. dev_dbg(&bp->pdev->dev, "Allocated ring entry %u\n", entry);
  485. mapping = dma_map_single(&bp->pdev->dev, skb->data,
  486. len, DMA_TO_DEVICE);
  487. bp->tx_skb[entry].skb = skb;
  488. bp->tx_skb[entry].mapping = mapping;
  489. dev_dbg(&bp->pdev->dev, "Mapped skb data %p to DMA addr %08lx\n",
  490. skb->data, (unsigned long)mapping);
  491. ctrl = MACB_BF(TX_FRMLEN, len);
  492. ctrl |= MACB_BIT(TX_LAST);
  493. if (entry == (TX_RING_SIZE - 1))
  494. ctrl |= MACB_BIT(TX_WRAP);
  495. bp->tx_ring[entry].addr = mapping;
  496. bp->tx_ring[entry].ctrl = ctrl;
  497. wmb();
  498. entry = NEXT_TX(entry);
  499. bp->tx_head = entry;
  500. macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART));
  501. if (TX_BUFFS_AVAIL(bp) < 1)
  502. netif_stop_queue(dev);
  503. spin_unlock_irq(&bp->lock);
  504. dev->trans_start = jiffies;
  505. return 0;
  506. }
  507. static void macb_free_consistent(struct macb *bp)
  508. {
  509. if (bp->tx_skb) {
  510. kfree(bp->tx_skb);
  511. bp->tx_skb = NULL;
  512. }
  513. if (bp->rx_ring) {
  514. dma_free_coherent(&bp->pdev->dev, RX_RING_BYTES,
  515. bp->rx_ring, bp->rx_ring_dma);
  516. bp->rx_ring = NULL;
  517. }
  518. if (bp->tx_ring) {
  519. dma_free_coherent(&bp->pdev->dev, TX_RING_BYTES,
  520. bp->tx_ring, bp->tx_ring_dma);
  521. bp->tx_ring = NULL;
  522. }
  523. if (bp->rx_buffers) {
  524. dma_free_coherent(&bp->pdev->dev,
  525. RX_RING_SIZE * RX_BUFFER_SIZE,
  526. bp->rx_buffers, bp->rx_buffers_dma);
  527. bp->rx_buffers = NULL;
  528. }
  529. }
  530. static int macb_alloc_consistent(struct macb *bp)
  531. {
  532. int size;
  533. size = TX_RING_SIZE * sizeof(struct ring_info);
  534. bp->tx_skb = kmalloc(size, GFP_KERNEL);
  535. if (!bp->tx_skb)
  536. goto out_err;
  537. size = RX_RING_BYTES;
  538. bp->rx_ring = dma_alloc_coherent(&bp->pdev->dev, size,
  539. &bp->rx_ring_dma, GFP_KERNEL);
  540. if (!bp->rx_ring)
  541. goto out_err;
  542. dev_dbg(&bp->pdev->dev,
  543. "Allocated RX ring of %d bytes at %08lx (mapped %p)\n",
  544. size, (unsigned long)bp->rx_ring_dma, bp->rx_ring);
  545. size = TX_RING_BYTES;
  546. bp->tx_ring = dma_alloc_coherent(&bp->pdev->dev, size,
  547. &bp->tx_ring_dma, GFP_KERNEL);
  548. if (!bp->tx_ring)
  549. goto out_err;
  550. dev_dbg(&bp->pdev->dev,
  551. "Allocated TX ring of %d bytes at %08lx (mapped %p)\n",
  552. size, (unsigned long)bp->tx_ring_dma, bp->tx_ring);
  553. size = RX_RING_SIZE * RX_BUFFER_SIZE;
  554. bp->rx_buffers = dma_alloc_coherent(&bp->pdev->dev, size,
  555. &bp->rx_buffers_dma, GFP_KERNEL);
  556. if (!bp->rx_buffers)
  557. goto out_err;
  558. dev_dbg(&bp->pdev->dev,
  559. "Allocated RX buffers of %d bytes at %08lx (mapped %p)\n",
  560. size, (unsigned long)bp->rx_buffers_dma, bp->rx_buffers);
  561. return 0;
  562. out_err:
  563. macb_free_consistent(bp);
  564. return -ENOMEM;
  565. }
  566. static void macb_init_rings(struct macb *bp)
  567. {
  568. int i;
  569. dma_addr_t addr;
  570. addr = bp->rx_buffers_dma;
  571. for (i = 0; i < RX_RING_SIZE; i++) {
  572. bp->rx_ring[i].addr = addr;
  573. bp->rx_ring[i].ctrl = 0;
  574. addr += RX_BUFFER_SIZE;
  575. }
  576. bp->rx_ring[RX_RING_SIZE - 1].addr |= MACB_BIT(RX_WRAP);
  577. for (i = 0; i < TX_RING_SIZE; i++) {
  578. bp->tx_ring[i].addr = 0;
  579. bp->tx_ring[i].ctrl = MACB_BIT(TX_USED);
  580. }
  581. bp->tx_ring[TX_RING_SIZE - 1].ctrl |= MACB_BIT(TX_WRAP);
  582. bp->rx_tail = bp->tx_head = bp->tx_tail = 0;
  583. }
  584. static void macb_reset_hw(struct macb *bp)
  585. {
  586. /* Make sure we have the write buffer for ourselves */
  587. wmb();
  588. /*
  589. * Disable RX and TX (XXX: Should we halt the transmission
  590. * more gracefully?)
  591. */
  592. macb_writel(bp, NCR, 0);
  593. /* Clear the stats registers (XXX: Update stats first?) */
  594. macb_writel(bp, NCR, MACB_BIT(CLRSTAT));
  595. /* Clear all status flags */
  596. macb_writel(bp, TSR, ~0UL);
  597. macb_writel(bp, RSR, ~0UL);
  598. /* Disable all interrupts */
  599. macb_writel(bp, IDR, ~0UL);
  600. macb_readl(bp, ISR);
  601. }
  602. static void macb_init_hw(struct macb *bp)
  603. {
  604. u32 config;
  605. macb_reset_hw(bp);
  606. __macb_set_hwaddr(bp);
  607. config = macb_readl(bp, NCFGR) & MACB_BF(CLK, -1L);
  608. config |= MACB_BIT(PAE); /* PAuse Enable */
  609. config |= MACB_BIT(DRFCS); /* Discard Rx FCS */
  610. if (bp->dev->flags & IFF_PROMISC)
  611. config |= MACB_BIT(CAF); /* Copy All Frames */
  612. if (!(bp->dev->flags & IFF_BROADCAST))
  613. config |= MACB_BIT(NBC); /* No BroadCast */
  614. macb_writel(bp, NCFGR, config);
  615. /* Initialize TX and RX buffers */
  616. macb_writel(bp, RBQP, bp->rx_ring_dma);
  617. macb_writel(bp, TBQP, bp->tx_ring_dma);
  618. /* Enable TX and RX */
  619. macb_writel(bp, NCR, MACB_BIT(RE) | MACB_BIT(TE));
  620. /* Enable interrupts */
  621. macb_writel(bp, IER, (MACB_BIT(RCOMP)
  622. | MACB_BIT(RXUBR)
  623. | MACB_BIT(ISR_TUND)
  624. | MACB_BIT(ISR_RLE)
  625. | MACB_BIT(TXERR)
  626. | MACB_BIT(TCOMP)
  627. | MACB_BIT(ISR_ROVR)
  628. | MACB_BIT(HRESP)));
  629. }
  630. static void macb_init_phy(struct net_device *dev)
  631. {
  632. struct macb *bp = netdev_priv(dev);
  633. /* Set some reasonable default settings */
  634. macb_mdio_write(dev, bp->mii.phy_id, MII_ADVERTISE,
  635. ADVERTISE_CSMA | ADVERTISE_ALL);
  636. macb_mdio_write(dev, bp->mii.phy_id, MII_BMCR,
  637. (BMCR_SPEED100 | BMCR_ANENABLE
  638. | BMCR_ANRESTART | BMCR_FULLDPLX));
  639. }
  640. static int macb_open(struct net_device *dev)
  641. {
  642. struct macb *bp = netdev_priv(dev);
  643. int err;
  644. dev_dbg(&bp->pdev->dev, "open\n");
  645. if (!is_valid_ether_addr(dev->dev_addr))
  646. return -EADDRNOTAVAIL;
  647. err = macb_alloc_consistent(bp);
  648. if (err) {
  649. printk(KERN_ERR
  650. "%s: Unable to allocate DMA memory (error %d)\n",
  651. dev->name, err);
  652. return err;
  653. }
  654. macb_init_rings(bp);
  655. macb_init_hw(bp);
  656. macb_init_phy(dev);
  657. macb_check_media(bp, 1, 1);
  658. netif_start_queue(dev);
  659. schedule_delayed_work(&bp->periodic_task, HZ);
  660. return 0;
  661. }
  662. static int macb_close(struct net_device *dev)
  663. {
  664. struct macb *bp = netdev_priv(dev);
  665. unsigned long flags;
  666. cancel_rearming_delayed_work(&bp->periodic_task);
  667. netif_stop_queue(dev);
  668. spin_lock_irqsave(&bp->lock, flags);
  669. macb_reset_hw(bp);
  670. netif_carrier_off(dev);
  671. spin_unlock_irqrestore(&bp->lock, flags);
  672. macb_free_consistent(bp);
  673. return 0;
  674. }
  675. static struct net_device_stats *macb_get_stats(struct net_device *dev)
  676. {
  677. struct macb *bp = netdev_priv(dev);
  678. struct net_device_stats *nstat = &bp->stats;
  679. struct macb_stats *hwstat = &bp->hw_stats;
  680. /* Convert HW stats into netdevice stats */
  681. nstat->rx_errors = (hwstat->rx_fcs_errors +
  682. hwstat->rx_align_errors +
  683. hwstat->rx_resource_errors +
  684. hwstat->rx_overruns +
  685. hwstat->rx_oversize_pkts +
  686. hwstat->rx_jabbers +
  687. hwstat->rx_undersize_pkts +
  688. hwstat->sqe_test_errors +
  689. hwstat->rx_length_mismatch);
  690. nstat->tx_errors = (hwstat->tx_late_cols +
  691. hwstat->tx_excessive_cols +
  692. hwstat->tx_underruns +
  693. hwstat->tx_carrier_errors);
  694. nstat->collisions = (hwstat->tx_single_cols +
  695. hwstat->tx_multiple_cols +
  696. hwstat->tx_excessive_cols);
  697. nstat->rx_length_errors = (hwstat->rx_oversize_pkts +
  698. hwstat->rx_jabbers +
  699. hwstat->rx_undersize_pkts +
  700. hwstat->rx_length_mismatch);
  701. nstat->rx_over_errors = hwstat->rx_resource_errors;
  702. nstat->rx_crc_errors = hwstat->rx_fcs_errors;
  703. nstat->rx_frame_errors = hwstat->rx_align_errors;
  704. nstat->rx_fifo_errors = hwstat->rx_overruns;
  705. /* XXX: What does "missed" mean? */
  706. nstat->tx_aborted_errors = hwstat->tx_excessive_cols;
  707. nstat->tx_carrier_errors = hwstat->tx_carrier_errors;
  708. nstat->tx_fifo_errors = hwstat->tx_underruns;
  709. /* Don't know about heartbeat or window errors... */
  710. return nstat;
  711. }
  712. static int macb_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
  713. {
  714. struct macb *bp = netdev_priv(dev);
  715. int ret;
  716. unsigned long flags;
  717. spin_lock_irqsave(&bp->lock, flags);
  718. ret = mii_ethtool_gset(&bp->mii, cmd);
  719. spin_unlock_irqrestore(&bp->lock, flags);
  720. return ret;
  721. }
  722. static int macb_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
  723. {
  724. struct macb *bp = netdev_priv(dev);
  725. int ret;
  726. unsigned long flags;
  727. spin_lock_irqsave(&bp->lock, flags);
  728. ret = mii_ethtool_sset(&bp->mii, cmd);
  729. spin_unlock_irqrestore(&bp->lock, flags);
  730. return ret;
  731. }
  732. static void macb_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
  733. {
  734. struct macb *bp = netdev_priv(dev);
  735. strcpy(info->driver, bp->pdev->dev.driver->name);
  736. strcpy(info->version, "$Revision: 1.14 $");
  737. strcpy(info->bus_info, bp->pdev->dev.bus_id);
  738. }
  739. static int macb_nway_reset(struct net_device *dev)
  740. {
  741. struct macb *bp = netdev_priv(dev);
  742. return mii_nway_restart(&bp->mii);
  743. }
  744. static struct ethtool_ops macb_ethtool_ops = {
  745. .get_settings = macb_get_settings,
  746. .set_settings = macb_set_settings,
  747. .get_drvinfo = macb_get_drvinfo,
  748. .nway_reset = macb_nway_reset,
  749. .get_link = ethtool_op_get_link,
  750. };
  751. static int macb_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
  752. {
  753. struct macb *bp = netdev_priv(dev);
  754. int ret;
  755. unsigned long flags;
  756. if (!netif_running(dev))
  757. return -EINVAL;
  758. spin_lock_irqsave(&bp->lock, flags);
  759. ret = generic_mii_ioctl(&bp->mii, if_mii(rq), cmd, NULL);
  760. spin_unlock_irqrestore(&bp->lock, flags);
  761. return ret;
  762. }
  763. static ssize_t macb_mii_show(const struct class_device *cd, char *buf,
  764. unsigned long addr)
  765. {
  766. struct net_device *dev = to_net_dev(cd);
  767. struct macb *bp = netdev_priv(dev);
  768. ssize_t ret = -EINVAL;
  769. if (netif_running(dev)) {
  770. int value;
  771. value = macb_mdio_read(dev, bp->mii.phy_id, addr);
  772. ret = sprintf(buf, "0x%04x\n", (uint16_t)value);
  773. }
  774. return ret;
  775. }
  776. #define MII_ENTRY(name, addr) \
  777. static ssize_t show_##name(struct class_device *cd, char *buf) \
  778. { \
  779. return macb_mii_show(cd, buf, addr); \
  780. } \
  781. static CLASS_DEVICE_ATTR(name, S_IRUGO, show_##name, NULL)
  782. MII_ENTRY(bmcr, MII_BMCR);
  783. MII_ENTRY(bmsr, MII_BMSR);
  784. MII_ENTRY(physid1, MII_PHYSID1);
  785. MII_ENTRY(physid2, MII_PHYSID2);
  786. MII_ENTRY(advertise, MII_ADVERTISE);
  787. MII_ENTRY(lpa, MII_LPA);
  788. MII_ENTRY(expansion, MII_EXPANSION);
  789. static struct attribute *macb_mii_attrs[] = {
  790. &class_device_attr_bmcr.attr,
  791. &class_device_attr_bmsr.attr,
  792. &class_device_attr_physid1.attr,
  793. &class_device_attr_physid2.attr,
  794. &class_device_attr_advertise.attr,
  795. &class_device_attr_lpa.attr,
  796. &class_device_attr_expansion.attr,
  797. NULL,
  798. };
  799. static struct attribute_group macb_mii_group = {
  800. .name = "mii",
  801. .attrs = macb_mii_attrs,
  802. };
  803. static void macb_unregister_sysfs(struct net_device *net)
  804. {
  805. struct class_device *class_dev = &net->class_dev;
  806. sysfs_remove_group(&class_dev->kobj, &macb_mii_group);
  807. }
  808. static int macb_register_sysfs(struct net_device *net)
  809. {
  810. struct class_device *class_dev = &net->class_dev;
  811. int ret;
  812. ret = sysfs_create_group(&class_dev->kobj, &macb_mii_group);
  813. if (ret)
  814. printk(KERN_WARNING
  815. "%s: sysfs mii attribute registration failed: %d\n",
  816. net->name, ret);
  817. return ret;
  818. }
  819. static int __devinit macb_probe(struct platform_device *pdev)
  820. {
  821. struct eth_platform_data *pdata;
  822. struct resource *regs;
  823. struct net_device *dev;
  824. struct macb *bp;
  825. unsigned long pclk_hz;
  826. u32 config;
  827. int err = -ENXIO;
  828. regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  829. if (!regs) {
  830. dev_err(&pdev->dev, "no mmio resource defined\n");
  831. goto err_out;
  832. }
  833. err = -ENOMEM;
  834. dev = alloc_etherdev(sizeof(*bp));
  835. if (!dev) {
  836. dev_err(&pdev->dev, "etherdev alloc failed, aborting.\n");
  837. goto err_out;
  838. }
  839. SET_MODULE_OWNER(dev);
  840. SET_NETDEV_DEV(dev, &pdev->dev);
  841. /* TODO: Actually, we have some interesting features... */
  842. dev->features |= 0;
  843. bp = netdev_priv(dev);
  844. bp->pdev = pdev;
  845. bp->dev = dev;
  846. spin_lock_init(&bp->lock);
  847. #if defined(CONFIG_ARCH_AT91)
  848. bp->pclk = clk_get(&pdev->dev, "macb_clk");
  849. if (IS_ERR(bp->pclk)) {
  850. dev_err(&pdev->dev, "failed to get macb_clk\n");
  851. goto err_out_free_dev;
  852. }
  853. clk_enable(bp->pclk);
  854. #else
  855. bp->pclk = clk_get(&pdev->dev, "pclk");
  856. if (IS_ERR(bp->pclk)) {
  857. dev_err(&pdev->dev, "failed to get pclk\n");
  858. goto err_out_free_dev;
  859. }
  860. bp->hclk = clk_get(&pdev->dev, "hclk");
  861. if (IS_ERR(bp->hclk)) {
  862. dev_err(&pdev->dev, "failed to get hclk\n");
  863. goto err_out_put_pclk;
  864. }
  865. clk_enable(bp->pclk);
  866. clk_enable(bp->hclk);
  867. #endif
  868. bp->regs = ioremap(regs->start, regs->end - regs->start + 1);
  869. if (!bp->regs) {
  870. dev_err(&pdev->dev, "failed to map registers, aborting.\n");
  871. err = -ENOMEM;
  872. goto err_out_disable_clocks;
  873. }
  874. dev->irq = platform_get_irq(pdev, 0);
  875. err = request_irq(dev->irq, macb_interrupt, SA_SAMPLE_RANDOM,
  876. dev->name, dev);
  877. if (err) {
  878. printk(KERN_ERR
  879. "%s: Unable to request IRQ %d (error %d)\n",
  880. dev->name, dev->irq, err);
  881. goto err_out_iounmap;
  882. }
  883. dev->open = macb_open;
  884. dev->stop = macb_close;
  885. dev->hard_start_xmit = macb_start_xmit;
  886. dev->get_stats = macb_get_stats;
  887. dev->do_ioctl = macb_ioctl;
  888. dev->poll = macb_poll;
  889. dev->weight = 64;
  890. dev->ethtool_ops = &macb_ethtool_ops;
  891. dev->base_addr = regs->start;
  892. INIT_DELAYED_WORK(&bp->periodic_task, macb_periodic_task);
  893. mutex_init(&bp->mdio_mutex);
  894. init_completion(&bp->mdio_complete);
  895. /* Set MII management clock divider */
  896. pclk_hz = clk_get_rate(bp->pclk);
  897. if (pclk_hz <= 20000000)
  898. config = MACB_BF(CLK, MACB_CLK_DIV8);
  899. else if (pclk_hz <= 40000000)
  900. config = MACB_BF(CLK, MACB_CLK_DIV16);
  901. else if (pclk_hz <= 80000000)
  902. config = MACB_BF(CLK, MACB_CLK_DIV32);
  903. else
  904. config = MACB_BF(CLK, MACB_CLK_DIV64);
  905. macb_writel(bp, NCFGR, config);
  906. bp->mii.dev = dev;
  907. bp->mii.mdio_read = macb_mdio_read;
  908. bp->mii.mdio_write = macb_mdio_write;
  909. bp->mii.phy_id_mask = 0x1f;
  910. bp->mii.reg_num_mask = 0x1f;
  911. macb_get_hwaddr(bp);
  912. err = macb_phy_probe(bp);
  913. if (err) {
  914. dev_err(&pdev->dev, "Failed to detect PHY, aborting.\n");
  915. goto err_out_free_irq;
  916. }
  917. pdata = pdev->dev.platform_data;
  918. if (pdata && pdata->is_rmii)
  919. #if defined(CONFIG_ARCH_AT91)
  920. macb_writel(bp, USRIO, (MACB_BIT(RMII) | MACB_BIT(CLKEN)) );
  921. #else
  922. macb_writel(bp, USRIO, 0);
  923. #endif
  924. else
  925. #if defined(CONFIG_ARCH_AT91)
  926. macb_writel(bp, USRIO, MACB_BIT(CLKEN));
  927. #else
  928. macb_writel(bp, USRIO, MACB_BIT(MII));
  929. #endif
  930. bp->tx_pending = DEF_TX_RING_PENDING;
  931. err = register_netdev(dev);
  932. if (err) {
  933. dev_err(&pdev->dev, "Cannot register net device, aborting.\n");
  934. goto err_out_free_irq;
  935. }
  936. platform_set_drvdata(pdev, dev);
  937. macb_register_sysfs(dev);
  938. printk(KERN_INFO "%s: Atmel MACB at 0x%08lx irq %d "
  939. "(%02x:%02x:%02x:%02x:%02x:%02x)\n",
  940. dev->name, dev->base_addr, dev->irq,
  941. dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
  942. dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
  943. return 0;
  944. err_out_free_irq:
  945. free_irq(dev->irq, dev);
  946. err_out_iounmap:
  947. iounmap(bp->regs);
  948. err_out_disable_clocks:
  949. #ifndef CONFIG_ARCH_AT91
  950. clk_disable(bp->hclk);
  951. clk_put(bp->hclk);
  952. #endif
  953. clk_disable(bp->pclk);
  954. err_out_put_pclk:
  955. clk_put(bp->pclk);
  956. err_out_free_dev:
  957. free_netdev(dev);
  958. err_out:
  959. platform_set_drvdata(pdev, NULL);
  960. return err;
  961. }
  962. static int __devexit macb_remove(struct platform_device *pdev)
  963. {
  964. struct net_device *dev;
  965. struct macb *bp;
  966. dev = platform_get_drvdata(pdev);
  967. if (dev) {
  968. bp = netdev_priv(dev);
  969. macb_unregister_sysfs(dev);
  970. unregister_netdev(dev);
  971. free_irq(dev->irq, dev);
  972. iounmap(bp->regs);
  973. #ifndef CONFIG_ARCH_AT91
  974. clk_disable(bp->hclk);
  975. clk_put(bp->hclk);
  976. #endif
  977. clk_disable(bp->pclk);
  978. clk_put(bp->pclk);
  979. free_netdev(dev);
  980. platform_set_drvdata(pdev, NULL);
  981. }
  982. return 0;
  983. }
  984. static struct platform_driver macb_driver = {
  985. .probe = macb_probe,
  986. .remove = __devexit_p(macb_remove),
  987. .driver = {
  988. .name = "macb",
  989. },
  990. };
  991. static int __init macb_init(void)
  992. {
  993. return platform_driver_register(&macb_driver);
  994. }
  995. static void __exit macb_exit(void)
  996. {
  997. platform_driver_unregister(&macb_driver);
  998. }
  999. module_init(macb_init);
  1000. module_exit(macb_exit);
  1001. MODULE_LICENSE("GPL");
  1002. MODULE_DESCRIPTION("Atmel MACB Ethernet driver");
  1003. MODULE_AUTHOR("Haavard Skinnemoen <hskinnemoen@atmel.com>");