omap2.c 40 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018101910201021102210231024102510261027102810291030103110321033103410351036103710381039104010411042104310441045104610471048104910501051105210531054105510561057105810591060106110621063106410651066106710681069107010711072107310741075107610771078107910801081108210831084108510861087108810891090109110921093109410951096109710981099110011011102110311041105110611071108110911101111111211131114111511161117111811191120112111221123112411251126112711281129113011311132113311341135113611371138113911401141114211431144114511461147114811491150115111521153115411551156115711581159116011611162116311641165116611671168116911701171117211731174117511761177117811791180118111821183118411851186118711881189119011911192119311941195119611971198119912001201120212031204120512061207120812091210121112121213121412151216121712181219122012211222122312241225122612271228122912301231123212331234123512361237123812391240124112421243124412451246124712481249125012511252125312541255125612571258125912601261126212631264126512661267126812691270127112721273127412751276127712781279128012811282128312841285128612871288128912901291129212931294129512961297129812991300130113021303130413051306130713081309131013111312131313141315131613171318131913201321132213231324132513261327132813291330133113321333133413351336133713381339134013411342134313441345134613471348134913501351135213531354135513561357135813591360136113621363136413651366136713681369137013711372137313741375137613771378137913801381138213831384138513861387138813891390139113921393139413951396139713981399140014011402140314041405140614071408140914101411141214131414141514161417141814191420142114221423142414251426142714281429143014311432143314341435143614371438143914401441144214431444144514461447144814491450145114521453145414551456145714581459146014611462146314641465146614671468146914701471147214731474147514761477147814791480148114821483148414851486148714881489149014911492
  1. /*
  2. * Copyright © 2004 Texas Instruments, Jian Zhang <jzhang@ti.com>
  3. * Copyright © 2004 Micron Technology Inc.
  4. * Copyright © 2004 David Brownell
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. */
  10. #include <linux/platform_device.h>
  11. #include <linux/dmaengine.h>
  12. #include <linux/dma-mapping.h>
  13. #include <linux/delay.h>
  14. #include <linux/module.h>
  15. #include <linux/interrupt.h>
  16. #include <linux/jiffies.h>
  17. #include <linux/sched.h>
  18. #include <linux/mtd/mtd.h>
  19. #include <linux/mtd/nand.h>
  20. #include <linux/mtd/partitions.h>
  21. #include <linux/omap-dma.h>
  22. #include <linux/io.h>
  23. #include <linux/slab.h>
  24. #ifdef CONFIG_MTD_NAND_OMAP_BCH
  25. #include <linux/bch.h>
  26. #endif
  27. #include <plat/dma.h>
  28. #include <plat/gpmc.h>
  29. #include <plat/nand.h>
  30. #define DRIVER_NAME "omap2-nand"
  31. #define OMAP_NAND_TIMEOUT_MS 5000
  32. #define NAND_Ecc_P1e (1 << 0)
  33. #define NAND_Ecc_P2e (1 << 1)
  34. #define NAND_Ecc_P4e (1 << 2)
  35. #define NAND_Ecc_P8e (1 << 3)
  36. #define NAND_Ecc_P16e (1 << 4)
  37. #define NAND_Ecc_P32e (1 << 5)
  38. #define NAND_Ecc_P64e (1 << 6)
  39. #define NAND_Ecc_P128e (1 << 7)
  40. #define NAND_Ecc_P256e (1 << 8)
  41. #define NAND_Ecc_P512e (1 << 9)
  42. #define NAND_Ecc_P1024e (1 << 10)
  43. #define NAND_Ecc_P2048e (1 << 11)
  44. #define NAND_Ecc_P1o (1 << 16)
  45. #define NAND_Ecc_P2o (1 << 17)
  46. #define NAND_Ecc_P4o (1 << 18)
  47. #define NAND_Ecc_P8o (1 << 19)
  48. #define NAND_Ecc_P16o (1 << 20)
  49. #define NAND_Ecc_P32o (1 << 21)
  50. #define NAND_Ecc_P64o (1 << 22)
  51. #define NAND_Ecc_P128o (1 << 23)
  52. #define NAND_Ecc_P256o (1 << 24)
  53. #define NAND_Ecc_P512o (1 << 25)
  54. #define NAND_Ecc_P1024o (1 << 26)
  55. #define NAND_Ecc_P2048o (1 << 27)
  56. #define TF(value) (value ? 1 : 0)
  57. #define P2048e(a) (TF(a & NAND_Ecc_P2048e) << 0)
  58. #define P2048o(a) (TF(a & NAND_Ecc_P2048o) << 1)
  59. #define P1e(a) (TF(a & NAND_Ecc_P1e) << 2)
  60. #define P1o(a) (TF(a & NAND_Ecc_P1o) << 3)
  61. #define P2e(a) (TF(a & NAND_Ecc_P2e) << 4)
  62. #define P2o(a) (TF(a & NAND_Ecc_P2o) << 5)
  63. #define P4e(a) (TF(a & NAND_Ecc_P4e) << 6)
  64. #define P4o(a) (TF(a & NAND_Ecc_P4o) << 7)
  65. #define P8e(a) (TF(a & NAND_Ecc_P8e) << 0)
  66. #define P8o(a) (TF(a & NAND_Ecc_P8o) << 1)
  67. #define P16e(a) (TF(a & NAND_Ecc_P16e) << 2)
  68. #define P16o(a) (TF(a & NAND_Ecc_P16o) << 3)
  69. #define P32e(a) (TF(a & NAND_Ecc_P32e) << 4)
  70. #define P32o(a) (TF(a & NAND_Ecc_P32o) << 5)
  71. #define P64e(a) (TF(a & NAND_Ecc_P64e) << 6)
  72. #define P64o(a) (TF(a & NAND_Ecc_P64o) << 7)
  73. #define P128e(a) (TF(a & NAND_Ecc_P128e) << 0)
  74. #define P128o(a) (TF(a & NAND_Ecc_P128o) << 1)
  75. #define P256e(a) (TF(a & NAND_Ecc_P256e) << 2)
  76. #define P256o(a) (TF(a & NAND_Ecc_P256o) << 3)
  77. #define P512e(a) (TF(a & NAND_Ecc_P512e) << 4)
  78. #define P512o(a) (TF(a & NAND_Ecc_P512o) << 5)
  79. #define P1024e(a) (TF(a & NAND_Ecc_P1024e) << 6)
  80. #define P1024o(a) (TF(a & NAND_Ecc_P1024o) << 7)
  81. #define P8e_s(a) (TF(a & NAND_Ecc_P8e) << 0)
  82. #define P8o_s(a) (TF(a & NAND_Ecc_P8o) << 1)
  83. #define P16e_s(a) (TF(a & NAND_Ecc_P16e) << 2)
  84. #define P16o_s(a) (TF(a & NAND_Ecc_P16o) << 3)
  85. #define P1e_s(a) (TF(a & NAND_Ecc_P1e) << 4)
  86. #define P1o_s(a) (TF(a & NAND_Ecc_P1o) << 5)
  87. #define P2e_s(a) (TF(a & NAND_Ecc_P2e) << 6)
  88. #define P2o_s(a) (TF(a & NAND_Ecc_P2o) << 7)
  89. #define P4e_s(a) (TF(a & NAND_Ecc_P4e) << 0)
  90. #define P4o_s(a) (TF(a & NAND_Ecc_P4o) << 1)
  91. /* oob info generated runtime depending on ecc algorithm and layout selected */
  92. static struct nand_ecclayout omap_oobinfo;
  93. /* Define some generic bad / good block scan pattern which are used
  94. * while scanning a device for factory marked good / bad blocks
  95. */
  96. static uint8_t scan_ff_pattern[] = { 0xff };
  97. static struct nand_bbt_descr bb_descrip_flashbased = {
  98. .options = NAND_BBT_SCANEMPTY | NAND_BBT_SCANALLPAGES,
  99. .offs = 0,
  100. .len = 1,
  101. .pattern = scan_ff_pattern,
  102. };
  103. struct omap_nand_info {
  104. struct nand_hw_control controller;
  105. struct omap_nand_platform_data *pdata;
  106. struct mtd_info mtd;
  107. struct nand_chip nand;
  108. struct platform_device *pdev;
  109. int gpmc_cs;
  110. unsigned long phys_base;
  111. struct completion comp;
  112. struct dma_chan *dma;
  113. int dma_ch;
  114. int gpmc_irq;
  115. enum {
  116. OMAP_NAND_IO_READ = 0, /* read */
  117. OMAP_NAND_IO_WRITE, /* write */
  118. } iomode;
  119. u_char *buf;
  120. int buf_len;
  121. #ifdef CONFIG_MTD_NAND_OMAP_BCH
  122. struct bch_control *bch;
  123. struct nand_ecclayout ecclayout;
  124. #endif
  125. };
  126. /**
  127. * omap_hwcontrol - hardware specific access to control-lines
  128. * @mtd: MTD device structure
  129. * @cmd: command to device
  130. * @ctrl:
  131. * NAND_NCE: bit 0 -> don't care
  132. * NAND_CLE: bit 1 -> Command Latch
  133. * NAND_ALE: bit 2 -> Address Latch
  134. *
  135. * NOTE: boards may use different bits for these!!
  136. */
  137. static void omap_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
  138. {
  139. struct omap_nand_info *info = container_of(mtd,
  140. struct omap_nand_info, mtd);
  141. if (cmd != NAND_CMD_NONE) {
  142. if (ctrl & NAND_CLE)
  143. gpmc_nand_write(info->gpmc_cs, GPMC_NAND_COMMAND, cmd);
  144. else if (ctrl & NAND_ALE)
  145. gpmc_nand_write(info->gpmc_cs, GPMC_NAND_ADDRESS, cmd);
  146. else /* NAND_NCE */
  147. gpmc_nand_write(info->gpmc_cs, GPMC_NAND_DATA, cmd);
  148. }
  149. }
  150. /**
  151. * omap_read_buf8 - read data from NAND controller into buffer
  152. * @mtd: MTD device structure
  153. * @buf: buffer to store date
  154. * @len: number of bytes to read
  155. */
  156. static void omap_read_buf8(struct mtd_info *mtd, u_char *buf, int len)
  157. {
  158. struct nand_chip *nand = mtd->priv;
  159. ioread8_rep(nand->IO_ADDR_R, buf, len);
  160. }
  161. /**
  162. * omap_write_buf8 - write buffer to NAND controller
  163. * @mtd: MTD device structure
  164. * @buf: data buffer
  165. * @len: number of bytes to write
  166. */
  167. static void omap_write_buf8(struct mtd_info *mtd, const u_char *buf, int len)
  168. {
  169. struct omap_nand_info *info = container_of(mtd,
  170. struct omap_nand_info, mtd);
  171. u_char *p = (u_char *)buf;
  172. u32 status = 0;
  173. while (len--) {
  174. iowrite8(*p++, info->nand.IO_ADDR_W);
  175. /* wait until buffer is available for write */
  176. do {
  177. status = gpmc_read_status(GPMC_STATUS_BUFFER);
  178. } while (!status);
  179. }
  180. }
  181. /**
  182. * omap_read_buf16 - read data from NAND controller into buffer
  183. * @mtd: MTD device structure
  184. * @buf: buffer to store date
  185. * @len: number of bytes to read
  186. */
  187. static void omap_read_buf16(struct mtd_info *mtd, u_char *buf, int len)
  188. {
  189. struct nand_chip *nand = mtd->priv;
  190. ioread16_rep(nand->IO_ADDR_R, buf, len / 2);
  191. }
  192. /**
  193. * omap_write_buf16 - write buffer to NAND controller
  194. * @mtd: MTD device structure
  195. * @buf: data buffer
  196. * @len: number of bytes to write
  197. */
  198. static void omap_write_buf16(struct mtd_info *mtd, const u_char * buf, int len)
  199. {
  200. struct omap_nand_info *info = container_of(mtd,
  201. struct omap_nand_info, mtd);
  202. u16 *p = (u16 *) buf;
  203. u32 status = 0;
  204. /* FIXME try bursts of writesw() or DMA ... */
  205. len >>= 1;
  206. while (len--) {
  207. iowrite16(*p++, info->nand.IO_ADDR_W);
  208. /* wait until buffer is available for write */
  209. do {
  210. status = gpmc_read_status(GPMC_STATUS_BUFFER);
  211. } while (!status);
  212. }
  213. }
  214. /**
  215. * omap_read_buf_pref - read data from NAND controller into buffer
  216. * @mtd: MTD device structure
  217. * @buf: buffer to store date
  218. * @len: number of bytes to read
  219. */
  220. static void omap_read_buf_pref(struct mtd_info *mtd, u_char *buf, int len)
  221. {
  222. struct omap_nand_info *info = container_of(mtd,
  223. struct omap_nand_info, mtd);
  224. uint32_t r_count = 0;
  225. int ret = 0;
  226. u32 *p = (u32 *)buf;
  227. /* take care of subpage reads */
  228. if (len % 4) {
  229. if (info->nand.options & NAND_BUSWIDTH_16)
  230. omap_read_buf16(mtd, buf, len % 4);
  231. else
  232. omap_read_buf8(mtd, buf, len % 4);
  233. p = (u32 *) (buf + len % 4);
  234. len -= len % 4;
  235. }
  236. /* configure and start prefetch transfer */
  237. ret = gpmc_prefetch_enable(info->gpmc_cs,
  238. PREFETCH_FIFOTHRESHOLD_MAX, 0x0, len, 0x0);
  239. if (ret) {
  240. /* PFPW engine is busy, use cpu copy method */
  241. if (info->nand.options & NAND_BUSWIDTH_16)
  242. omap_read_buf16(mtd, (u_char *)p, len);
  243. else
  244. omap_read_buf8(mtd, (u_char *)p, len);
  245. } else {
  246. do {
  247. r_count = gpmc_read_status(GPMC_PREFETCH_FIFO_CNT);
  248. r_count = r_count >> 2;
  249. ioread32_rep(info->nand.IO_ADDR_R, p, r_count);
  250. p += r_count;
  251. len -= r_count << 2;
  252. } while (len);
  253. /* disable and stop the PFPW engine */
  254. gpmc_prefetch_reset(info->gpmc_cs);
  255. }
  256. }
  257. /**
  258. * omap_write_buf_pref - write buffer to NAND controller
  259. * @mtd: MTD device structure
  260. * @buf: data buffer
  261. * @len: number of bytes to write
  262. */
  263. static void omap_write_buf_pref(struct mtd_info *mtd,
  264. const u_char *buf, int len)
  265. {
  266. struct omap_nand_info *info = container_of(mtd,
  267. struct omap_nand_info, mtd);
  268. uint32_t w_count = 0;
  269. int i = 0, ret = 0;
  270. u16 *p = (u16 *)buf;
  271. unsigned long tim, limit;
  272. /* take care of subpage writes */
  273. if (len % 2 != 0) {
  274. writeb(*buf, info->nand.IO_ADDR_W);
  275. p = (u16 *)(buf + 1);
  276. len--;
  277. }
  278. /* configure and start prefetch transfer */
  279. ret = gpmc_prefetch_enable(info->gpmc_cs,
  280. PREFETCH_FIFOTHRESHOLD_MAX, 0x0, len, 0x1);
  281. if (ret) {
  282. /* PFPW engine is busy, use cpu copy method */
  283. if (info->nand.options & NAND_BUSWIDTH_16)
  284. omap_write_buf16(mtd, (u_char *)p, len);
  285. else
  286. omap_write_buf8(mtd, (u_char *)p, len);
  287. } else {
  288. while (len) {
  289. w_count = gpmc_read_status(GPMC_PREFETCH_FIFO_CNT);
  290. w_count = w_count >> 1;
  291. for (i = 0; (i < w_count) && len; i++, len -= 2)
  292. iowrite16(*p++, info->nand.IO_ADDR_W);
  293. }
  294. /* wait for data to flushed-out before reset the prefetch */
  295. tim = 0;
  296. limit = (loops_per_jiffy *
  297. msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS));
  298. while (gpmc_read_status(GPMC_PREFETCH_COUNT) && (tim++ < limit))
  299. cpu_relax();
  300. /* disable and stop the PFPW engine */
  301. gpmc_prefetch_reset(info->gpmc_cs);
  302. }
  303. }
  304. /*
  305. * omap_nand_dma_cb: callback on the completion of dma transfer
  306. * @lch: logical channel
  307. * @ch_satuts: channel status
  308. * @data: pointer to completion data structure
  309. */
  310. static void omap_nand_dma_cb(int lch, u16 ch_status, void *data)
  311. {
  312. complete((struct completion *) data);
  313. }
  314. static void omap_nand_dma_callback(void *data)
  315. {
  316. complete((struct completion *) data);
  317. }
  318. /*
  319. * omap_nand_dma_transfer: configer and start dma transfer
  320. * @mtd: MTD device structure
  321. * @addr: virtual address in RAM of source/destination
  322. * @len: number of data bytes to be transferred
  323. * @is_write: flag for read/write operation
  324. */
  325. static inline int omap_nand_dma_transfer(struct mtd_info *mtd, void *addr,
  326. unsigned int len, int is_write)
  327. {
  328. struct omap_nand_info *info = container_of(mtd,
  329. struct omap_nand_info, mtd);
  330. enum dma_data_direction dir = is_write ? DMA_TO_DEVICE :
  331. DMA_FROM_DEVICE;
  332. dma_addr_t dma_addr;
  333. int ret;
  334. unsigned long tim, limit;
  335. /* The fifo depth is 64 bytes max.
  336. * But configure the FIFO-threahold to 32 to get a sync at each frame
  337. * and frame length is 32 bytes.
  338. */
  339. int buf_len = len >> 6;
  340. if (addr >= high_memory) {
  341. struct page *p1;
  342. if (((size_t)addr & PAGE_MASK) !=
  343. ((size_t)(addr + len - 1) & PAGE_MASK))
  344. goto out_copy;
  345. p1 = vmalloc_to_page(addr);
  346. if (!p1)
  347. goto out_copy;
  348. addr = page_address(p1) + ((size_t)addr & ~PAGE_MASK);
  349. }
  350. if (info->dma) {
  351. struct dma_async_tx_descriptor *tx;
  352. struct scatterlist sg;
  353. unsigned n;
  354. sg_init_one(&sg, addr, len);
  355. n = dma_map_sg(info->dma->device->dev, &sg, 1, dir);
  356. if (n == 0) {
  357. dev_err(&info->pdev->dev,
  358. "Couldn't DMA map a %d byte buffer\n", len);
  359. goto out_copy;
  360. }
  361. tx = dmaengine_prep_slave_sg(info->dma, &sg, n,
  362. is_write ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM,
  363. DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
  364. if (!tx) {
  365. dma_unmap_sg(info->dma->device->dev, &sg, 1, dir);
  366. goto out_copy;
  367. }
  368. tx->callback = omap_nand_dma_callback;
  369. tx->callback_param = &info->comp;
  370. dmaengine_submit(tx);
  371. /* configure and start prefetch transfer */
  372. ret = gpmc_prefetch_enable(info->gpmc_cs,
  373. PREFETCH_FIFOTHRESHOLD_MAX, 0x1, len, is_write);
  374. if (ret) {
  375. /* PFPW engine is busy, use cpu copy method */
  376. dma_unmap_sg(info->dma->device->dev, &sg, 1, dir);
  377. goto out_copy;
  378. }
  379. init_completion(&info->comp);
  380. dma_async_issue_pending(info->dma);
  381. /* setup and start DMA using dma_addr */
  382. wait_for_completion(&info->comp);
  383. tim = 0;
  384. limit = (loops_per_jiffy * msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS));
  385. while (gpmc_read_status(GPMC_PREFETCH_COUNT) && (tim++ < limit))
  386. cpu_relax();
  387. /* disable and stop the PFPW engine */
  388. gpmc_prefetch_reset(info->gpmc_cs);
  389. dma_unmap_sg(info->dma->device->dev, &sg, 1, dir);
  390. return 0;
  391. }
  392. dma_addr = dma_map_single(&info->pdev->dev, addr, len, dir);
  393. if (dma_mapping_error(&info->pdev->dev, dma_addr)) {
  394. dev_err(&info->pdev->dev,
  395. "Couldn't DMA map a %d byte buffer\n", len);
  396. goto out_copy;
  397. }
  398. if (is_write) {
  399. omap_set_dma_dest_params(info->dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
  400. info->phys_base, 0, 0);
  401. omap_set_dma_src_params(info->dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
  402. dma_addr, 0, 0);
  403. omap_set_dma_transfer_params(info->dma_ch, OMAP_DMA_DATA_TYPE_S32,
  404. 0x10, buf_len, OMAP_DMA_SYNC_FRAME,
  405. OMAP24XX_DMA_GPMC, OMAP_DMA_DST_SYNC);
  406. } else {
  407. omap_set_dma_src_params(info->dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
  408. info->phys_base, 0, 0);
  409. omap_set_dma_dest_params(info->dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
  410. dma_addr, 0, 0);
  411. omap_set_dma_transfer_params(info->dma_ch, OMAP_DMA_DATA_TYPE_S32,
  412. 0x10, buf_len, OMAP_DMA_SYNC_FRAME,
  413. OMAP24XX_DMA_GPMC, OMAP_DMA_SRC_SYNC);
  414. }
  415. /* configure and start prefetch transfer */
  416. ret = gpmc_prefetch_enable(info->gpmc_cs,
  417. PREFETCH_FIFOTHRESHOLD_MAX, 0x1, len, is_write);
  418. if (ret)
  419. /* PFPW engine is busy, use cpu copy method */
  420. goto out_copy_unmap;
  421. init_completion(&info->comp);
  422. omap_start_dma(info->dma_ch);
  423. /* setup and start DMA using dma_addr */
  424. wait_for_completion(&info->comp);
  425. tim = 0;
  426. limit = (loops_per_jiffy * msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS));
  427. while (gpmc_read_status(GPMC_PREFETCH_COUNT) && (tim++ < limit))
  428. cpu_relax();
  429. /* disable and stop the PFPW engine */
  430. gpmc_prefetch_reset(info->gpmc_cs);
  431. dma_unmap_single(&info->pdev->dev, dma_addr, len, dir);
  432. return 0;
  433. out_copy_unmap:
  434. dma_unmap_single(&info->pdev->dev, dma_addr, len, dir);
  435. out_copy:
  436. if (info->nand.options & NAND_BUSWIDTH_16)
  437. is_write == 0 ? omap_read_buf16(mtd, (u_char *) addr, len)
  438. : omap_write_buf16(mtd, (u_char *) addr, len);
  439. else
  440. is_write == 0 ? omap_read_buf8(mtd, (u_char *) addr, len)
  441. : omap_write_buf8(mtd, (u_char *) addr, len);
  442. return 0;
  443. }
  444. /**
  445. * omap_read_buf_dma_pref - read data from NAND controller into buffer
  446. * @mtd: MTD device structure
  447. * @buf: buffer to store date
  448. * @len: number of bytes to read
  449. */
  450. static void omap_read_buf_dma_pref(struct mtd_info *mtd, u_char *buf, int len)
  451. {
  452. if (len <= mtd->oobsize)
  453. omap_read_buf_pref(mtd, buf, len);
  454. else
  455. /* start transfer in DMA mode */
  456. omap_nand_dma_transfer(mtd, buf, len, 0x0);
  457. }
  458. /**
  459. * omap_write_buf_dma_pref - write buffer to NAND controller
  460. * @mtd: MTD device structure
  461. * @buf: data buffer
  462. * @len: number of bytes to write
  463. */
  464. static void omap_write_buf_dma_pref(struct mtd_info *mtd,
  465. const u_char *buf, int len)
  466. {
  467. if (len <= mtd->oobsize)
  468. omap_write_buf_pref(mtd, buf, len);
  469. else
  470. /* start transfer in DMA mode */
  471. omap_nand_dma_transfer(mtd, (u_char *) buf, len, 0x1);
  472. }
  473. /*
  474. * omap_nand_irq - GMPC irq handler
  475. * @this_irq: gpmc irq number
  476. * @dev: omap_nand_info structure pointer is passed here
  477. */
  478. static irqreturn_t omap_nand_irq(int this_irq, void *dev)
  479. {
  480. struct omap_nand_info *info = (struct omap_nand_info *) dev;
  481. u32 bytes;
  482. u32 irq_stat;
  483. irq_stat = gpmc_read_status(GPMC_GET_IRQ_STATUS);
  484. bytes = gpmc_read_status(GPMC_PREFETCH_FIFO_CNT);
  485. bytes = bytes & 0xFFFC; /* io in multiple of 4 bytes */
  486. if (info->iomode == OMAP_NAND_IO_WRITE) { /* checks for write io */
  487. if (irq_stat & 0x2)
  488. goto done;
  489. if (info->buf_len && (info->buf_len < bytes))
  490. bytes = info->buf_len;
  491. else if (!info->buf_len)
  492. bytes = 0;
  493. iowrite32_rep(info->nand.IO_ADDR_W,
  494. (u32 *)info->buf, bytes >> 2);
  495. info->buf = info->buf + bytes;
  496. info->buf_len -= bytes;
  497. } else {
  498. ioread32_rep(info->nand.IO_ADDR_R,
  499. (u32 *)info->buf, bytes >> 2);
  500. info->buf = info->buf + bytes;
  501. if (irq_stat & 0x2)
  502. goto done;
  503. }
  504. gpmc_cs_configure(info->gpmc_cs, GPMC_SET_IRQ_STATUS, irq_stat);
  505. return IRQ_HANDLED;
  506. done:
  507. complete(&info->comp);
  508. /* disable irq */
  509. gpmc_cs_configure(info->gpmc_cs, GPMC_ENABLE_IRQ, 0);
  510. /* clear status */
  511. gpmc_cs_configure(info->gpmc_cs, GPMC_SET_IRQ_STATUS, irq_stat);
  512. return IRQ_HANDLED;
  513. }
  514. /*
  515. * omap_read_buf_irq_pref - read data from NAND controller into buffer
  516. * @mtd: MTD device structure
  517. * @buf: buffer to store date
  518. * @len: number of bytes to read
  519. */
  520. static void omap_read_buf_irq_pref(struct mtd_info *mtd, u_char *buf, int len)
  521. {
  522. struct omap_nand_info *info = container_of(mtd,
  523. struct omap_nand_info, mtd);
  524. int ret = 0;
  525. if (len <= mtd->oobsize) {
  526. omap_read_buf_pref(mtd, buf, len);
  527. return;
  528. }
  529. info->iomode = OMAP_NAND_IO_READ;
  530. info->buf = buf;
  531. init_completion(&info->comp);
  532. /* configure and start prefetch transfer */
  533. ret = gpmc_prefetch_enable(info->gpmc_cs,
  534. PREFETCH_FIFOTHRESHOLD_MAX/2, 0x0, len, 0x0);
  535. if (ret)
  536. /* PFPW engine is busy, use cpu copy method */
  537. goto out_copy;
  538. info->buf_len = len;
  539. /* enable irq */
  540. gpmc_cs_configure(info->gpmc_cs, GPMC_ENABLE_IRQ,
  541. (GPMC_IRQ_FIFOEVENTENABLE | GPMC_IRQ_COUNT_EVENT));
  542. /* waiting for read to complete */
  543. wait_for_completion(&info->comp);
  544. /* disable and stop the PFPW engine */
  545. gpmc_prefetch_reset(info->gpmc_cs);
  546. return;
  547. out_copy:
  548. if (info->nand.options & NAND_BUSWIDTH_16)
  549. omap_read_buf16(mtd, buf, len);
  550. else
  551. omap_read_buf8(mtd, buf, len);
  552. }
  553. /*
  554. * omap_write_buf_irq_pref - write buffer to NAND controller
  555. * @mtd: MTD device structure
  556. * @buf: data buffer
  557. * @len: number of bytes to write
  558. */
  559. static void omap_write_buf_irq_pref(struct mtd_info *mtd,
  560. const u_char *buf, int len)
  561. {
  562. struct omap_nand_info *info = container_of(mtd,
  563. struct omap_nand_info, mtd);
  564. int ret = 0;
  565. unsigned long tim, limit;
  566. if (len <= mtd->oobsize) {
  567. omap_write_buf_pref(mtd, buf, len);
  568. return;
  569. }
  570. info->iomode = OMAP_NAND_IO_WRITE;
  571. info->buf = (u_char *) buf;
  572. init_completion(&info->comp);
  573. /* configure and start prefetch transfer : size=24 */
  574. ret = gpmc_prefetch_enable(info->gpmc_cs,
  575. (PREFETCH_FIFOTHRESHOLD_MAX * 3) / 8, 0x0, len, 0x1);
  576. if (ret)
  577. /* PFPW engine is busy, use cpu copy method */
  578. goto out_copy;
  579. info->buf_len = len;
  580. /* enable irq */
  581. gpmc_cs_configure(info->gpmc_cs, GPMC_ENABLE_IRQ,
  582. (GPMC_IRQ_FIFOEVENTENABLE | GPMC_IRQ_COUNT_EVENT));
  583. /* waiting for write to complete */
  584. wait_for_completion(&info->comp);
  585. /* wait for data to flushed-out before reset the prefetch */
  586. tim = 0;
  587. limit = (loops_per_jiffy * msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS));
  588. while (gpmc_read_status(GPMC_PREFETCH_COUNT) && (tim++ < limit))
  589. cpu_relax();
  590. /* disable and stop the PFPW engine */
  591. gpmc_prefetch_reset(info->gpmc_cs);
  592. return;
  593. out_copy:
  594. if (info->nand.options & NAND_BUSWIDTH_16)
  595. omap_write_buf16(mtd, buf, len);
  596. else
  597. omap_write_buf8(mtd, buf, len);
  598. }
  599. /**
  600. * omap_verify_buf - Verify chip data against buffer
  601. * @mtd: MTD device structure
  602. * @buf: buffer containing the data to compare
  603. * @len: number of bytes to compare
  604. */
  605. static int omap_verify_buf(struct mtd_info *mtd, const u_char * buf, int len)
  606. {
  607. struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
  608. mtd);
  609. u16 *p = (u16 *) buf;
  610. len >>= 1;
  611. while (len--) {
  612. if (*p++ != cpu_to_le16(readw(info->nand.IO_ADDR_R)))
  613. return -EFAULT;
  614. }
  615. return 0;
  616. }
  617. /**
  618. * gen_true_ecc - This function will generate true ECC value
  619. * @ecc_buf: buffer to store ecc code
  620. *
  621. * This generated true ECC value can be used when correcting
  622. * data read from NAND flash memory core
  623. */
  624. static void gen_true_ecc(u8 *ecc_buf)
  625. {
  626. u32 tmp = ecc_buf[0] | (ecc_buf[1] << 16) |
  627. ((ecc_buf[2] & 0xF0) << 20) | ((ecc_buf[2] & 0x0F) << 8);
  628. ecc_buf[0] = ~(P64o(tmp) | P64e(tmp) | P32o(tmp) | P32e(tmp) |
  629. P16o(tmp) | P16e(tmp) | P8o(tmp) | P8e(tmp));
  630. ecc_buf[1] = ~(P1024o(tmp) | P1024e(tmp) | P512o(tmp) | P512e(tmp) |
  631. P256o(tmp) | P256e(tmp) | P128o(tmp) | P128e(tmp));
  632. ecc_buf[2] = ~(P4o(tmp) | P4e(tmp) | P2o(tmp) | P2e(tmp) | P1o(tmp) |
  633. P1e(tmp) | P2048o(tmp) | P2048e(tmp));
  634. }
  635. /**
  636. * omap_compare_ecc - Detect (2 bits) and correct (1 bit) error in data
  637. * @ecc_data1: ecc code from nand spare area
  638. * @ecc_data2: ecc code from hardware register obtained from hardware ecc
  639. * @page_data: page data
  640. *
  641. * This function compares two ECC's and indicates if there is an error.
  642. * If the error can be corrected it will be corrected to the buffer.
  643. * If there is no error, %0 is returned. If there is an error but it
  644. * was corrected, %1 is returned. Otherwise, %-1 is returned.
  645. */
  646. static int omap_compare_ecc(u8 *ecc_data1, /* read from NAND memory */
  647. u8 *ecc_data2, /* read from register */
  648. u8 *page_data)
  649. {
  650. uint i;
  651. u8 tmp0_bit[8], tmp1_bit[8], tmp2_bit[8];
  652. u8 comp0_bit[8], comp1_bit[8], comp2_bit[8];
  653. u8 ecc_bit[24];
  654. u8 ecc_sum = 0;
  655. u8 find_bit = 0;
  656. uint find_byte = 0;
  657. int isEccFF;
  658. isEccFF = ((*(u32 *)ecc_data1 & 0xFFFFFF) == 0xFFFFFF);
  659. gen_true_ecc(ecc_data1);
  660. gen_true_ecc(ecc_data2);
  661. for (i = 0; i <= 2; i++) {
  662. *(ecc_data1 + i) = ~(*(ecc_data1 + i));
  663. *(ecc_data2 + i) = ~(*(ecc_data2 + i));
  664. }
  665. for (i = 0; i < 8; i++) {
  666. tmp0_bit[i] = *ecc_data1 % 2;
  667. *ecc_data1 = *ecc_data1 / 2;
  668. }
  669. for (i = 0; i < 8; i++) {
  670. tmp1_bit[i] = *(ecc_data1 + 1) % 2;
  671. *(ecc_data1 + 1) = *(ecc_data1 + 1) / 2;
  672. }
  673. for (i = 0; i < 8; i++) {
  674. tmp2_bit[i] = *(ecc_data1 + 2) % 2;
  675. *(ecc_data1 + 2) = *(ecc_data1 + 2) / 2;
  676. }
  677. for (i = 0; i < 8; i++) {
  678. comp0_bit[i] = *ecc_data2 % 2;
  679. *ecc_data2 = *ecc_data2 / 2;
  680. }
  681. for (i = 0; i < 8; i++) {
  682. comp1_bit[i] = *(ecc_data2 + 1) % 2;
  683. *(ecc_data2 + 1) = *(ecc_data2 + 1) / 2;
  684. }
  685. for (i = 0; i < 8; i++) {
  686. comp2_bit[i] = *(ecc_data2 + 2) % 2;
  687. *(ecc_data2 + 2) = *(ecc_data2 + 2) / 2;
  688. }
  689. for (i = 0; i < 6; i++)
  690. ecc_bit[i] = tmp2_bit[i + 2] ^ comp2_bit[i + 2];
  691. for (i = 0; i < 8; i++)
  692. ecc_bit[i + 6] = tmp0_bit[i] ^ comp0_bit[i];
  693. for (i = 0; i < 8; i++)
  694. ecc_bit[i + 14] = tmp1_bit[i] ^ comp1_bit[i];
  695. ecc_bit[22] = tmp2_bit[0] ^ comp2_bit[0];
  696. ecc_bit[23] = tmp2_bit[1] ^ comp2_bit[1];
  697. for (i = 0; i < 24; i++)
  698. ecc_sum += ecc_bit[i];
  699. switch (ecc_sum) {
  700. case 0:
  701. /* Not reached because this function is not called if
  702. * ECC values are equal
  703. */
  704. return 0;
  705. case 1:
  706. /* Uncorrectable error */
  707. pr_debug("ECC UNCORRECTED_ERROR 1\n");
  708. return -1;
  709. case 11:
  710. /* UN-Correctable error */
  711. pr_debug("ECC UNCORRECTED_ERROR B\n");
  712. return -1;
  713. case 12:
  714. /* Correctable error */
  715. find_byte = (ecc_bit[23] << 8) +
  716. (ecc_bit[21] << 7) +
  717. (ecc_bit[19] << 6) +
  718. (ecc_bit[17] << 5) +
  719. (ecc_bit[15] << 4) +
  720. (ecc_bit[13] << 3) +
  721. (ecc_bit[11] << 2) +
  722. (ecc_bit[9] << 1) +
  723. ecc_bit[7];
  724. find_bit = (ecc_bit[5] << 2) + (ecc_bit[3] << 1) + ecc_bit[1];
  725. pr_debug("Correcting single bit ECC error at offset: "
  726. "%d, bit: %d\n", find_byte, find_bit);
  727. page_data[find_byte] ^= (1 << find_bit);
  728. return 1;
  729. default:
  730. if (isEccFF) {
  731. if (ecc_data2[0] == 0 &&
  732. ecc_data2[1] == 0 &&
  733. ecc_data2[2] == 0)
  734. return 0;
  735. }
  736. pr_debug("UNCORRECTED_ERROR default\n");
  737. return -1;
  738. }
  739. }
  740. /**
  741. * omap_correct_data - Compares the ECC read with HW generated ECC
  742. * @mtd: MTD device structure
  743. * @dat: page data
  744. * @read_ecc: ecc read from nand flash
  745. * @calc_ecc: ecc read from HW ECC registers
  746. *
  747. * Compares the ecc read from nand spare area with ECC registers values
  748. * and if ECC's mismatched, it will call 'omap_compare_ecc' for error
  749. * detection and correction. If there are no errors, %0 is returned. If
  750. * there were errors and all of the errors were corrected, the number of
  751. * corrected errors is returned. If uncorrectable errors exist, %-1 is
  752. * returned.
  753. */
  754. static int omap_correct_data(struct mtd_info *mtd, u_char *dat,
  755. u_char *read_ecc, u_char *calc_ecc)
  756. {
  757. struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
  758. mtd);
  759. int blockCnt = 0, i = 0, ret = 0;
  760. int stat = 0;
  761. /* Ex NAND_ECC_HW12_2048 */
  762. if ((info->nand.ecc.mode == NAND_ECC_HW) &&
  763. (info->nand.ecc.size == 2048))
  764. blockCnt = 4;
  765. else
  766. blockCnt = 1;
  767. for (i = 0; i < blockCnt; i++) {
  768. if (memcmp(read_ecc, calc_ecc, 3) != 0) {
  769. ret = omap_compare_ecc(read_ecc, calc_ecc, dat);
  770. if (ret < 0)
  771. return ret;
  772. /* keep track of the number of corrected errors */
  773. stat += ret;
  774. }
  775. read_ecc += 3;
  776. calc_ecc += 3;
  777. dat += 512;
  778. }
  779. return stat;
  780. }
  781. /**
  782. * omap_calcuate_ecc - Generate non-inverted ECC bytes.
  783. * @mtd: MTD device structure
  784. * @dat: The pointer to data on which ecc is computed
  785. * @ecc_code: The ecc_code buffer
  786. *
  787. * Using noninverted ECC can be considered ugly since writing a blank
  788. * page ie. padding will clear the ECC bytes. This is no problem as long
  789. * nobody is trying to write data on the seemingly unused page. Reading
  790. * an erased page will produce an ECC mismatch between generated and read
  791. * ECC bytes that has to be dealt with separately.
  792. */
  793. static int omap_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
  794. u_char *ecc_code)
  795. {
  796. struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
  797. mtd);
  798. return gpmc_calculate_ecc(info->gpmc_cs, dat, ecc_code);
  799. }
  800. /**
  801. * omap_enable_hwecc - This function enables the hardware ecc functionality
  802. * @mtd: MTD device structure
  803. * @mode: Read/Write mode
  804. */
  805. static void omap_enable_hwecc(struct mtd_info *mtd, int mode)
  806. {
  807. struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
  808. mtd);
  809. struct nand_chip *chip = mtd->priv;
  810. unsigned int dev_width = (chip->options & NAND_BUSWIDTH_16) ? 1 : 0;
  811. gpmc_enable_hwecc(info->gpmc_cs, mode, dev_width, info->nand.ecc.size);
  812. }
  813. /**
  814. * omap_wait - wait until the command is done
  815. * @mtd: MTD device structure
  816. * @chip: NAND Chip structure
  817. *
  818. * Wait function is called during Program and erase operations and
  819. * the way it is called from MTD layer, we should wait till the NAND
  820. * chip is ready after the programming/erase operation has completed.
  821. *
  822. * Erase can take up to 400ms and program up to 20ms according to
  823. * general NAND and SmartMedia specs
  824. */
  825. static int omap_wait(struct mtd_info *mtd, struct nand_chip *chip)
  826. {
  827. struct nand_chip *this = mtd->priv;
  828. struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
  829. mtd);
  830. unsigned long timeo = jiffies;
  831. int status, state = this->state;
  832. if (state == FL_ERASING)
  833. timeo += (HZ * 400) / 1000;
  834. else
  835. timeo += (HZ * 20) / 1000;
  836. gpmc_nand_write(info->gpmc_cs,
  837. GPMC_NAND_COMMAND, (NAND_CMD_STATUS & 0xFF));
  838. while (time_before(jiffies, timeo)) {
  839. status = gpmc_nand_read(info->gpmc_cs, GPMC_NAND_DATA);
  840. if (status & NAND_STATUS_READY)
  841. break;
  842. cond_resched();
  843. }
  844. status = gpmc_nand_read(info->gpmc_cs, GPMC_NAND_DATA);
  845. return status;
  846. }
  847. /**
  848. * omap_dev_ready - calls the platform specific dev_ready function
  849. * @mtd: MTD device structure
  850. */
  851. static int omap_dev_ready(struct mtd_info *mtd)
  852. {
  853. unsigned int val = 0;
  854. struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
  855. mtd);
  856. val = gpmc_read_status(GPMC_GET_IRQ_STATUS);
  857. if ((val & 0x100) == 0x100) {
  858. /* Clear IRQ Interrupt */
  859. val |= 0x100;
  860. val &= ~(0x0);
  861. gpmc_cs_configure(info->gpmc_cs, GPMC_SET_IRQ_STATUS, val);
  862. } else {
  863. unsigned int cnt = 0;
  864. while (cnt++ < 0x1FF) {
  865. if ((val & 0x100) == 0x100)
  866. return 0;
  867. val = gpmc_read_status(GPMC_GET_IRQ_STATUS);
  868. }
  869. }
  870. return 1;
  871. }
  872. #ifdef CONFIG_MTD_NAND_OMAP_BCH
  873. /**
  874. * omap3_enable_hwecc_bch - Program OMAP3 GPMC to perform BCH ECC correction
  875. * @mtd: MTD device structure
  876. * @mode: Read/Write mode
  877. */
  878. static void omap3_enable_hwecc_bch(struct mtd_info *mtd, int mode)
  879. {
  880. int nerrors;
  881. unsigned int dev_width;
  882. struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
  883. mtd);
  884. struct nand_chip *chip = mtd->priv;
  885. nerrors = (info->nand.ecc.bytes == 13) ? 8 : 4;
  886. dev_width = (chip->options & NAND_BUSWIDTH_16) ? 1 : 0;
  887. /*
  888. * Program GPMC to perform correction on one 512-byte sector at a time.
  889. * Using 4 sectors at a time (i.e. ecc.size = 2048) is also possible and
  890. * gives a slight (5%) performance gain (but requires additional code).
  891. */
  892. (void)gpmc_enable_hwecc_bch(info->gpmc_cs, mode, dev_width, 1, nerrors);
  893. }
  894. /**
  895. * omap3_calculate_ecc_bch4 - Generate 7 bytes of ECC bytes
  896. * @mtd: MTD device structure
  897. * @dat: The pointer to data on which ecc is computed
  898. * @ecc_code: The ecc_code buffer
  899. */
  900. static int omap3_calculate_ecc_bch4(struct mtd_info *mtd, const u_char *dat,
  901. u_char *ecc_code)
  902. {
  903. struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
  904. mtd);
  905. return gpmc_calculate_ecc_bch4(info->gpmc_cs, dat, ecc_code);
  906. }
  907. /**
  908. * omap3_calculate_ecc_bch8 - Generate 13 bytes of ECC bytes
  909. * @mtd: MTD device structure
  910. * @dat: The pointer to data on which ecc is computed
  911. * @ecc_code: The ecc_code buffer
  912. */
  913. static int omap3_calculate_ecc_bch8(struct mtd_info *mtd, const u_char *dat,
  914. u_char *ecc_code)
  915. {
  916. struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
  917. mtd);
  918. return gpmc_calculate_ecc_bch8(info->gpmc_cs, dat, ecc_code);
  919. }
  920. /**
  921. * omap3_correct_data_bch - Decode received data and correct errors
  922. * @mtd: MTD device structure
  923. * @data: page data
  924. * @read_ecc: ecc read from nand flash
  925. * @calc_ecc: ecc read from HW ECC registers
  926. */
  927. static int omap3_correct_data_bch(struct mtd_info *mtd, u_char *data,
  928. u_char *read_ecc, u_char *calc_ecc)
  929. {
  930. int i, count;
  931. /* cannot correct more than 8 errors */
  932. unsigned int errloc[8];
  933. struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
  934. mtd);
  935. count = decode_bch(info->bch, NULL, 512, read_ecc, calc_ecc, NULL,
  936. errloc);
  937. if (count > 0) {
  938. /* correct errors */
  939. for (i = 0; i < count; i++) {
  940. /* correct data only, not ecc bytes */
  941. if (errloc[i] < 8*512)
  942. data[errloc[i]/8] ^= 1 << (errloc[i] & 7);
  943. pr_debug("corrected bitflip %u\n", errloc[i]);
  944. }
  945. } else if (count < 0) {
  946. pr_err("ecc unrecoverable error\n");
  947. }
  948. return count;
  949. }
  950. /**
  951. * omap3_free_bch - Release BCH ecc resources
  952. * @mtd: MTD device structure
  953. */
  954. static void omap3_free_bch(struct mtd_info *mtd)
  955. {
  956. struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
  957. mtd);
  958. if (info->bch) {
  959. free_bch(info->bch);
  960. info->bch = NULL;
  961. }
  962. }
  963. /**
  964. * omap3_init_bch - Initialize BCH ECC
  965. * @mtd: MTD device structure
  966. * @ecc_opt: OMAP ECC mode (OMAP_ECC_BCH4_CODE_HW or OMAP_ECC_BCH8_CODE_HW)
  967. */
  968. static int omap3_init_bch(struct mtd_info *mtd, int ecc_opt)
  969. {
  970. int ret, max_errors;
  971. struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
  972. mtd);
  973. #ifdef CONFIG_MTD_NAND_OMAP_BCH8
  974. const int hw_errors = 8;
  975. #else
  976. const int hw_errors = 4;
  977. #endif
  978. info->bch = NULL;
  979. max_errors = (ecc_opt == OMAP_ECC_BCH8_CODE_HW) ? 8 : 4;
  980. if (max_errors != hw_errors) {
  981. pr_err("cannot configure %d-bit BCH ecc, only %d-bit supported",
  982. max_errors, hw_errors);
  983. goto fail;
  984. }
  985. /* initialize GPMC BCH engine */
  986. ret = gpmc_init_hwecc_bch(info->gpmc_cs, 1, max_errors);
  987. if (ret)
  988. goto fail;
  989. /* software bch library is only used to detect and locate errors */
  990. info->bch = init_bch(13, max_errors, 0x201b /* hw polynomial */);
  991. if (!info->bch)
  992. goto fail;
  993. info->nand.ecc.size = 512;
  994. info->nand.ecc.hwctl = omap3_enable_hwecc_bch;
  995. info->nand.ecc.correct = omap3_correct_data_bch;
  996. info->nand.ecc.mode = NAND_ECC_HW;
  997. /*
  998. * The number of corrected errors in an ecc block that will trigger
  999. * block scrubbing defaults to the ecc strength (4 or 8).
  1000. * Set mtd->bitflip_threshold here to define a custom threshold.
  1001. */
  1002. if (max_errors == 8) {
  1003. info->nand.ecc.strength = 8;
  1004. info->nand.ecc.bytes = 13;
  1005. info->nand.ecc.calculate = omap3_calculate_ecc_bch8;
  1006. } else {
  1007. info->nand.ecc.strength = 4;
  1008. info->nand.ecc.bytes = 7;
  1009. info->nand.ecc.calculate = omap3_calculate_ecc_bch4;
  1010. }
  1011. pr_info("enabling NAND BCH ecc with %d-bit correction\n", max_errors);
  1012. return 0;
  1013. fail:
  1014. omap3_free_bch(mtd);
  1015. return -1;
  1016. }
  1017. /**
  1018. * omap3_init_bch_tail - Build an oob layout for BCH ECC correction.
  1019. * @mtd: MTD device structure
  1020. */
  1021. static int omap3_init_bch_tail(struct mtd_info *mtd)
  1022. {
  1023. int i, steps;
  1024. struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
  1025. mtd);
  1026. struct nand_ecclayout *layout = &info->ecclayout;
  1027. /* build oob layout */
  1028. steps = mtd->writesize/info->nand.ecc.size;
  1029. layout->eccbytes = steps*info->nand.ecc.bytes;
  1030. /* do not bother creating special oob layouts for small page devices */
  1031. if (mtd->oobsize < 64) {
  1032. pr_err("BCH ecc is not supported on small page devices\n");
  1033. goto fail;
  1034. }
  1035. /* reserve 2 bytes for bad block marker */
  1036. if (layout->eccbytes+2 > mtd->oobsize) {
  1037. pr_err("no oob layout available for oobsize %d eccbytes %u\n",
  1038. mtd->oobsize, layout->eccbytes);
  1039. goto fail;
  1040. }
  1041. /* put ecc bytes at oob tail */
  1042. for (i = 0; i < layout->eccbytes; i++)
  1043. layout->eccpos[i] = mtd->oobsize-layout->eccbytes+i;
  1044. layout->oobfree[0].offset = 2;
  1045. layout->oobfree[0].length = mtd->oobsize-2-layout->eccbytes;
  1046. info->nand.ecc.layout = layout;
  1047. if (!(info->nand.options & NAND_BUSWIDTH_16))
  1048. info->nand.badblock_pattern = &bb_descrip_flashbased;
  1049. return 0;
  1050. fail:
  1051. omap3_free_bch(mtd);
  1052. return -1;
  1053. }
  1054. #else
  1055. static int omap3_init_bch(struct mtd_info *mtd, int ecc_opt)
  1056. {
  1057. pr_err("CONFIG_MTD_NAND_OMAP_BCH is not enabled\n");
  1058. return -1;
  1059. }
  1060. static int omap3_init_bch_tail(struct mtd_info *mtd)
  1061. {
  1062. return -1;
  1063. }
  1064. static void omap3_free_bch(struct mtd_info *mtd)
  1065. {
  1066. }
  1067. #endif /* CONFIG_MTD_NAND_OMAP_BCH */
  1068. static int __devinit omap_nand_probe(struct platform_device *pdev)
  1069. {
  1070. struct omap_nand_info *info;
  1071. struct omap_nand_platform_data *pdata;
  1072. int err;
  1073. int i, offset;
  1074. dma_cap_mask_t mask;
  1075. unsigned sig;
  1076. pdata = pdev->dev.platform_data;
  1077. if (pdata == NULL) {
  1078. dev_err(&pdev->dev, "platform data missing\n");
  1079. return -ENODEV;
  1080. }
  1081. info = kzalloc(sizeof(struct omap_nand_info), GFP_KERNEL);
  1082. if (!info)
  1083. return -ENOMEM;
  1084. platform_set_drvdata(pdev, info);
  1085. spin_lock_init(&info->controller.lock);
  1086. init_waitqueue_head(&info->controller.wq);
  1087. info->pdev = pdev;
  1088. info->gpmc_cs = pdata->cs;
  1089. info->phys_base = pdata->phys_base;
  1090. info->mtd.priv = &info->nand;
  1091. info->mtd.name = dev_name(&pdev->dev);
  1092. info->mtd.owner = THIS_MODULE;
  1093. info->nand.options = pdata->devsize;
  1094. info->nand.options |= NAND_SKIP_BBTSCAN;
  1095. /* NAND write protect off */
  1096. gpmc_cs_configure(info->gpmc_cs, GPMC_CONFIG_WP, 0);
  1097. if (!request_mem_region(info->phys_base, NAND_IO_SIZE,
  1098. pdev->dev.driver->name)) {
  1099. err = -EBUSY;
  1100. goto out_free_info;
  1101. }
  1102. info->nand.IO_ADDR_R = ioremap(info->phys_base, NAND_IO_SIZE);
  1103. if (!info->nand.IO_ADDR_R) {
  1104. err = -ENOMEM;
  1105. goto out_release_mem_region;
  1106. }
  1107. info->nand.controller = &info->controller;
  1108. info->nand.IO_ADDR_W = info->nand.IO_ADDR_R;
  1109. info->nand.cmd_ctrl = omap_hwcontrol;
  1110. /*
  1111. * If RDY/BSY line is connected to OMAP then use the omap ready
  1112. * funcrtion and the generic nand_wait function which reads the status
  1113. * register after monitoring the RDY/BSY line.Otherwise use a standard
  1114. * chip delay which is slightly more than tR (AC Timing) of the NAND
  1115. * device and read status register until you get a failure or success
  1116. */
  1117. if (pdata->dev_ready) {
  1118. info->nand.dev_ready = omap_dev_ready;
  1119. info->nand.chip_delay = 0;
  1120. } else {
  1121. info->nand.waitfunc = omap_wait;
  1122. info->nand.chip_delay = 50;
  1123. }
  1124. switch (pdata->xfer_type) {
  1125. case NAND_OMAP_PREFETCH_POLLED:
  1126. info->nand.read_buf = omap_read_buf_pref;
  1127. info->nand.write_buf = omap_write_buf_pref;
  1128. break;
  1129. case NAND_OMAP_POLLED:
  1130. if (info->nand.options & NAND_BUSWIDTH_16) {
  1131. info->nand.read_buf = omap_read_buf16;
  1132. info->nand.write_buf = omap_write_buf16;
  1133. } else {
  1134. info->nand.read_buf = omap_read_buf8;
  1135. info->nand.write_buf = omap_write_buf8;
  1136. }
  1137. break;
  1138. case NAND_OMAP_PREFETCH_DMA:
  1139. dma_cap_zero(mask);
  1140. dma_cap_set(DMA_SLAVE, mask);
  1141. sig = OMAP24XX_DMA_GPMC;
  1142. info->dma = dma_request_channel(mask, omap_dma_filter_fn, &sig);
  1143. if (!info->dma) {
  1144. dev_warn(&pdev->dev, "DMA engine request failed\n");
  1145. } else {
  1146. struct dma_slave_config cfg;
  1147. int rc;
  1148. memset(&cfg, 0, sizeof(cfg));
  1149. cfg.src_addr = info->phys_base;
  1150. cfg.dst_addr = info->phys_base;
  1151. cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
  1152. cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
  1153. cfg.src_maxburst = 16;
  1154. cfg.dst_maxburst = 16;
  1155. rc = dmaengine_slave_config(info->dma, &cfg);
  1156. if (rc) {
  1157. dev_err(&pdev->dev, "DMA engine slave config failed: %d\n",
  1158. rc);
  1159. goto out_release_mem_region;
  1160. }
  1161. info->nand.read_buf = omap_read_buf_dma_pref;
  1162. info->nand.write_buf = omap_write_buf_dma_pref;
  1163. break;
  1164. }
  1165. err = omap_request_dma(OMAP24XX_DMA_GPMC, "NAND",
  1166. omap_nand_dma_cb, &info->comp, &info->dma_ch);
  1167. if (err < 0) {
  1168. info->dma_ch = -1;
  1169. dev_err(&pdev->dev, "DMA request failed!\n");
  1170. goto out_release_mem_region;
  1171. } else {
  1172. omap_set_dma_dest_burst_mode(info->dma_ch,
  1173. OMAP_DMA_DATA_BURST_16);
  1174. omap_set_dma_src_burst_mode(info->dma_ch,
  1175. OMAP_DMA_DATA_BURST_16);
  1176. info->nand.read_buf = omap_read_buf_dma_pref;
  1177. info->nand.write_buf = omap_write_buf_dma_pref;
  1178. }
  1179. break;
  1180. case NAND_OMAP_PREFETCH_IRQ:
  1181. err = request_irq(pdata->gpmc_irq,
  1182. omap_nand_irq, IRQF_SHARED, "gpmc-nand", info);
  1183. if (err) {
  1184. dev_err(&pdev->dev, "requesting irq(%d) error:%d",
  1185. pdata->gpmc_irq, err);
  1186. goto out_release_mem_region;
  1187. } else {
  1188. info->gpmc_irq = pdata->gpmc_irq;
  1189. info->nand.read_buf = omap_read_buf_irq_pref;
  1190. info->nand.write_buf = omap_write_buf_irq_pref;
  1191. }
  1192. break;
  1193. default:
  1194. dev_err(&pdev->dev,
  1195. "xfer_type(%d) not supported!\n", pdata->xfer_type);
  1196. err = -EINVAL;
  1197. goto out_release_mem_region;
  1198. }
  1199. info->nand.verify_buf = omap_verify_buf;
  1200. /* selsect the ecc type */
  1201. if (pdata->ecc_opt == OMAP_ECC_HAMMING_CODE_DEFAULT)
  1202. info->nand.ecc.mode = NAND_ECC_SOFT;
  1203. else if ((pdata->ecc_opt == OMAP_ECC_HAMMING_CODE_HW) ||
  1204. (pdata->ecc_opt == OMAP_ECC_HAMMING_CODE_HW_ROMCODE)) {
  1205. info->nand.ecc.bytes = 3;
  1206. info->nand.ecc.size = 512;
  1207. info->nand.ecc.strength = 1;
  1208. info->nand.ecc.calculate = omap_calculate_ecc;
  1209. info->nand.ecc.hwctl = omap_enable_hwecc;
  1210. info->nand.ecc.correct = omap_correct_data;
  1211. info->nand.ecc.mode = NAND_ECC_HW;
  1212. } else if ((pdata->ecc_opt == OMAP_ECC_BCH4_CODE_HW) ||
  1213. (pdata->ecc_opt == OMAP_ECC_BCH8_CODE_HW)) {
  1214. err = omap3_init_bch(&info->mtd, pdata->ecc_opt);
  1215. if (err) {
  1216. err = -EINVAL;
  1217. goto out_release_mem_region;
  1218. }
  1219. }
  1220. /* DIP switches on some boards change between 8 and 16 bit
  1221. * bus widths for flash. Try the other width if the first try fails.
  1222. */
  1223. if (nand_scan_ident(&info->mtd, 1, NULL)) {
  1224. info->nand.options ^= NAND_BUSWIDTH_16;
  1225. if (nand_scan_ident(&info->mtd, 1, NULL)) {
  1226. err = -ENXIO;
  1227. goto out_release_mem_region;
  1228. }
  1229. }
  1230. /* rom code layout */
  1231. if (pdata->ecc_opt == OMAP_ECC_HAMMING_CODE_HW_ROMCODE) {
  1232. if (info->nand.options & NAND_BUSWIDTH_16)
  1233. offset = 2;
  1234. else {
  1235. offset = 1;
  1236. info->nand.badblock_pattern = &bb_descrip_flashbased;
  1237. }
  1238. omap_oobinfo.eccbytes = 3 * (info->mtd.oobsize/16);
  1239. for (i = 0; i < omap_oobinfo.eccbytes; i++)
  1240. omap_oobinfo.eccpos[i] = i+offset;
  1241. omap_oobinfo.oobfree->offset = offset + omap_oobinfo.eccbytes;
  1242. omap_oobinfo.oobfree->length = info->mtd.oobsize -
  1243. (offset + omap_oobinfo.eccbytes);
  1244. info->nand.ecc.layout = &omap_oobinfo;
  1245. } else if ((pdata->ecc_opt == OMAP_ECC_BCH4_CODE_HW) ||
  1246. (pdata->ecc_opt == OMAP_ECC_BCH8_CODE_HW)) {
  1247. /* build OOB layout for BCH ECC correction */
  1248. err = omap3_init_bch_tail(&info->mtd);
  1249. if (err) {
  1250. err = -EINVAL;
  1251. goto out_release_mem_region;
  1252. }
  1253. }
  1254. /* second phase scan */
  1255. if (nand_scan_tail(&info->mtd)) {
  1256. err = -ENXIO;
  1257. goto out_release_mem_region;
  1258. }
  1259. mtd_device_parse_register(&info->mtd, NULL, NULL, pdata->parts,
  1260. pdata->nr_parts);
  1261. platform_set_drvdata(pdev, &info->mtd);
  1262. return 0;
  1263. out_release_mem_region:
  1264. if (info->dma)
  1265. dma_release_channel(info->dma);
  1266. release_mem_region(info->phys_base, NAND_IO_SIZE);
  1267. out_free_info:
  1268. kfree(info);
  1269. return err;
  1270. }
  1271. static int omap_nand_remove(struct platform_device *pdev)
  1272. {
  1273. struct mtd_info *mtd = platform_get_drvdata(pdev);
  1274. struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
  1275. mtd);
  1276. omap3_free_bch(&info->mtd);
  1277. platform_set_drvdata(pdev, NULL);
  1278. if (info->dma_ch != -1)
  1279. omap_free_dma(info->dma_ch);
  1280. if (info->dma)
  1281. dma_release_channel(info->dma);
  1282. if (info->gpmc_irq)
  1283. free_irq(info->gpmc_irq, info);
  1284. /* Release NAND device, its internal structures and partitions */
  1285. nand_release(&info->mtd);
  1286. iounmap(info->nand.IO_ADDR_R);
  1287. kfree(&info->mtd);
  1288. return 0;
  1289. }
  1290. static struct platform_driver omap_nand_driver = {
  1291. .probe = omap_nand_probe,
  1292. .remove = omap_nand_remove,
  1293. .driver = {
  1294. .name = DRIVER_NAME,
  1295. .owner = THIS_MODULE,
  1296. },
  1297. };
  1298. module_platform_driver(omap_nand_driver);
  1299. MODULE_ALIAS("platform:" DRIVER_NAME);
  1300. MODULE_LICENSE("GPL");
  1301. MODULE_DESCRIPTION("Glue layer for NAND flash on TI OMAP boards");