s3c2410_udc.c 50 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010101110121013101410151016101710181019102010211022102310241025102610271028102910301031103210331034103510361037103810391040104110421043104410451046104710481049105010511052105310541055105610571058105910601061106210631064106510661067106810691070107110721073107410751076107710781079108010811082108310841085108610871088108910901091109210931094109510961097109810991100110111021103110411051106110711081109111011111112111311141115111611171118111911201121112211231124112511261127112811291130113111321133113411351136113711381139114011411142114311441145114611471148114911501151115211531154115511561157115811591160116111621163116411651166116711681169117011711172117311741175117611771178117911801181118211831184118511861187118811891190119111921193119411951196119711981199120012011202120312041205120612071208120912101211121212131214121512161217121812191220122112221223122412251226122712281229123012311232123312341235123612371238123912401241124212431244124512461247124812491250125112521253125412551256125712581259126012611262126312641265126612671268126912701271127212731274127512761277127812791280128112821283128412851286128712881289129012911292129312941295129612971298129913001301130213031304130513061307130813091310131113121313131413151316131713181319132013211322132313241325132613271328132913301331133213331334133513361337133813391340134113421343134413451346134713481349135013511352135313541355135613571358135913601361136213631364136513661367136813691370137113721373137413751376137713781379138013811382138313841385138613871388138913901391139213931394139513961397139813991400140114021403140414051406140714081409141014111412141314141415141614171418141914201421142214231424142514261427142814291430143114321433143414351436143714381439144014411442144314441445144614471448144914501451145214531454145514561457145814591460146114621463146414651466146714681469147014711472147314741475147614771478147914801481148214831484148514861487148814891490149114921493149414951496149714981499150015011502150315041505150615071508150915101511151215131514151515161517151815191520152115221523152415251526152715281529153015311532153315341535153615371538153915401541154215431544154515461547154815491550155115521553155415551556155715581559156015611562156315641565156615671568156915701571157215731574157515761577157815791580158115821583158415851586158715881589159015911592159315941595159615971598159916001601160216031604160516061607160816091610161116121613161416151616161716181619162016211622162316241625162616271628162916301631163216331634163516361637163816391640164116421643164416451646164716481649165016511652165316541655165616571658165916601661166216631664166516661667166816691670167116721673167416751676167716781679168016811682168316841685168616871688168916901691169216931694169516961697169816991700170117021703170417051706170717081709171017111712171317141715171617171718171917201721172217231724172517261727172817291730173117321733173417351736173717381739174017411742174317441745174617471748174917501751175217531754175517561757175817591760176117621763176417651766176717681769177017711772177317741775177617771778177917801781178217831784178517861787178817891790179117921793179417951796179717981799180018011802180318041805180618071808180918101811181218131814181518161817181818191820182118221823182418251826182718281829183018311832183318341835183618371838183918401841184218431844184518461847184818491850185118521853185418551856185718581859186018611862186318641865186618671868186918701871187218731874187518761877187818791880188118821883188418851886188718881889189018911892189318941895189618971898189919001901190219031904190519061907190819091910191119121913191419151916191719181919192019211922192319241925192619271928192919301931193219331934193519361937193819391940194119421943194419451946194719481949195019511952195319541955195619571958195919601961196219631964196519661967196819691970197119721973197419751976197719781979198019811982198319841985198619871988198919901991199219931994199519961997199819992000200120022003200420052006200720082009201020112012201320142015201620172018201920202021202220232024202520262027202820292030203120322033203420352036203720382039204020412042204320442045204620472048204920502051205220532054205520562057205820592060206120622063206420652066206720682069207020712072207320742075207620772078207920802081208220832084208520862087208820892090209120922093209420952096209720982099210021012102210321042105210621072108210921102111211221132114
  1. /*
  2. * linux/drivers/usb/gadget/s3c2410_udc.c
  3. *
  4. * Samsung S3C24xx series on-chip full speed USB device controllers
  5. *
  6. * Copyright (C) 2004-2007 Herbert Pötzl - Arnaud Patard
  7. * Additional cleanups by Ben Dooks <ben-linux@fluff.org>
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License as published by
  11. * the Free Software Foundation; either version 2 of the License, or
  12. * (at your option) any later version.
  13. *
  14. * This program is distributed in the hope that it will be useful,
  15. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17. * GNU General Public License for more details.
  18. *
  19. * You should have received a copy of the GNU General Public License
  20. * along with this program; if not, write to the Free Software
  21. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  22. *
  23. */
  24. #include <linux/module.h>
  25. #include <linux/kernel.h>
  26. #include <linux/delay.h>
  27. #include <linux/ioport.h>
  28. #include <linux/sched.h>
  29. #include <linux/slab.h>
  30. #include <linux/errno.h>
  31. #include <linux/init.h>
  32. #include <linux/timer.h>
  33. #include <linux/list.h>
  34. #include <linux/interrupt.h>
  35. #include <linux/platform_device.h>
  36. #include <linux/clk.h>
  37. #include <linux/gpio.h>
  38. #include <linux/prefetch.h>
  39. #include <linux/debugfs.h>
  40. #include <linux/seq_file.h>
  41. #include <linux/usb.h>
  42. #include <linux/usb/gadget.h>
  43. #include <asm/byteorder.h>
  44. #include <asm/io.h>
  45. #include <asm/irq.h>
  46. #include <asm/system.h>
  47. #include <asm/unaligned.h>
  48. #include <mach/irqs.h>
  49. #include <mach/hardware.h>
  50. #include <plat/regs-udc.h>
  51. #include <plat/udc.h>
  52. #include "s3c2410_udc.h"
  53. #define DRIVER_DESC "S3C2410 USB Device Controller Gadget"
  54. #define DRIVER_VERSION "29 Apr 2007"
  55. #define DRIVER_AUTHOR "Herbert Pötzl <herbert@13thfloor.at>, " \
  56. "Arnaud Patard <arnaud.patard@rtp-net.org>"
  57. static const char gadget_name[] = "s3c2410_udc";
  58. static const char driver_desc[] = DRIVER_DESC;
  59. static struct s3c2410_udc *the_controller;
  60. static struct clk *udc_clock;
  61. static struct clk *usb_bus_clock;
  62. static void __iomem *base_addr;
  63. static u64 rsrc_start;
  64. static u64 rsrc_len;
  65. static struct dentry *s3c2410_udc_debugfs_root;
  66. static inline u32 udc_read(u32 reg)
  67. {
  68. return readb(base_addr + reg);
  69. }
  70. static inline void udc_write(u32 value, u32 reg)
  71. {
  72. writeb(value, base_addr + reg);
  73. }
  74. static inline void udc_writeb(void __iomem *base, u32 value, u32 reg)
  75. {
  76. writeb(value, base + reg);
  77. }
  78. static struct s3c2410_udc_mach_info *udc_info;
  79. /*************************** DEBUG FUNCTION ***************************/
  80. #define DEBUG_NORMAL 1
  81. #define DEBUG_VERBOSE 2
  82. #ifdef CONFIG_USB_S3C2410_DEBUG
  83. #define USB_S3C2410_DEBUG_LEVEL 0
  84. static uint32_t s3c2410_ticks = 0;
  85. static int dprintk(int level, const char *fmt, ...)
  86. {
  87. static char printk_buf[1024];
  88. static long prevticks;
  89. static int invocation;
  90. va_list args;
  91. int len;
  92. if (level > USB_S3C2410_DEBUG_LEVEL)
  93. return 0;
  94. if (s3c2410_ticks != prevticks) {
  95. prevticks = s3c2410_ticks;
  96. invocation = 0;
  97. }
  98. len = scnprintf(printk_buf,
  99. sizeof(printk_buf), "%1lu.%02d USB: ",
  100. prevticks, invocation++);
  101. va_start(args, fmt);
  102. len = vscnprintf(printk_buf+len,
  103. sizeof(printk_buf)-len, fmt, args);
  104. va_end(args);
  105. return printk(KERN_DEBUG "%s", printk_buf);
  106. }
  107. #else
  108. static int dprintk(int level, const char *fmt, ...)
  109. {
  110. return 0;
  111. }
  112. #endif
  113. static int s3c2410_udc_debugfs_seq_show(struct seq_file *m, void *p)
  114. {
  115. u32 addr_reg,pwr_reg,ep_int_reg,usb_int_reg;
  116. u32 ep_int_en_reg, usb_int_en_reg, ep0_csr;
  117. u32 ep1_i_csr1,ep1_i_csr2,ep1_o_csr1,ep1_o_csr2;
  118. u32 ep2_i_csr1,ep2_i_csr2,ep2_o_csr1,ep2_o_csr2;
  119. addr_reg = udc_read(S3C2410_UDC_FUNC_ADDR_REG);
  120. pwr_reg = udc_read(S3C2410_UDC_PWR_REG);
  121. ep_int_reg = udc_read(S3C2410_UDC_EP_INT_REG);
  122. usb_int_reg = udc_read(S3C2410_UDC_USB_INT_REG);
  123. ep_int_en_reg = udc_read(S3C2410_UDC_EP_INT_EN_REG);
  124. usb_int_en_reg = udc_read(S3C2410_UDC_USB_INT_EN_REG);
  125. udc_write(0, S3C2410_UDC_INDEX_REG);
  126. ep0_csr = udc_read(S3C2410_UDC_IN_CSR1_REG);
  127. udc_write(1, S3C2410_UDC_INDEX_REG);
  128. ep1_i_csr1 = udc_read(S3C2410_UDC_IN_CSR1_REG);
  129. ep1_i_csr2 = udc_read(S3C2410_UDC_IN_CSR2_REG);
  130. ep1_o_csr1 = udc_read(S3C2410_UDC_IN_CSR1_REG);
  131. ep1_o_csr2 = udc_read(S3C2410_UDC_IN_CSR2_REG);
  132. udc_write(2, S3C2410_UDC_INDEX_REG);
  133. ep2_i_csr1 = udc_read(S3C2410_UDC_IN_CSR1_REG);
  134. ep2_i_csr2 = udc_read(S3C2410_UDC_IN_CSR2_REG);
  135. ep2_o_csr1 = udc_read(S3C2410_UDC_IN_CSR1_REG);
  136. ep2_o_csr2 = udc_read(S3C2410_UDC_IN_CSR2_REG);
  137. seq_printf(m, "FUNC_ADDR_REG : 0x%04X\n"
  138. "PWR_REG : 0x%04X\n"
  139. "EP_INT_REG : 0x%04X\n"
  140. "USB_INT_REG : 0x%04X\n"
  141. "EP_INT_EN_REG : 0x%04X\n"
  142. "USB_INT_EN_REG : 0x%04X\n"
  143. "EP0_CSR : 0x%04X\n"
  144. "EP1_I_CSR1 : 0x%04X\n"
  145. "EP1_I_CSR2 : 0x%04X\n"
  146. "EP1_O_CSR1 : 0x%04X\n"
  147. "EP1_O_CSR2 : 0x%04X\n"
  148. "EP2_I_CSR1 : 0x%04X\n"
  149. "EP2_I_CSR2 : 0x%04X\n"
  150. "EP2_O_CSR1 : 0x%04X\n"
  151. "EP2_O_CSR2 : 0x%04X\n",
  152. addr_reg,pwr_reg,ep_int_reg,usb_int_reg,
  153. ep_int_en_reg, usb_int_en_reg, ep0_csr,
  154. ep1_i_csr1,ep1_i_csr2,ep1_o_csr1,ep1_o_csr2,
  155. ep2_i_csr1,ep2_i_csr2,ep2_o_csr1,ep2_o_csr2
  156. );
  157. return 0;
  158. }
  159. static int s3c2410_udc_debugfs_fops_open(struct inode *inode,
  160. struct file *file)
  161. {
  162. return single_open(file, s3c2410_udc_debugfs_seq_show, NULL);
  163. }
  164. static const struct file_operations s3c2410_udc_debugfs_fops = {
  165. .open = s3c2410_udc_debugfs_fops_open,
  166. .read = seq_read,
  167. .llseek = seq_lseek,
  168. .release = single_release,
  169. .owner = THIS_MODULE,
  170. };
  171. /* io macros */
  172. static inline void s3c2410_udc_clear_ep0_opr(void __iomem *base)
  173. {
  174. udc_writeb(base, S3C2410_UDC_INDEX_EP0, S3C2410_UDC_INDEX_REG);
  175. udc_writeb(base, S3C2410_UDC_EP0_CSR_SOPKTRDY,
  176. S3C2410_UDC_EP0_CSR_REG);
  177. }
  178. static inline void s3c2410_udc_clear_ep0_sst(void __iomem *base)
  179. {
  180. udc_writeb(base, S3C2410_UDC_INDEX_EP0, S3C2410_UDC_INDEX_REG);
  181. writeb(0x00, base + S3C2410_UDC_EP0_CSR_REG);
  182. }
  183. static inline void s3c2410_udc_clear_ep0_se(void __iomem *base)
  184. {
  185. udc_writeb(base, S3C2410_UDC_INDEX_EP0, S3C2410_UDC_INDEX_REG);
  186. udc_writeb(base, S3C2410_UDC_EP0_CSR_SSE, S3C2410_UDC_EP0_CSR_REG);
  187. }
  188. static inline void s3c2410_udc_set_ep0_ipr(void __iomem *base)
  189. {
  190. udc_writeb(base, S3C2410_UDC_INDEX_EP0, S3C2410_UDC_INDEX_REG);
  191. udc_writeb(base, S3C2410_UDC_EP0_CSR_IPKRDY, S3C2410_UDC_EP0_CSR_REG);
  192. }
  193. static inline void s3c2410_udc_set_ep0_de(void __iomem *base)
  194. {
  195. udc_writeb(base, S3C2410_UDC_INDEX_EP0, S3C2410_UDC_INDEX_REG);
  196. udc_writeb(base, S3C2410_UDC_EP0_CSR_DE, S3C2410_UDC_EP0_CSR_REG);
  197. }
  198. inline void s3c2410_udc_set_ep0_ss(void __iomem *b)
  199. {
  200. udc_writeb(b, S3C2410_UDC_INDEX_EP0, S3C2410_UDC_INDEX_REG);
  201. udc_writeb(b, S3C2410_UDC_EP0_CSR_SENDSTL, S3C2410_UDC_EP0_CSR_REG);
  202. }
  203. static inline void s3c2410_udc_set_ep0_de_out(void __iomem *base)
  204. {
  205. udc_writeb(base, S3C2410_UDC_INDEX_EP0, S3C2410_UDC_INDEX_REG);
  206. udc_writeb(base,(S3C2410_UDC_EP0_CSR_SOPKTRDY
  207. | S3C2410_UDC_EP0_CSR_DE),
  208. S3C2410_UDC_EP0_CSR_REG);
  209. }
  210. static inline void s3c2410_udc_set_ep0_sse_out(void __iomem *base)
  211. {
  212. udc_writeb(base, S3C2410_UDC_INDEX_EP0, S3C2410_UDC_INDEX_REG);
  213. udc_writeb(base, (S3C2410_UDC_EP0_CSR_SOPKTRDY
  214. | S3C2410_UDC_EP0_CSR_SSE),
  215. S3C2410_UDC_EP0_CSR_REG);
  216. }
  217. static inline void s3c2410_udc_set_ep0_de_in(void __iomem *base)
  218. {
  219. udc_writeb(base, S3C2410_UDC_INDEX_EP0, S3C2410_UDC_INDEX_REG);
  220. udc_writeb(base, (S3C2410_UDC_EP0_CSR_IPKRDY
  221. | S3C2410_UDC_EP0_CSR_DE),
  222. S3C2410_UDC_EP0_CSR_REG);
  223. }
  224. /*------------------------- I/O ----------------------------------*/
  225. /*
  226. * s3c2410_udc_done
  227. */
  228. static void s3c2410_udc_done(struct s3c2410_ep *ep,
  229. struct s3c2410_request *req, int status)
  230. {
  231. unsigned halted = ep->halted;
  232. list_del_init(&req->queue);
  233. if (likely (req->req.status == -EINPROGRESS))
  234. req->req.status = status;
  235. else
  236. status = req->req.status;
  237. ep->halted = 1;
  238. req->req.complete(&ep->ep, &req->req);
  239. ep->halted = halted;
  240. }
  241. static void s3c2410_udc_nuke(struct s3c2410_udc *udc,
  242. struct s3c2410_ep *ep, int status)
  243. {
  244. /* Sanity check */
  245. if (&ep->queue == NULL)
  246. return;
  247. while (!list_empty (&ep->queue)) {
  248. struct s3c2410_request *req;
  249. req = list_entry (ep->queue.next, struct s3c2410_request,
  250. queue);
  251. s3c2410_udc_done(ep, req, status);
  252. }
  253. }
  254. static inline void s3c2410_udc_clear_ep_state(struct s3c2410_udc *dev)
  255. {
  256. unsigned i;
  257. /* hardware SET_{CONFIGURATION,INTERFACE} automagic resets endpoint
  258. * fifos, and pending transactions mustn't be continued in any case.
  259. */
  260. for (i = 1; i < S3C2410_ENDPOINTS; i++)
  261. s3c2410_udc_nuke(dev, &dev->ep[i], -ECONNABORTED);
  262. }
  263. static inline int s3c2410_udc_fifo_count_out(void)
  264. {
  265. int tmp;
  266. tmp = udc_read(S3C2410_UDC_OUT_FIFO_CNT2_REG) << 8;
  267. tmp |= udc_read(S3C2410_UDC_OUT_FIFO_CNT1_REG);
  268. return tmp;
  269. }
  270. /*
  271. * s3c2410_udc_write_packet
  272. */
  273. static inline int s3c2410_udc_write_packet(int fifo,
  274. struct s3c2410_request *req,
  275. unsigned max)
  276. {
  277. unsigned len = min(req->req.length - req->req.actual, max);
  278. u8 *buf = req->req.buf + req->req.actual;
  279. prefetch(buf);
  280. dprintk(DEBUG_VERBOSE, "%s %d %d %d %d\n", __func__,
  281. req->req.actual, req->req.length, len, req->req.actual + len);
  282. req->req.actual += len;
  283. udelay(5);
  284. writesb(base_addr + fifo, buf, len);
  285. return len;
  286. }
  287. /*
  288. * s3c2410_udc_write_fifo
  289. *
  290. * return: 0 = still running, 1 = completed, negative = errno
  291. */
  292. static int s3c2410_udc_write_fifo(struct s3c2410_ep *ep,
  293. struct s3c2410_request *req)
  294. {
  295. unsigned count;
  296. int is_last;
  297. u32 idx;
  298. int fifo_reg;
  299. u32 ep_csr;
  300. idx = ep->bEndpointAddress & 0x7F;
  301. switch (idx) {
  302. default:
  303. idx = 0;
  304. case 0:
  305. fifo_reg = S3C2410_UDC_EP0_FIFO_REG;
  306. break;
  307. case 1:
  308. fifo_reg = S3C2410_UDC_EP1_FIFO_REG;
  309. break;
  310. case 2:
  311. fifo_reg = S3C2410_UDC_EP2_FIFO_REG;
  312. break;
  313. case 3:
  314. fifo_reg = S3C2410_UDC_EP3_FIFO_REG;
  315. break;
  316. case 4:
  317. fifo_reg = S3C2410_UDC_EP4_FIFO_REG;
  318. break;
  319. }
  320. count = s3c2410_udc_write_packet(fifo_reg, req, ep->ep.maxpacket);
  321. /* last packet is often short (sometimes a zlp) */
  322. if (count != ep->ep.maxpacket)
  323. is_last = 1;
  324. else if (req->req.length != req->req.actual || req->req.zero)
  325. is_last = 0;
  326. else
  327. is_last = 2;
  328. /* Only ep0 debug messages are interesting */
  329. if (idx == 0)
  330. dprintk(DEBUG_NORMAL,
  331. "Written ep%d %d.%d of %d b [last %d,z %d]\n",
  332. idx, count, req->req.actual, req->req.length,
  333. is_last, req->req.zero);
  334. if (is_last) {
  335. /* The order is important. It prevents sending 2 packets
  336. * at the same time */
  337. if (idx == 0) {
  338. /* Reset signal => no need to say 'data sent' */
  339. if (! (udc_read(S3C2410_UDC_USB_INT_REG)
  340. & S3C2410_UDC_USBINT_RESET))
  341. s3c2410_udc_set_ep0_de_in(base_addr);
  342. ep->dev->ep0state=EP0_IDLE;
  343. } else {
  344. udc_write(idx, S3C2410_UDC_INDEX_REG);
  345. ep_csr = udc_read(S3C2410_UDC_IN_CSR1_REG);
  346. udc_write(idx, S3C2410_UDC_INDEX_REG);
  347. udc_write(ep_csr | S3C2410_UDC_ICSR1_PKTRDY,
  348. S3C2410_UDC_IN_CSR1_REG);
  349. }
  350. s3c2410_udc_done(ep, req, 0);
  351. is_last = 1;
  352. } else {
  353. if (idx == 0) {
  354. /* Reset signal => no need to say 'data sent' */
  355. if (! (udc_read(S3C2410_UDC_USB_INT_REG)
  356. & S3C2410_UDC_USBINT_RESET))
  357. s3c2410_udc_set_ep0_ipr(base_addr);
  358. } else {
  359. udc_write(idx, S3C2410_UDC_INDEX_REG);
  360. ep_csr = udc_read(S3C2410_UDC_IN_CSR1_REG);
  361. udc_write(idx, S3C2410_UDC_INDEX_REG);
  362. udc_write(ep_csr | S3C2410_UDC_ICSR1_PKTRDY,
  363. S3C2410_UDC_IN_CSR1_REG);
  364. }
  365. }
  366. return is_last;
  367. }
  368. static inline int s3c2410_udc_read_packet(int fifo, u8 *buf,
  369. struct s3c2410_request *req, unsigned avail)
  370. {
  371. unsigned len;
  372. len = min(req->req.length - req->req.actual, avail);
  373. req->req.actual += len;
  374. readsb(fifo + base_addr, buf, len);
  375. return len;
  376. }
  377. /*
  378. * return: 0 = still running, 1 = queue empty, negative = errno
  379. */
  380. static int s3c2410_udc_read_fifo(struct s3c2410_ep *ep,
  381. struct s3c2410_request *req)
  382. {
  383. u8 *buf;
  384. u32 ep_csr;
  385. unsigned bufferspace;
  386. int is_last=1;
  387. unsigned avail;
  388. int fifo_count = 0;
  389. u32 idx;
  390. int fifo_reg;
  391. idx = ep->bEndpointAddress & 0x7F;
  392. switch (idx) {
  393. default:
  394. idx = 0;
  395. case 0:
  396. fifo_reg = S3C2410_UDC_EP0_FIFO_REG;
  397. break;
  398. case 1:
  399. fifo_reg = S3C2410_UDC_EP1_FIFO_REG;
  400. break;
  401. case 2:
  402. fifo_reg = S3C2410_UDC_EP2_FIFO_REG;
  403. break;
  404. case 3:
  405. fifo_reg = S3C2410_UDC_EP3_FIFO_REG;
  406. break;
  407. case 4:
  408. fifo_reg = S3C2410_UDC_EP4_FIFO_REG;
  409. break;
  410. }
  411. if (!req->req.length)
  412. return 1;
  413. buf = req->req.buf + req->req.actual;
  414. bufferspace = req->req.length - req->req.actual;
  415. if (!bufferspace) {
  416. dprintk(DEBUG_NORMAL, "%s: buffer full!\n", __func__);
  417. return -1;
  418. }
  419. udc_write(idx, S3C2410_UDC_INDEX_REG);
  420. fifo_count = s3c2410_udc_fifo_count_out();
  421. dprintk(DEBUG_NORMAL, "%s fifo count : %d\n", __func__, fifo_count);
  422. if (fifo_count > ep->ep.maxpacket)
  423. avail = ep->ep.maxpacket;
  424. else
  425. avail = fifo_count;
  426. fifo_count = s3c2410_udc_read_packet(fifo_reg, buf, req, avail);
  427. /* checking this with ep0 is not accurate as we already
  428. * read a control request
  429. **/
  430. if (idx != 0 && fifo_count < ep->ep.maxpacket) {
  431. is_last = 1;
  432. /* overflowed this request? flush extra data */
  433. if (fifo_count != avail)
  434. req->req.status = -EOVERFLOW;
  435. } else {
  436. is_last = (req->req.length <= req->req.actual) ? 1 : 0;
  437. }
  438. udc_write(idx, S3C2410_UDC_INDEX_REG);
  439. fifo_count = s3c2410_udc_fifo_count_out();
  440. /* Only ep0 debug messages are interesting */
  441. if (idx == 0)
  442. dprintk(DEBUG_VERBOSE, "%s fifo count : %d [last %d]\n",
  443. __func__, fifo_count,is_last);
  444. if (is_last) {
  445. if (idx == 0) {
  446. s3c2410_udc_set_ep0_de_out(base_addr);
  447. ep->dev->ep0state = EP0_IDLE;
  448. } else {
  449. udc_write(idx, S3C2410_UDC_INDEX_REG);
  450. ep_csr = udc_read(S3C2410_UDC_OUT_CSR1_REG);
  451. udc_write(idx, S3C2410_UDC_INDEX_REG);
  452. udc_write(ep_csr & ~S3C2410_UDC_OCSR1_PKTRDY,
  453. S3C2410_UDC_OUT_CSR1_REG);
  454. }
  455. s3c2410_udc_done(ep, req, 0);
  456. } else {
  457. if (idx == 0) {
  458. s3c2410_udc_clear_ep0_opr(base_addr);
  459. } else {
  460. udc_write(idx, S3C2410_UDC_INDEX_REG);
  461. ep_csr = udc_read(S3C2410_UDC_OUT_CSR1_REG);
  462. udc_write(idx, S3C2410_UDC_INDEX_REG);
  463. udc_write(ep_csr & ~S3C2410_UDC_OCSR1_PKTRDY,
  464. S3C2410_UDC_OUT_CSR1_REG);
  465. }
  466. }
  467. return is_last;
  468. }
  469. static int s3c2410_udc_read_fifo_crq(struct usb_ctrlrequest *crq)
  470. {
  471. unsigned char *outbuf = (unsigned char*)crq;
  472. int bytes_read = 0;
  473. udc_write(0, S3C2410_UDC_INDEX_REG);
  474. bytes_read = s3c2410_udc_fifo_count_out();
  475. dprintk(DEBUG_NORMAL, "%s: fifo_count=%d\n", __func__, bytes_read);
  476. if (bytes_read > sizeof(struct usb_ctrlrequest))
  477. bytes_read = sizeof(struct usb_ctrlrequest);
  478. readsb(S3C2410_UDC_EP0_FIFO_REG + base_addr, outbuf, bytes_read);
  479. dprintk(DEBUG_VERBOSE, "%s: len=%d %02x:%02x {%x,%x,%x}\n", __func__,
  480. bytes_read, crq->bRequest, crq->bRequestType,
  481. crq->wValue, crq->wIndex, crq->wLength);
  482. return bytes_read;
  483. }
  484. static int s3c2410_udc_get_status(struct s3c2410_udc *dev,
  485. struct usb_ctrlrequest *crq)
  486. {
  487. u16 status = 0;
  488. u8 ep_num = crq->wIndex & 0x7F;
  489. u8 is_in = crq->wIndex & USB_DIR_IN;
  490. switch (crq->bRequestType & USB_RECIP_MASK) {
  491. case USB_RECIP_INTERFACE:
  492. break;
  493. case USB_RECIP_DEVICE:
  494. status = dev->devstatus;
  495. break;
  496. case USB_RECIP_ENDPOINT:
  497. if (ep_num > 4 || crq->wLength > 2)
  498. return 1;
  499. if (ep_num == 0) {
  500. udc_write(0, S3C2410_UDC_INDEX_REG);
  501. status = udc_read(S3C2410_UDC_IN_CSR1_REG);
  502. status = status & S3C2410_UDC_EP0_CSR_SENDSTL;
  503. } else {
  504. udc_write(ep_num, S3C2410_UDC_INDEX_REG);
  505. if (is_in) {
  506. status = udc_read(S3C2410_UDC_IN_CSR1_REG);
  507. status = status & S3C2410_UDC_ICSR1_SENDSTL;
  508. } else {
  509. status = udc_read(S3C2410_UDC_OUT_CSR1_REG);
  510. status = status & S3C2410_UDC_OCSR1_SENDSTL;
  511. }
  512. }
  513. status = status ? 1 : 0;
  514. break;
  515. default:
  516. return 1;
  517. }
  518. /* Seems to be needed to get it working. ouch :( */
  519. udelay(5);
  520. udc_write(status & 0xFF, S3C2410_UDC_EP0_FIFO_REG);
  521. udc_write(status >> 8, S3C2410_UDC_EP0_FIFO_REG);
  522. s3c2410_udc_set_ep0_de_in(base_addr);
  523. return 0;
  524. }
  525. /*------------------------- usb state machine -------------------------------*/
  526. static int s3c2410_udc_set_halt(struct usb_ep *_ep, int value);
  527. static void s3c2410_udc_handle_ep0_idle(struct s3c2410_udc *dev,
  528. struct s3c2410_ep *ep,
  529. struct usb_ctrlrequest *crq,
  530. u32 ep0csr)
  531. {
  532. int len, ret, tmp;
  533. /* start control request? */
  534. if (!(ep0csr & S3C2410_UDC_EP0_CSR_OPKRDY))
  535. return;
  536. s3c2410_udc_nuke(dev, ep, -EPROTO);
  537. len = s3c2410_udc_read_fifo_crq(crq);
  538. if (len != sizeof(*crq)) {
  539. dprintk(DEBUG_NORMAL, "setup begin: fifo READ ERROR"
  540. " wanted %d bytes got %d. Stalling out...\n",
  541. sizeof(*crq), len);
  542. s3c2410_udc_set_ep0_ss(base_addr);
  543. return;
  544. }
  545. dprintk(DEBUG_NORMAL, "bRequest = %d bRequestType %d wLength = %d\n",
  546. crq->bRequest, crq->bRequestType, crq->wLength);
  547. /* cope with automagic for some standard requests. */
  548. dev->req_std = (crq->bRequestType & USB_TYPE_MASK)
  549. == USB_TYPE_STANDARD;
  550. dev->req_config = 0;
  551. dev->req_pending = 1;
  552. switch (crq->bRequest) {
  553. case USB_REQ_SET_CONFIGURATION:
  554. dprintk(DEBUG_NORMAL, "USB_REQ_SET_CONFIGURATION ... \n");
  555. if (crq->bRequestType == USB_RECIP_DEVICE) {
  556. dev->req_config = 1;
  557. s3c2410_udc_set_ep0_de_out(base_addr);
  558. }
  559. break;
  560. case USB_REQ_SET_INTERFACE:
  561. dprintk(DEBUG_NORMAL, "USB_REQ_SET_INTERFACE ... \n");
  562. if (crq->bRequestType == USB_RECIP_INTERFACE) {
  563. dev->req_config = 1;
  564. s3c2410_udc_set_ep0_de_out(base_addr);
  565. }
  566. break;
  567. case USB_REQ_SET_ADDRESS:
  568. dprintk(DEBUG_NORMAL, "USB_REQ_SET_ADDRESS ... \n");
  569. if (crq->bRequestType == USB_RECIP_DEVICE) {
  570. tmp = crq->wValue & 0x7F;
  571. dev->address = tmp;
  572. udc_write((tmp | S3C2410_UDC_FUNCADDR_UPDATE),
  573. S3C2410_UDC_FUNC_ADDR_REG);
  574. s3c2410_udc_set_ep0_de_out(base_addr);
  575. return;
  576. }
  577. break;
  578. case USB_REQ_GET_STATUS:
  579. dprintk(DEBUG_NORMAL, "USB_REQ_GET_STATUS ... \n");
  580. s3c2410_udc_clear_ep0_opr(base_addr);
  581. if (dev->req_std) {
  582. if (!s3c2410_udc_get_status(dev, crq)) {
  583. return;
  584. }
  585. }
  586. break;
  587. case USB_REQ_CLEAR_FEATURE:
  588. s3c2410_udc_clear_ep0_opr(base_addr);
  589. if (crq->bRequestType != USB_RECIP_ENDPOINT)
  590. break;
  591. if (crq->wValue != USB_ENDPOINT_HALT || crq->wLength != 0)
  592. break;
  593. s3c2410_udc_set_halt(&dev->ep[crq->wIndex & 0x7f].ep, 0);
  594. s3c2410_udc_set_ep0_de_out(base_addr);
  595. return;
  596. case USB_REQ_SET_FEATURE:
  597. s3c2410_udc_clear_ep0_opr(base_addr);
  598. if (crq->bRequestType != USB_RECIP_ENDPOINT)
  599. break;
  600. if (crq->wValue != USB_ENDPOINT_HALT || crq->wLength != 0)
  601. break;
  602. s3c2410_udc_set_halt(&dev->ep[crq->wIndex & 0x7f].ep, 1);
  603. s3c2410_udc_set_ep0_de_out(base_addr);
  604. return;
  605. default:
  606. s3c2410_udc_clear_ep0_opr(base_addr);
  607. break;
  608. }
  609. if (crq->bRequestType & USB_DIR_IN)
  610. dev->ep0state = EP0_IN_DATA_PHASE;
  611. else
  612. dev->ep0state = EP0_OUT_DATA_PHASE;
  613. if (!dev->driver)
  614. return;
  615. /* deliver the request to the gadget driver */
  616. ret = dev->driver->setup(&dev->gadget, crq);
  617. if (ret < 0) {
  618. if (dev->req_config) {
  619. dprintk(DEBUG_NORMAL, "config change %02x fail %d?\n",
  620. crq->bRequest, ret);
  621. return;
  622. }
  623. if (ret == -EOPNOTSUPP)
  624. dprintk(DEBUG_NORMAL, "Operation not supported\n");
  625. else
  626. dprintk(DEBUG_NORMAL,
  627. "dev->driver->setup failed. (%d)\n", ret);
  628. udelay(5);
  629. s3c2410_udc_set_ep0_ss(base_addr);
  630. s3c2410_udc_set_ep0_de_out(base_addr);
  631. dev->ep0state = EP0_IDLE;
  632. /* deferred i/o == no response yet */
  633. } else if (dev->req_pending) {
  634. dprintk(DEBUG_VERBOSE, "dev->req_pending... what now?\n");
  635. dev->req_pending=0;
  636. }
  637. dprintk(DEBUG_VERBOSE, "ep0state %s\n", ep0states[dev->ep0state]);
  638. }
  639. static void s3c2410_udc_handle_ep0(struct s3c2410_udc *dev)
  640. {
  641. u32 ep0csr;
  642. struct s3c2410_ep *ep = &dev->ep[0];
  643. struct s3c2410_request *req;
  644. struct usb_ctrlrequest crq;
  645. if (list_empty(&ep->queue))
  646. req = NULL;
  647. else
  648. req = list_entry(ep->queue.next, struct s3c2410_request, queue);
  649. /* We make the assumption that S3C2410_UDC_IN_CSR1_REG equal to
  650. * S3C2410_UDC_EP0_CSR_REG when index is zero */
  651. udc_write(0, S3C2410_UDC_INDEX_REG);
  652. ep0csr = udc_read(S3C2410_UDC_IN_CSR1_REG);
  653. dprintk(DEBUG_NORMAL, "ep0csr %x ep0state %s\n",
  654. ep0csr, ep0states[dev->ep0state]);
  655. /* clear stall status */
  656. if (ep0csr & S3C2410_UDC_EP0_CSR_SENTSTL) {
  657. s3c2410_udc_nuke(dev, ep, -EPIPE);
  658. dprintk(DEBUG_NORMAL, "... clear SENT_STALL ...\n");
  659. s3c2410_udc_clear_ep0_sst(base_addr);
  660. dev->ep0state = EP0_IDLE;
  661. return;
  662. }
  663. /* clear setup end */
  664. if (ep0csr & S3C2410_UDC_EP0_CSR_SE) {
  665. dprintk(DEBUG_NORMAL, "... serviced SETUP_END ...\n");
  666. s3c2410_udc_nuke(dev, ep, 0);
  667. s3c2410_udc_clear_ep0_se(base_addr);
  668. dev->ep0state = EP0_IDLE;
  669. }
  670. switch (dev->ep0state) {
  671. case EP0_IDLE:
  672. s3c2410_udc_handle_ep0_idle(dev, ep, &crq, ep0csr);
  673. break;
  674. case EP0_IN_DATA_PHASE: /* GET_DESCRIPTOR etc */
  675. dprintk(DEBUG_NORMAL, "EP0_IN_DATA_PHASE ... what now?\n");
  676. if (!(ep0csr & S3C2410_UDC_EP0_CSR_IPKRDY) && req) {
  677. s3c2410_udc_write_fifo(ep, req);
  678. }
  679. break;
  680. case EP0_OUT_DATA_PHASE: /* SET_DESCRIPTOR etc */
  681. dprintk(DEBUG_NORMAL, "EP0_OUT_DATA_PHASE ... what now?\n");
  682. if ((ep0csr & S3C2410_UDC_EP0_CSR_OPKRDY) && req ) {
  683. s3c2410_udc_read_fifo(ep,req);
  684. }
  685. break;
  686. case EP0_END_XFER:
  687. dprintk(DEBUG_NORMAL, "EP0_END_XFER ... what now?\n");
  688. dev->ep0state = EP0_IDLE;
  689. break;
  690. case EP0_STALL:
  691. dprintk(DEBUG_NORMAL, "EP0_STALL ... what now?\n");
  692. dev->ep0state = EP0_IDLE;
  693. break;
  694. }
  695. }
  696. /*
  697. * handle_ep - Manage I/O endpoints
  698. */
  699. static void s3c2410_udc_handle_ep(struct s3c2410_ep *ep)
  700. {
  701. struct s3c2410_request *req;
  702. int is_in = ep->bEndpointAddress & USB_DIR_IN;
  703. u32 ep_csr1;
  704. u32 idx;
  705. if (likely (!list_empty(&ep->queue)))
  706. req = list_entry(ep->queue.next,
  707. struct s3c2410_request, queue);
  708. else
  709. req = NULL;
  710. idx = ep->bEndpointAddress & 0x7F;
  711. if (is_in) {
  712. udc_write(idx, S3C2410_UDC_INDEX_REG);
  713. ep_csr1 = udc_read(S3C2410_UDC_IN_CSR1_REG);
  714. dprintk(DEBUG_VERBOSE, "ep%01d write csr:%02x %d\n",
  715. idx, ep_csr1, req ? 1 : 0);
  716. if (ep_csr1 & S3C2410_UDC_ICSR1_SENTSTL) {
  717. dprintk(DEBUG_VERBOSE, "st\n");
  718. udc_write(idx, S3C2410_UDC_INDEX_REG);
  719. udc_write(ep_csr1 & ~S3C2410_UDC_ICSR1_SENTSTL,
  720. S3C2410_UDC_IN_CSR1_REG);
  721. return;
  722. }
  723. if (!(ep_csr1 & S3C2410_UDC_ICSR1_PKTRDY) && req) {
  724. s3c2410_udc_write_fifo(ep,req);
  725. }
  726. } else {
  727. udc_write(idx, S3C2410_UDC_INDEX_REG);
  728. ep_csr1 = udc_read(S3C2410_UDC_OUT_CSR1_REG);
  729. dprintk(DEBUG_VERBOSE, "ep%01d rd csr:%02x\n", idx, ep_csr1);
  730. if (ep_csr1 & S3C2410_UDC_OCSR1_SENTSTL) {
  731. udc_write(idx, S3C2410_UDC_INDEX_REG);
  732. udc_write(ep_csr1 & ~S3C2410_UDC_OCSR1_SENTSTL,
  733. S3C2410_UDC_OUT_CSR1_REG);
  734. return;
  735. }
  736. if ((ep_csr1 & S3C2410_UDC_OCSR1_PKTRDY) && req) {
  737. s3c2410_udc_read_fifo(ep,req);
  738. }
  739. }
  740. }
  741. #include <mach/regs-irq.h>
  742. /*
  743. * s3c2410_udc_irq - interrupt handler
  744. */
  745. static irqreturn_t s3c2410_udc_irq(int dummy, void *_dev)
  746. {
  747. struct s3c2410_udc *dev = _dev;
  748. int usb_status;
  749. int usbd_status;
  750. int pwr_reg;
  751. int ep0csr;
  752. int i;
  753. u32 idx, idx2;
  754. unsigned long flags;
  755. spin_lock_irqsave(&dev->lock, flags);
  756. /* Driver connected ? */
  757. if (!dev->driver) {
  758. /* Clear interrupts */
  759. udc_write(udc_read(S3C2410_UDC_USB_INT_REG),
  760. S3C2410_UDC_USB_INT_REG);
  761. udc_write(udc_read(S3C2410_UDC_EP_INT_REG),
  762. S3C2410_UDC_EP_INT_REG);
  763. }
  764. /* Save index */
  765. idx = udc_read(S3C2410_UDC_INDEX_REG);
  766. /* Read status registers */
  767. usb_status = udc_read(S3C2410_UDC_USB_INT_REG);
  768. usbd_status = udc_read(S3C2410_UDC_EP_INT_REG);
  769. pwr_reg = udc_read(S3C2410_UDC_PWR_REG);
  770. udc_writeb(base_addr, S3C2410_UDC_INDEX_EP0, S3C2410_UDC_INDEX_REG);
  771. ep0csr = udc_read(S3C2410_UDC_IN_CSR1_REG);
  772. dprintk(DEBUG_NORMAL, "usbs=%02x, usbds=%02x, pwr=%02x ep0csr=%02x\n",
  773. usb_status, usbd_status, pwr_reg, ep0csr);
  774. /*
  775. * Now, handle interrupts. There's two types :
  776. * - Reset, Resume, Suspend coming -> usb_int_reg
  777. * - EP -> ep_int_reg
  778. */
  779. /* RESET */
  780. if (usb_status & S3C2410_UDC_USBINT_RESET) {
  781. /* two kind of reset :
  782. * - reset start -> pwr reg = 8
  783. * - reset end -> pwr reg = 0
  784. **/
  785. dprintk(DEBUG_NORMAL, "USB reset csr %x pwr %x\n",
  786. ep0csr, pwr_reg);
  787. dev->gadget.speed = USB_SPEED_UNKNOWN;
  788. udc_write(0x00, S3C2410_UDC_INDEX_REG);
  789. udc_write((dev->ep[0].ep.maxpacket & 0x7ff) >> 3,
  790. S3C2410_UDC_MAXP_REG);
  791. dev->address = 0;
  792. dev->ep0state = EP0_IDLE;
  793. dev->gadget.speed = USB_SPEED_FULL;
  794. /* clear interrupt */
  795. udc_write(S3C2410_UDC_USBINT_RESET,
  796. S3C2410_UDC_USB_INT_REG);
  797. udc_write(idx, S3C2410_UDC_INDEX_REG);
  798. spin_unlock_irqrestore(&dev->lock, flags);
  799. return IRQ_HANDLED;
  800. }
  801. /* RESUME */
  802. if (usb_status & S3C2410_UDC_USBINT_RESUME) {
  803. dprintk(DEBUG_NORMAL, "USB resume\n");
  804. /* clear interrupt */
  805. udc_write(S3C2410_UDC_USBINT_RESUME,
  806. S3C2410_UDC_USB_INT_REG);
  807. if (dev->gadget.speed != USB_SPEED_UNKNOWN
  808. && dev->driver
  809. && dev->driver->resume)
  810. dev->driver->resume(&dev->gadget);
  811. }
  812. /* SUSPEND */
  813. if (usb_status & S3C2410_UDC_USBINT_SUSPEND) {
  814. dprintk(DEBUG_NORMAL, "USB suspend\n");
  815. /* clear interrupt */
  816. udc_write(S3C2410_UDC_USBINT_SUSPEND,
  817. S3C2410_UDC_USB_INT_REG);
  818. if (dev->gadget.speed != USB_SPEED_UNKNOWN
  819. && dev->driver
  820. && dev->driver->suspend)
  821. dev->driver->suspend(&dev->gadget);
  822. dev->ep0state = EP0_IDLE;
  823. }
  824. /* EP */
  825. /* control traffic */
  826. /* check on ep0csr != 0 is not a good idea as clearing in_pkt_ready
  827. * generate an interrupt
  828. */
  829. if (usbd_status & S3C2410_UDC_INT_EP0) {
  830. dprintk(DEBUG_VERBOSE, "USB ep0 irq\n");
  831. /* Clear the interrupt bit by setting it to 1 */
  832. udc_write(S3C2410_UDC_INT_EP0, S3C2410_UDC_EP_INT_REG);
  833. s3c2410_udc_handle_ep0(dev);
  834. }
  835. /* endpoint data transfers */
  836. for (i = 1; i < S3C2410_ENDPOINTS; i++) {
  837. u32 tmp = 1 << i;
  838. if (usbd_status & tmp) {
  839. dprintk(DEBUG_VERBOSE, "USB ep%d irq\n", i);
  840. /* Clear the interrupt bit by setting it to 1 */
  841. udc_write(tmp, S3C2410_UDC_EP_INT_REG);
  842. s3c2410_udc_handle_ep(&dev->ep[i]);
  843. }
  844. }
  845. /* what else causes this interrupt? a receive! who is it? */
  846. if (!usb_status && !usbd_status && !pwr_reg && !ep0csr) {
  847. for (i = 1; i < S3C2410_ENDPOINTS; i++) {
  848. idx2 = udc_read(S3C2410_UDC_INDEX_REG);
  849. udc_write(i, S3C2410_UDC_INDEX_REG);
  850. if (udc_read(S3C2410_UDC_OUT_CSR1_REG) & 0x1)
  851. s3c2410_udc_handle_ep(&dev->ep[i]);
  852. /* restore index */
  853. udc_write(idx2, S3C2410_UDC_INDEX_REG);
  854. }
  855. }
  856. dprintk(DEBUG_VERBOSE, "irq: %d s3c2410_udc_done.\n", IRQ_USBD);
  857. /* Restore old index */
  858. udc_write(idx, S3C2410_UDC_INDEX_REG);
  859. spin_unlock_irqrestore(&dev->lock, flags);
  860. return IRQ_HANDLED;
  861. }
  862. /*------------------------- s3c2410_ep_ops ----------------------------------*/
  863. static inline struct s3c2410_ep *to_s3c2410_ep(struct usb_ep *ep)
  864. {
  865. return container_of(ep, struct s3c2410_ep, ep);
  866. }
  867. static inline struct s3c2410_udc *to_s3c2410_udc(struct usb_gadget *gadget)
  868. {
  869. return container_of(gadget, struct s3c2410_udc, gadget);
  870. }
  871. static inline struct s3c2410_request *to_s3c2410_req(struct usb_request *req)
  872. {
  873. return container_of(req, struct s3c2410_request, req);
  874. }
  875. /*
  876. * s3c2410_udc_ep_enable
  877. */
  878. static int s3c2410_udc_ep_enable(struct usb_ep *_ep,
  879. const struct usb_endpoint_descriptor *desc)
  880. {
  881. struct s3c2410_udc *dev;
  882. struct s3c2410_ep *ep;
  883. u32 max, tmp;
  884. unsigned long flags;
  885. u32 csr1,csr2;
  886. u32 int_en_reg;
  887. ep = to_s3c2410_ep(_ep);
  888. if (!_ep || !desc || ep->desc
  889. || _ep->name == ep0name
  890. || desc->bDescriptorType != USB_DT_ENDPOINT)
  891. return -EINVAL;
  892. dev = ep->dev;
  893. if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN)
  894. return -ESHUTDOWN;
  895. max = le16_to_cpu(desc->wMaxPacketSize) & 0x1fff;
  896. local_irq_save (flags);
  897. _ep->maxpacket = max & 0x7ff;
  898. ep->desc = desc;
  899. ep->halted = 0;
  900. ep->bEndpointAddress = desc->bEndpointAddress;
  901. /* set max packet */
  902. udc_write(ep->num, S3C2410_UDC_INDEX_REG);
  903. udc_write(max >> 3, S3C2410_UDC_MAXP_REG);
  904. /* set type, direction, address; reset fifo counters */
  905. if (desc->bEndpointAddress & USB_DIR_IN) {
  906. csr1 = S3C2410_UDC_ICSR1_FFLUSH|S3C2410_UDC_ICSR1_CLRDT;
  907. csr2 = S3C2410_UDC_ICSR2_MODEIN|S3C2410_UDC_ICSR2_DMAIEN;
  908. udc_write(ep->num, S3C2410_UDC_INDEX_REG);
  909. udc_write(csr1, S3C2410_UDC_IN_CSR1_REG);
  910. udc_write(ep->num, S3C2410_UDC_INDEX_REG);
  911. udc_write(csr2, S3C2410_UDC_IN_CSR2_REG);
  912. } else {
  913. /* don't flush in fifo or it will cause endpoint interrupt */
  914. csr1 = S3C2410_UDC_ICSR1_CLRDT;
  915. csr2 = S3C2410_UDC_ICSR2_DMAIEN;
  916. udc_write(ep->num, S3C2410_UDC_INDEX_REG);
  917. udc_write(csr1, S3C2410_UDC_IN_CSR1_REG);
  918. udc_write(ep->num, S3C2410_UDC_INDEX_REG);
  919. udc_write(csr2, S3C2410_UDC_IN_CSR2_REG);
  920. csr1 = S3C2410_UDC_OCSR1_FFLUSH | S3C2410_UDC_OCSR1_CLRDT;
  921. csr2 = S3C2410_UDC_OCSR2_DMAIEN;
  922. udc_write(ep->num, S3C2410_UDC_INDEX_REG);
  923. udc_write(csr1, S3C2410_UDC_OUT_CSR1_REG);
  924. udc_write(ep->num, S3C2410_UDC_INDEX_REG);
  925. udc_write(csr2, S3C2410_UDC_OUT_CSR2_REG);
  926. }
  927. /* enable irqs */
  928. int_en_reg = udc_read(S3C2410_UDC_EP_INT_EN_REG);
  929. udc_write(int_en_reg | (1 << ep->num), S3C2410_UDC_EP_INT_EN_REG);
  930. /* print some debug message */
  931. tmp = desc->bEndpointAddress;
  932. dprintk (DEBUG_NORMAL, "enable %s(%d) ep%x%s-blk max %02x\n",
  933. _ep->name,ep->num, tmp,
  934. desc->bEndpointAddress & USB_DIR_IN ? "in" : "out", max);
  935. local_irq_restore (flags);
  936. s3c2410_udc_set_halt(_ep, 0);
  937. return 0;
  938. }
  939. /*
  940. * s3c2410_udc_ep_disable
  941. */
  942. static int s3c2410_udc_ep_disable(struct usb_ep *_ep)
  943. {
  944. struct s3c2410_ep *ep = to_s3c2410_ep(_ep);
  945. unsigned long flags;
  946. u32 int_en_reg;
  947. if (!_ep || !ep->desc) {
  948. dprintk(DEBUG_NORMAL, "%s not enabled\n",
  949. _ep ? ep->ep.name : NULL);
  950. return -EINVAL;
  951. }
  952. local_irq_save(flags);
  953. dprintk(DEBUG_NORMAL, "ep_disable: %s\n", _ep->name);
  954. ep->desc = NULL;
  955. ep->halted = 1;
  956. s3c2410_udc_nuke (ep->dev, ep, -ESHUTDOWN);
  957. /* disable irqs */
  958. int_en_reg = udc_read(S3C2410_UDC_EP_INT_EN_REG);
  959. udc_write(int_en_reg & ~(1<<ep->num), S3C2410_UDC_EP_INT_EN_REG);
  960. local_irq_restore(flags);
  961. dprintk(DEBUG_NORMAL, "%s disabled\n", _ep->name);
  962. return 0;
  963. }
  964. /*
  965. * s3c2410_udc_alloc_request
  966. */
  967. static struct usb_request *
  968. s3c2410_udc_alloc_request(struct usb_ep *_ep, gfp_t mem_flags)
  969. {
  970. struct s3c2410_request *req;
  971. dprintk(DEBUG_VERBOSE,"%s(%p,%d)\n", __func__, _ep, mem_flags);
  972. if (!_ep)
  973. return NULL;
  974. req = kzalloc (sizeof(struct s3c2410_request), mem_flags);
  975. if (!req)
  976. return NULL;
  977. INIT_LIST_HEAD (&req->queue);
  978. return &req->req;
  979. }
  980. /*
  981. * s3c2410_udc_free_request
  982. */
  983. static void
  984. s3c2410_udc_free_request(struct usb_ep *_ep, struct usb_request *_req)
  985. {
  986. struct s3c2410_ep *ep = to_s3c2410_ep(_ep);
  987. struct s3c2410_request *req = to_s3c2410_req(_req);
  988. dprintk(DEBUG_VERBOSE, "%s(%p,%p)\n", __func__, _ep, _req);
  989. if (!ep || !_req || (!ep->desc && _ep->name != ep0name))
  990. return;
  991. WARN_ON (!list_empty (&req->queue));
  992. kfree(req);
  993. }
  994. /*
  995. * s3c2410_udc_queue
  996. */
  997. static int s3c2410_udc_queue(struct usb_ep *_ep, struct usb_request *_req,
  998. gfp_t gfp_flags)
  999. {
  1000. struct s3c2410_request *req = to_s3c2410_req(_req);
  1001. struct s3c2410_ep *ep = to_s3c2410_ep(_ep);
  1002. struct s3c2410_udc *dev;
  1003. u32 ep_csr = 0;
  1004. int fifo_count = 0;
  1005. unsigned long flags;
  1006. if (unlikely (!_ep || (!ep->desc && ep->ep.name != ep0name))) {
  1007. dprintk(DEBUG_NORMAL, "%s: invalid args\n", __func__);
  1008. return -EINVAL;
  1009. }
  1010. dev = ep->dev;
  1011. if (unlikely (!dev->driver
  1012. || dev->gadget.speed == USB_SPEED_UNKNOWN)) {
  1013. return -ESHUTDOWN;
  1014. }
  1015. local_irq_save (flags);
  1016. if (unlikely(!_req || !_req->complete
  1017. || !_req->buf || !list_empty(&req->queue))) {
  1018. if (!_req)
  1019. dprintk(DEBUG_NORMAL, "%s: 1 X X X\n", __func__);
  1020. else {
  1021. dprintk(DEBUG_NORMAL, "%s: 0 %01d %01d %01d\n",
  1022. __func__, !_req->complete,!_req->buf,
  1023. !list_empty(&req->queue));
  1024. }
  1025. local_irq_restore(flags);
  1026. return -EINVAL;
  1027. }
  1028. _req->status = -EINPROGRESS;
  1029. _req->actual = 0;
  1030. dprintk(DEBUG_VERBOSE, "%s: ep%x len %d\n",
  1031. __func__, ep->bEndpointAddress, _req->length);
  1032. if (ep->bEndpointAddress) {
  1033. udc_write(ep->bEndpointAddress & 0x7F, S3C2410_UDC_INDEX_REG);
  1034. ep_csr = udc_read((ep->bEndpointAddress & USB_DIR_IN)
  1035. ? S3C2410_UDC_IN_CSR1_REG
  1036. : S3C2410_UDC_OUT_CSR1_REG);
  1037. fifo_count = s3c2410_udc_fifo_count_out();
  1038. } else {
  1039. udc_write(0, S3C2410_UDC_INDEX_REG);
  1040. ep_csr = udc_read(S3C2410_UDC_IN_CSR1_REG);
  1041. fifo_count = s3c2410_udc_fifo_count_out();
  1042. }
  1043. /* kickstart this i/o queue? */
  1044. if (list_empty(&ep->queue) && !ep->halted) {
  1045. if (ep->bEndpointAddress == 0 /* ep0 */) {
  1046. switch (dev->ep0state) {
  1047. case EP0_IN_DATA_PHASE:
  1048. if (!(ep_csr&S3C2410_UDC_EP0_CSR_IPKRDY)
  1049. && s3c2410_udc_write_fifo(ep,
  1050. req)) {
  1051. dev->ep0state = EP0_IDLE;
  1052. req = NULL;
  1053. }
  1054. break;
  1055. case EP0_OUT_DATA_PHASE:
  1056. if ((!_req->length)
  1057. || ((ep_csr & S3C2410_UDC_OCSR1_PKTRDY)
  1058. && s3c2410_udc_read_fifo(ep,
  1059. req))) {
  1060. dev->ep0state = EP0_IDLE;
  1061. req = NULL;
  1062. }
  1063. break;
  1064. default:
  1065. local_irq_restore(flags);
  1066. return -EL2HLT;
  1067. }
  1068. } else if ((ep->bEndpointAddress & USB_DIR_IN) != 0
  1069. && (!(ep_csr&S3C2410_UDC_OCSR1_PKTRDY))
  1070. && s3c2410_udc_write_fifo(ep, req)) {
  1071. req = NULL;
  1072. } else if ((ep_csr & S3C2410_UDC_OCSR1_PKTRDY)
  1073. && fifo_count
  1074. && s3c2410_udc_read_fifo(ep, req)) {
  1075. req = NULL;
  1076. }
  1077. }
  1078. /* pio or dma irq handler advances the queue. */
  1079. if (likely (req != 0))
  1080. list_add_tail(&req->queue, &ep->queue);
  1081. local_irq_restore(flags);
  1082. dprintk(DEBUG_VERBOSE, "%s ok\n", __func__);
  1083. return 0;
  1084. }
  1085. /*
  1086. * s3c2410_udc_dequeue
  1087. */
  1088. static int s3c2410_udc_dequeue(struct usb_ep *_ep, struct usb_request *_req)
  1089. {
  1090. struct s3c2410_ep *ep = to_s3c2410_ep(_ep);
  1091. struct s3c2410_udc *udc;
  1092. int retval = -EINVAL;
  1093. unsigned long flags;
  1094. struct s3c2410_request *req = NULL;
  1095. dprintk(DEBUG_VERBOSE, "%s(%p,%p)\n", __func__, _ep, _req);
  1096. if (!the_controller->driver)
  1097. return -ESHUTDOWN;
  1098. if (!_ep || !_req)
  1099. return retval;
  1100. udc = to_s3c2410_udc(ep->gadget);
  1101. local_irq_save (flags);
  1102. list_for_each_entry (req, &ep->queue, queue) {
  1103. if (&req->req == _req) {
  1104. list_del_init (&req->queue);
  1105. _req->status = -ECONNRESET;
  1106. retval = 0;
  1107. break;
  1108. }
  1109. }
  1110. if (retval == 0) {
  1111. dprintk(DEBUG_VERBOSE,
  1112. "dequeued req %p from %s, len %d buf %p\n",
  1113. req, _ep->name, _req->length, _req->buf);
  1114. s3c2410_udc_done(ep, req, -ECONNRESET);
  1115. }
  1116. local_irq_restore (flags);
  1117. return retval;
  1118. }
  1119. /*
  1120. * s3c2410_udc_set_halt
  1121. */
  1122. static int s3c2410_udc_set_halt(struct usb_ep *_ep, int value)
  1123. {
  1124. struct s3c2410_ep *ep = to_s3c2410_ep(_ep);
  1125. u32 ep_csr = 0;
  1126. unsigned long flags;
  1127. u32 idx;
  1128. if (unlikely (!_ep || (!ep->desc && ep->ep.name != ep0name))) {
  1129. dprintk(DEBUG_NORMAL, "%s: inval 2\n", __func__);
  1130. return -EINVAL;
  1131. }
  1132. local_irq_save (flags);
  1133. idx = ep->bEndpointAddress & 0x7F;
  1134. if (idx == 0) {
  1135. s3c2410_udc_set_ep0_ss(base_addr);
  1136. s3c2410_udc_set_ep0_de_out(base_addr);
  1137. } else {
  1138. udc_write(idx, S3C2410_UDC_INDEX_REG);
  1139. ep_csr = udc_read((ep->bEndpointAddress &USB_DIR_IN)
  1140. ? S3C2410_UDC_IN_CSR1_REG
  1141. : S3C2410_UDC_OUT_CSR1_REG);
  1142. if ((ep->bEndpointAddress & USB_DIR_IN) != 0) {
  1143. if (value)
  1144. udc_write(ep_csr | S3C2410_UDC_ICSR1_SENDSTL,
  1145. S3C2410_UDC_IN_CSR1_REG);
  1146. else {
  1147. ep_csr &= ~S3C2410_UDC_ICSR1_SENDSTL;
  1148. udc_write(ep_csr, S3C2410_UDC_IN_CSR1_REG);
  1149. ep_csr |= S3C2410_UDC_ICSR1_CLRDT;
  1150. udc_write(ep_csr, S3C2410_UDC_IN_CSR1_REG);
  1151. }
  1152. } else {
  1153. if (value)
  1154. udc_write(ep_csr | S3C2410_UDC_OCSR1_SENDSTL,
  1155. S3C2410_UDC_OUT_CSR1_REG);
  1156. else {
  1157. ep_csr &= ~S3C2410_UDC_OCSR1_SENDSTL;
  1158. udc_write(ep_csr, S3C2410_UDC_OUT_CSR1_REG);
  1159. ep_csr |= S3C2410_UDC_OCSR1_CLRDT;
  1160. udc_write(ep_csr, S3C2410_UDC_OUT_CSR1_REG);
  1161. }
  1162. }
  1163. }
  1164. ep->halted = value ? 1 : 0;
  1165. local_irq_restore (flags);
  1166. return 0;
  1167. }
  1168. static const struct usb_ep_ops s3c2410_ep_ops = {
  1169. .enable = s3c2410_udc_ep_enable,
  1170. .disable = s3c2410_udc_ep_disable,
  1171. .alloc_request = s3c2410_udc_alloc_request,
  1172. .free_request = s3c2410_udc_free_request,
  1173. .queue = s3c2410_udc_queue,
  1174. .dequeue = s3c2410_udc_dequeue,
  1175. .set_halt = s3c2410_udc_set_halt,
  1176. };
  1177. /*------------------------- usb_gadget_ops ----------------------------------*/
  1178. /*
  1179. * s3c2410_udc_get_frame
  1180. */
  1181. static int s3c2410_udc_get_frame(struct usb_gadget *_gadget)
  1182. {
  1183. int tmp;
  1184. dprintk(DEBUG_VERBOSE, "%s()\n", __func__);
  1185. tmp = udc_read(S3C2410_UDC_FRAME_NUM2_REG) << 8;
  1186. tmp |= udc_read(S3C2410_UDC_FRAME_NUM1_REG);
  1187. return tmp;
  1188. }
  1189. /*
  1190. * s3c2410_udc_wakeup
  1191. */
  1192. static int s3c2410_udc_wakeup(struct usb_gadget *_gadget)
  1193. {
  1194. dprintk(DEBUG_NORMAL, "%s()\n", __func__);
  1195. return 0;
  1196. }
  1197. /*
  1198. * s3c2410_udc_set_selfpowered
  1199. */
  1200. static int s3c2410_udc_set_selfpowered(struct usb_gadget *gadget, int value)
  1201. {
  1202. struct s3c2410_udc *udc = to_s3c2410_udc(gadget);
  1203. dprintk(DEBUG_NORMAL, "%s()\n", __func__);
  1204. if (value)
  1205. udc->devstatus |= (1 << USB_DEVICE_SELF_POWERED);
  1206. else
  1207. udc->devstatus &= ~(1 << USB_DEVICE_SELF_POWERED);
  1208. return 0;
  1209. }
  1210. static void s3c2410_udc_disable(struct s3c2410_udc *dev);
  1211. static void s3c2410_udc_enable(struct s3c2410_udc *dev);
  1212. static int s3c2410_udc_set_pullup(struct s3c2410_udc *udc, int is_on)
  1213. {
  1214. dprintk(DEBUG_NORMAL, "%s()\n", __func__);
  1215. if (udc_info && (udc_info->udc_command ||
  1216. gpio_is_valid(udc_info->pullup_pin))) {
  1217. if (is_on)
  1218. s3c2410_udc_enable(udc);
  1219. else {
  1220. if (udc->gadget.speed != USB_SPEED_UNKNOWN) {
  1221. if (udc->driver && udc->driver->disconnect)
  1222. udc->driver->disconnect(&udc->gadget);
  1223. }
  1224. s3c2410_udc_disable(udc);
  1225. }
  1226. }
  1227. else
  1228. return -EOPNOTSUPP;
  1229. return 0;
  1230. }
  1231. static int s3c2410_udc_vbus_session(struct usb_gadget *gadget, int is_active)
  1232. {
  1233. struct s3c2410_udc *udc = to_s3c2410_udc(gadget);
  1234. dprintk(DEBUG_NORMAL, "%s()\n", __func__);
  1235. udc->vbus = (is_active != 0);
  1236. s3c2410_udc_set_pullup(udc, is_active);
  1237. return 0;
  1238. }
  1239. static int s3c2410_udc_pullup(struct usb_gadget *gadget, int is_on)
  1240. {
  1241. struct s3c2410_udc *udc = to_s3c2410_udc(gadget);
  1242. dprintk(DEBUG_NORMAL, "%s()\n", __func__);
  1243. s3c2410_udc_set_pullup(udc, is_on ? 0 : 1);
  1244. return 0;
  1245. }
  1246. static irqreturn_t s3c2410_udc_vbus_irq(int irq, void *_dev)
  1247. {
  1248. struct s3c2410_udc *dev = _dev;
  1249. unsigned int value;
  1250. dprintk(DEBUG_NORMAL, "%s()\n", __func__);
  1251. value = gpio_get_value(udc_info->vbus_pin) ? 1 : 0;
  1252. if (udc_info->vbus_pin_inverted)
  1253. value = !value;
  1254. if (value != dev->vbus)
  1255. s3c2410_udc_vbus_session(&dev->gadget, value);
  1256. return IRQ_HANDLED;
  1257. }
  1258. static int s3c2410_vbus_draw(struct usb_gadget *_gadget, unsigned ma)
  1259. {
  1260. dprintk(DEBUG_NORMAL, "%s()\n", __func__);
  1261. if (udc_info && udc_info->vbus_draw) {
  1262. udc_info->vbus_draw(ma);
  1263. return 0;
  1264. }
  1265. return -ENOTSUPP;
  1266. }
  1267. static int s3c2410_udc_start(struct usb_gadget_driver *driver,
  1268. int (*bind)(struct usb_gadget *));
  1269. static int s3c2410_udc_stop(struct usb_gadget_driver *driver);
  1270. static const struct usb_gadget_ops s3c2410_ops = {
  1271. .get_frame = s3c2410_udc_get_frame,
  1272. .wakeup = s3c2410_udc_wakeup,
  1273. .set_selfpowered = s3c2410_udc_set_selfpowered,
  1274. .pullup = s3c2410_udc_pullup,
  1275. .vbus_session = s3c2410_udc_vbus_session,
  1276. .vbus_draw = s3c2410_vbus_draw,
  1277. .start = s3c2410_udc_start,
  1278. .stop = s3c2410_udc_stop,
  1279. };
  1280. static void s3c2410_udc_command(enum s3c2410_udc_cmd_e cmd)
  1281. {
  1282. if (!udc_info)
  1283. return;
  1284. if (udc_info->udc_command) {
  1285. udc_info->udc_command(cmd);
  1286. } else if (gpio_is_valid(udc_info->pullup_pin)) {
  1287. int value;
  1288. switch (cmd) {
  1289. case S3C2410_UDC_P_ENABLE:
  1290. value = 1;
  1291. break;
  1292. case S3C2410_UDC_P_DISABLE:
  1293. value = 0;
  1294. break;
  1295. default:
  1296. return;
  1297. }
  1298. value ^= udc_info->pullup_pin_inverted;
  1299. gpio_set_value(udc_info->pullup_pin, value);
  1300. }
  1301. }
  1302. /*------------------------- gadget driver handling---------------------------*/
  1303. /*
  1304. * s3c2410_udc_disable
  1305. */
  1306. static void s3c2410_udc_disable(struct s3c2410_udc *dev)
  1307. {
  1308. dprintk(DEBUG_NORMAL, "%s()\n", __func__);
  1309. /* Disable all interrupts */
  1310. udc_write(0x00, S3C2410_UDC_USB_INT_EN_REG);
  1311. udc_write(0x00, S3C2410_UDC_EP_INT_EN_REG);
  1312. /* Clear the interrupt registers */
  1313. udc_write(S3C2410_UDC_USBINT_RESET
  1314. | S3C2410_UDC_USBINT_RESUME
  1315. | S3C2410_UDC_USBINT_SUSPEND,
  1316. S3C2410_UDC_USB_INT_REG);
  1317. udc_write(0x1F, S3C2410_UDC_EP_INT_REG);
  1318. /* Good bye, cruel world */
  1319. s3c2410_udc_command(S3C2410_UDC_P_DISABLE);
  1320. /* Set speed to unknown */
  1321. dev->gadget.speed = USB_SPEED_UNKNOWN;
  1322. }
  1323. /*
  1324. * s3c2410_udc_reinit
  1325. */
  1326. static void s3c2410_udc_reinit(struct s3c2410_udc *dev)
  1327. {
  1328. u32 i;
  1329. /* device/ep0 records init */
  1330. INIT_LIST_HEAD (&dev->gadget.ep_list);
  1331. INIT_LIST_HEAD (&dev->gadget.ep0->ep_list);
  1332. dev->ep0state = EP0_IDLE;
  1333. for (i = 0; i < S3C2410_ENDPOINTS; i++) {
  1334. struct s3c2410_ep *ep = &dev->ep[i];
  1335. if (i != 0)
  1336. list_add_tail (&ep->ep.ep_list, &dev->gadget.ep_list);
  1337. ep->dev = dev;
  1338. ep->desc = NULL;
  1339. ep->halted = 0;
  1340. INIT_LIST_HEAD (&ep->queue);
  1341. }
  1342. }
  1343. /*
  1344. * s3c2410_udc_enable
  1345. */
  1346. static void s3c2410_udc_enable(struct s3c2410_udc *dev)
  1347. {
  1348. int i;
  1349. dprintk(DEBUG_NORMAL, "s3c2410_udc_enable called\n");
  1350. /* dev->gadget.speed = USB_SPEED_UNKNOWN; */
  1351. dev->gadget.speed = USB_SPEED_FULL;
  1352. /* Set MAXP for all endpoints */
  1353. for (i = 0; i < S3C2410_ENDPOINTS; i++) {
  1354. udc_write(i, S3C2410_UDC_INDEX_REG);
  1355. udc_write((dev->ep[i].ep.maxpacket & 0x7ff) >> 3,
  1356. S3C2410_UDC_MAXP_REG);
  1357. }
  1358. /* Set default power state */
  1359. udc_write(DEFAULT_POWER_STATE, S3C2410_UDC_PWR_REG);
  1360. /* Enable reset and suspend interrupt interrupts */
  1361. udc_write(S3C2410_UDC_USBINT_RESET | S3C2410_UDC_USBINT_SUSPEND,
  1362. S3C2410_UDC_USB_INT_EN_REG);
  1363. /* Enable ep0 interrupt */
  1364. udc_write(S3C2410_UDC_INT_EP0, S3C2410_UDC_EP_INT_EN_REG);
  1365. /* time to say "hello, world" */
  1366. s3c2410_udc_command(S3C2410_UDC_P_ENABLE);
  1367. }
  1368. static int s3c2410_udc_start(struct usb_gadget_driver *driver,
  1369. int (*bind)(struct usb_gadget *))
  1370. {
  1371. struct s3c2410_udc *udc = the_controller;
  1372. int retval;
  1373. dprintk(DEBUG_NORMAL, "%s() '%s'\n", __func__, driver->driver.name);
  1374. /* Sanity checks */
  1375. if (!udc)
  1376. return -ENODEV;
  1377. if (udc->driver)
  1378. return -EBUSY;
  1379. if (!bind || !driver->setup || driver->speed < USB_SPEED_FULL) {
  1380. printk(KERN_ERR "Invalid driver: bind %p setup %p speed %d\n",
  1381. bind, driver->setup, driver->speed);
  1382. return -EINVAL;
  1383. }
  1384. #if defined(MODULE)
  1385. if (!driver->unbind) {
  1386. printk(KERN_ERR "Invalid driver: no unbind method\n");
  1387. return -EINVAL;
  1388. }
  1389. #endif
  1390. /* Hook the driver */
  1391. udc->driver = driver;
  1392. udc->gadget.dev.driver = &driver->driver;
  1393. /* Bind the driver */
  1394. if ((retval = device_add(&udc->gadget.dev)) != 0) {
  1395. printk(KERN_ERR "Error in device_add() : %d\n",retval);
  1396. goto register_error;
  1397. }
  1398. dprintk(DEBUG_NORMAL, "binding gadget driver '%s'\n",
  1399. driver->driver.name);
  1400. if ((retval = bind(&udc->gadget)) != 0) {
  1401. device_del(&udc->gadget.dev);
  1402. goto register_error;
  1403. }
  1404. /* Enable udc */
  1405. s3c2410_udc_enable(udc);
  1406. return 0;
  1407. register_error:
  1408. udc->driver = NULL;
  1409. udc->gadget.dev.driver = NULL;
  1410. return retval;
  1411. }
  1412. static int s3c2410_udc_stop(struct usb_gadget_driver *driver)
  1413. {
  1414. struct s3c2410_udc *udc = the_controller;
  1415. if (!udc)
  1416. return -ENODEV;
  1417. if (!driver || driver != udc->driver || !driver->unbind)
  1418. return -EINVAL;
  1419. dprintk(DEBUG_NORMAL, "usb_gadget_unregister_driver() '%s'\n",
  1420. driver->driver.name);
  1421. /* report disconnect */
  1422. if (driver->disconnect)
  1423. driver->disconnect(&udc->gadget);
  1424. driver->unbind(&udc->gadget);
  1425. device_del(&udc->gadget.dev);
  1426. udc->driver = NULL;
  1427. /* Disable udc */
  1428. s3c2410_udc_disable(udc);
  1429. return 0;
  1430. }
  1431. /*---------------------------------------------------------------------------*/
  1432. static struct s3c2410_udc memory = {
  1433. .gadget = {
  1434. .ops = &s3c2410_ops,
  1435. .ep0 = &memory.ep[0].ep,
  1436. .name = gadget_name,
  1437. .dev = {
  1438. .init_name = "gadget",
  1439. },
  1440. },
  1441. /* control endpoint */
  1442. .ep[0] = {
  1443. .num = 0,
  1444. .ep = {
  1445. .name = ep0name,
  1446. .ops = &s3c2410_ep_ops,
  1447. .maxpacket = EP0_FIFO_SIZE,
  1448. },
  1449. .dev = &memory,
  1450. },
  1451. /* first group of endpoints */
  1452. .ep[1] = {
  1453. .num = 1,
  1454. .ep = {
  1455. .name = "ep1-bulk",
  1456. .ops = &s3c2410_ep_ops,
  1457. .maxpacket = EP_FIFO_SIZE,
  1458. },
  1459. .dev = &memory,
  1460. .fifo_size = EP_FIFO_SIZE,
  1461. .bEndpointAddress = 1,
  1462. .bmAttributes = USB_ENDPOINT_XFER_BULK,
  1463. },
  1464. .ep[2] = {
  1465. .num = 2,
  1466. .ep = {
  1467. .name = "ep2-bulk",
  1468. .ops = &s3c2410_ep_ops,
  1469. .maxpacket = EP_FIFO_SIZE,
  1470. },
  1471. .dev = &memory,
  1472. .fifo_size = EP_FIFO_SIZE,
  1473. .bEndpointAddress = 2,
  1474. .bmAttributes = USB_ENDPOINT_XFER_BULK,
  1475. },
  1476. .ep[3] = {
  1477. .num = 3,
  1478. .ep = {
  1479. .name = "ep3-bulk",
  1480. .ops = &s3c2410_ep_ops,
  1481. .maxpacket = EP_FIFO_SIZE,
  1482. },
  1483. .dev = &memory,
  1484. .fifo_size = EP_FIFO_SIZE,
  1485. .bEndpointAddress = 3,
  1486. .bmAttributes = USB_ENDPOINT_XFER_BULK,
  1487. },
  1488. .ep[4] = {
  1489. .num = 4,
  1490. .ep = {
  1491. .name = "ep4-bulk",
  1492. .ops = &s3c2410_ep_ops,
  1493. .maxpacket = EP_FIFO_SIZE,
  1494. },
  1495. .dev = &memory,
  1496. .fifo_size = EP_FIFO_SIZE,
  1497. .bEndpointAddress = 4,
  1498. .bmAttributes = USB_ENDPOINT_XFER_BULK,
  1499. }
  1500. };
  1501. /*
  1502. * probe - binds to the platform device
  1503. */
  1504. static int s3c2410_udc_probe(struct platform_device *pdev)
  1505. {
  1506. struct s3c2410_udc *udc = &memory;
  1507. struct device *dev = &pdev->dev;
  1508. int retval;
  1509. int irq;
  1510. dev_dbg(dev, "%s()\n", __func__);
  1511. usb_bus_clock = clk_get(NULL, "usb-bus-gadget");
  1512. if (IS_ERR(usb_bus_clock)) {
  1513. dev_err(dev, "failed to get usb bus clock source\n");
  1514. return PTR_ERR(usb_bus_clock);
  1515. }
  1516. clk_enable(usb_bus_clock);
  1517. udc_clock = clk_get(NULL, "usb-device");
  1518. if (IS_ERR(udc_clock)) {
  1519. dev_err(dev, "failed to get udc clock source\n");
  1520. return PTR_ERR(udc_clock);
  1521. }
  1522. clk_enable(udc_clock);
  1523. mdelay(10);
  1524. dev_dbg(dev, "got and enabled clocks\n");
  1525. if (strncmp(pdev->name, "s3c2440", 7) == 0) {
  1526. dev_info(dev, "S3C2440: increasing FIFO to 128 bytes\n");
  1527. memory.ep[1].fifo_size = S3C2440_EP_FIFO_SIZE;
  1528. memory.ep[2].fifo_size = S3C2440_EP_FIFO_SIZE;
  1529. memory.ep[3].fifo_size = S3C2440_EP_FIFO_SIZE;
  1530. memory.ep[4].fifo_size = S3C2440_EP_FIFO_SIZE;
  1531. }
  1532. spin_lock_init (&udc->lock);
  1533. udc_info = pdev->dev.platform_data;
  1534. rsrc_start = S3C2410_PA_USBDEV;
  1535. rsrc_len = S3C24XX_SZ_USBDEV;
  1536. if (!request_mem_region(rsrc_start, rsrc_len, gadget_name))
  1537. return -EBUSY;
  1538. base_addr = ioremap(rsrc_start, rsrc_len);
  1539. if (!base_addr) {
  1540. retval = -ENOMEM;
  1541. goto err_mem;
  1542. }
  1543. device_initialize(&udc->gadget.dev);
  1544. udc->gadget.dev.parent = &pdev->dev;
  1545. udc->gadget.dev.dma_mask = pdev->dev.dma_mask;
  1546. the_controller = udc;
  1547. platform_set_drvdata(pdev, udc);
  1548. s3c2410_udc_disable(udc);
  1549. s3c2410_udc_reinit(udc);
  1550. /* irq setup after old hardware state is cleaned up */
  1551. retval = request_irq(IRQ_USBD, s3c2410_udc_irq,
  1552. IRQF_DISABLED, gadget_name, udc);
  1553. if (retval != 0) {
  1554. dev_err(dev, "cannot get irq %i, err %d\n", IRQ_USBD, retval);
  1555. retval = -EBUSY;
  1556. goto err_map;
  1557. }
  1558. dev_dbg(dev, "got irq %i\n", IRQ_USBD);
  1559. if (udc_info && udc_info->vbus_pin > 0) {
  1560. retval = gpio_request(udc_info->vbus_pin, "udc vbus");
  1561. if (retval < 0) {
  1562. dev_err(dev, "cannot claim vbus pin\n");
  1563. goto err_int;
  1564. }
  1565. irq = gpio_to_irq(udc_info->vbus_pin);
  1566. if (irq < 0) {
  1567. dev_err(dev, "no irq for gpio vbus pin\n");
  1568. goto err_gpio_claim;
  1569. }
  1570. retval = request_irq(irq, s3c2410_udc_vbus_irq,
  1571. IRQF_DISABLED | IRQF_TRIGGER_RISING
  1572. | IRQF_TRIGGER_FALLING | IRQF_SHARED,
  1573. gadget_name, udc);
  1574. if (retval != 0) {
  1575. dev_err(dev, "can't get vbus irq %d, err %d\n",
  1576. irq, retval);
  1577. retval = -EBUSY;
  1578. goto err_gpio_claim;
  1579. }
  1580. dev_dbg(dev, "got irq %i\n", irq);
  1581. } else {
  1582. udc->vbus = 1;
  1583. }
  1584. if (udc_info && !udc_info->udc_command &&
  1585. gpio_is_valid(udc_info->pullup_pin)) {
  1586. retval = gpio_request_one(udc_info->pullup_pin,
  1587. udc_info->vbus_pin_inverted ?
  1588. GPIOF_OUT_INIT_HIGH : GPIOF_OUT_INIT_LOW,
  1589. "udc pullup");
  1590. if (retval)
  1591. goto err_vbus_irq;
  1592. }
  1593. retval = usb_add_gadget_udc(&pdev->dev, &udc->gadget);
  1594. if (retval)
  1595. goto err_add_udc;
  1596. if (s3c2410_udc_debugfs_root) {
  1597. udc->regs_info = debugfs_create_file("registers", S_IRUGO,
  1598. s3c2410_udc_debugfs_root,
  1599. udc, &s3c2410_udc_debugfs_fops);
  1600. if (!udc->regs_info)
  1601. dev_warn(dev, "debugfs file creation failed\n");
  1602. }
  1603. dev_dbg(dev, "probe ok\n");
  1604. return 0;
  1605. err_add_udc:
  1606. if (udc_info && !udc_info->udc_command &&
  1607. gpio_is_valid(udc_info->pullup_pin))
  1608. gpio_free(udc_info->pullup_pin);
  1609. err_vbus_irq:
  1610. if (udc_info && udc_info->vbus_pin > 0)
  1611. free_irq(gpio_to_irq(udc_info->vbus_pin), udc);
  1612. err_gpio_claim:
  1613. if (udc_info && udc_info->vbus_pin > 0)
  1614. gpio_free(udc_info->vbus_pin);
  1615. err_int:
  1616. free_irq(IRQ_USBD, udc);
  1617. err_map:
  1618. iounmap(base_addr);
  1619. err_mem:
  1620. release_mem_region(rsrc_start, rsrc_len);
  1621. return retval;
  1622. }
  1623. /*
  1624. * s3c2410_udc_remove
  1625. */
  1626. static int s3c2410_udc_remove(struct platform_device *pdev)
  1627. {
  1628. struct s3c2410_udc *udc = platform_get_drvdata(pdev);
  1629. unsigned int irq;
  1630. dev_dbg(&pdev->dev, "%s()\n", __func__);
  1631. usb_del_gadget_udc(&udc->gadget);
  1632. if (udc->driver)
  1633. return -EBUSY;
  1634. debugfs_remove(udc->regs_info);
  1635. if (udc_info && !udc_info->udc_command &&
  1636. gpio_is_valid(udc_info->pullup_pin))
  1637. gpio_free(udc_info->pullup_pin);
  1638. if (udc_info && udc_info->vbus_pin > 0) {
  1639. irq = gpio_to_irq(udc_info->vbus_pin);
  1640. free_irq(irq, udc);
  1641. }
  1642. free_irq(IRQ_USBD, udc);
  1643. iounmap(base_addr);
  1644. release_mem_region(rsrc_start, rsrc_len);
  1645. platform_set_drvdata(pdev, NULL);
  1646. if (!IS_ERR(udc_clock) && udc_clock != NULL) {
  1647. clk_disable(udc_clock);
  1648. clk_put(udc_clock);
  1649. udc_clock = NULL;
  1650. }
  1651. if (!IS_ERR(usb_bus_clock) && usb_bus_clock != NULL) {
  1652. clk_disable(usb_bus_clock);
  1653. clk_put(usb_bus_clock);
  1654. usb_bus_clock = NULL;
  1655. }
  1656. dev_dbg(&pdev->dev, "%s: remove ok\n", __func__);
  1657. return 0;
  1658. }
  1659. #ifdef CONFIG_PM
  1660. static int s3c2410_udc_suspend(struct platform_device *pdev, pm_message_t message)
  1661. {
  1662. s3c2410_udc_command(S3C2410_UDC_P_DISABLE);
  1663. return 0;
  1664. }
  1665. static int s3c2410_udc_resume(struct platform_device *pdev)
  1666. {
  1667. s3c2410_udc_command(S3C2410_UDC_P_ENABLE);
  1668. return 0;
  1669. }
  1670. #else
  1671. #define s3c2410_udc_suspend NULL
  1672. #define s3c2410_udc_resume NULL
  1673. #endif
  1674. static const struct platform_device_id s3c_udc_ids[] = {
  1675. { "s3c2410-usbgadget", },
  1676. { "s3c2440-usbgadget", },
  1677. };
  1678. MODULE_DEVICE_TABLE(platform, s3c_udc_ids);
  1679. static struct platform_driver udc_driver_24x0 = {
  1680. .driver = {
  1681. .name = "s3c24x0-usbgadget",
  1682. .owner = THIS_MODULE,
  1683. },
  1684. .probe = s3c2410_udc_probe,
  1685. .remove = s3c2410_udc_remove,
  1686. .suspend = s3c2410_udc_suspend,
  1687. .resume = s3c2410_udc_resume,
  1688. .id_table = s3c_udc_ids,
  1689. };
  1690. static int __init udc_init(void)
  1691. {
  1692. int retval;
  1693. dprintk(DEBUG_NORMAL, "%s: version %s\n", gadget_name, DRIVER_VERSION);
  1694. s3c2410_udc_debugfs_root = debugfs_create_dir(gadget_name, NULL);
  1695. if (IS_ERR(s3c2410_udc_debugfs_root)) {
  1696. printk(KERN_ERR "%s: debugfs dir creation failed %ld\n",
  1697. gadget_name, PTR_ERR(s3c2410_udc_debugfs_root));
  1698. s3c2410_udc_debugfs_root = NULL;
  1699. }
  1700. retval = platform_driver_register(&udc_driver_24x0);
  1701. if (retval)
  1702. goto err;
  1703. return 0;
  1704. err:
  1705. debugfs_remove(s3c2410_udc_debugfs_root);
  1706. return retval;
  1707. }
  1708. static void __exit udc_exit(void)
  1709. {
  1710. platform_driver_unregister(&udc_driver_24x0);
  1711. debugfs_remove(s3c2410_udc_debugfs_root);
  1712. }
  1713. module_init(udc_init);
  1714. module_exit(udc_exit);
  1715. MODULE_AUTHOR(DRIVER_AUTHOR);
  1716. MODULE_DESCRIPTION(DRIVER_DESC);
  1717. MODULE_VERSION(DRIVER_VERSION);
  1718. MODULE_LICENSE("GPL");