fusb300_udc.c 40 KB

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  1. /*
  2. * Fusb300 UDC (USB gadget)
  3. *
  4. * Copyright (C) 2010 Faraday Technology Corp.
  5. *
  6. * Author : Yuan-hsin Chen <yhchen@faraday-tech.com>
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License as published by
  10. * the Free Software Foundation; version 2 of the License.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  20. *
  21. */
  22. #include <linux/dma-mapping.h>
  23. #include <linux/err.h>
  24. #include <linux/interrupt.h>
  25. #include <linux/io.h>
  26. #include <linux/platform_device.h>
  27. #include <linux/usb/ch9.h>
  28. #include <linux/usb/gadget.h>
  29. #include "fusb300_udc.h"
  30. MODULE_DESCRIPTION("FUSB300 USB gadget driver");
  31. MODULE_LICENSE("GPL");
  32. MODULE_AUTHOR("Yuan Hsin Chen <yhchen@faraday-tech.com>");
  33. MODULE_ALIAS("platform:fusb300_udc");
  34. #define DRIVER_VERSION "20 October 2010"
  35. static const char udc_name[] = "fusb300_udc";
  36. static const char * const fusb300_ep_name[] = {
  37. "ep0", "ep1", "ep2", "ep3", "ep4", "ep5", "ep6", "ep7", "ep8", "ep9",
  38. "ep10", "ep11", "ep12", "ep13", "ep14", "ep15"
  39. };
  40. static void done(struct fusb300_ep *ep, struct fusb300_request *req,
  41. int status);
  42. static void fusb300_enable_bit(struct fusb300 *fusb300, u32 offset,
  43. u32 value)
  44. {
  45. u32 reg = ioread32(fusb300->reg + offset);
  46. reg |= value;
  47. iowrite32(reg, fusb300->reg + offset);
  48. }
  49. static void fusb300_disable_bit(struct fusb300 *fusb300, u32 offset,
  50. u32 value)
  51. {
  52. u32 reg = ioread32(fusb300->reg + offset);
  53. reg &= ~value;
  54. iowrite32(reg, fusb300->reg + offset);
  55. }
  56. static void fusb300_ep_setting(struct fusb300_ep *ep,
  57. struct fusb300_ep_info info)
  58. {
  59. ep->epnum = info.epnum;
  60. ep->type = info.type;
  61. }
  62. static int fusb300_ep_release(struct fusb300_ep *ep)
  63. {
  64. if (!ep->epnum)
  65. return 0;
  66. ep->epnum = 0;
  67. ep->stall = 0;
  68. ep->wedged = 0;
  69. return 0;
  70. }
  71. static void fusb300_set_fifo_entry(struct fusb300 *fusb300,
  72. u32 ep)
  73. {
  74. u32 val = ioread32(fusb300->reg + FUSB300_OFFSET_EPSET1(ep));
  75. val &= ~FUSB300_EPSET1_FIFOENTRY_MSK;
  76. val |= FUSB300_EPSET1_FIFOENTRY(FUSB300_FIFO_ENTRY_NUM);
  77. iowrite32(val, fusb300->reg + FUSB300_OFFSET_EPSET1(ep));
  78. }
  79. static void fusb300_set_start_entry(struct fusb300 *fusb300,
  80. u8 ep)
  81. {
  82. u32 reg = ioread32(fusb300->reg + FUSB300_OFFSET_EPSET1(ep));
  83. u32 start_entry = fusb300->fifo_entry_num * FUSB300_FIFO_ENTRY_NUM;
  84. reg &= ~FUSB300_EPSET1_START_ENTRY_MSK ;
  85. reg |= FUSB300_EPSET1_START_ENTRY(start_entry);
  86. iowrite32(reg, fusb300->reg + FUSB300_OFFSET_EPSET1(ep));
  87. if (fusb300->fifo_entry_num == FUSB300_MAX_FIFO_ENTRY) {
  88. fusb300->fifo_entry_num = 0;
  89. fusb300->addrofs = 0;
  90. pr_err("fifo entry is over the maximum number!\n");
  91. } else
  92. fusb300->fifo_entry_num++;
  93. }
  94. /* set fusb300_set_start_entry first before fusb300_set_epaddrofs */
  95. static void fusb300_set_epaddrofs(struct fusb300 *fusb300,
  96. struct fusb300_ep_info info)
  97. {
  98. u32 reg = ioread32(fusb300->reg + FUSB300_OFFSET_EPSET2(info.epnum));
  99. reg &= ~FUSB300_EPSET2_ADDROFS_MSK;
  100. reg |= FUSB300_EPSET2_ADDROFS(fusb300->addrofs);
  101. iowrite32(reg, fusb300->reg + FUSB300_OFFSET_EPSET2(info.epnum));
  102. fusb300->addrofs += (info.maxpacket + 7) / 8 * FUSB300_FIFO_ENTRY_NUM;
  103. }
  104. static void ep_fifo_setting(struct fusb300 *fusb300,
  105. struct fusb300_ep_info info)
  106. {
  107. fusb300_set_fifo_entry(fusb300, info.epnum);
  108. fusb300_set_start_entry(fusb300, info.epnum);
  109. fusb300_set_epaddrofs(fusb300, info);
  110. }
  111. static void fusb300_set_eptype(struct fusb300 *fusb300,
  112. struct fusb300_ep_info info)
  113. {
  114. u32 reg = ioread32(fusb300->reg + FUSB300_OFFSET_EPSET1(info.epnum));
  115. reg &= ~FUSB300_EPSET1_TYPE_MSK;
  116. reg |= FUSB300_EPSET1_TYPE(info.type);
  117. iowrite32(reg, fusb300->reg + FUSB300_OFFSET_EPSET1(info.epnum));
  118. }
  119. static void fusb300_set_epdir(struct fusb300 *fusb300,
  120. struct fusb300_ep_info info)
  121. {
  122. u32 reg;
  123. if (!info.dir_in)
  124. return;
  125. reg = ioread32(fusb300->reg + FUSB300_OFFSET_EPSET1(info.epnum));
  126. reg &= ~FUSB300_EPSET1_DIR_MSK;
  127. reg |= FUSB300_EPSET1_DIRIN;
  128. iowrite32(reg, fusb300->reg + FUSB300_OFFSET_EPSET1(info.epnum));
  129. }
  130. static void fusb300_set_ep_active(struct fusb300 *fusb300,
  131. u8 ep)
  132. {
  133. u32 reg = ioread32(fusb300->reg + FUSB300_OFFSET_EPSET1(ep));
  134. reg |= FUSB300_EPSET1_ACTEN;
  135. iowrite32(reg, fusb300->reg + FUSB300_OFFSET_EPSET1(ep));
  136. }
  137. static void fusb300_set_epmps(struct fusb300 *fusb300,
  138. struct fusb300_ep_info info)
  139. {
  140. u32 reg = ioread32(fusb300->reg + FUSB300_OFFSET_EPSET2(info.epnum));
  141. reg &= ~FUSB300_EPSET2_MPS_MSK;
  142. reg |= FUSB300_EPSET2_MPS(info.maxpacket);
  143. iowrite32(reg, fusb300->reg + FUSB300_OFFSET_EPSET2(info.epnum));
  144. }
  145. static void fusb300_set_interval(struct fusb300 *fusb300,
  146. struct fusb300_ep_info info)
  147. {
  148. u32 reg = ioread32(fusb300->reg + FUSB300_OFFSET_EPSET1(info.epnum));
  149. reg &= ~FUSB300_EPSET1_INTERVAL(0x7);
  150. reg |= FUSB300_EPSET1_INTERVAL(info.interval);
  151. iowrite32(reg, fusb300->reg + FUSB300_OFFSET_EPSET1(info.epnum));
  152. }
  153. static void fusb300_set_bwnum(struct fusb300 *fusb300,
  154. struct fusb300_ep_info info)
  155. {
  156. u32 reg = ioread32(fusb300->reg + FUSB300_OFFSET_EPSET1(info.epnum));
  157. reg &= ~FUSB300_EPSET1_BWNUM(0x3);
  158. reg |= FUSB300_EPSET1_BWNUM(info.bw_num);
  159. iowrite32(reg, fusb300->reg + FUSB300_OFFSET_EPSET1(info.epnum));
  160. }
  161. static void set_ep_reg(struct fusb300 *fusb300,
  162. struct fusb300_ep_info info)
  163. {
  164. fusb300_set_eptype(fusb300, info);
  165. fusb300_set_epdir(fusb300, info);
  166. fusb300_set_epmps(fusb300, info);
  167. if (info.interval)
  168. fusb300_set_interval(fusb300, info);
  169. if (info.bw_num)
  170. fusb300_set_bwnum(fusb300, info);
  171. fusb300_set_ep_active(fusb300, info.epnum);
  172. }
  173. static int config_ep(struct fusb300_ep *ep,
  174. const struct usb_endpoint_descriptor *desc)
  175. {
  176. struct fusb300 *fusb300 = ep->fusb300;
  177. struct fusb300_ep_info info;
  178. ep->desc = desc;
  179. info.interval = 0;
  180. info.addrofs = 0;
  181. info.bw_num = 0;
  182. info.type = desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK;
  183. info.dir_in = (desc->bEndpointAddress & USB_ENDPOINT_DIR_MASK) ? 1 : 0;
  184. info.maxpacket = le16_to_cpu(desc->wMaxPacketSize);
  185. info.epnum = desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK;
  186. if ((info.type == USB_ENDPOINT_XFER_INT) ||
  187. (info.type == USB_ENDPOINT_XFER_ISOC)) {
  188. info.interval = desc->bInterval;
  189. if (info.type == USB_ENDPOINT_XFER_ISOC)
  190. info.bw_num = ((desc->wMaxPacketSize & 0x1800) >> 11);
  191. }
  192. ep_fifo_setting(fusb300, info);
  193. set_ep_reg(fusb300, info);
  194. fusb300_ep_setting(ep, info);
  195. fusb300->ep[info.epnum] = ep;
  196. return 0;
  197. }
  198. static int fusb300_enable(struct usb_ep *_ep,
  199. const struct usb_endpoint_descriptor *desc)
  200. {
  201. struct fusb300_ep *ep;
  202. ep = container_of(_ep, struct fusb300_ep, ep);
  203. if (ep->fusb300->reenum) {
  204. ep->fusb300->fifo_entry_num = 0;
  205. ep->fusb300->addrofs = 0;
  206. ep->fusb300->reenum = 0;
  207. }
  208. return config_ep(ep, desc);
  209. }
  210. static int fusb300_disable(struct usb_ep *_ep)
  211. {
  212. struct fusb300_ep *ep;
  213. struct fusb300_request *req;
  214. unsigned long flags;
  215. ep = container_of(_ep, struct fusb300_ep, ep);
  216. BUG_ON(!ep);
  217. while (!list_empty(&ep->queue)) {
  218. req = list_entry(ep->queue.next, struct fusb300_request, queue);
  219. spin_lock_irqsave(&ep->fusb300->lock, flags);
  220. done(ep, req, -ECONNRESET);
  221. spin_unlock_irqrestore(&ep->fusb300->lock, flags);
  222. }
  223. return fusb300_ep_release(ep);
  224. }
  225. static struct usb_request *fusb300_alloc_request(struct usb_ep *_ep,
  226. gfp_t gfp_flags)
  227. {
  228. struct fusb300_request *req;
  229. req = kzalloc(sizeof(struct fusb300_request), gfp_flags);
  230. if (!req)
  231. return NULL;
  232. INIT_LIST_HEAD(&req->queue);
  233. return &req->req;
  234. }
  235. static void fusb300_free_request(struct usb_ep *_ep, struct usb_request *_req)
  236. {
  237. struct fusb300_request *req;
  238. req = container_of(_req, struct fusb300_request, req);
  239. kfree(req);
  240. }
  241. static int enable_fifo_int(struct fusb300_ep *ep)
  242. {
  243. struct fusb300 *fusb300 = ep->fusb300;
  244. if (ep->epnum) {
  245. fusb300_enable_bit(fusb300, FUSB300_OFFSET_IGER0,
  246. FUSB300_IGER0_EEPn_FIFO_INT(ep->epnum));
  247. } else {
  248. pr_err("can't enable_fifo_int ep0\n");
  249. return -EINVAL;
  250. }
  251. return 0;
  252. }
  253. static int disable_fifo_int(struct fusb300_ep *ep)
  254. {
  255. struct fusb300 *fusb300 = ep->fusb300;
  256. if (ep->epnum) {
  257. fusb300_disable_bit(fusb300, FUSB300_OFFSET_IGER0,
  258. FUSB300_IGER0_EEPn_FIFO_INT(ep->epnum));
  259. } else {
  260. pr_err("can't disable_fifo_int ep0\n");
  261. return -EINVAL;
  262. }
  263. return 0;
  264. }
  265. static void fusb300_set_cxlen(struct fusb300 *fusb300, u32 length)
  266. {
  267. u32 reg;
  268. reg = ioread32(fusb300->reg + FUSB300_OFFSET_CSR);
  269. reg &= ~FUSB300_CSR_LEN_MSK;
  270. reg |= FUSB300_CSR_LEN(length);
  271. iowrite32(reg, fusb300->reg + FUSB300_OFFSET_CSR);
  272. }
  273. /* write data to cx fifo */
  274. static void fusb300_wrcxf(struct fusb300_ep *ep,
  275. struct fusb300_request *req)
  276. {
  277. int i = 0;
  278. u8 *tmp;
  279. u32 data;
  280. struct fusb300 *fusb300 = ep->fusb300;
  281. u32 length = req->req.length - req->req.actual;
  282. tmp = req->req.buf + req->req.actual;
  283. if (length > SS_CTL_MAX_PACKET_SIZE) {
  284. fusb300_set_cxlen(fusb300, SS_CTL_MAX_PACKET_SIZE);
  285. for (i = (SS_CTL_MAX_PACKET_SIZE >> 2); i > 0; i--) {
  286. data = *tmp | *(tmp + 1) << 8 | *(tmp + 2) << 16 |
  287. *(tmp + 3) << 24;
  288. iowrite32(data, fusb300->reg + FUSB300_OFFSET_CXPORT);
  289. tmp += 4;
  290. }
  291. req->req.actual += SS_CTL_MAX_PACKET_SIZE;
  292. } else { /* length is less than max packet size */
  293. fusb300_set_cxlen(fusb300, length);
  294. for (i = length >> 2; i > 0; i--) {
  295. data = *tmp | *(tmp + 1) << 8 | *(tmp + 2) << 16 |
  296. *(tmp + 3) << 24;
  297. printk(KERN_DEBUG " 0x%x\n", data);
  298. iowrite32(data, fusb300->reg + FUSB300_OFFSET_CXPORT);
  299. tmp = tmp + 4;
  300. }
  301. switch (length % 4) {
  302. case 1:
  303. data = *tmp;
  304. printk(KERN_DEBUG " 0x%x\n", data);
  305. iowrite32(data, fusb300->reg + FUSB300_OFFSET_CXPORT);
  306. break;
  307. case 2:
  308. data = *tmp | *(tmp + 1) << 8;
  309. printk(KERN_DEBUG " 0x%x\n", data);
  310. iowrite32(data, fusb300->reg + FUSB300_OFFSET_CXPORT);
  311. break;
  312. case 3:
  313. data = *tmp | *(tmp + 1) << 8 | *(tmp + 2) << 16;
  314. printk(KERN_DEBUG " 0x%x\n", data);
  315. iowrite32(data, fusb300->reg + FUSB300_OFFSET_CXPORT);
  316. break;
  317. default:
  318. break;
  319. }
  320. req->req.actual += length;
  321. }
  322. }
  323. static void fusb300_set_epnstall(struct fusb300 *fusb300, u8 ep)
  324. {
  325. fusb300_enable_bit(fusb300, FUSB300_OFFSET_EPSET0(ep),
  326. FUSB300_EPSET0_STL);
  327. }
  328. static void fusb300_clear_epnstall(struct fusb300 *fusb300, u8 ep)
  329. {
  330. u32 reg = ioread32(fusb300->reg + FUSB300_OFFSET_EPSET0(ep));
  331. if (reg & FUSB300_EPSET0_STL) {
  332. printk(KERN_DEBUG "EP%d stall... Clear!!\n", ep);
  333. reg &= ~FUSB300_EPSET0_STL;
  334. iowrite32(reg, fusb300->reg + FUSB300_OFFSET_EPSET0(ep));
  335. }
  336. }
  337. static void ep0_queue(struct fusb300_ep *ep, struct fusb300_request *req)
  338. {
  339. if (ep->fusb300->ep0_dir) { /* if IN */
  340. if (req->req.length) {
  341. fusb300_wrcxf(ep, req);
  342. } else
  343. printk(KERN_DEBUG "%s : req->req.length = 0x%x\n",
  344. __func__, req->req.length);
  345. if ((req->req.length == req->req.actual) ||
  346. (req->req.actual < ep->ep.maxpacket))
  347. done(ep, req, 0);
  348. } else { /* OUT */
  349. if (!req->req.length)
  350. done(ep, req, 0);
  351. else
  352. fusb300_enable_bit(ep->fusb300, FUSB300_OFFSET_IGER1,
  353. FUSB300_IGER1_CX_OUT_INT);
  354. }
  355. }
  356. static int fusb300_queue(struct usb_ep *_ep, struct usb_request *_req,
  357. gfp_t gfp_flags)
  358. {
  359. struct fusb300_ep *ep;
  360. struct fusb300_request *req;
  361. unsigned long flags;
  362. int request = 0;
  363. ep = container_of(_ep, struct fusb300_ep, ep);
  364. req = container_of(_req, struct fusb300_request, req);
  365. if (ep->fusb300->gadget.speed == USB_SPEED_UNKNOWN)
  366. return -ESHUTDOWN;
  367. spin_lock_irqsave(&ep->fusb300->lock, flags);
  368. if (list_empty(&ep->queue))
  369. request = 1;
  370. list_add_tail(&req->queue, &ep->queue);
  371. req->req.actual = 0;
  372. req->req.status = -EINPROGRESS;
  373. if (ep->desc == NULL) /* ep0 */
  374. ep0_queue(ep, req);
  375. else if (request && !ep->stall)
  376. enable_fifo_int(ep);
  377. spin_unlock_irqrestore(&ep->fusb300->lock, flags);
  378. return 0;
  379. }
  380. static int fusb300_dequeue(struct usb_ep *_ep, struct usb_request *_req)
  381. {
  382. struct fusb300_ep *ep;
  383. struct fusb300_request *req;
  384. unsigned long flags;
  385. ep = container_of(_ep, struct fusb300_ep, ep);
  386. req = container_of(_req, struct fusb300_request, req);
  387. spin_lock_irqsave(&ep->fusb300->lock, flags);
  388. if (!list_empty(&ep->queue))
  389. done(ep, req, -ECONNRESET);
  390. spin_unlock_irqrestore(&ep->fusb300->lock, flags);
  391. return 0;
  392. }
  393. static int fusb300_set_halt_and_wedge(struct usb_ep *_ep, int value, int wedge)
  394. {
  395. struct fusb300_ep *ep;
  396. struct fusb300 *fusb300;
  397. unsigned long flags;
  398. int ret = 0;
  399. ep = container_of(_ep, struct fusb300_ep, ep);
  400. fusb300 = ep->fusb300;
  401. spin_lock_irqsave(&ep->fusb300->lock, flags);
  402. if (!list_empty(&ep->queue)) {
  403. ret = -EAGAIN;
  404. goto out;
  405. }
  406. if (value) {
  407. fusb300_set_epnstall(fusb300, ep->epnum);
  408. ep->stall = 1;
  409. if (wedge)
  410. ep->wedged = 1;
  411. } else {
  412. fusb300_clear_epnstall(fusb300, ep->epnum);
  413. ep->stall = 0;
  414. ep->wedged = 0;
  415. }
  416. out:
  417. spin_unlock_irqrestore(&ep->fusb300->lock, flags);
  418. return ret;
  419. }
  420. static int fusb300_set_halt(struct usb_ep *_ep, int value)
  421. {
  422. return fusb300_set_halt_and_wedge(_ep, value, 0);
  423. }
  424. static int fusb300_set_wedge(struct usb_ep *_ep)
  425. {
  426. return fusb300_set_halt_and_wedge(_ep, 1, 1);
  427. }
  428. static void fusb300_fifo_flush(struct usb_ep *_ep)
  429. {
  430. }
  431. static struct usb_ep_ops fusb300_ep_ops = {
  432. .enable = fusb300_enable,
  433. .disable = fusb300_disable,
  434. .alloc_request = fusb300_alloc_request,
  435. .free_request = fusb300_free_request,
  436. .queue = fusb300_queue,
  437. .dequeue = fusb300_dequeue,
  438. .set_halt = fusb300_set_halt,
  439. .fifo_flush = fusb300_fifo_flush,
  440. .set_wedge = fusb300_set_wedge,
  441. };
  442. /*****************************************************************************/
  443. static void fusb300_clear_int(struct fusb300 *fusb300, u32 offset,
  444. u32 value)
  445. {
  446. iowrite32(value, fusb300->reg + offset);
  447. }
  448. static void fusb300_reset(void)
  449. {
  450. }
  451. static void fusb300_set_cxstall(struct fusb300 *fusb300)
  452. {
  453. fusb300_enable_bit(fusb300, FUSB300_OFFSET_CSR,
  454. FUSB300_CSR_STL);
  455. }
  456. static void fusb300_set_cxdone(struct fusb300 *fusb300)
  457. {
  458. fusb300_enable_bit(fusb300, FUSB300_OFFSET_CSR,
  459. FUSB300_CSR_DONE);
  460. }
  461. /* read data from cx fifo */
  462. void fusb300_rdcxf(struct fusb300 *fusb300,
  463. u8 *buffer, u32 length)
  464. {
  465. int i = 0;
  466. u8 *tmp;
  467. u32 data;
  468. tmp = buffer;
  469. for (i = (length >> 2); i > 0; i--) {
  470. data = ioread32(fusb300->reg + FUSB300_OFFSET_CXPORT);
  471. printk(KERN_DEBUG " 0x%x\n", data);
  472. *tmp = data & 0xFF;
  473. *(tmp + 1) = (data >> 8) & 0xFF;
  474. *(tmp + 2) = (data >> 16) & 0xFF;
  475. *(tmp + 3) = (data >> 24) & 0xFF;
  476. tmp = tmp + 4;
  477. }
  478. switch (length % 4) {
  479. case 1:
  480. data = ioread32(fusb300->reg + FUSB300_OFFSET_CXPORT);
  481. printk(KERN_DEBUG " 0x%x\n", data);
  482. *tmp = data & 0xFF;
  483. break;
  484. case 2:
  485. data = ioread32(fusb300->reg + FUSB300_OFFSET_CXPORT);
  486. printk(KERN_DEBUG " 0x%x\n", data);
  487. *tmp = data & 0xFF;
  488. *(tmp + 1) = (data >> 8) & 0xFF;
  489. break;
  490. case 3:
  491. data = ioread32(fusb300->reg + FUSB300_OFFSET_CXPORT);
  492. printk(KERN_DEBUG " 0x%x\n", data);
  493. *tmp = data & 0xFF;
  494. *(tmp + 1) = (data >> 8) & 0xFF;
  495. *(tmp + 2) = (data >> 16) & 0xFF;
  496. break;
  497. default:
  498. break;
  499. }
  500. }
  501. #if 0
  502. static void fusb300_dbg_fifo(struct fusb300_ep *ep,
  503. u8 entry, u16 length)
  504. {
  505. u32 reg;
  506. u32 i = 0;
  507. u32 j = 0;
  508. reg = ioread32(ep->fusb300->reg + FUSB300_OFFSET_GTM);
  509. reg &= ~(FUSB300_GTM_TST_EP_ENTRY(0xF) |
  510. FUSB300_GTM_TST_EP_NUM(0xF) | FUSB300_GTM_TST_FIFO_DEG);
  511. reg |= (FUSB300_GTM_TST_EP_ENTRY(entry) |
  512. FUSB300_GTM_TST_EP_NUM(ep->epnum) | FUSB300_GTM_TST_FIFO_DEG);
  513. iowrite32(reg, ep->fusb300->reg + FUSB300_OFFSET_GTM);
  514. for (i = 0; i < (length >> 2); i++) {
  515. if (i * 4 == 1024)
  516. break;
  517. reg = ioread32(ep->fusb300->reg +
  518. FUSB300_OFFSET_BUFDBG_START + i * 4);
  519. printk(KERN_DEBUG" 0x%-8x", reg);
  520. j++;
  521. if ((j % 4) == 0)
  522. printk(KERN_DEBUG "\n");
  523. }
  524. if (length % 4) {
  525. reg = ioread32(ep->fusb300->reg +
  526. FUSB300_OFFSET_BUFDBG_START + i * 4);
  527. printk(KERN_DEBUG " 0x%x\n", reg);
  528. }
  529. if ((j % 4) != 0)
  530. printk(KERN_DEBUG "\n");
  531. fusb300_disable_bit(ep->fusb300, FUSB300_OFFSET_GTM,
  532. FUSB300_GTM_TST_FIFO_DEG);
  533. }
  534. static void fusb300_cmp_dbg_fifo(struct fusb300_ep *ep,
  535. u8 entry, u16 length, u8 *golden)
  536. {
  537. u32 reg;
  538. u32 i = 0;
  539. u32 golden_value;
  540. u8 *tmp;
  541. tmp = golden;
  542. printk(KERN_DEBUG "fusb300_cmp_dbg_fifo (entry %d) : start\n", entry);
  543. reg = ioread32(ep->fusb300->reg + FUSB300_OFFSET_GTM);
  544. reg &= ~(FUSB300_GTM_TST_EP_ENTRY(0xF) |
  545. FUSB300_GTM_TST_EP_NUM(0xF) | FUSB300_GTM_TST_FIFO_DEG);
  546. reg |= (FUSB300_GTM_TST_EP_ENTRY(entry) |
  547. FUSB300_GTM_TST_EP_NUM(ep->epnum) | FUSB300_GTM_TST_FIFO_DEG);
  548. iowrite32(reg, ep->fusb300->reg + FUSB300_OFFSET_GTM);
  549. for (i = 0; i < (length >> 2); i++) {
  550. if (i * 4 == 1024)
  551. break;
  552. golden_value = *tmp | *(tmp + 1) << 8 |
  553. *(tmp + 2) << 16 | *(tmp + 3) << 24;
  554. reg = ioread32(ep->fusb300->reg +
  555. FUSB300_OFFSET_BUFDBG_START + i*4);
  556. if (reg != golden_value) {
  557. printk(KERN_DEBUG "0x%x : ", (u32)(ep->fusb300->reg +
  558. FUSB300_OFFSET_BUFDBG_START + i*4));
  559. printk(KERN_DEBUG " golden = 0x%x, reg = 0x%x\n",
  560. golden_value, reg);
  561. }
  562. tmp += 4;
  563. }
  564. switch (length % 4) {
  565. case 1:
  566. golden_value = *tmp;
  567. case 2:
  568. golden_value = *tmp | *(tmp + 1) << 8;
  569. case 3:
  570. golden_value = *tmp | *(tmp + 1) << 8 | *(tmp + 2) << 16;
  571. default:
  572. break;
  573. reg = ioread32(ep->fusb300->reg + FUSB300_OFFSET_BUFDBG_START + i*4);
  574. if (reg != golden_value) {
  575. printk(KERN_DEBUG "0x%x:", (u32)(ep->fusb300->reg +
  576. FUSB300_OFFSET_BUFDBG_START + i*4));
  577. printk(KERN_DEBUG " golden = 0x%x, reg = 0x%x\n",
  578. golden_value, reg);
  579. }
  580. }
  581. printk(KERN_DEBUG "fusb300_cmp_dbg_fifo : end\n");
  582. fusb300_disable_bit(ep->fusb300, FUSB300_OFFSET_GTM,
  583. FUSB300_GTM_TST_FIFO_DEG);
  584. }
  585. #endif
  586. static void fusb300_rdfifo(struct fusb300_ep *ep,
  587. struct fusb300_request *req,
  588. u32 length)
  589. {
  590. int i = 0;
  591. u8 *tmp;
  592. u32 data, reg;
  593. struct fusb300 *fusb300 = ep->fusb300;
  594. tmp = req->req.buf + req->req.actual;
  595. req->req.actual += length;
  596. if (req->req.actual > req->req.length)
  597. printk(KERN_DEBUG "req->req.actual > req->req.length\n");
  598. for (i = (length >> 2); i > 0; i--) {
  599. data = ioread32(fusb300->reg +
  600. FUSB300_OFFSET_EPPORT(ep->epnum));
  601. *tmp = data & 0xFF;
  602. *(tmp + 1) = (data >> 8) & 0xFF;
  603. *(tmp + 2) = (data >> 16) & 0xFF;
  604. *(tmp + 3) = (data >> 24) & 0xFF;
  605. tmp = tmp + 4;
  606. }
  607. switch (length % 4) {
  608. case 1:
  609. data = ioread32(fusb300->reg +
  610. FUSB300_OFFSET_EPPORT(ep->epnum));
  611. *tmp = data & 0xFF;
  612. break;
  613. case 2:
  614. data = ioread32(fusb300->reg +
  615. FUSB300_OFFSET_EPPORT(ep->epnum));
  616. *tmp = data & 0xFF;
  617. *(tmp + 1) = (data >> 8) & 0xFF;
  618. break;
  619. case 3:
  620. data = ioread32(fusb300->reg +
  621. FUSB300_OFFSET_EPPORT(ep->epnum));
  622. *tmp = data & 0xFF;
  623. *(tmp + 1) = (data >> 8) & 0xFF;
  624. *(tmp + 2) = (data >> 16) & 0xFF;
  625. break;
  626. default:
  627. break;
  628. }
  629. do {
  630. reg = ioread32(fusb300->reg + FUSB300_OFFSET_IGR1);
  631. reg &= FUSB300_IGR1_SYNF0_EMPTY_INT;
  632. if (i)
  633. printk(KERN_INFO "sync fifo is not empty!\n");
  634. i++;
  635. } while (!reg);
  636. }
  637. static u8 fusb300_get_epnstall(struct fusb300 *fusb300, u8 ep)
  638. {
  639. u8 value;
  640. u32 reg = ioread32(fusb300->reg + FUSB300_OFFSET_EPSET0(ep));
  641. value = reg & FUSB300_EPSET0_STL;
  642. return value;
  643. }
  644. static u8 fusb300_get_cxstall(struct fusb300 *fusb300)
  645. {
  646. u8 value;
  647. u32 reg = ioread32(fusb300->reg + FUSB300_OFFSET_CSR);
  648. value = (reg & FUSB300_CSR_STL) >> 1;
  649. return value;
  650. }
  651. static void request_error(struct fusb300 *fusb300)
  652. {
  653. fusb300_set_cxstall(fusb300);
  654. printk(KERN_DEBUG "request error!!\n");
  655. }
  656. static void get_status(struct fusb300 *fusb300, struct usb_ctrlrequest *ctrl)
  657. __releases(fusb300->lock)
  658. __acquires(fusb300->lock)
  659. {
  660. u8 ep;
  661. u16 status = 0;
  662. u16 w_index = ctrl->wIndex;
  663. switch (ctrl->bRequestType & USB_RECIP_MASK) {
  664. case USB_RECIP_DEVICE:
  665. status = 1 << USB_DEVICE_SELF_POWERED;
  666. break;
  667. case USB_RECIP_INTERFACE:
  668. status = 0;
  669. break;
  670. case USB_RECIP_ENDPOINT:
  671. ep = w_index & USB_ENDPOINT_NUMBER_MASK;
  672. if (ep) {
  673. if (fusb300_get_epnstall(fusb300, ep))
  674. status = 1 << USB_ENDPOINT_HALT;
  675. } else {
  676. if (fusb300_get_cxstall(fusb300))
  677. status = 0;
  678. }
  679. break;
  680. default:
  681. request_error(fusb300);
  682. return; /* exit */
  683. }
  684. fusb300->ep0_data = cpu_to_le16(status);
  685. fusb300->ep0_req->buf = &fusb300->ep0_data;
  686. fusb300->ep0_req->length = 2;
  687. spin_unlock(&fusb300->lock);
  688. fusb300_queue(fusb300->gadget.ep0, fusb300->ep0_req, GFP_KERNEL);
  689. spin_lock(&fusb300->lock);
  690. }
  691. static void set_feature(struct fusb300 *fusb300, struct usb_ctrlrequest *ctrl)
  692. {
  693. u8 ep;
  694. switch (ctrl->bRequestType & USB_RECIP_MASK) {
  695. case USB_RECIP_DEVICE:
  696. fusb300_set_cxdone(fusb300);
  697. break;
  698. case USB_RECIP_INTERFACE:
  699. fusb300_set_cxdone(fusb300);
  700. break;
  701. case USB_RECIP_ENDPOINT: {
  702. u16 w_index = le16_to_cpu(ctrl->wIndex);
  703. ep = w_index & USB_ENDPOINT_NUMBER_MASK;
  704. if (ep)
  705. fusb300_set_epnstall(fusb300, ep);
  706. else
  707. fusb300_set_cxstall(fusb300);
  708. fusb300_set_cxdone(fusb300);
  709. }
  710. break;
  711. default:
  712. request_error(fusb300);
  713. break;
  714. }
  715. }
  716. static void fusb300_clear_seqnum(struct fusb300 *fusb300, u8 ep)
  717. {
  718. fusb300_enable_bit(fusb300, FUSB300_OFFSET_EPSET0(ep),
  719. FUSB300_EPSET0_CLRSEQNUM);
  720. }
  721. static void clear_feature(struct fusb300 *fusb300, struct usb_ctrlrequest *ctrl)
  722. {
  723. struct fusb300_ep *ep =
  724. fusb300->ep[ctrl->wIndex & USB_ENDPOINT_NUMBER_MASK];
  725. switch (ctrl->bRequestType & USB_RECIP_MASK) {
  726. case USB_RECIP_DEVICE:
  727. fusb300_set_cxdone(fusb300);
  728. break;
  729. case USB_RECIP_INTERFACE:
  730. fusb300_set_cxdone(fusb300);
  731. break;
  732. case USB_RECIP_ENDPOINT:
  733. if (ctrl->wIndex & USB_ENDPOINT_NUMBER_MASK) {
  734. if (ep->wedged) {
  735. fusb300_set_cxdone(fusb300);
  736. break;
  737. }
  738. if (ep->stall) {
  739. ep->stall = 0;
  740. fusb300_clear_seqnum(fusb300, ep->epnum);
  741. fusb300_clear_epnstall(fusb300, ep->epnum);
  742. if (!list_empty(&ep->queue))
  743. enable_fifo_int(ep);
  744. }
  745. }
  746. fusb300_set_cxdone(fusb300);
  747. break;
  748. default:
  749. request_error(fusb300);
  750. break;
  751. }
  752. }
  753. static void fusb300_set_dev_addr(struct fusb300 *fusb300, u16 addr)
  754. {
  755. u32 reg = ioread32(fusb300->reg + FUSB300_OFFSET_DAR);
  756. reg &= ~FUSB300_DAR_DRVADDR_MSK;
  757. reg |= FUSB300_DAR_DRVADDR(addr);
  758. iowrite32(reg, fusb300->reg + FUSB300_OFFSET_DAR);
  759. }
  760. static void set_address(struct fusb300 *fusb300, struct usb_ctrlrequest *ctrl)
  761. {
  762. if (ctrl->wValue >= 0x0100)
  763. request_error(fusb300);
  764. else {
  765. fusb300_set_dev_addr(fusb300, ctrl->wValue);
  766. fusb300_set_cxdone(fusb300);
  767. }
  768. }
  769. #define UVC_COPY_DESCRIPTORS(mem, src) \
  770. do { \
  771. const struct usb_descriptor_header * const *__src; \
  772. for (__src = src; *__src; ++__src) { \
  773. memcpy(mem, *__src, (*__src)->bLength); \
  774. mem += (*__src)->bLength; \
  775. } \
  776. } while (0)
  777. static int setup_packet(struct fusb300 *fusb300, struct usb_ctrlrequest *ctrl)
  778. {
  779. u8 *p = (u8 *)ctrl;
  780. u8 ret = 0;
  781. u8 i = 0;
  782. fusb300_rdcxf(fusb300, p, 8);
  783. fusb300->ep0_dir = ctrl->bRequestType & USB_DIR_IN;
  784. fusb300->ep0_length = ctrl->wLength;
  785. /* check request */
  786. if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
  787. switch (ctrl->bRequest) {
  788. case USB_REQ_GET_STATUS:
  789. get_status(fusb300, ctrl);
  790. break;
  791. case USB_REQ_CLEAR_FEATURE:
  792. clear_feature(fusb300, ctrl);
  793. break;
  794. case USB_REQ_SET_FEATURE:
  795. set_feature(fusb300, ctrl);
  796. break;
  797. case USB_REQ_SET_ADDRESS:
  798. set_address(fusb300, ctrl);
  799. break;
  800. case USB_REQ_SET_CONFIGURATION:
  801. fusb300_enable_bit(fusb300, FUSB300_OFFSET_DAR,
  802. FUSB300_DAR_SETCONFG);
  803. /* clear sequence number */
  804. for (i = 1; i <= FUSB300_MAX_NUM_EP; i++)
  805. fusb300_clear_seqnum(fusb300, i);
  806. fusb300->reenum = 1;
  807. ret = 1;
  808. break;
  809. default:
  810. ret = 1;
  811. break;
  812. }
  813. } else
  814. ret = 1;
  815. return ret;
  816. }
  817. static void done(struct fusb300_ep *ep, struct fusb300_request *req,
  818. int status)
  819. {
  820. list_del_init(&req->queue);
  821. /* don't modify queue heads during completion callback */
  822. if (ep->fusb300->gadget.speed == USB_SPEED_UNKNOWN)
  823. req->req.status = -ESHUTDOWN;
  824. else
  825. req->req.status = status;
  826. spin_unlock(&ep->fusb300->lock);
  827. req->req.complete(&ep->ep, &req->req);
  828. spin_lock(&ep->fusb300->lock);
  829. if (ep->epnum) {
  830. disable_fifo_int(ep);
  831. if (!list_empty(&ep->queue))
  832. enable_fifo_int(ep);
  833. } else
  834. fusb300_set_cxdone(ep->fusb300);
  835. }
  836. static void fusb300_fill_idma_prdtbl(struct fusb300_ep *ep, dma_addr_t d,
  837. u32 len)
  838. {
  839. u32 value;
  840. u32 reg;
  841. /* wait SW owner */
  842. do {
  843. reg = ioread32(ep->fusb300->reg +
  844. FUSB300_OFFSET_EPPRD_W0(ep->epnum));
  845. reg &= FUSB300_EPPRD0_H;
  846. } while (reg);
  847. iowrite32(d, ep->fusb300->reg + FUSB300_OFFSET_EPPRD_W1(ep->epnum));
  848. value = FUSB300_EPPRD0_BTC(len) | FUSB300_EPPRD0_H |
  849. FUSB300_EPPRD0_F | FUSB300_EPPRD0_L | FUSB300_EPPRD0_I;
  850. iowrite32(value, ep->fusb300->reg + FUSB300_OFFSET_EPPRD_W0(ep->epnum));
  851. iowrite32(0x0, ep->fusb300->reg + FUSB300_OFFSET_EPPRD_W2(ep->epnum));
  852. fusb300_enable_bit(ep->fusb300, FUSB300_OFFSET_EPPRDRDY,
  853. FUSB300_EPPRDR_EP_PRD_RDY(ep->epnum));
  854. }
  855. static void fusb300_wait_idma_finished(struct fusb300_ep *ep)
  856. {
  857. u32 reg;
  858. do {
  859. reg = ioread32(ep->fusb300->reg + FUSB300_OFFSET_IGR1);
  860. if ((reg & FUSB300_IGR1_VBUS_CHG_INT) ||
  861. (reg & FUSB300_IGR1_WARM_RST_INT) ||
  862. (reg & FUSB300_IGR1_HOT_RST_INT) ||
  863. (reg & FUSB300_IGR1_USBRST_INT)
  864. )
  865. goto IDMA_RESET;
  866. reg = ioread32(ep->fusb300->reg + FUSB300_OFFSET_IGR0);
  867. reg &= FUSB300_IGR0_EPn_PRD_INT(ep->epnum);
  868. } while (!reg);
  869. fusb300_clear_int(ep->fusb300, FUSB300_OFFSET_IGR0,
  870. FUSB300_IGR0_EPn_PRD_INT(ep->epnum));
  871. IDMA_RESET:
  872. fusb300_clear_int(ep->fusb300, FUSB300_OFFSET_IGER0,
  873. FUSB300_IGER0_EEPn_PRD_INT(ep->epnum));
  874. }
  875. static void fusb300_set_idma(struct fusb300_ep *ep,
  876. struct fusb300_request *req)
  877. {
  878. dma_addr_t d;
  879. d = dma_map_single(NULL, req->req.buf, req->req.length, DMA_TO_DEVICE);
  880. if (dma_mapping_error(NULL, d)) {
  881. printk(KERN_DEBUG "dma_mapping_error\n");
  882. return;
  883. }
  884. dma_sync_single_for_device(NULL, d, req->req.length, DMA_TO_DEVICE);
  885. fusb300_enable_bit(ep->fusb300, FUSB300_OFFSET_IGER0,
  886. FUSB300_IGER0_EEPn_PRD_INT(ep->epnum));
  887. fusb300_fill_idma_prdtbl(ep, d, req->req.length);
  888. /* check idma is done */
  889. fusb300_wait_idma_finished(ep);
  890. dma_unmap_single(NULL, d, req->req.length, DMA_TO_DEVICE);
  891. }
  892. static void in_ep_fifo_handler(struct fusb300_ep *ep)
  893. {
  894. struct fusb300_request *req = list_entry(ep->queue.next,
  895. struct fusb300_request, queue);
  896. if (req->req.length)
  897. fusb300_set_idma(ep, req);
  898. done(ep, req, 0);
  899. }
  900. static void out_ep_fifo_handler(struct fusb300_ep *ep)
  901. {
  902. struct fusb300 *fusb300 = ep->fusb300;
  903. struct fusb300_request *req = list_entry(ep->queue.next,
  904. struct fusb300_request, queue);
  905. u32 reg = ioread32(fusb300->reg + FUSB300_OFFSET_EPFFR(ep->epnum));
  906. u32 length = reg & FUSB300_FFR_BYCNT;
  907. fusb300_rdfifo(ep, req, length);
  908. /* finish out transfer */
  909. if ((req->req.length == req->req.actual) || (length < ep->ep.maxpacket))
  910. done(ep, req, 0);
  911. }
  912. static void check_device_mode(struct fusb300 *fusb300)
  913. {
  914. u32 reg = ioread32(fusb300->reg + FUSB300_OFFSET_GCR);
  915. switch (reg & FUSB300_GCR_DEVEN_MSK) {
  916. case FUSB300_GCR_DEVEN_SS:
  917. fusb300->gadget.speed = USB_SPEED_SUPER;
  918. break;
  919. case FUSB300_GCR_DEVEN_HS:
  920. fusb300->gadget.speed = USB_SPEED_HIGH;
  921. break;
  922. case FUSB300_GCR_DEVEN_FS:
  923. fusb300->gadget.speed = USB_SPEED_FULL;
  924. break;
  925. default:
  926. fusb300->gadget.speed = USB_SPEED_UNKNOWN;
  927. break;
  928. }
  929. printk(KERN_INFO "dev_mode = %d\n", (reg & FUSB300_GCR_DEVEN_MSK));
  930. }
  931. static void fusb300_ep0out(struct fusb300 *fusb300)
  932. {
  933. struct fusb300_ep *ep = fusb300->ep[0];
  934. u32 reg;
  935. if (!list_empty(&ep->queue)) {
  936. struct fusb300_request *req;
  937. req = list_first_entry(&ep->queue,
  938. struct fusb300_request, queue);
  939. if (req->req.length)
  940. fusb300_rdcxf(ep->fusb300, req->req.buf,
  941. req->req.length);
  942. done(ep, req, 0);
  943. reg = ioread32(fusb300->reg + FUSB300_OFFSET_IGER1);
  944. reg &= ~FUSB300_IGER1_CX_OUT_INT;
  945. iowrite32(reg, fusb300->reg + FUSB300_OFFSET_IGER1);
  946. } else
  947. pr_err("%s : empty queue\n", __func__);
  948. }
  949. static void fusb300_ep0in(struct fusb300 *fusb300)
  950. {
  951. struct fusb300_request *req;
  952. struct fusb300_ep *ep = fusb300->ep[0];
  953. if ((!list_empty(&ep->queue)) && (fusb300->ep0_dir)) {
  954. req = list_entry(ep->queue.next,
  955. struct fusb300_request, queue);
  956. if (req->req.length)
  957. fusb300_wrcxf(ep, req);
  958. if ((req->req.length - req->req.actual) < ep->ep.maxpacket)
  959. done(ep, req, 0);
  960. } else
  961. fusb300_set_cxdone(fusb300);
  962. }
  963. static void fusb300_grp2_handler(void)
  964. {
  965. }
  966. static void fusb300_grp3_handler(void)
  967. {
  968. }
  969. static void fusb300_grp4_handler(void)
  970. {
  971. }
  972. static void fusb300_grp5_handler(void)
  973. {
  974. }
  975. static irqreturn_t fusb300_irq(int irq, void *_fusb300)
  976. {
  977. struct fusb300 *fusb300 = _fusb300;
  978. u32 int_grp1 = ioread32(fusb300->reg + FUSB300_OFFSET_IGR1);
  979. u32 int_grp1_en = ioread32(fusb300->reg + FUSB300_OFFSET_IGER1);
  980. u32 int_grp0 = ioread32(fusb300->reg + FUSB300_OFFSET_IGR0);
  981. u32 int_grp0_en = ioread32(fusb300->reg + FUSB300_OFFSET_IGER0);
  982. struct usb_ctrlrequest ctrl;
  983. u8 in;
  984. u32 reg;
  985. int i;
  986. spin_lock(&fusb300->lock);
  987. int_grp1 &= int_grp1_en;
  988. int_grp0 &= int_grp0_en;
  989. if (int_grp1 & FUSB300_IGR1_WARM_RST_INT) {
  990. fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1,
  991. FUSB300_IGR1_WARM_RST_INT);
  992. printk(KERN_INFO"fusb300_warmreset\n");
  993. fusb300_reset();
  994. }
  995. if (int_grp1 & FUSB300_IGR1_HOT_RST_INT) {
  996. fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1,
  997. FUSB300_IGR1_HOT_RST_INT);
  998. printk(KERN_INFO"fusb300_hotreset\n");
  999. fusb300_reset();
  1000. }
  1001. if (int_grp1 & FUSB300_IGR1_USBRST_INT) {
  1002. fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1,
  1003. FUSB300_IGR1_USBRST_INT);
  1004. fusb300_reset();
  1005. }
  1006. /* COMABT_INT has a highest priority */
  1007. if (int_grp1 & FUSB300_IGR1_CX_COMABT_INT) {
  1008. fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1,
  1009. FUSB300_IGR1_CX_COMABT_INT);
  1010. printk(KERN_INFO"fusb300_ep0abt\n");
  1011. }
  1012. if (int_grp1 & FUSB300_IGR1_VBUS_CHG_INT) {
  1013. fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1,
  1014. FUSB300_IGR1_VBUS_CHG_INT);
  1015. printk(KERN_INFO"fusb300_vbus_change\n");
  1016. }
  1017. if (int_grp1 & FUSB300_IGR1_U3_EXIT_FAIL_INT) {
  1018. fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1,
  1019. FUSB300_IGR1_U3_EXIT_FAIL_INT);
  1020. }
  1021. if (int_grp1 & FUSB300_IGR1_U2_EXIT_FAIL_INT) {
  1022. fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1,
  1023. FUSB300_IGR1_U2_EXIT_FAIL_INT);
  1024. }
  1025. if (int_grp1 & FUSB300_IGR1_U1_EXIT_FAIL_INT) {
  1026. fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1,
  1027. FUSB300_IGR1_U1_EXIT_FAIL_INT);
  1028. }
  1029. if (int_grp1 & FUSB300_IGR1_U2_ENTRY_FAIL_INT) {
  1030. fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1,
  1031. FUSB300_IGR1_U2_ENTRY_FAIL_INT);
  1032. }
  1033. if (int_grp1 & FUSB300_IGR1_U1_ENTRY_FAIL_INT) {
  1034. fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1,
  1035. FUSB300_IGR1_U1_ENTRY_FAIL_INT);
  1036. }
  1037. if (int_grp1 & FUSB300_IGR1_U3_EXIT_INT) {
  1038. fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1,
  1039. FUSB300_IGR1_U3_EXIT_INT);
  1040. printk(KERN_INFO "FUSB300_IGR1_U3_EXIT_INT\n");
  1041. }
  1042. if (int_grp1 & FUSB300_IGR1_U2_EXIT_INT) {
  1043. fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1,
  1044. FUSB300_IGR1_U2_EXIT_INT);
  1045. printk(KERN_INFO "FUSB300_IGR1_U2_EXIT_INT\n");
  1046. }
  1047. if (int_grp1 & FUSB300_IGR1_U1_EXIT_INT) {
  1048. fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1,
  1049. FUSB300_IGR1_U1_EXIT_INT);
  1050. printk(KERN_INFO "FUSB300_IGR1_U1_EXIT_INT\n");
  1051. }
  1052. if (int_grp1 & FUSB300_IGR1_U3_ENTRY_INT) {
  1053. fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1,
  1054. FUSB300_IGR1_U3_ENTRY_INT);
  1055. printk(KERN_INFO "FUSB300_IGR1_U3_ENTRY_INT\n");
  1056. fusb300_enable_bit(fusb300, FUSB300_OFFSET_SSCR1,
  1057. FUSB300_SSCR1_GO_U3_DONE);
  1058. }
  1059. if (int_grp1 & FUSB300_IGR1_U2_ENTRY_INT) {
  1060. fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1,
  1061. FUSB300_IGR1_U2_ENTRY_INT);
  1062. printk(KERN_INFO "FUSB300_IGR1_U2_ENTRY_INT\n");
  1063. }
  1064. if (int_grp1 & FUSB300_IGR1_U1_ENTRY_INT) {
  1065. fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1,
  1066. FUSB300_IGR1_U1_ENTRY_INT);
  1067. printk(KERN_INFO "FUSB300_IGR1_U1_ENTRY_INT\n");
  1068. }
  1069. if (int_grp1 & FUSB300_IGR1_RESM_INT) {
  1070. fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1,
  1071. FUSB300_IGR1_RESM_INT);
  1072. printk(KERN_INFO "fusb300_resume\n");
  1073. }
  1074. if (int_grp1 & FUSB300_IGR1_SUSP_INT) {
  1075. fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1,
  1076. FUSB300_IGR1_SUSP_INT);
  1077. printk(KERN_INFO "fusb300_suspend\n");
  1078. }
  1079. if (int_grp1 & FUSB300_IGR1_HS_LPM_INT) {
  1080. fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1,
  1081. FUSB300_IGR1_HS_LPM_INT);
  1082. printk(KERN_INFO "fusb300_HS_LPM_INT\n");
  1083. }
  1084. if (int_grp1 & FUSB300_IGR1_DEV_MODE_CHG_INT) {
  1085. fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1,
  1086. FUSB300_IGR1_DEV_MODE_CHG_INT);
  1087. check_device_mode(fusb300);
  1088. }
  1089. if (int_grp1 & FUSB300_IGR1_CX_COMFAIL_INT) {
  1090. fusb300_set_cxstall(fusb300);
  1091. printk(KERN_INFO "fusb300_ep0fail\n");
  1092. }
  1093. if (int_grp1 & FUSB300_IGR1_CX_SETUP_INT) {
  1094. printk(KERN_INFO "fusb300_ep0setup\n");
  1095. if (setup_packet(fusb300, &ctrl)) {
  1096. spin_unlock(&fusb300->lock);
  1097. if (fusb300->driver->setup(&fusb300->gadget, &ctrl) < 0)
  1098. fusb300_set_cxstall(fusb300);
  1099. spin_lock(&fusb300->lock);
  1100. }
  1101. }
  1102. if (int_grp1 & FUSB300_IGR1_CX_CMDEND_INT)
  1103. printk(KERN_INFO "fusb300_cmdend\n");
  1104. if (int_grp1 & FUSB300_IGR1_CX_OUT_INT) {
  1105. printk(KERN_INFO "fusb300_cxout\n");
  1106. fusb300_ep0out(fusb300);
  1107. }
  1108. if (int_grp1 & FUSB300_IGR1_CX_IN_INT) {
  1109. printk(KERN_INFO "fusb300_cxin\n");
  1110. fusb300_ep0in(fusb300);
  1111. }
  1112. if (int_grp1 & FUSB300_IGR1_INTGRP5)
  1113. fusb300_grp5_handler();
  1114. if (int_grp1 & FUSB300_IGR1_INTGRP4)
  1115. fusb300_grp4_handler();
  1116. if (int_grp1 & FUSB300_IGR1_INTGRP3)
  1117. fusb300_grp3_handler();
  1118. if (int_grp1 & FUSB300_IGR1_INTGRP2)
  1119. fusb300_grp2_handler();
  1120. if (int_grp0) {
  1121. for (i = 1; i < FUSB300_MAX_NUM_EP; i++) {
  1122. if (int_grp0 & FUSB300_IGR0_EPn_FIFO_INT(i)) {
  1123. reg = ioread32(fusb300->reg +
  1124. FUSB300_OFFSET_EPSET1(i));
  1125. in = (reg & FUSB300_EPSET1_DIRIN) ? 1 : 0;
  1126. if (in)
  1127. in_ep_fifo_handler(fusb300->ep[i]);
  1128. else
  1129. out_ep_fifo_handler(fusb300->ep[i]);
  1130. }
  1131. }
  1132. }
  1133. spin_unlock(&fusb300->lock);
  1134. return IRQ_HANDLED;
  1135. }
  1136. static void fusb300_set_u2_timeout(struct fusb300 *fusb300,
  1137. u32 time)
  1138. {
  1139. u32 reg;
  1140. reg = ioread32(fusb300->reg + FUSB300_OFFSET_TT);
  1141. reg &= ~0xff;
  1142. reg |= FUSB300_SSCR2_U2TIMEOUT(time);
  1143. iowrite32(reg, fusb300->reg + FUSB300_OFFSET_TT);
  1144. }
  1145. static void fusb300_set_u1_timeout(struct fusb300 *fusb300,
  1146. u32 time)
  1147. {
  1148. u32 reg;
  1149. reg = ioread32(fusb300->reg + FUSB300_OFFSET_TT);
  1150. reg &= ~(0xff << 8);
  1151. reg |= FUSB300_SSCR2_U1TIMEOUT(time);
  1152. iowrite32(reg, fusb300->reg + FUSB300_OFFSET_TT);
  1153. }
  1154. static void init_controller(struct fusb300 *fusb300)
  1155. {
  1156. u32 reg;
  1157. u32 mask = 0;
  1158. u32 val = 0;
  1159. /* split on */
  1160. mask = val = FUSB300_AHBBCR_S0_SPLIT_ON | FUSB300_AHBBCR_S1_SPLIT_ON;
  1161. reg = ioread32(fusb300->reg + FUSB300_OFFSET_AHBCR);
  1162. reg &= ~mask;
  1163. reg |= val;
  1164. iowrite32(reg, fusb300->reg + FUSB300_OFFSET_AHBCR);
  1165. /* enable high-speed LPM */
  1166. mask = val = FUSB300_HSCR_HS_LPM_PERMIT;
  1167. reg = ioread32(fusb300->reg + FUSB300_OFFSET_HSCR);
  1168. reg &= ~mask;
  1169. reg |= val;
  1170. iowrite32(reg, fusb300->reg + FUSB300_OFFSET_HSCR);
  1171. /*set u1 u2 timmer*/
  1172. fusb300_set_u2_timeout(fusb300, 0xff);
  1173. fusb300_set_u1_timeout(fusb300, 0xff);
  1174. /* enable all grp1 interrupt */
  1175. iowrite32(0xcfffff9f, fusb300->reg + FUSB300_OFFSET_IGER1);
  1176. }
  1177. /*------------------------------------------------------------------------*/
  1178. static struct fusb300 *the_controller;
  1179. static int fusb300_udc_start(struct usb_gadget_driver *driver,
  1180. int (*bind)(struct usb_gadget *))
  1181. {
  1182. struct fusb300 *fusb300 = the_controller;
  1183. int retval;
  1184. if (!driver
  1185. || driver->speed < USB_SPEED_FULL
  1186. || !bind
  1187. || !driver->setup)
  1188. return -EINVAL;
  1189. if (!fusb300)
  1190. return -ENODEV;
  1191. if (fusb300->driver)
  1192. return -EBUSY;
  1193. /* hook up the driver */
  1194. driver->driver.bus = NULL;
  1195. fusb300->driver = driver;
  1196. fusb300->gadget.dev.driver = &driver->driver;
  1197. retval = device_add(&fusb300->gadget.dev);
  1198. if (retval) {
  1199. pr_err("device_add error (%d)\n", retval);
  1200. goto error;
  1201. }
  1202. retval = bind(&fusb300->gadget);
  1203. if (retval) {
  1204. pr_err("bind to driver error (%d)\n", retval);
  1205. device_del(&fusb300->gadget.dev);
  1206. goto error;
  1207. }
  1208. return 0;
  1209. error:
  1210. fusb300->driver = NULL;
  1211. fusb300->gadget.dev.driver = NULL;
  1212. return retval;
  1213. }
  1214. static int fusb300_udc_stop(struct usb_gadget_driver *driver)
  1215. {
  1216. struct fusb300 *fusb300 = the_controller;
  1217. if (driver != fusb300->driver || !driver->unbind)
  1218. return -EINVAL;
  1219. driver->unbind(&fusb300->gadget);
  1220. fusb300->gadget.dev.driver = NULL;
  1221. init_controller(fusb300);
  1222. device_del(&fusb300->gadget.dev);
  1223. fusb300->driver = NULL;
  1224. return 0;
  1225. }
  1226. /*--------------------------------------------------------------------------*/
  1227. static int fusb300_udc_pullup(struct usb_gadget *_gadget, int is_active)
  1228. {
  1229. return 0;
  1230. }
  1231. static struct usb_gadget_ops fusb300_gadget_ops = {
  1232. .pullup = fusb300_udc_pullup,
  1233. .start = fusb300_udc_start,
  1234. .stop = fusb300_udc_stop,
  1235. };
  1236. static int __exit fusb300_remove(struct platform_device *pdev)
  1237. {
  1238. struct fusb300 *fusb300 = dev_get_drvdata(&pdev->dev);
  1239. usb_del_gadget_udc(&fusb300->gadget);
  1240. iounmap(fusb300->reg);
  1241. free_irq(platform_get_irq(pdev, 0), fusb300);
  1242. fusb300_free_request(&fusb300->ep[0]->ep, fusb300->ep0_req);
  1243. kfree(fusb300);
  1244. return 0;
  1245. }
  1246. static int __init fusb300_probe(struct platform_device *pdev)
  1247. {
  1248. struct resource *res, *ires, *ires1;
  1249. void __iomem *reg = NULL;
  1250. struct fusb300 *fusb300 = NULL;
  1251. struct fusb300_ep *_ep[FUSB300_MAX_NUM_EP];
  1252. int ret = 0;
  1253. int i;
  1254. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1255. if (!res) {
  1256. ret = -ENODEV;
  1257. pr_err("platform_get_resource error.\n");
  1258. goto clean_up;
  1259. }
  1260. ires = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
  1261. if (!ires) {
  1262. ret = -ENODEV;
  1263. dev_err(&pdev->dev,
  1264. "platform_get_resource IORESOURCE_IRQ error.\n");
  1265. goto clean_up;
  1266. }
  1267. ires1 = platform_get_resource(pdev, IORESOURCE_IRQ, 1);
  1268. if (!ires1) {
  1269. ret = -ENODEV;
  1270. dev_err(&pdev->dev,
  1271. "platform_get_resource IORESOURCE_IRQ 1 error.\n");
  1272. goto clean_up;
  1273. }
  1274. reg = ioremap(res->start, resource_size(res));
  1275. if (reg == NULL) {
  1276. ret = -ENOMEM;
  1277. pr_err("ioremap error.\n");
  1278. goto clean_up;
  1279. }
  1280. /* initialize udc */
  1281. fusb300 = kzalloc(sizeof(struct fusb300), GFP_KERNEL);
  1282. if (fusb300 == NULL) {
  1283. pr_err("kzalloc error\n");
  1284. goto clean_up;
  1285. }
  1286. for (i = 0; i < FUSB300_MAX_NUM_EP; i++) {
  1287. _ep[i] = kzalloc(sizeof(struct fusb300_ep), GFP_KERNEL);
  1288. if (_ep[i] == NULL) {
  1289. pr_err("_ep kzalloc error\n");
  1290. goto clean_up;
  1291. }
  1292. fusb300->ep[i] = _ep[i];
  1293. }
  1294. spin_lock_init(&fusb300->lock);
  1295. dev_set_drvdata(&pdev->dev, fusb300);
  1296. fusb300->gadget.ops = &fusb300_gadget_ops;
  1297. device_initialize(&fusb300->gadget.dev);
  1298. dev_set_name(&fusb300->gadget.dev, "gadget");
  1299. fusb300->gadget.is_dualspeed = 1;
  1300. fusb300->gadget.dev.parent = &pdev->dev;
  1301. fusb300->gadget.dev.dma_mask = pdev->dev.dma_mask;
  1302. fusb300->gadget.dev.release = pdev->dev.release;
  1303. fusb300->gadget.name = udc_name;
  1304. fusb300->reg = reg;
  1305. ret = request_irq(ires->start, fusb300_irq, IRQF_DISABLED | IRQF_SHARED,
  1306. udc_name, fusb300);
  1307. if (ret < 0) {
  1308. pr_err("request_irq error (%d)\n", ret);
  1309. goto clean_up;
  1310. }
  1311. ret = request_irq(ires1->start, fusb300_irq,
  1312. IRQF_DISABLED | IRQF_SHARED, udc_name, fusb300);
  1313. if (ret < 0) {
  1314. pr_err("request_irq1 error (%d)\n", ret);
  1315. goto clean_up;
  1316. }
  1317. INIT_LIST_HEAD(&fusb300->gadget.ep_list);
  1318. for (i = 0; i < FUSB300_MAX_NUM_EP ; i++) {
  1319. struct fusb300_ep *ep = fusb300->ep[i];
  1320. if (i != 0) {
  1321. INIT_LIST_HEAD(&fusb300->ep[i]->ep.ep_list);
  1322. list_add_tail(&fusb300->ep[i]->ep.ep_list,
  1323. &fusb300->gadget.ep_list);
  1324. }
  1325. ep->fusb300 = fusb300;
  1326. INIT_LIST_HEAD(&ep->queue);
  1327. ep->ep.name = fusb300_ep_name[i];
  1328. ep->ep.ops = &fusb300_ep_ops;
  1329. ep->ep.maxpacket = HS_BULK_MAX_PACKET_SIZE;
  1330. }
  1331. fusb300->ep[0]->ep.maxpacket = HS_CTL_MAX_PACKET_SIZE;
  1332. fusb300->ep[0]->epnum = 0;
  1333. fusb300->gadget.ep0 = &fusb300->ep[0]->ep;
  1334. INIT_LIST_HEAD(&fusb300->gadget.ep0->ep_list);
  1335. the_controller = fusb300;
  1336. fusb300->ep0_req = fusb300_alloc_request(&fusb300->ep[0]->ep,
  1337. GFP_KERNEL);
  1338. if (fusb300->ep0_req == NULL)
  1339. goto clean_up3;
  1340. init_controller(fusb300);
  1341. ret = usb_add_gadget_udc(&pdev->dev, &fusb300->gadget);
  1342. if (ret)
  1343. goto err_add_udc;
  1344. dev_info(&pdev->dev, "version %s\n", DRIVER_VERSION);
  1345. return 0;
  1346. err_add_udc:
  1347. fusb300_free_request(&fusb300->ep[0]->ep, fusb300->ep0_req);
  1348. clean_up3:
  1349. free_irq(ires->start, fusb300);
  1350. clean_up:
  1351. if (fusb300) {
  1352. if (fusb300->ep0_req)
  1353. fusb300_free_request(&fusb300->ep[0]->ep,
  1354. fusb300->ep0_req);
  1355. kfree(fusb300);
  1356. }
  1357. if (reg)
  1358. iounmap(reg);
  1359. return ret;
  1360. }
  1361. static struct platform_driver fusb300_driver = {
  1362. .remove = __exit_p(fusb300_remove),
  1363. .driver = {
  1364. .name = (char *) udc_name,
  1365. .owner = THIS_MODULE,
  1366. },
  1367. };
  1368. static int __init fusb300_udc_init(void)
  1369. {
  1370. return platform_driver_probe(&fusb300_driver, fusb300_probe);
  1371. }
  1372. module_init(fusb300_udc_init);
  1373. static void __exit fusb300_udc_cleanup(void)
  1374. {
  1375. platform_driver_unregister(&fusb300_driver);
  1376. }
  1377. module_exit(fusb300_udc_cleanup);