mv_sas.c 57 KB

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  1. /*
  2. * Marvell 88SE64xx/88SE94xx main function
  3. *
  4. * Copyright 2007 Red Hat, Inc.
  5. * Copyright 2008 Marvell. <kewei@marvell.com>
  6. * Copyright 2009-2011 Marvell. <yuxiangl@marvell.com>
  7. *
  8. * This file is licensed under GPLv2.
  9. *
  10. * This program is free software; you can redistribute it and/or
  11. * modify it under the terms of the GNU General Public License as
  12. * published by the Free Software Foundation; version 2 of the
  13. * License.
  14. *
  15. * This program is distributed in the hope that it will be useful,
  16. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  18. * General Public License for more details.
  19. *
  20. * You should have received a copy of the GNU General Public License
  21. * along with this program; if not, write to the Free Software
  22. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
  23. * USA
  24. */
  25. #include "mv_sas.h"
  26. static int mvs_find_tag(struct mvs_info *mvi, struct sas_task *task, u32 *tag)
  27. {
  28. if (task->lldd_task) {
  29. struct mvs_slot_info *slot;
  30. slot = task->lldd_task;
  31. *tag = slot->slot_tag;
  32. return 1;
  33. }
  34. return 0;
  35. }
  36. void mvs_tag_clear(struct mvs_info *mvi, u32 tag)
  37. {
  38. void *bitmap = mvi->tags;
  39. clear_bit(tag, bitmap);
  40. }
  41. void mvs_tag_free(struct mvs_info *mvi, u32 tag)
  42. {
  43. mvs_tag_clear(mvi, tag);
  44. }
  45. void mvs_tag_set(struct mvs_info *mvi, unsigned int tag)
  46. {
  47. void *bitmap = mvi->tags;
  48. set_bit(tag, bitmap);
  49. }
  50. inline int mvs_tag_alloc(struct mvs_info *mvi, u32 *tag_out)
  51. {
  52. unsigned int index, tag;
  53. void *bitmap = mvi->tags;
  54. index = find_first_zero_bit(bitmap, mvi->tags_num);
  55. tag = index;
  56. if (tag >= mvi->tags_num)
  57. return -SAS_QUEUE_FULL;
  58. mvs_tag_set(mvi, tag);
  59. *tag_out = tag;
  60. return 0;
  61. }
  62. void mvs_tag_init(struct mvs_info *mvi)
  63. {
  64. int i;
  65. for (i = 0; i < mvi->tags_num; ++i)
  66. mvs_tag_clear(mvi, i);
  67. }
  68. struct mvs_info *mvs_find_dev_mvi(struct domain_device *dev)
  69. {
  70. unsigned long i = 0, j = 0, hi = 0;
  71. struct sas_ha_struct *sha = dev->port->ha;
  72. struct mvs_info *mvi = NULL;
  73. struct asd_sas_phy *phy;
  74. while (sha->sas_port[i]) {
  75. if (sha->sas_port[i] == dev->port) {
  76. phy = container_of(sha->sas_port[i]->phy_list.next,
  77. struct asd_sas_phy, port_phy_el);
  78. j = 0;
  79. while (sha->sas_phy[j]) {
  80. if (sha->sas_phy[j] == phy)
  81. break;
  82. j++;
  83. }
  84. break;
  85. }
  86. i++;
  87. }
  88. hi = j/((struct mvs_prv_info *)sha->lldd_ha)->n_phy;
  89. mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[hi];
  90. return mvi;
  91. }
  92. int mvs_find_dev_phyno(struct domain_device *dev, int *phyno)
  93. {
  94. unsigned long i = 0, j = 0, n = 0, num = 0;
  95. struct mvs_device *mvi_dev = (struct mvs_device *)dev->lldd_dev;
  96. struct mvs_info *mvi = mvi_dev->mvi_info;
  97. struct sas_ha_struct *sha = dev->port->ha;
  98. while (sha->sas_port[i]) {
  99. if (sha->sas_port[i] == dev->port) {
  100. struct asd_sas_phy *phy;
  101. list_for_each_entry(phy,
  102. &sha->sas_port[i]->phy_list, port_phy_el) {
  103. j = 0;
  104. while (sha->sas_phy[j]) {
  105. if (sha->sas_phy[j] == phy)
  106. break;
  107. j++;
  108. }
  109. phyno[n] = (j >= mvi->chip->n_phy) ?
  110. (j - mvi->chip->n_phy) : j;
  111. num++;
  112. n++;
  113. }
  114. break;
  115. }
  116. i++;
  117. }
  118. return num;
  119. }
  120. struct mvs_device *mvs_find_dev_by_reg_set(struct mvs_info *mvi,
  121. u8 reg_set)
  122. {
  123. u32 dev_no;
  124. for (dev_no = 0; dev_no < MVS_MAX_DEVICES; dev_no++) {
  125. if (mvi->devices[dev_no].taskfileset == MVS_ID_NOT_MAPPED)
  126. continue;
  127. if (mvi->devices[dev_no].taskfileset == reg_set)
  128. return &mvi->devices[dev_no];
  129. }
  130. return NULL;
  131. }
  132. static inline void mvs_free_reg_set(struct mvs_info *mvi,
  133. struct mvs_device *dev)
  134. {
  135. if (!dev) {
  136. mv_printk("device has been free.\n");
  137. return;
  138. }
  139. if (dev->taskfileset == MVS_ID_NOT_MAPPED)
  140. return;
  141. MVS_CHIP_DISP->free_reg_set(mvi, &dev->taskfileset);
  142. }
  143. static inline u8 mvs_assign_reg_set(struct mvs_info *mvi,
  144. struct mvs_device *dev)
  145. {
  146. if (dev->taskfileset != MVS_ID_NOT_MAPPED)
  147. return 0;
  148. return MVS_CHIP_DISP->assign_reg_set(mvi, &dev->taskfileset);
  149. }
  150. void mvs_phys_reset(struct mvs_info *mvi, u32 phy_mask, int hard)
  151. {
  152. u32 no;
  153. for_each_phy(phy_mask, phy_mask, no) {
  154. if (!(phy_mask & 1))
  155. continue;
  156. MVS_CHIP_DISP->phy_reset(mvi, no, hard);
  157. }
  158. }
  159. int mvs_phy_control(struct asd_sas_phy *sas_phy, enum phy_func func,
  160. void *funcdata)
  161. {
  162. int rc = 0, phy_id = sas_phy->id;
  163. u32 tmp, i = 0, hi;
  164. struct sas_ha_struct *sha = sas_phy->ha;
  165. struct mvs_info *mvi = NULL;
  166. while (sha->sas_phy[i]) {
  167. if (sha->sas_phy[i] == sas_phy)
  168. break;
  169. i++;
  170. }
  171. hi = i/((struct mvs_prv_info *)sha->lldd_ha)->n_phy;
  172. mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[hi];
  173. switch (func) {
  174. case PHY_FUNC_SET_LINK_RATE:
  175. MVS_CHIP_DISP->phy_set_link_rate(mvi, phy_id, funcdata);
  176. break;
  177. case PHY_FUNC_HARD_RESET:
  178. tmp = MVS_CHIP_DISP->read_phy_ctl(mvi, phy_id);
  179. if (tmp & PHY_RST_HARD)
  180. break;
  181. MVS_CHIP_DISP->phy_reset(mvi, phy_id, MVS_HARD_RESET);
  182. break;
  183. case PHY_FUNC_LINK_RESET:
  184. MVS_CHIP_DISP->phy_enable(mvi, phy_id);
  185. MVS_CHIP_DISP->phy_reset(mvi, phy_id, MVS_SOFT_RESET);
  186. break;
  187. case PHY_FUNC_DISABLE:
  188. MVS_CHIP_DISP->phy_disable(mvi, phy_id);
  189. break;
  190. case PHY_FUNC_RELEASE_SPINUP_HOLD:
  191. default:
  192. rc = -EOPNOTSUPP;
  193. }
  194. msleep(200);
  195. return rc;
  196. }
  197. void __devinit mvs_set_sas_addr(struct mvs_info *mvi, int port_id,
  198. u32 off_lo, u32 off_hi, u64 sas_addr)
  199. {
  200. u32 lo = (u32)sas_addr;
  201. u32 hi = (u32)(sas_addr>>32);
  202. MVS_CHIP_DISP->write_port_cfg_addr(mvi, port_id, off_lo);
  203. MVS_CHIP_DISP->write_port_cfg_data(mvi, port_id, lo);
  204. MVS_CHIP_DISP->write_port_cfg_addr(mvi, port_id, off_hi);
  205. MVS_CHIP_DISP->write_port_cfg_data(mvi, port_id, hi);
  206. }
  207. static void mvs_bytes_dmaed(struct mvs_info *mvi, int i)
  208. {
  209. struct mvs_phy *phy = &mvi->phy[i];
  210. struct asd_sas_phy *sas_phy = &phy->sas_phy;
  211. struct sas_ha_struct *sas_ha;
  212. if (!phy->phy_attached)
  213. return;
  214. if (!(phy->att_dev_info & PORT_DEV_TRGT_MASK)
  215. && phy->phy_type & PORT_TYPE_SAS) {
  216. return;
  217. }
  218. sas_ha = mvi->sas;
  219. sas_ha->notify_phy_event(sas_phy, PHYE_OOB_DONE);
  220. if (sas_phy->phy) {
  221. struct sas_phy *sphy = sas_phy->phy;
  222. sphy->negotiated_linkrate = sas_phy->linkrate;
  223. sphy->minimum_linkrate = phy->minimum_linkrate;
  224. sphy->minimum_linkrate_hw = SAS_LINK_RATE_1_5_GBPS;
  225. sphy->maximum_linkrate = phy->maximum_linkrate;
  226. sphy->maximum_linkrate_hw = MVS_CHIP_DISP->phy_max_link_rate();
  227. }
  228. if (phy->phy_type & PORT_TYPE_SAS) {
  229. struct sas_identify_frame *id;
  230. id = (struct sas_identify_frame *)phy->frame_rcvd;
  231. id->dev_type = phy->identify.device_type;
  232. id->initiator_bits = SAS_PROTOCOL_ALL;
  233. id->target_bits = phy->identify.target_port_protocols;
  234. } else if (phy->phy_type & PORT_TYPE_SATA) {
  235. /*Nothing*/
  236. }
  237. mv_dprintk("phy %d byte dmaded.\n", i + mvi->id * mvi->chip->n_phy);
  238. sas_phy->frame_rcvd_size = phy->frame_rcvd_size;
  239. mvi->sas->notify_port_event(sas_phy,
  240. PORTE_BYTES_DMAED);
  241. }
  242. int mvs_slave_alloc(struct scsi_device *scsi_dev)
  243. {
  244. struct domain_device *dev = sdev_to_domain_dev(scsi_dev);
  245. if (dev_is_sata(dev)) {
  246. /* We don't need to rescan targets
  247. * if REPORT_LUNS request is failed
  248. */
  249. if (scsi_dev->lun > 0)
  250. return -ENXIO;
  251. scsi_dev->tagged_supported = 1;
  252. }
  253. return sas_slave_alloc(scsi_dev);
  254. }
  255. int mvs_slave_configure(struct scsi_device *sdev)
  256. {
  257. struct domain_device *dev = sdev_to_domain_dev(sdev);
  258. int ret = sas_slave_configure(sdev);
  259. if (ret)
  260. return ret;
  261. if (!dev_is_sata(dev)) {
  262. sas_change_queue_depth(sdev,
  263. MVS_QUEUE_SIZE,
  264. SCSI_QDEPTH_DEFAULT);
  265. }
  266. return 0;
  267. }
  268. void mvs_scan_start(struct Scsi_Host *shost)
  269. {
  270. int i, j;
  271. unsigned short core_nr;
  272. struct mvs_info *mvi;
  273. struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
  274. struct mvs_prv_info *mvs_prv = sha->lldd_ha;
  275. core_nr = ((struct mvs_prv_info *)sha->lldd_ha)->n_host;
  276. for (j = 0; j < core_nr; j++) {
  277. mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[j];
  278. for (i = 0; i < mvi->chip->n_phy; ++i)
  279. mvs_bytes_dmaed(mvi, i);
  280. }
  281. mvs_prv->scan_finished = 1;
  282. }
  283. int mvs_scan_finished(struct Scsi_Host *shost, unsigned long time)
  284. {
  285. struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
  286. struct mvs_prv_info *mvs_prv = sha->lldd_ha;
  287. if (mvs_prv->scan_finished == 0)
  288. return 0;
  289. scsi_flush_work(shost);
  290. return 1;
  291. }
  292. static int mvs_task_prep_smp(struct mvs_info *mvi,
  293. struct mvs_task_exec_info *tei)
  294. {
  295. int elem, rc, i;
  296. struct sas_task *task = tei->task;
  297. struct mvs_cmd_hdr *hdr = tei->hdr;
  298. struct domain_device *dev = task->dev;
  299. struct asd_sas_port *sas_port = dev->port;
  300. struct scatterlist *sg_req, *sg_resp;
  301. u32 req_len, resp_len, tag = tei->tag;
  302. void *buf_tmp;
  303. u8 *buf_oaf;
  304. dma_addr_t buf_tmp_dma;
  305. void *buf_prd;
  306. struct mvs_slot_info *slot = &mvi->slot_info[tag];
  307. u32 flags = (tei->n_elem << MCH_PRD_LEN_SHIFT);
  308. /*
  309. * DMA-map SMP request, response buffers
  310. */
  311. sg_req = &task->smp_task.smp_req;
  312. elem = dma_map_sg(mvi->dev, sg_req, 1, PCI_DMA_TODEVICE);
  313. if (!elem)
  314. return -ENOMEM;
  315. req_len = sg_dma_len(sg_req);
  316. sg_resp = &task->smp_task.smp_resp;
  317. elem = dma_map_sg(mvi->dev, sg_resp, 1, PCI_DMA_FROMDEVICE);
  318. if (!elem) {
  319. rc = -ENOMEM;
  320. goto err_out;
  321. }
  322. resp_len = SB_RFB_MAX;
  323. /* must be in dwords */
  324. if ((req_len & 0x3) || (resp_len & 0x3)) {
  325. rc = -EINVAL;
  326. goto err_out_2;
  327. }
  328. /*
  329. * arrange MVS_SLOT_BUF_SZ-sized DMA buffer according to our needs
  330. */
  331. /* region 1: command table area (MVS_SSP_CMD_SZ bytes) ***** */
  332. buf_tmp = slot->buf;
  333. buf_tmp_dma = slot->buf_dma;
  334. hdr->cmd_tbl = cpu_to_le64(sg_dma_address(sg_req));
  335. /* region 2: open address frame area (MVS_OAF_SZ bytes) ********* */
  336. buf_oaf = buf_tmp;
  337. hdr->open_frame = cpu_to_le64(buf_tmp_dma);
  338. buf_tmp += MVS_OAF_SZ;
  339. buf_tmp_dma += MVS_OAF_SZ;
  340. /* region 3: PRD table *********************************** */
  341. buf_prd = buf_tmp;
  342. if (tei->n_elem)
  343. hdr->prd_tbl = cpu_to_le64(buf_tmp_dma);
  344. else
  345. hdr->prd_tbl = 0;
  346. i = MVS_CHIP_DISP->prd_size() * tei->n_elem;
  347. buf_tmp += i;
  348. buf_tmp_dma += i;
  349. /* region 4: status buffer (larger the PRD, smaller this buf) ****** */
  350. slot->response = buf_tmp;
  351. hdr->status_buf = cpu_to_le64(buf_tmp_dma);
  352. if (mvi->flags & MVF_FLAG_SOC)
  353. hdr->reserved[0] = 0;
  354. /*
  355. * Fill in TX ring and command slot header
  356. */
  357. slot->tx = mvi->tx_prod;
  358. mvi->tx[mvi->tx_prod] = cpu_to_le32((TXQ_CMD_SMP << TXQ_CMD_SHIFT) |
  359. TXQ_MODE_I | tag |
  360. (sas_port->phy_mask << TXQ_PHY_SHIFT));
  361. hdr->flags |= flags;
  362. hdr->lens = cpu_to_le32(((resp_len / 4) << 16) | ((req_len - 4) / 4));
  363. hdr->tags = cpu_to_le32(tag);
  364. hdr->data_len = 0;
  365. /* generate open address frame hdr (first 12 bytes) */
  366. /* initiator, SMP, ftype 1h */
  367. buf_oaf[0] = (1 << 7) | (PROTOCOL_SMP << 4) | 0x01;
  368. buf_oaf[1] = dev->linkrate & 0xf;
  369. *(u16 *)(buf_oaf + 2) = 0xFFFF; /* SAS SPEC */
  370. memcpy(buf_oaf + 4, dev->sas_addr, SAS_ADDR_SIZE);
  371. /* fill in PRD (scatter/gather) table, if any */
  372. MVS_CHIP_DISP->make_prd(task->scatter, tei->n_elem, buf_prd);
  373. return 0;
  374. err_out_2:
  375. dma_unmap_sg(mvi->dev, &tei->task->smp_task.smp_resp, 1,
  376. PCI_DMA_FROMDEVICE);
  377. err_out:
  378. dma_unmap_sg(mvi->dev, &tei->task->smp_task.smp_req, 1,
  379. PCI_DMA_TODEVICE);
  380. return rc;
  381. }
  382. static u32 mvs_get_ncq_tag(struct sas_task *task, u32 *tag)
  383. {
  384. struct ata_queued_cmd *qc = task->uldd_task;
  385. if (qc) {
  386. if (qc->tf.command == ATA_CMD_FPDMA_WRITE ||
  387. qc->tf.command == ATA_CMD_FPDMA_READ) {
  388. *tag = qc->tag;
  389. return 1;
  390. }
  391. }
  392. return 0;
  393. }
  394. static int mvs_task_prep_ata(struct mvs_info *mvi,
  395. struct mvs_task_exec_info *tei)
  396. {
  397. struct sas_task *task = tei->task;
  398. struct domain_device *dev = task->dev;
  399. struct mvs_device *mvi_dev = dev->lldd_dev;
  400. struct mvs_cmd_hdr *hdr = tei->hdr;
  401. struct asd_sas_port *sas_port = dev->port;
  402. struct mvs_slot_info *slot;
  403. void *buf_prd;
  404. u32 tag = tei->tag, hdr_tag;
  405. u32 flags, del_q;
  406. void *buf_tmp;
  407. u8 *buf_cmd, *buf_oaf;
  408. dma_addr_t buf_tmp_dma;
  409. u32 i, req_len, resp_len;
  410. const u32 max_resp_len = SB_RFB_MAX;
  411. if (mvs_assign_reg_set(mvi, mvi_dev) == MVS_ID_NOT_MAPPED) {
  412. mv_dprintk("Have not enough regiset for dev %d.\n",
  413. mvi_dev->device_id);
  414. return -EBUSY;
  415. }
  416. slot = &mvi->slot_info[tag];
  417. slot->tx = mvi->tx_prod;
  418. del_q = TXQ_MODE_I | tag |
  419. (TXQ_CMD_STP << TXQ_CMD_SHIFT) |
  420. (sas_port->phy_mask << TXQ_PHY_SHIFT) |
  421. (mvi_dev->taskfileset << TXQ_SRS_SHIFT);
  422. mvi->tx[mvi->tx_prod] = cpu_to_le32(del_q);
  423. if (task->data_dir == DMA_FROM_DEVICE)
  424. flags = (MVS_CHIP_DISP->prd_count() << MCH_PRD_LEN_SHIFT);
  425. else
  426. flags = (tei->n_elem << MCH_PRD_LEN_SHIFT);
  427. if (task->ata_task.use_ncq)
  428. flags |= MCH_FPDMA;
  429. if (dev->sata_dev.command_set == ATAPI_COMMAND_SET) {
  430. if (task->ata_task.fis.command != ATA_CMD_ID_ATAPI)
  431. flags |= MCH_ATAPI;
  432. }
  433. hdr->flags = cpu_to_le32(flags);
  434. if (task->ata_task.use_ncq && mvs_get_ncq_tag(task, &hdr_tag))
  435. task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3);
  436. else
  437. hdr_tag = tag;
  438. hdr->tags = cpu_to_le32(hdr_tag);
  439. hdr->data_len = cpu_to_le32(task->total_xfer_len);
  440. /*
  441. * arrange MVS_SLOT_BUF_SZ-sized DMA buffer according to our needs
  442. */
  443. /* region 1: command table area (MVS_ATA_CMD_SZ bytes) ************** */
  444. buf_cmd = buf_tmp = slot->buf;
  445. buf_tmp_dma = slot->buf_dma;
  446. hdr->cmd_tbl = cpu_to_le64(buf_tmp_dma);
  447. buf_tmp += MVS_ATA_CMD_SZ;
  448. buf_tmp_dma += MVS_ATA_CMD_SZ;
  449. /* region 2: open address frame area (MVS_OAF_SZ bytes) ********* */
  450. /* used for STP. unused for SATA? */
  451. buf_oaf = buf_tmp;
  452. hdr->open_frame = cpu_to_le64(buf_tmp_dma);
  453. buf_tmp += MVS_OAF_SZ;
  454. buf_tmp_dma += MVS_OAF_SZ;
  455. /* region 3: PRD table ********************************************* */
  456. buf_prd = buf_tmp;
  457. if (tei->n_elem)
  458. hdr->prd_tbl = cpu_to_le64(buf_tmp_dma);
  459. else
  460. hdr->prd_tbl = 0;
  461. i = MVS_CHIP_DISP->prd_size() * MVS_CHIP_DISP->prd_count();
  462. buf_tmp += i;
  463. buf_tmp_dma += i;
  464. /* region 4: status buffer (larger the PRD, smaller this buf) ****** */
  465. slot->response = buf_tmp;
  466. hdr->status_buf = cpu_to_le64(buf_tmp_dma);
  467. if (mvi->flags & MVF_FLAG_SOC)
  468. hdr->reserved[0] = 0;
  469. req_len = sizeof(struct host_to_dev_fis);
  470. resp_len = MVS_SLOT_BUF_SZ - MVS_ATA_CMD_SZ -
  471. sizeof(struct mvs_err_info) - i;
  472. /* request, response lengths */
  473. resp_len = min(resp_len, max_resp_len);
  474. hdr->lens = cpu_to_le32(((resp_len / 4) << 16) | (req_len / 4));
  475. if (likely(!task->ata_task.device_control_reg_update))
  476. task->ata_task.fis.flags |= 0x80; /* C=1: update ATA cmd reg */
  477. /* fill in command FIS and ATAPI CDB */
  478. memcpy(buf_cmd, &task->ata_task.fis, sizeof(struct host_to_dev_fis));
  479. if (dev->sata_dev.command_set == ATAPI_COMMAND_SET)
  480. memcpy(buf_cmd + STP_ATAPI_CMD,
  481. task->ata_task.atapi_packet, 16);
  482. /* generate open address frame hdr (first 12 bytes) */
  483. /* initiator, STP, ftype 1h */
  484. buf_oaf[0] = (1 << 7) | (PROTOCOL_STP << 4) | 0x1;
  485. buf_oaf[1] = dev->linkrate & 0xf;
  486. *(u16 *)(buf_oaf + 2) = cpu_to_be16(mvi_dev->device_id + 1);
  487. memcpy(buf_oaf + 4, dev->sas_addr, SAS_ADDR_SIZE);
  488. /* fill in PRD (scatter/gather) table, if any */
  489. MVS_CHIP_DISP->make_prd(task->scatter, tei->n_elem, buf_prd);
  490. if (task->data_dir == DMA_FROM_DEVICE)
  491. MVS_CHIP_DISP->dma_fix(mvi, sas_port->phy_mask,
  492. TRASH_BUCKET_SIZE, tei->n_elem, buf_prd);
  493. return 0;
  494. }
  495. static int mvs_task_prep_ssp(struct mvs_info *mvi,
  496. struct mvs_task_exec_info *tei, int is_tmf,
  497. struct mvs_tmf_task *tmf)
  498. {
  499. struct sas_task *task = tei->task;
  500. struct mvs_cmd_hdr *hdr = tei->hdr;
  501. struct mvs_port *port = tei->port;
  502. struct domain_device *dev = task->dev;
  503. struct mvs_device *mvi_dev = dev->lldd_dev;
  504. struct asd_sas_port *sas_port = dev->port;
  505. struct mvs_slot_info *slot;
  506. void *buf_prd;
  507. struct ssp_frame_hdr *ssp_hdr;
  508. void *buf_tmp;
  509. u8 *buf_cmd, *buf_oaf, fburst = 0;
  510. dma_addr_t buf_tmp_dma;
  511. u32 flags;
  512. u32 resp_len, req_len, i, tag = tei->tag;
  513. const u32 max_resp_len = SB_RFB_MAX;
  514. u32 phy_mask;
  515. slot = &mvi->slot_info[tag];
  516. phy_mask = ((port->wide_port_phymap) ? port->wide_port_phymap :
  517. sas_port->phy_mask) & TXQ_PHY_MASK;
  518. slot->tx = mvi->tx_prod;
  519. mvi->tx[mvi->tx_prod] = cpu_to_le32(TXQ_MODE_I | tag |
  520. (TXQ_CMD_SSP << TXQ_CMD_SHIFT) |
  521. (phy_mask << TXQ_PHY_SHIFT));
  522. flags = MCH_RETRY;
  523. if (task->ssp_task.enable_first_burst) {
  524. flags |= MCH_FBURST;
  525. fburst = (1 << 7);
  526. }
  527. if (is_tmf)
  528. flags |= (MCH_SSP_FR_TASK << MCH_SSP_FR_TYPE_SHIFT);
  529. else
  530. flags |= (MCH_SSP_FR_CMD << MCH_SSP_FR_TYPE_SHIFT);
  531. hdr->flags = cpu_to_le32(flags | (tei->n_elem << MCH_PRD_LEN_SHIFT));
  532. hdr->tags = cpu_to_le32(tag);
  533. hdr->data_len = cpu_to_le32(task->total_xfer_len);
  534. /*
  535. * arrange MVS_SLOT_BUF_SZ-sized DMA buffer according to our needs
  536. */
  537. /* region 1: command table area (MVS_SSP_CMD_SZ bytes) ************** */
  538. buf_cmd = buf_tmp = slot->buf;
  539. buf_tmp_dma = slot->buf_dma;
  540. hdr->cmd_tbl = cpu_to_le64(buf_tmp_dma);
  541. buf_tmp += MVS_SSP_CMD_SZ;
  542. buf_tmp_dma += MVS_SSP_CMD_SZ;
  543. /* region 2: open address frame area (MVS_OAF_SZ bytes) ********* */
  544. buf_oaf = buf_tmp;
  545. hdr->open_frame = cpu_to_le64(buf_tmp_dma);
  546. buf_tmp += MVS_OAF_SZ;
  547. buf_tmp_dma += MVS_OAF_SZ;
  548. /* region 3: PRD table ********************************************* */
  549. buf_prd = buf_tmp;
  550. if (tei->n_elem)
  551. hdr->prd_tbl = cpu_to_le64(buf_tmp_dma);
  552. else
  553. hdr->prd_tbl = 0;
  554. i = MVS_CHIP_DISP->prd_size() * tei->n_elem;
  555. buf_tmp += i;
  556. buf_tmp_dma += i;
  557. /* region 4: status buffer (larger the PRD, smaller this buf) ****** */
  558. slot->response = buf_tmp;
  559. hdr->status_buf = cpu_to_le64(buf_tmp_dma);
  560. if (mvi->flags & MVF_FLAG_SOC)
  561. hdr->reserved[0] = 0;
  562. resp_len = MVS_SLOT_BUF_SZ - MVS_SSP_CMD_SZ - MVS_OAF_SZ -
  563. sizeof(struct mvs_err_info) - i;
  564. resp_len = min(resp_len, max_resp_len);
  565. req_len = sizeof(struct ssp_frame_hdr) + 28;
  566. /* request, response lengths */
  567. hdr->lens = cpu_to_le32(((resp_len / 4) << 16) | (req_len / 4));
  568. /* generate open address frame hdr (first 12 bytes) */
  569. /* initiator, SSP, ftype 1h */
  570. buf_oaf[0] = (1 << 7) | (PROTOCOL_SSP << 4) | 0x1;
  571. buf_oaf[1] = dev->linkrate & 0xf;
  572. *(u16 *)(buf_oaf + 2) = cpu_to_be16(mvi_dev->device_id + 1);
  573. memcpy(buf_oaf + 4, dev->sas_addr, SAS_ADDR_SIZE);
  574. /* fill in SSP frame header (Command Table.SSP frame header) */
  575. ssp_hdr = (struct ssp_frame_hdr *)buf_cmd;
  576. if (is_tmf)
  577. ssp_hdr->frame_type = SSP_TASK;
  578. else
  579. ssp_hdr->frame_type = SSP_COMMAND;
  580. memcpy(ssp_hdr->hashed_dest_addr, dev->hashed_sas_addr,
  581. HASHED_SAS_ADDR_SIZE);
  582. memcpy(ssp_hdr->hashed_src_addr,
  583. dev->hashed_sas_addr, HASHED_SAS_ADDR_SIZE);
  584. ssp_hdr->tag = cpu_to_be16(tag);
  585. /* fill in IU for TASK and Command Frame */
  586. buf_cmd += sizeof(*ssp_hdr);
  587. memcpy(buf_cmd, &task->ssp_task.LUN, 8);
  588. if (ssp_hdr->frame_type != SSP_TASK) {
  589. buf_cmd[9] = fburst | task->ssp_task.task_attr |
  590. (task->ssp_task.task_prio << 3);
  591. memcpy(buf_cmd + 12, &task->ssp_task.cdb, 16);
  592. } else{
  593. buf_cmd[10] = tmf->tmf;
  594. switch (tmf->tmf) {
  595. case TMF_ABORT_TASK:
  596. case TMF_QUERY_TASK:
  597. buf_cmd[12] =
  598. (tmf->tag_of_task_to_be_managed >> 8) & 0xff;
  599. buf_cmd[13] =
  600. tmf->tag_of_task_to_be_managed & 0xff;
  601. break;
  602. default:
  603. break;
  604. }
  605. }
  606. /* fill in PRD (scatter/gather) table, if any */
  607. MVS_CHIP_DISP->make_prd(task->scatter, tei->n_elem, buf_prd);
  608. return 0;
  609. }
  610. #define DEV_IS_GONE(mvi_dev) ((!mvi_dev || (mvi_dev->dev_type == NO_DEVICE)))
  611. static int mvs_task_prep(struct sas_task *task, struct mvs_info *mvi, int is_tmf,
  612. struct mvs_tmf_task *tmf, int *pass)
  613. {
  614. struct domain_device *dev = task->dev;
  615. struct mvs_device *mvi_dev = dev->lldd_dev;
  616. struct mvs_task_exec_info tei;
  617. struct mvs_slot_info *slot;
  618. u32 tag = 0xdeadbeef, n_elem = 0;
  619. int rc = 0;
  620. if (!dev->port) {
  621. struct task_status_struct *tsm = &task->task_status;
  622. tsm->resp = SAS_TASK_UNDELIVERED;
  623. tsm->stat = SAS_PHY_DOWN;
  624. /*
  625. * libsas will use dev->port, should
  626. * not call task_done for sata
  627. */
  628. if (dev->dev_type != SATA_DEV)
  629. task->task_done(task);
  630. return rc;
  631. }
  632. if (DEV_IS_GONE(mvi_dev)) {
  633. if (mvi_dev)
  634. mv_dprintk("device %d not ready.\n",
  635. mvi_dev->device_id);
  636. else
  637. mv_dprintk("device %016llx not ready.\n",
  638. SAS_ADDR(dev->sas_addr));
  639. rc = SAS_PHY_DOWN;
  640. return rc;
  641. }
  642. tei.port = dev->port->lldd_port;
  643. if (tei.port && !tei.port->port_attached && !tmf) {
  644. if (sas_protocol_ata(task->task_proto)) {
  645. struct task_status_struct *ts = &task->task_status;
  646. mv_dprintk("SATA/STP port %d does not attach"
  647. "device.\n", dev->port->id);
  648. ts->resp = SAS_TASK_COMPLETE;
  649. ts->stat = SAS_PHY_DOWN;
  650. task->task_done(task);
  651. } else {
  652. struct task_status_struct *ts = &task->task_status;
  653. mv_dprintk("SAS port %d does not attach"
  654. "device.\n", dev->port->id);
  655. ts->resp = SAS_TASK_UNDELIVERED;
  656. ts->stat = SAS_PHY_DOWN;
  657. task->task_done(task);
  658. }
  659. return rc;
  660. }
  661. if (!sas_protocol_ata(task->task_proto)) {
  662. if (task->num_scatter) {
  663. n_elem = dma_map_sg(mvi->dev,
  664. task->scatter,
  665. task->num_scatter,
  666. task->data_dir);
  667. if (!n_elem) {
  668. rc = -ENOMEM;
  669. goto prep_out;
  670. }
  671. }
  672. } else {
  673. n_elem = task->num_scatter;
  674. }
  675. rc = mvs_tag_alloc(mvi, &tag);
  676. if (rc)
  677. goto err_out;
  678. slot = &mvi->slot_info[tag];
  679. task->lldd_task = NULL;
  680. slot->n_elem = n_elem;
  681. slot->slot_tag = tag;
  682. slot->buf = pci_pool_alloc(mvi->dma_pool, GFP_ATOMIC, &slot->buf_dma);
  683. if (!slot->buf)
  684. goto err_out_tag;
  685. memset(slot->buf, 0, MVS_SLOT_BUF_SZ);
  686. tei.task = task;
  687. tei.hdr = &mvi->slot[tag];
  688. tei.tag = tag;
  689. tei.n_elem = n_elem;
  690. switch (task->task_proto) {
  691. case SAS_PROTOCOL_SMP:
  692. rc = mvs_task_prep_smp(mvi, &tei);
  693. break;
  694. case SAS_PROTOCOL_SSP:
  695. rc = mvs_task_prep_ssp(mvi, &tei, is_tmf, tmf);
  696. break;
  697. case SAS_PROTOCOL_SATA:
  698. case SAS_PROTOCOL_STP:
  699. case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
  700. rc = mvs_task_prep_ata(mvi, &tei);
  701. break;
  702. default:
  703. dev_printk(KERN_ERR, mvi->dev,
  704. "unknown sas_task proto: 0x%x\n",
  705. task->task_proto);
  706. rc = -EINVAL;
  707. break;
  708. }
  709. if (rc) {
  710. mv_dprintk("rc is %x\n", rc);
  711. goto err_out_slot_buf;
  712. }
  713. slot->task = task;
  714. slot->port = tei.port;
  715. task->lldd_task = slot;
  716. list_add_tail(&slot->entry, &tei.port->list);
  717. spin_lock(&task->task_state_lock);
  718. task->task_state_flags |= SAS_TASK_AT_INITIATOR;
  719. spin_unlock(&task->task_state_lock);
  720. mvi_dev->running_req++;
  721. ++(*pass);
  722. mvi->tx_prod = (mvi->tx_prod + 1) & (MVS_CHIP_SLOT_SZ - 1);
  723. return rc;
  724. err_out_slot_buf:
  725. pci_pool_free(mvi->dma_pool, slot->buf, slot->buf_dma);
  726. err_out_tag:
  727. mvs_tag_free(mvi, tag);
  728. err_out:
  729. dev_printk(KERN_ERR, mvi->dev, "mvsas prep failed[%d]!\n", rc);
  730. if (!sas_protocol_ata(task->task_proto))
  731. if (n_elem)
  732. dma_unmap_sg(mvi->dev, task->scatter, n_elem,
  733. task->data_dir);
  734. prep_out:
  735. return rc;
  736. }
  737. static struct mvs_task_list *mvs_task_alloc_list(int *num, gfp_t gfp_flags)
  738. {
  739. struct mvs_task_list *first = NULL;
  740. for (; *num > 0; --*num) {
  741. struct mvs_task_list *mvs_list = kmem_cache_zalloc(mvs_task_list_cache, gfp_flags);
  742. if (!mvs_list)
  743. break;
  744. INIT_LIST_HEAD(&mvs_list->list);
  745. if (!first)
  746. first = mvs_list;
  747. else
  748. list_add_tail(&mvs_list->list, &first->list);
  749. }
  750. return first;
  751. }
  752. static inline void mvs_task_free_list(struct mvs_task_list *mvs_list)
  753. {
  754. LIST_HEAD(list);
  755. struct list_head *pos, *a;
  756. struct mvs_task_list *mlist = NULL;
  757. __list_add(&list, mvs_list->list.prev, &mvs_list->list);
  758. list_for_each_safe(pos, a, &list) {
  759. list_del_init(pos);
  760. mlist = list_entry(pos, struct mvs_task_list, list);
  761. kmem_cache_free(mvs_task_list_cache, mlist);
  762. }
  763. }
  764. static int mvs_task_exec(struct sas_task *task, const int num, gfp_t gfp_flags,
  765. struct completion *completion, int is_tmf,
  766. struct mvs_tmf_task *tmf)
  767. {
  768. struct domain_device *dev = task->dev;
  769. struct mvs_info *mvi = NULL;
  770. u32 rc = 0;
  771. u32 pass = 0;
  772. unsigned long flags = 0;
  773. mvi = ((struct mvs_device *)task->dev->lldd_dev)->mvi_info;
  774. if ((dev->dev_type == SATA_DEV) && (dev->sata_dev.ap != NULL))
  775. spin_unlock_irq(dev->sata_dev.ap->lock);
  776. spin_lock_irqsave(&mvi->lock, flags);
  777. rc = mvs_task_prep(task, mvi, is_tmf, tmf, &pass);
  778. if (rc)
  779. dev_printk(KERN_ERR, mvi->dev, "mvsas exec failed[%d]!\n", rc);
  780. if (likely(pass))
  781. MVS_CHIP_DISP->start_delivery(mvi, (mvi->tx_prod - 1) &
  782. (MVS_CHIP_SLOT_SZ - 1));
  783. spin_unlock_irqrestore(&mvi->lock, flags);
  784. if ((dev->dev_type == SATA_DEV) && (dev->sata_dev.ap != NULL))
  785. spin_lock_irq(dev->sata_dev.ap->lock);
  786. return rc;
  787. }
  788. static int mvs_collector_task_exec(struct sas_task *task, const int num, gfp_t gfp_flags,
  789. struct completion *completion, int is_tmf,
  790. struct mvs_tmf_task *tmf)
  791. {
  792. struct domain_device *dev = task->dev;
  793. struct mvs_prv_info *mpi = dev->port->ha->lldd_ha;
  794. struct mvs_info *mvi = NULL;
  795. struct sas_task *t = task;
  796. struct mvs_task_list *mvs_list = NULL, *a;
  797. LIST_HEAD(q);
  798. int pass[2] = {0};
  799. u32 rc = 0;
  800. u32 n = num;
  801. unsigned long flags = 0;
  802. mvs_list = mvs_task_alloc_list(&n, gfp_flags);
  803. if (n) {
  804. printk(KERN_ERR "%s: mvs alloc list failed.\n", __func__);
  805. rc = -ENOMEM;
  806. goto free_list;
  807. }
  808. __list_add(&q, mvs_list->list.prev, &mvs_list->list);
  809. list_for_each_entry(a, &q, list) {
  810. a->task = t;
  811. t = list_entry(t->list.next, struct sas_task, list);
  812. }
  813. list_for_each_entry(a, &q , list) {
  814. t = a->task;
  815. mvi = ((struct mvs_device *)t->dev->lldd_dev)->mvi_info;
  816. spin_lock_irqsave(&mvi->lock, flags);
  817. rc = mvs_task_prep(t, mvi, is_tmf, tmf, &pass[mvi->id]);
  818. if (rc)
  819. dev_printk(KERN_ERR, mvi->dev, "mvsas exec failed[%d]!\n", rc);
  820. spin_unlock_irqrestore(&mvi->lock, flags);
  821. }
  822. if (likely(pass[0]))
  823. MVS_CHIP_DISP->start_delivery(mpi->mvi[0],
  824. (mpi->mvi[0]->tx_prod - 1) & (MVS_CHIP_SLOT_SZ - 1));
  825. if (likely(pass[1]))
  826. MVS_CHIP_DISP->start_delivery(mpi->mvi[1],
  827. (mpi->mvi[1]->tx_prod - 1) & (MVS_CHIP_SLOT_SZ - 1));
  828. list_del_init(&q);
  829. free_list:
  830. if (mvs_list)
  831. mvs_task_free_list(mvs_list);
  832. return rc;
  833. }
  834. int mvs_queue_command(struct sas_task *task, const int num,
  835. gfp_t gfp_flags)
  836. {
  837. struct mvs_device *mvi_dev = task->dev->lldd_dev;
  838. struct sas_ha_struct *sas = mvi_dev->mvi_info->sas;
  839. if (sas->lldd_max_execute_num < 2)
  840. return mvs_task_exec(task, num, gfp_flags, NULL, 0, NULL);
  841. else
  842. return mvs_collector_task_exec(task, num, gfp_flags, NULL, 0, NULL);
  843. }
  844. static void mvs_slot_free(struct mvs_info *mvi, u32 rx_desc)
  845. {
  846. u32 slot_idx = rx_desc & RXQ_SLOT_MASK;
  847. mvs_tag_clear(mvi, slot_idx);
  848. }
  849. static void mvs_slot_task_free(struct mvs_info *mvi, struct sas_task *task,
  850. struct mvs_slot_info *slot, u32 slot_idx)
  851. {
  852. if (!slot->task)
  853. return;
  854. if (!sas_protocol_ata(task->task_proto))
  855. if (slot->n_elem)
  856. dma_unmap_sg(mvi->dev, task->scatter,
  857. slot->n_elem, task->data_dir);
  858. switch (task->task_proto) {
  859. case SAS_PROTOCOL_SMP:
  860. dma_unmap_sg(mvi->dev, &task->smp_task.smp_resp, 1,
  861. PCI_DMA_FROMDEVICE);
  862. dma_unmap_sg(mvi->dev, &task->smp_task.smp_req, 1,
  863. PCI_DMA_TODEVICE);
  864. break;
  865. case SAS_PROTOCOL_SATA:
  866. case SAS_PROTOCOL_STP:
  867. case SAS_PROTOCOL_SSP:
  868. default:
  869. /* do nothing */
  870. break;
  871. }
  872. if (slot->buf) {
  873. pci_pool_free(mvi->dma_pool, slot->buf, slot->buf_dma);
  874. slot->buf = NULL;
  875. }
  876. list_del_init(&slot->entry);
  877. task->lldd_task = NULL;
  878. slot->task = NULL;
  879. slot->port = NULL;
  880. slot->slot_tag = 0xFFFFFFFF;
  881. mvs_slot_free(mvi, slot_idx);
  882. }
  883. static void mvs_update_wideport(struct mvs_info *mvi, int phy_no)
  884. {
  885. struct mvs_phy *phy = &mvi->phy[phy_no];
  886. struct mvs_port *port = phy->port;
  887. int j, no;
  888. for_each_phy(port->wide_port_phymap, j, no) {
  889. if (j & 1) {
  890. MVS_CHIP_DISP->write_port_cfg_addr(mvi, no,
  891. PHYR_WIDE_PORT);
  892. MVS_CHIP_DISP->write_port_cfg_data(mvi, no,
  893. port->wide_port_phymap);
  894. } else {
  895. MVS_CHIP_DISP->write_port_cfg_addr(mvi, no,
  896. PHYR_WIDE_PORT);
  897. MVS_CHIP_DISP->write_port_cfg_data(mvi, no,
  898. 0);
  899. }
  900. }
  901. }
  902. static u32 mvs_is_phy_ready(struct mvs_info *mvi, int i)
  903. {
  904. u32 tmp;
  905. struct mvs_phy *phy = &mvi->phy[i];
  906. struct mvs_port *port = phy->port;
  907. tmp = MVS_CHIP_DISP->read_phy_ctl(mvi, i);
  908. if ((tmp & PHY_READY_MASK) && !(phy->irq_status & PHYEV_POOF)) {
  909. if (!port)
  910. phy->phy_attached = 1;
  911. return tmp;
  912. }
  913. if (port) {
  914. if (phy->phy_type & PORT_TYPE_SAS) {
  915. port->wide_port_phymap &= ~(1U << i);
  916. if (!port->wide_port_phymap)
  917. port->port_attached = 0;
  918. mvs_update_wideport(mvi, i);
  919. } else if (phy->phy_type & PORT_TYPE_SATA)
  920. port->port_attached = 0;
  921. phy->port = NULL;
  922. phy->phy_attached = 0;
  923. phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA);
  924. }
  925. return 0;
  926. }
  927. static void *mvs_get_d2h_reg(struct mvs_info *mvi, int i, void *buf)
  928. {
  929. u32 *s = (u32 *) buf;
  930. if (!s)
  931. return NULL;
  932. MVS_CHIP_DISP->write_port_cfg_addr(mvi, i, PHYR_SATA_SIG3);
  933. s[3] = cpu_to_le32(MVS_CHIP_DISP->read_port_cfg_data(mvi, i));
  934. MVS_CHIP_DISP->write_port_cfg_addr(mvi, i, PHYR_SATA_SIG2);
  935. s[2] = cpu_to_le32(MVS_CHIP_DISP->read_port_cfg_data(mvi, i));
  936. MVS_CHIP_DISP->write_port_cfg_addr(mvi, i, PHYR_SATA_SIG1);
  937. s[1] = cpu_to_le32(MVS_CHIP_DISP->read_port_cfg_data(mvi, i));
  938. MVS_CHIP_DISP->write_port_cfg_addr(mvi, i, PHYR_SATA_SIG0);
  939. s[0] = cpu_to_le32(MVS_CHIP_DISP->read_port_cfg_data(mvi, i));
  940. if (((s[1] & 0x00FFFFFF) == 0x00EB1401) && (*(u8 *)&s[3] == 0x01))
  941. s[1] = 0x00EB1401 | (*((u8 *)&s[1] + 3) & 0x10);
  942. return s;
  943. }
  944. static u32 mvs_is_sig_fis_received(u32 irq_status)
  945. {
  946. return irq_status & PHYEV_SIG_FIS;
  947. }
  948. static void mvs_sig_remove_timer(struct mvs_phy *phy)
  949. {
  950. if (phy->timer.function)
  951. del_timer(&phy->timer);
  952. phy->timer.function = NULL;
  953. }
  954. void mvs_update_phyinfo(struct mvs_info *mvi, int i, int get_st)
  955. {
  956. struct mvs_phy *phy = &mvi->phy[i];
  957. struct sas_identify_frame *id;
  958. id = (struct sas_identify_frame *)phy->frame_rcvd;
  959. if (get_st) {
  960. phy->irq_status = MVS_CHIP_DISP->read_port_irq_stat(mvi, i);
  961. phy->phy_status = mvs_is_phy_ready(mvi, i);
  962. }
  963. if (phy->phy_status) {
  964. int oob_done = 0;
  965. struct asd_sas_phy *sas_phy = &mvi->phy[i].sas_phy;
  966. oob_done = MVS_CHIP_DISP->oob_done(mvi, i);
  967. MVS_CHIP_DISP->fix_phy_info(mvi, i, id);
  968. if (phy->phy_type & PORT_TYPE_SATA) {
  969. phy->identify.target_port_protocols = SAS_PROTOCOL_STP;
  970. if (mvs_is_sig_fis_received(phy->irq_status)) {
  971. mvs_sig_remove_timer(phy);
  972. phy->phy_attached = 1;
  973. phy->att_dev_sas_addr =
  974. i + mvi->id * mvi->chip->n_phy;
  975. if (oob_done)
  976. sas_phy->oob_mode = SATA_OOB_MODE;
  977. phy->frame_rcvd_size =
  978. sizeof(struct dev_to_host_fis);
  979. mvs_get_d2h_reg(mvi, i, id);
  980. } else {
  981. u32 tmp;
  982. dev_printk(KERN_DEBUG, mvi->dev,
  983. "Phy%d : No sig fis\n", i);
  984. tmp = MVS_CHIP_DISP->read_port_irq_mask(mvi, i);
  985. MVS_CHIP_DISP->write_port_irq_mask(mvi, i,
  986. tmp | PHYEV_SIG_FIS);
  987. phy->phy_attached = 0;
  988. phy->phy_type &= ~PORT_TYPE_SATA;
  989. goto out_done;
  990. }
  991. } else if (phy->phy_type & PORT_TYPE_SAS
  992. || phy->att_dev_info & PORT_SSP_INIT_MASK) {
  993. phy->phy_attached = 1;
  994. phy->identify.device_type =
  995. phy->att_dev_info & PORT_DEV_TYPE_MASK;
  996. if (phy->identify.device_type == SAS_END_DEV)
  997. phy->identify.target_port_protocols =
  998. SAS_PROTOCOL_SSP;
  999. else if (phy->identify.device_type != NO_DEVICE)
  1000. phy->identify.target_port_protocols =
  1001. SAS_PROTOCOL_SMP;
  1002. if (oob_done)
  1003. sas_phy->oob_mode = SAS_OOB_MODE;
  1004. phy->frame_rcvd_size =
  1005. sizeof(struct sas_identify_frame);
  1006. }
  1007. memcpy(sas_phy->attached_sas_addr,
  1008. &phy->att_dev_sas_addr, SAS_ADDR_SIZE);
  1009. if (MVS_CHIP_DISP->phy_work_around)
  1010. MVS_CHIP_DISP->phy_work_around(mvi, i);
  1011. }
  1012. mv_dprintk("phy %d attach dev info is %x\n",
  1013. i + mvi->id * mvi->chip->n_phy, phy->att_dev_info);
  1014. mv_dprintk("phy %d attach sas addr is %llx\n",
  1015. i + mvi->id * mvi->chip->n_phy, phy->att_dev_sas_addr);
  1016. out_done:
  1017. if (get_st)
  1018. MVS_CHIP_DISP->write_port_irq_stat(mvi, i, phy->irq_status);
  1019. }
  1020. static void mvs_port_notify_formed(struct asd_sas_phy *sas_phy, int lock)
  1021. {
  1022. struct sas_ha_struct *sas_ha = sas_phy->ha;
  1023. struct mvs_info *mvi = NULL; int i = 0, hi;
  1024. struct mvs_phy *phy = sas_phy->lldd_phy;
  1025. struct asd_sas_port *sas_port = sas_phy->port;
  1026. struct mvs_port *port;
  1027. unsigned long flags = 0;
  1028. if (!sas_port)
  1029. return;
  1030. while (sas_ha->sas_phy[i]) {
  1031. if (sas_ha->sas_phy[i] == sas_phy)
  1032. break;
  1033. i++;
  1034. }
  1035. hi = i/((struct mvs_prv_info *)sas_ha->lldd_ha)->n_phy;
  1036. mvi = ((struct mvs_prv_info *)sas_ha->lldd_ha)->mvi[hi];
  1037. if (i >= mvi->chip->n_phy)
  1038. port = &mvi->port[i - mvi->chip->n_phy];
  1039. else
  1040. port = &mvi->port[i];
  1041. if (lock)
  1042. spin_lock_irqsave(&mvi->lock, flags);
  1043. port->port_attached = 1;
  1044. phy->port = port;
  1045. sas_port->lldd_port = port;
  1046. if (phy->phy_type & PORT_TYPE_SAS) {
  1047. port->wide_port_phymap = sas_port->phy_mask;
  1048. mv_printk("set wide port phy map %x\n", sas_port->phy_mask);
  1049. mvs_update_wideport(mvi, sas_phy->id);
  1050. }
  1051. if (lock)
  1052. spin_unlock_irqrestore(&mvi->lock, flags);
  1053. }
  1054. static void mvs_port_notify_deformed(struct asd_sas_phy *sas_phy, int lock)
  1055. {
  1056. struct domain_device *dev;
  1057. struct mvs_phy *phy = sas_phy->lldd_phy;
  1058. struct mvs_info *mvi = phy->mvi;
  1059. struct asd_sas_port *port = sas_phy->port;
  1060. int phy_no = 0;
  1061. while (phy != &mvi->phy[phy_no]) {
  1062. phy_no++;
  1063. if (phy_no >= MVS_MAX_PHYS)
  1064. return;
  1065. }
  1066. list_for_each_entry(dev, &port->dev_list, dev_list_node)
  1067. mvs_do_release_task(phy->mvi, phy_no, dev);
  1068. }
  1069. void mvs_port_formed(struct asd_sas_phy *sas_phy)
  1070. {
  1071. mvs_port_notify_formed(sas_phy, 1);
  1072. }
  1073. void mvs_port_deformed(struct asd_sas_phy *sas_phy)
  1074. {
  1075. mvs_port_notify_deformed(sas_phy, 1);
  1076. }
  1077. struct mvs_device *mvs_alloc_dev(struct mvs_info *mvi)
  1078. {
  1079. u32 dev;
  1080. for (dev = 0; dev < MVS_MAX_DEVICES; dev++) {
  1081. if (mvi->devices[dev].dev_type == NO_DEVICE) {
  1082. mvi->devices[dev].device_id = dev;
  1083. return &mvi->devices[dev];
  1084. }
  1085. }
  1086. if (dev == MVS_MAX_DEVICES)
  1087. mv_printk("max support %d devices, ignore ..\n",
  1088. MVS_MAX_DEVICES);
  1089. return NULL;
  1090. }
  1091. void mvs_free_dev(struct mvs_device *mvi_dev)
  1092. {
  1093. u32 id = mvi_dev->device_id;
  1094. memset(mvi_dev, 0, sizeof(*mvi_dev));
  1095. mvi_dev->device_id = id;
  1096. mvi_dev->dev_type = NO_DEVICE;
  1097. mvi_dev->dev_status = MVS_DEV_NORMAL;
  1098. mvi_dev->taskfileset = MVS_ID_NOT_MAPPED;
  1099. }
  1100. int mvs_dev_found_notify(struct domain_device *dev, int lock)
  1101. {
  1102. unsigned long flags = 0;
  1103. int res = 0;
  1104. struct mvs_info *mvi = NULL;
  1105. struct domain_device *parent_dev = dev->parent;
  1106. struct mvs_device *mvi_device;
  1107. mvi = mvs_find_dev_mvi(dev);
  1108. if (lock)
  1109. spin_lock_irqsave(&mvi->lock, flags);
  1110. mvi_device = mvs_alloc_dev(mvi);
  1111. if (!mvi_device) {
  1112. res = -1;
  1113. goto found_out;
  1114. }
  1115. dev->lldd_dev = mvi_device;
  1116. mvi_device->dev_status = MVS_DEV_NORMAL;
  1117. mvi_device->dev_type = dev->dev_type;
  1118. mvi_device->mvi_info = mvi;
  1119. mvi_device->sas_device = dev;
  1120. if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type)) {
  1121. int phy_id;
  1122. u8 phy_num = parent_dev->ex_dev.num_phys;
  1123. struct ex_phy *phy;
  1124. for (phy_id = 0; phy_id < phy_num; phy_id++) {
  1125. phy = &parent_dev->ex_dev.ex_phy[phy_id];
  1126. if (SAS_ADDR(phy->attached_sas_addr) ==
  1127. SAS_ADDR(dev->sas_addr)) {
  1128. mvi_device->attached_phy = phy_id;
  1129. break;
  1130. }
  1131. }
  1132. if (phy_id == phy_num) {
  1133. mv_printk("Error: no attached dev:%016llx"
  1134. "at ex:%016llx.\n",
  1135. SAS_ADDR(dev->sas_addr),
  1136. SAS_ADDR(parent_dev->sas_addr));
  1137. res = -1;
  1138. }
  1139. }
  1140. found_out:
  1141. if (lock)
  1142. spin_unlock_irqrestore(&mvi->lock, flags);
  1143. return res;
  1144. }
  1145. int mvs_dev_found(struct domain_device *dev)
  1146. {
  1147. return mvs_dev_found_notify(dev, 1);
  1148. }
  1149. void mvs_dev_gone_notify(struct domain_device *dev)
  1150. {
  1151. unsigned long flags = 0;
  1152. struct mvs_device *mvi_dev = dev->lldd_dev;
  1153. struct mvs_info *mvi = mvi_dev->mvi_info;
  1154. spin_lock_irqsave(&mvi->lock, flags);
  1155. if (mvi_dev) {
  1156. mv_dprintk("found dev[%d:%x] is gone.\n",
  1157. mvi_dev->device_id, mvi_dev->dev_type);
  1158. mvs_release_task(mvi, dev);
  1159. mvs_free_reg_set(mvi, mvi_dev);
  1160. mvs_free_dev(mvi_dev);
  1161. } else {
  1162. mv_dprintk("found dev has gone.\n");
  1163. }
  1164. dev->lldd_dev = NULL;
  1165. mvi_dev->sas_device = NULL;
  1166. spin_unlock_irqrestore(&mvi->lock, flags);
  1167. }
  1168. void mvs_dev_gone(struct domain_device *dev)
  1169. {
  1170. mvs_dev_gone_notify(dev);
  1171. }
  1172. static struct sas_task *mvs_alloc_task(void)
  1173. {
  1174. struct sas_task *task = kzalloc(sizeof(struct sas_task), GFP_KERNEL);
  1175. if (task) {
  1176. INIT_LIST_HEAD(&task->list);
  1177. spin_lock_init(&task->task_state_lock);
  1178. task->task_state_flags = SAS_TASK_STATE_PENDING;
  1179. init_timer(&task->timer);
  1180. init_completion(&task->completion);
  1181. }
  1182. return task;
  1183. }
  1184. static void mvs_free_task(struct sas_task *task)
  1185. {
  1186. if (task) {
  1187. BUG_ON(!list_empty(&task->list));
  1188. kfree(task);
  1189. }
  1190. }
  1191. static void mvs_task_done(struct sas_task *task)
  1192. {
  1193. if (!del_timer(&task->timer))
  1194. return;
  1195. complete(&task->completion);
  1196. }
  1197. static void mvs_tmf_timedout(unsigned long data)
  1198. {
  1199. struct sas_task *task = (struct sas_task *)data;
  1200. task->task_state_flags |= SAS_TASK_STATE_ABORTED;
  1201. complete(&task->completion);
  1202. }
  1203. #define MVS_TASK_TIMEOUT 20
  1204. static int mvs_exec_internal_tmf_task(struct domain_device *dev,
  1205. void *parameter, u32 para_len, struct mvs_tmf_task *tmf)
  1206. {
  1207. int res, retry;
  1208. struct sas_task *task = NULL;
  1209. for (retry = 0; retry < 3; retry++) {
  1210. task = mvs_alloc_task();
  1211. if (!task)
  1212. return -ENOMEM;
  1213. task->dev = dev;
  1214. task->task_proto = dev->tproto;
  1215. memcpy(&task->ssp_task, parameter, para_len);
  1216. task->task_done = mvs_task_done;
  1217. task->timer.data = (unsigned long) task;
  1218. task->timer.function = mvs_tmf_timedout;
  1219. task->timer.expires = jiffies + MVS_TASK_TIMEOUT*HZ;
  1220. add_timer(&task->timer);
  1221. res = mvs_task_exec(task, 1, GFP_KERNEL, NULL, 1, tmf);
  1222. if (res) {
  1223. del_timer(&task->timer);
  1224. mv_printk("executing internel task failed:%d\n", res);
  1225. goto ex_err;
  1226. }
  1227. wait_for_completion(&task->completion);
  1228. res = TMF_RESP_FUNC_FAILED;
  1229. /* Even TMF timed out, return direct. */
  1230. if ((task->task_state_flags & SAS_TASK_STATE_ABORTED)) {
  1231. if (!(task->task_state_flags & SAS_TASK_STATE_DONE)) {
  1232. mv_printk("TMF task[%x] timeout.\n", tmf->tmf);
  1233. goto ex_err;
  1234. }
  1235. }
  1236. if (task->task_status.resp == SAS_TASK_COMPLETE &&
  1237. task->task_status.stat == SAM_STAT_GOOD) {
  1238. res = TMF_RESP_FUNC_COMPLETE;
  1239. break;
  1240. }
  1241. if (task->task_status.resp == SAS_TASK_COMPLETE &&
  1242. task->task_status.stat == SAS_DATA_UNDERRUN) {
  1243. /* no error, but return the number of bytes of
  1244. * underrun */
  1245. res = task->task_status.residual;
  1246. break;
  1247. }
  1248. if (task->task_status.resp == SAS_TASK_COMPLETE &&
  1249. task->task_status.stat == SAS_DATA_OVERRUN) {
  1250. mv_dprintk("blocked task error.\n");
  1251. res = -EMSGSIZE;
  1252. break;
  1253. } else {
  1254. mv_dprintk(" task to dev %016llx response: 0x%x "
  1255. "status 0x%x\n",
  1256. SAS_ADDR(dev->sas_addr),
  1257. task->task_status.resp,
  1258. task->task_status.stat);
  1259. mvs_free_task(task);
  1260. task = NULL;
  1261. }
  1262. }
  1263. ex_err:
  1264. BUG_ON(retry == 3 && task != NULL);
  1265. if (task != NULL)
  1266. mvs_free_task(task);
  1267. return res;
  1268. }
  1269. static int mvs_debug_issue_ssp_tmf(struct domain_device *dev,
  1270. u8 *lun, struct mvs_tmf_task *tmf)
  1271. {
  1272. struct sas_ssp_task ssp_task;
  1273. if (!(dev->tproto & SAS_PROTOCOL_SSP))
  1274. return TMF_RESP_FUNC_ESUPP;
  1275. memcpy(ssp_task.LUN, lun, 8);
  1276. return mvs_exec_internal_tmf_task(dev, &ssp_task,
  1277. sizeof(ssp_task), tmf);
  1278. }
  1279. /* Standard mandates link reset for ATA (type 0)
  1280. and hard reset for SSP (type 1) , only for RECOVERY */
  1281. static int mvs_debug_I_T_nexus_reset(struct domain_device *dev)
  1282. {
  1283. int rc;
  1284. struct sas_phy *phy = sas_find_local_phy(dev);
  1285. int reset_type = (dev->dev_type == SATA_DEV ||
  1286. (dev->tproto & SAS_PROTOCOL_STP)) ? 0 : 1;
  1287. rc = sas_phy_reset(phy, reset_type);
  1288. msleep(2000);
  1289. return rc;
  1290. }
  1291. /* mandatory SAM-3 */
  1292. int mvs_lu_reset(struct domain_device *dev, u8 *lun)
  1293. {
  1294. unsigned long flags;
  1295. int rc = TMF_RESP_FUNC_FAILED;
  1296. struct mvs_tmf_task tmf_task;
  1297. struct mvs_device * mvi_dev = dev->lldd_dev;
  1298. struct mvs_info *mvi = mvi_dev->mvi_info;
  1299. tmf_task.tmf = TMF_LU_RESET;
  1300. mvi_dev->dev_status = MVS_DEV_EH;
  1301. rc = mvs_debug_issue_ssp_tmf(dev, lun, &tmf_task);
  1302. if (rc == TMF_RESP_FUNC_COMPLETE) {
  1303. spin_lock_irqsave(&mvi->lock, flags);
  1304. mvs_release_task(mvi, dev);
  1305. spin_unlock_irqrestore(&mvi->lock, flags);
  1306. }
  1307. /* If failed, fall-through I_T_Nexus reset */
  1308. mv_printk("%s for device[%x]:rc= %d\n", __func__,
  1309. mvi_dev->device_id, rc);
  1310. return rc;
  1311. }
  1312. int mvs_I_T_nexus_reset(struct domain_device *dev)
  1313. {
  1314. unsigned long flags;
  1315. int rc = TMF_RESP_FUNC_FAILED;
  1316. struct mvs_device * mvi_dev = (struct mvs_device *)dev->lldd_dev;
  1317. struct mvs_info *mvi = mvi_dev->mvi_info;
  1318. if (mvi_dev->dev_status != MVS_DEV_EH)
  1319. return TMF_RESP_FUNC_COMPLETE;
  1320. else
  1321. mvi_dev->dev_status = MVS_DEV_NORMAL;
  1322. rc = mvs_debug_I_T_nexus_reset(dev);
  1323. mv_printk("%s for device[%x]:rc= %d\n",
  1324. __func__, mvi_dev->device_id, rc);
  1325. spin_lock_irqsave(&mvi->lock, flags);
  1326. mvs_release_task(mvi, dev);
  1327. spin_unlock_irqrestore(&mvi->lock, flags);
  1328. return rc;
  1329. }
  1330. /* optional SAM-3 */
  1331. int mvs_query_task(struct sas_task *task)
  1332. {
  1333. u32 tag;
  1334. struct scsi_lun lun;
  1335. struct mvs_tmf_task tmf_task;
  1336. int rc = TMF_RESP_FUNC_FAILED;
  1337. if (task->lldd_task && task->task_proto & SAS_PROTOCOL_SSP) {
  1338. struct scsi_cmnd * cmnd = (struct scsi_cmnd *)task->uldd_task;
  1339. struct domain_device *dev = task->dev;
  1340. struct mvs_device *mvi_dev = (struct mvs_device *)dev->lldd_dev;
  1341. struct mvs_info *mvi = mvi_dev->mvi_info;
  1342. int_to_scsilun(cmnd->device->lun, &lun);
  1343. rc = mvs_find_tag(mvi, task, &tag);
  1344. if (rc == 0) {
  1345. rc = TMF_RESP_FUNC_FAILED;
  1346. return rc;
  1347. }
  1348. tmf_task.tmf = TMF_QUERY_TASK;
  1349. tmf_task.tag_of_task_to_be_managed = cpu_to_le16(tag);
  1350. rc = mvs_debug_issue_ssp_tmf(dev, lun.scsi_lun, &tmf_task);
  1351. switch (rc) {
  1352. /* The task is still in Lun, release it then */
  1353. case TMF_RESP_FUNC_SUCC:
  1354. /* The task is not in Lun or failed, reset the phy */
  1355. case TMF_RESP_FUNC_FAILED:
  1356. case TMF_RESP_FUNC_COMPLETE:
  1357. break;
  1358. }
  1359. }
  1360. mv_printk("%s:rc= %d\n", __func__, rc);
  1361. return rc;
  1362. }
  1363. /* mandatory SAM-3, still need free task/slot info */
  1364. int mvs_abort_task(struct sas_task *task)
  1365. {
  1366. struct scsi_lun lun;
  1367. struct mvs_tmf_task tmf_task;
  1368. struct domain_device *dev = task->dev;
  1369. struct mvs_device *mvi_dev = (struct mvs_device *)dev->lldd_dev;
  1370. struct mvs_info *mvi;
  1371. int rc = TMF_RESP_FUNC_FAILED;
  1372. unsigned long flags;
  1373. u32 tag;
  1374. if (!mvi_dev) {
  1375. mv_printk("Device has removed\n");
  1376. return TMF_RESP_FUNC_FAILED;
  1377. }
  1378. mvi = mvi_dev->mvi_info;
  1379. spin_lock_irqsave(&task->task_state_lock, flags);
  1380. if (task->task_state_flags & SAS_TASK_STATE_DONE) {
  1381. spin_unlock_irqrestore(&task->task_state_lock, flags);
  1382. rc = TMF_RESP_FUNC_COMPLETE;
  1383. goto out;
  1384. }
  1385. spin_unlock_irqrestore(&task->task_state_lock, flags);
  1386. mvi_dev->dev_status = MVS_DEV_EH;
  1387. if (task->lldd_task && task->task_proto & SAS_PROTOCOL_SSP) {
  1388. struct scsi_cmnd * cmnd = (struct scsi_cmnd *)task->uldd_task;
  1389. int_to_scsilun(cmnd->device->lun, &lun);
  1390. rc = mvs_find_tag(mvi, task, &tag);
  1391. if (rc == 0) {
  1392. mv_printk("No such tag in %s\n", __func__);
  1393. rc = TMF_RESP_FUNC_FAILED;
  1394. return rc;
  1395. }
  1396. tmf_task.tmf = TMF_ABORT_TASK;
  1397. tmf_task.tag_of_task_to_be_managed = cpu_to_le16(tag);
  1398. rc = mvs_debug_issue_ssp_tmf(dev, lun.scsi_lun, &tmf_task);
  1399. /* if successful, clear the task and callback forwards.*/
  1400. if (rc == TMF_RESP_FUNC_COMPLETE) {
  1401. u32 slot_no;
  1402. struct mvs_slot_info *slot;
  1403. if (task->lldd_task) {
  1404. slot = task->lldd_task;
  1405. slot_no = (u32) (slot - mvi->slot_info);
  1406. spin_lock_irqsave(&mvi->lock, flags);
  1407. mvs_slot_complete(mvi, slot_no, 1);
  1408. spin_unlock_irqrestore(&mvi->lock, flags);
  1409. }
  1410. }
  1411. } else if (task->task_proto & SAS_PROTOCOL_SATA ||
  1412. task->task_proto & SAS_PROTOCOL_STP) {
  1413. if (SATA_DEV == dev->dev_type) {
  1414. struct mvs_slot_info *slot = task->lldd_task;
  1415. u32 slot_idx = (u32)(slot - mvi->slot_info);
  1416. mv_dprintk("mvs_abort_task() mvi=%p task=%p "
  1417. "slot=%p slot_idx=x%x\n",
  1418. mvi, task, slot, slot_idx);
  1419. mvs_tmf_timedout((unsigned long)task);
  1420. mvs_slot_task_free(mvi, task, slot, slot_idx);
  1421. rc = TMF_RESP_FUNC_COMPLETE;
  1422. goto out;
  1423. }
  1424. }
  1425. out:
  1426. if (rc != TMF_RESP_FUNC_COMPLETE)
  1427. mv_printk("%s:rc= %d\n", __func__, rc);
  1428. return rc;
  1429. }
  1430. int mvs_abort_task_set(struct domain_device *dev, u8 *lun)
  1431. {
  1432. int rc = TMF_RESP_FUNC_FAILED;
  1433. struct mvs_tmf_task tmf_task;
  1434. tmf_task.tmf = TMF_ABORT_TASK_SET;
  1435. rc = mvs_debug_issue_ssp_tmf(dev, lun, &tmf_task);
  1436. return rc;
  1437. }
  1438. int mvs_clear_aca(struct domain_device *dev, u8 *lun)
  1439. {
  1440. int rc = TMF_RESP_FUNC_FAILED;
  1441. struct mvs_tmf_task tmf_task;
  1442. tmf_task.tmf = TMF_CLEAR_ACA;
  1443. rc = mvs_debug_issue_ssp_tmf(dev, lun, &tmf_task);
  1444. return rc;
  1445. }
  1446. int mvs_clear_task_set(struct domain_device *dev, u8 *lun)
  1447. {
  1448. int rc = TMF_RESP_FUNC_FAILED;
  1449. struct mvs_tmf_task tmf_task;
  1450. tmf_task.tmf = TMF_CLEAR_TASK_SET;
  1451. rc = mvs_debug_issue_ssp_tmf(dev, lun, &tmf_task);
  1452. return rc;
  1453. }
  1454. static int mvs_sata_done(struct mvs_info *mvi, struct sas_task *task,
  1455. u32 slot_idx, int err)
  1456. {
  1457. struct mvs_device *mvi_dev = task->dev->lldd_dev;
  1458. struct task_status_struct *tstat = &task->task_status;
  1459. struct ata_task_resp *resp = (struct ata_task_resp *)tstat->buf;
  1460. int stat = SAM_STAT_GOOD;
  1461. resp->frame_len = sizeof(struct dev_to_host_fis);
  1462. memcpy(&resp->ending_fis[0],
  1463. SATA_RECEIVED_D2H_FIS(mvi_dev->taskfileset),
  1464. sizeof(struct dev_to_host_fis));
  1465. tstat->buf_valid_size = sizeof(*resp);
  1466. if (unlikely(err)) {
  1467. if (unlikely(err & CMD_ISS_STPD))
  1468. stat = SAS_OPEN_REJECT;
  1469. else
  1470. stat = SAS_PROTO_RESPONSE;
  1471. }
  1472. return stat;
  1473. }
  1474. void mvs_set_sense(u8 *buffer, int len, int d_sense,
  1475. int key, int asc, int ascq)
  1476. {
  1477. memset(buffer, 0, len);
  1478. if (d_sense) {
  1479. /* Descriptor format */
  1480. if (len < 4) {
  1481. mv_printk("Length %d of sense buffer too small to "
  1482. "fit sense %x:%x:%x", len, key, asc, ascq);
  1483. }
  1484. buffer[0] = 0x72; /* Response Code */
  1485. if (len > 1)
  1486. buffer[1] = key; /* Sense Key */
  1487. if (len > 2)
  1488. buffer[2] = asc; /* ASC */
  1489. if (len > 3)
  1490. buffer[3] = ascq; /* ASCQ */
  1491. } else {
  1492. if (len < 14) {
  1493. mv_printk("Length %d of sense buffer too small to "
  1494. "fit sense %x:%x:%x", len, key, asc, ascq);
  1495. }
  1496. buffer[0] = 0x70; /* Response Code */
  1497. if (len > 2)
  1498. buffer[2] = key; /* Sense Key */
  1499. if (len > 7)
  1500. buffer[7] = 0x0a; /* Additional Sense Length */
  1501. if (len > 12)
  1502. buffer[12] = asc; /* ASC */
  1503. if (len > 13)
  1504. buffer[13] = ascq; /* ASCQ */
  1505. }
  1506. return;
  1507. }
  1508. void mvs_fill_ssp_resp_iu(struct ssp_response_iu *iu,
  1509. u8 key, u8 asc, u8 asc_q)
  1510. {
  1511. iu->datapres = 2;
  1512. iu->response_data_len = 0;
  1513. iu->sense_data_len = 17;
  1514. iu->status = 02;
  1515. mvs_set_sense(iu->sense_data, 17, 0,
  1516. key, asc, asc_q);
  1517. }
  1518. static int mvs_slot_err(struct mvs_info *mvi, struct sas_task *task,
  1519. u32 slot_idx)
  1520. {
  1521. struct mvs_slot_info *slot = &mvi->slot_info[slot_idx];
  1522. int stat;
  1523. u32 err_dw0 = le32_to_cpu(*(u32 *)slot->response);
  1524. u32 err_dw1 = le32_to_cpu(*((u32 *)slot->response + 1));
  1525. u32 tfs = 0;
  1526. enum mvs_port_type type = PORT_TYPE_SAS;
  1527. if (err_dw0 & CMD_ISS_STPD)
  1528. MVS_CHIP_DISP->issue_stop(mvi, type, tfs);
  1529. MVS_CHIP_DISP->command_active(mvi, slot_idx);
  1530. stat = SAM_STAT_CHECK_CONDITION;
  1531. switch (task->task_proto) {
  1532. case SAS_PROTOCOL_SSP:
  1533. {
  1534. stat = SAS_ABORTED_TASK;
  1535. if ((err_dw0 & NO_DEST) || err_dw1 & bit(31)) {
  1536. struct ssp_response_iu *iu = slot->response +
  1537. sizeof(struct mvs_err_info);
  1538. mvs_fill_ssp_resp_iu(iu, NOT_READY, 0x04, 01);
  1539. sas_ssp_task_response(mvi->dev, task, iu);
  1540. stat = SAM_STAT_CHECK_CONDITION;
  1541. }
  1542. if (err_dw1 & bit(31))
  1543. mv_printk("reuse same slot, retry command.\n");
  1544. break;
  1545. }
  1546. case SAS_PROTOCOL_SMP:
  1547. stat = SAM_STAT_CHECK_CONDITION;
  1548. break;
  1549. case SAS_PROTOCOL_SATA:
  1550. case SAS_PROTOCOL_STP:
  1551. case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
  1552. {
  1553. task->ata_task.use_ncq = 0;
  1554. stat = SAS_PROTO_RESPONSE;
  1555. mvs_sata_done(mvi, task, slot_idx, err_dw0);
  1556. }
  1557. break;
  1558. default:
  1559. break;
  1560. }
  1561. return stat;
  1562. }
  1563. int mvs_slot_complete(struct mvs_info *mvi, u32 rx_desc, u32 flags)
  1564. {
  1565. u32 slot_idx = rx_desc & RXQ_SLOT_MASK;
  1566. struct mvs_slot_info *slot = &mvi->slot_info[slot_idx];
  1567. struct sas_task *task = slot->task;
  1568. struct mvs_device *mvi_dev = NULL;
  1569. struct task_status_struct *tstat;
  1570. struct domain_device *dev;
  1571. u32 aborted;
  1572. void *to;
  1573. enum exec_status sts;
  1574. if (unlikely(!task || !task->lldd_task || !task->dev))
  1575. return -1;
  1576. tstat = &task->task_status;
  1577. dev = task->dev;
  1578. mvi_dev = dev->lldd_dev;
  1579. spin_lock(&task->task_state_lock);
  1580. task->task_state_flags &=
  1581. ~(SAS_TASK_STATE_PENDING | SAS_TASK_AT_INITIATOR);
  1582. task->task_state_flags |= SAS_TASK_STATE_DONE;
  1583. /* race condition*/
  1584. aborted = task->task_state_flags & SAS_TASK_STATE_ABORTED;
  1585. spin_unlock(&task->task_state_lock);
  1586. memset(tstat, 0, sizeof(*tstat));
  1587. tstat->resp = SAS_TASK_COMPLETE;
  1588. if (unlikely(aborted)) {
  1589. tstat->stat = SAS_ABORTED_TASK;
  1590. if (mvi_dev && mvi_dev->running_req)
  1591. mvi_dev->running_req--;
  1592. if (sas_protocol_ata(task->task_proto))
  1593. mvs_free_reg_set(mvi, mvi_dev);
  1594. mvs_slot_task_free(mvi, task, slot, slot_idx);
  1595. return -1;
  1596. }
  1597. /* when no device attaching, go ahead and complete by error handling*/
  1598. if (unlikely(!mvi_dev || flags)) {
  1599. if (!mvi_dev)
  1600. mv_dprintk("port has not device.\n");
  1601. tstat->stat = SAS_PHY_DOWN;
  1602. goto out;
  1603. }
  1604. /* error info record present */
  1605. if (unlikely((rx_desc & RXQ_ERR) && (*(u64 *) slot->response))) {
  1606. mv_dprintk("port %d slot %d rx_desc %X has error info"
  1607. "%016llX.\n", slot->port->sas_port.id, slot_idx,
  1608. rx_desc, (u64)(*(u64 *)slot->response));
  1609. tstat->stat = mvs_slot_err(mvi, task, slot_idx);
  1610. tstat->resp = SAS_TASK_COMPLETE;
  1611. goto out;
  1612. }
  1613. switch (task->task_proto) {
  1614. case SAS_PROTOCOL_SSP:
  1615. /* hw says status == 0, datapres == 0 */
  1616. if (rx_desc & RXQ_GOOD) {
  1617. tstat->stat = SAM_STAT_GOOD;
  1618. tstat->resp = SAS_TASK_COMPLETE;
  1619. }
  1620. /* response frame present */
  1621. else if (rx_desc & RXQ_RSP) {
  1622. struct ssp_response_iu *iu = slot->response +
  1623. sizeof(struct mvs_err_info);
  1624. sas_ssp_task_response(mvi->dev, task, iu);
  1625. } else
  1626. tstat->stat = SAM_STAT_CHECK_CONDITION;
  1627. break;
  1628. case SAS_PROTOCOL_SMP: {
  1629. struct scatterlist *sg_resp = &task->smp_task.smp_resp;
  1630. tstat->stat = SAM_STAT_GOOD;
  1631. to = kmap_atomic(sg_page(sg_resp), KM_IRQ0);
  1632. memcpy(to + sg_resp->offset,
  1633. slot->response + sizeof(struct mvs_err_info),
  1634. sg_dma_len(sg_resp));
  1635. kunmap_atomic(to, KM_IRQ0);
  1636. break;
  1637. }
  1638. case SAS_PROTOCOL_SATA:
  1639. case SAS_PROTOCOL_STP:
  1640. case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP: {
  1641. tstat->stat = mvs_sata_done(mvi, task, slot_idx, 0);
  1642. break;
  1643. }
  1644. default:
  1645. tstat->stat = SAM_STAT_CHECK_CONDITION;
  1646. break;
  1647. }
  1648. if (!slot->port->port_attached) {
  1649. mv_dprintk("port %d has removed.\n", slot->port->sas_port.id);
  1650. tstat->stat = SAS_PHY_DOWN;
  1651. }
  1652. out:
  1653. if (mvi_dev && mvi_dev->running_req) {
  1654. mvi_dev->running_req--;
  1655. if (sas_protocol_ata(task->task_proto) && !mvi_dev->running_req)
  1656. mvs_free_reg_set(mvi, mvi_dev);
  1657. }
  1658. mvs_slot_task_free(mvi, task, slot, slot_idx);
  1659. sts = tstat->stat;
  1660. spin_unlock(&mvi->lock);
  1661. if (task->task_done)
  1662. task->task_done(task);
  1663. spin_lock(&mvi->lock);
  1664. return sts;
  1665. }
  1666. void mvs_do_release_task(struct mvs_info *mvi,
  1667. int phy_no, struct domain_device *dev)
  1668. {
  1669. u32 slot_idx;
  1670. struct mvs_phy *phy;
  1671. struct mvs_port *port;
  1672. struct mvs_slot_info *slot, *slot2;
  1673. phy = &mvi->phy[phy_no];
  1674. port = phy->port;
  1675. if (!port)
  1676. return;
  1677. /* clean cmpl queue in case request is already finished */
  1678. mvs_int_rx(mvi, false);
  1679. list_for_each_entry_safe(slot, slot2, &port->list, entry) {
  1680. struct sas_task *task;
  1681. slot_idx = (u32) (slot - mvi->slot_info);
  1682. task = slot->task;
  1683. if (dev && task->dev != dev)
  1684. continue;
  1685. mv_printk("Release slot [%x] tag[%x], task [%p]:\n",
  1686. slot_idx, slot->slot_tag, task);
  1687. MVS_CHIP_DISP->command_active(mvi, slot_idx);
  1688. mvs_slot_complete(mvi, slot_idx, 1);
  1689. }
  1690. }
  1691. void mvs_release_task(struct mvs_info *mvi,
  1692. struct domain_device *dev)
  1693. {
  1694. int i, phyno[WIDE_PORT_MAX_PHY], num;
  1695. num = mvs_find_dev_phyno(dev, phyno);
  1696. for (i = 0; i < num; i++)
  1697. mvs_do_release_task(mvi, phyno[i], dev);
  1698. }
  1699. static void mvs_phy_disconnected(struct mvs_phy *phy)
  1700. {
  1701. phy->phy_attached = 0;
  1702. phy->att_dev_info = 0;
  1703. phy->att_dev_sas_addr = 0;
  1704. }
  1705. static void mvs_work_queue(struct work_struct *work)
  1706. {
  1707. struct delayed_work *dw = container_of(work, struct delayed_work, work);
  1708. struct mvs_wq *mwq = container_of(dw, struct mvs_wq, work_q);
  1709. struct mvs_info *mvi = mwq->mvi;
  1710. unsigned long flags;
  1711. u32 phy_no = (unsigned long) mwq->data;
  1712. struct sas_ha_struct *sas_ha = mvi->sas;
  1713. struct mvs_phy *phy = &mvi->phy[phy_no];
  1714. struct asd_sas_phy *sas_phy = &phy->sas_phy;
  1715. spin_lock_irqsave(&mvi->lock, flags);
  1716. if (mwq->handler & PHY_PLUG_EVENT) {
  1717. if (phy->phy_event & PHY_PLUG_OUT) {
  1718. u32 tmp;
  1719. struct sas_identify_frame *id;
  1720. id = (struct sas_identify_frame *)phy->frame_rcvd;
  1721. tmp = MVS_CHIP_DISP->read_phy_ctl(mvi, phy_no);
  1722. phy->phy_event &= ~PHY_PLUG_OUT;
  1723. if (!(tmp & PHY_READY_MASK)) {
  1724. sas_phy_disconnected(sas_phy);
  1725. mvs_phy_disconnected(phy);
  1726. sas_ha->notify_phy_event(sas_phy,
  1727. PHYE_LOSS_OF_SIGNAL);
  1728. mv_dprintk("phy%d Removed Device\n", phy_no);
  1729. } else {
  1730. MVS_CHIP_DISP->detect_porttype(mvi, phy_no);
  1731. mvs_update_phyinfo(mvi, phy_no, 1);
  1732. mvs_bytes_dmaed(mvi, phy_no);
  1733. mvs_port_notify_formed(sas_phy, 0);
  1734. mv_dprintk("phy%d Attached Device\n", phy_no);
  1735. }
  1736. }
  1737. } else if (mwq->handler & EXP_BRCT_CHG) {
  1738. phy->phy_event &= ~EXP_BRCT_CHG;
  1739. sas_ha->notify_port_event(sas_phy,
  1740. PORTE_BROADCAST_RCVD);
  1741. mv_dprintk("phy%d Got Broadcast Change\n", phy_no);
  1742. }
  1743. list_del(&mwq->entry);
  1744. spin_unlock_irqrestore(&mvi->lock, flags);
  1745. kfree(mwq);
  1746. }
  1747. static int mvs_handle_event(struct mvs_info *mvi, void *data, int handler)
  1748. {
  1749. struct mvs_wq *mwq;
  1750. int ret = 0;
  1751. mwq = kmalloc(sizeof(struct mvs_wq), GFP_ATOMIC);
  1752. if (mwq) {
  1753. mwq->mvi = mvi;
  1754. mwq->data = data;
  1755. mwq->handler = handler;
  1756. MV_INIT_DELAYED_WORK(&mwq->work_q, mvs_work_queue, mwq);
  1757. list_add_tail(&mwq->entry, &mvi->wq_list);
  1758. schedule_delayed_work(&mwq->work_q, HZ * 2);
  1759. } else
  1760. ret = -ENOMEM;
  1761. return ret;
  1762. }
  1763. static void mvs_sig_time_out(unsigned long tphy)
  1764. {
  1765. struct mvs_phy *phy = (struct mvs_phy *)tphy;
  1766. struct mvs_info *mvi = phy->mvi;
  1767. u8 phy_no;
  1768. for (phy_no = 0; phy_no < mvi->chip->n_phy; phy_no++) {
  1769. if (&mvi->phy[phy_no] == phy) {
  1770. mv_dprintk("Get signature time out, reset phy %d\n",
  1771. phy_no+mvi->id*mvi->chip->n_phy);
  1772. MVS_CHIP_DISP->phy_reset(mvi, phy_no, MVS_HARD_RESET);
  1773. }
  1774. }
  1775. }
  1776. void mvs_int_port(struct mvs_info *mvi, int phy_no, u32 events)
  1777. {
  1778. u32 tmp;
  1779. struct mvs_phy *phy = &mvi->phy[phy_no];
  1780. phy->irq_status = MVS_CHIP_DISP->read_port_irq_stat(mvi, phy_no);
  1781. MVS_CHIP_DISP->write_port_irq_stat(mvi, phy_no, phy->irq_status);
  1782. mv_dprintk("phy %d ctrl sts=0x%08X.\n", phy_no+mvi->id*mvi->chip->n_phy,
  1783. MVS_CHIP_DISP->read_phy_ctl(mvi, phy_no));
  1784. mv_dprintk("phy %d irq sts = 0x%08X\n", phy_no+mvi->id*mvi->chip->n_phy,
  1785. phy->irq_status);
  1786. /*
  1787. * events is port event now ,
  1788. * we need check the interrupt status which belongs to per port.
  1789. */
  1790. if (phy->irq_status & PHYEV_DCDR_ERR) {
  1791. mv_dprintk("phy %d STP decoding error.\n",
  1792. phy_no + mvi->id*mvi->chip->n_phy);
  1793. }
  1794. if (phy->irq_status & PHYEV_POOF) {
  1795. mdelay(500);
  1796. if (!(phy->phy_event & PHY_PLUG_OUT)) {
  1797. int dev_sata = phy->phy_type & PORT_TYPE_SATA;
  1798. int ready;
  1799. mvs_do_release_task(mvi, phy_no, NULL);
  1800. phy->phy_event |= PHY_PLUG_OUT;
  1801. MVS_CHIP_DISP->clear_srs_irq(mvi, 0, 1);
  1802. mvs_handle_event(mvi,
  1803. (void *)(unsigned long)phy_no,
  1804. PHY_PLUG_EVENT);
  1805. ready = mvs_is_phy_ready(mvi, phy_no);
  1806. if (ready || dev_sata) {
  1807. if (MVS_CHIP_DISP->stp_reset)
  1808. MVS_CHIP_DISP->stp_reset(mvi,
  1809. phy_no);
  1810. else
  1811. MVS_CHIP_DISP->phy_reset(mvi,
  1812. phy_no, MVS_SOFT_RESET);
  1813. return;
  1814. }
  1815. }
  1816. }
  1817. if (phy->irq_status & PHYEV_COMWAKE) {
  1818. tmp = MVS_CHIP_DISP->read_port_irq_mask(mvi, phy_no);
  1819. MVS_CHIP_DISP->write_port_irq_mask(mvi, phy_no,
  1820. tmp | PHYEV_SIG_FIS);
  1821. if (phy->timer.function == NULL) {
  1822. phy->timer.data = (unsigned long)phy;
  1823. phy->timer.function = mvs_sig_time_out;
  1824. phy->timer.expires = jiffies + 5*HZ;
  1825. add_timer(&phy->timer);
  1826. }
  1827. }
  1828. if (phy->irq_status & (PHYEV_SIG_FIS | PHYEV_ID_DONE)) {
  1829. phy->phy_status = mvs_is_phy_ready(mvi, phy_no);
  1830. mv_dprintk("notify plug in on phy[%d]\n", phy_no);
  1831. if (phy->phy_status) {
  1832. mdelay(10);
  1833. MVS_CHIP_DISP->detect_porttype(mvi, phy_no);
  1834. if (phy->phy_type & PORT_TYPE_SATA) {
  1835. tmp = MVS_CHIP_DISP->read_port_irq_mask(
  1836. mvi, phy_no);
  1837. tmp &= ~PHYEV_SIG_FIS;
  1838. MVS_CHIP_DISP->write_port_irq_mask(mvi,
  1839. phy_no, tmp);
  1840. }
  1841. mvs_update_phyinfo(mvi, phy_no, 0);
  1842. if (phy->phy_type & PORT_TYPE_SAS) {
  1843. MVS_CHIP_DISP->phy_reset(mvi, phy_no, MVS_PHY_TUNE);
  1844. mdelay(10);
  1845. }
  1846. mvs_bytes_dmaed(mvi, phy_no);
  1847. /* whether driver is going to handle hot plug */
  1848. if (phy->phy_event & PHY_PLUG_OUT) {
  1849. mvs_port_notify_formed(&phy->sas_phy, 0);
  1850. phy->phy_event &= ~PHY_PLUG_OUT;
  1851. }
  1852. } else {
  1853. mv_dprintk("plugin interrupt but phy%d is gone\n",
  1854. phy_no + mvi->id*mvi->chip->n_phy);
  1855. }
  1856. } else if (phy->irq_status & PHYEV_BROAD_CH) {
  1857. mv_dprintk("phy %d broadcast change.\n",
  1858. phy_no + mvi->id*mvi->chip->n_phy);
  1859. mvs_handle_event(mvi, (void *)(unsigned long)phy_no,
  1860. EXP_BRCT_CHG);
  1861. }
  1862. }
  1863. int mvs_int_rx(struct mvs_info *mvi, bool self_clear)
  1864. {
  1865. u32 rx_prod_idx, rx_desc;
  1866. bool attn = false;
  1867. /* the first dword in the RX ring is special: it contains
  1868. * a mirror of the hardware's RX producer index, so that
  1869. * we don't have to stall the CPU reading that register.
  1870. * The actual RX ring is offset by one dword, due to this.
  1871. */
  1872. rx_prod_idx = mvi->rx_cons;
  1873. mvi->rx_cons = le32_to_cpu(mvi->rx[0]);
  1874. if (mvi->rx_cons == 0xfff) /* h/w hasn't touched RX ring yet */
  1875. return 0;
  1876. /* The CMPL_Q may come late, read from register and try again
  1877. * note: if coalescing is enabled,
  1878. * it will need to read from register every time for sure
  1879. */
  1880. if (unlikely(mvi->rx_cons == rx_prod_idx))
  1881. mvi->rx_cons = MVS_CHIP_DISP->rx_update(mvi) & RX_RING_SZ_MASK;
  1882. if (mvi->rx_cons == rx_prod_idx)
  1883. return 0;
  1884. while (mvi->rx_cons != rx_prod_idx) {
  1885. /* increment our internal RX consumer pointer */
  1886. rx_prod_idx = (rx_prod_idx + 1) & (MVS_RX_RING_SZ - 1);
  1887. rx_desc = le32_to_cpu(mvi->rx[rx_prod_idx + 1]);
  1888. if (likely(rx_desc & RXQ_DONE))
  1889. mvs_slot_complete(mvi, rx_desc, 0);
  1890. if (rx_desc & RXQ_ATTN) {
  1891. attn = true;
  1892. } else if (rx_desc & RXQ_ERR) {
  1893. if (!(rx_desc & RXQ_DONE))
  1894. mvs_slot_complete(mvi, rx_desc, 0);
  1895. } else if (rx_desc & RXQ_SLOT_RESET) {
  1896. mvs_slot_free(mvi, rx_desc);
  1897. }
  1898. }
  1899. if (attn && self_clear)
  1900. MVS_CHIP_DISP->int_full(mvi);
  1901. return 0;
  1902. }