sun4m_smp.c 7.2 KB

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  1. /*
  2. * sun4m SMP support.
  3. *
  4. * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu)
  5. */
  6. #include <linux/interrupt.h>
  7. #include <linux/profile.h>
  8. #include <linux/delay.h>
  9. #include <linux/cpu.h>
  10. #include <asm/cacheflush.h>
  11. #include <asm/tlbflush.h>
  12. #include "irq.h"
  13. #include "kernel.h"
  14. #define IRQ_IPI_SINGLE 12
  15. #define IRQ_IPI_MASK 13
  16. #define IRQ_IPI_RESCHED 14
  17. #define IRQ_CROSS_CALL 15
  18. static inline unsigned long
  19. swap_ulong(volatile unsigned long *ptr, unsigned long val)
  20. {
  21. __asm__ __volatile__("swap [%1], %0\n\t" :
  22. "=&r" (val), "=&r" (ptr) :
  23. "0" (val), "1" (ptr));
  24. return val;
  25. }
  26. static void smp4m_ipi_init(void);
  27. static void smp_setup_percpu_timer(void);
  28. void __cpuinit smp4m_callin(void)
  29. {
  30. int cpuid = hard_smp_processor_id();
  31. local_flush_cache_all();
  32. local_flush_tlb_all();
  33. notify_cpu_starting(cpuid);
  34. /* Get our local ticker going. */
  35. smp_setup_percpu_timer();
  36. calibrate_delay();
  37. smp_store_cpu_info(cpuid);
  38. local_flush_cache_all();
  39. local_flush_tlb_all();
  40. /*
  41. * Unblock the master CPU _only_ when the scheduler state
  42. * of all secondary CPUs will be up-to-date, so after
  43. * the SMP initialization the master will be just allowed
  44. * to call the scheduler code.
  45. */
  46. /* Allow master to continue. */
  47. swap_ulong(&cpu_callin_map[cpuid], 1);
  48. /* XXX: What's up with all the flushes? */
  49. local_flush_cache_all();
  50. local_flush_tlb_all();
  51. /* Fix idle thread fields. */
  52. __asm__ __volatile__("ld [%0], %%g6\n\t"
  53. : : "r" (&current_set[cpuid])
  54. : "memory" /* paranoid */);
  55. /* Attach to the address space of init_task. */
  56. atomic_inc(&init_mm.mm_count);
  57. current->active_mm = &init_mm;
  58. while (!cpumask_test_cpu(cpuid, &smp_commenced_mask))
  59. mb();
  60. local_irq_enable();
  61. set_cpu_online(cpuid, true);
  62. }
  63. /*
  64. * Cycle through the processors asking the PROM to start each one.
  65. */
  66. void __init smp4m_boot_cpus(void)
  67. {
  68. smp4m_ipi_init();
  69. smp_setup_percpu_timer();
  70. local_flush_cache_all();
  71. }
  72. int __cpuinit smp4m_boot_one_cpu(int i)
  73. {
  74. unsigned long *entry = &sun4m_cpu_startup;
  75. struct task_struct *p;
  76. int timeout;
  77. int cpu_node;
  78. cpu_find_by_mid(i, &cpu_node);
  79. /* Cook up an idler for this guy. */
  80. p = fork_idle(i);
  81. current_set[i] = task_thread_info(p);
  82. /* See trampoline.S for details... */
  83. entry += ((i - 1) * 3);
  84. /*
  85. * Initialize the contexts table
  86. * Since the call to prom_startcpu() trashes the structure,
  87. * we need to re-initialize it for each cpu
  88. */
  89. smp_penguin_ctable.which_io = 0;
  90. smp_penguin_ctable.phys_addr = (unsigned int) srmmu_ctx_table_phys;
  91. smp_penguin_ctable.reg_size = 0;
  92. /* whirrr, whirrr, whirrrrrrrrr... */
  93. printk(KERN_INFO "Starting CPU %d at %p\n", i, entry);
  94. local_flush_cache_all();
  95. prom_startcpu(cpu_node, &smp_penguin_ctable, 0, (char *)entry);
  96. /* wheee... it's going... */
  97. for (timeout = 0; timeout < 10000; timeout++) {
  98. if (cpu_callin_map[i])
  99. break;
  100. udelay(200);
  101. }
  102. if (!(cpu_callin_map[i])) {
  103. printk(KERN_ERR "Processor %d is stuck.\n", i);
  104. return -ENODEV;
  105. }
  106. local_flush_cache_all();
  107. return 0;
  108. }
  109. void __init smp4m_smp_done(void)
  110. {
  111. int i, first;
  112. int *prev;
  113. /* setup cpu list for irq rotation */
  114. first = 0;
  115. prev = &first;
  116. for_each_online_cpu(i) {
  117. *prev = i;
  118. prev = &cpu_data(i).next;
  119. }
  120. *prev = first;
  121. local_flush_cache_all();
  122. /* Ok, they are spinning and ready to go. */
  123. }
  124. /* Initialize IPIs on the SUN4M SMP machine */
  125. static void __init smp4m_ipi_init(void)
  126. {
  127. }
  128. static void smp4m_ipi_resched(int cpu)
  129. {
  130. set_cpu_int(cpu, IRQ_IPI_RESCHED);
  131. }
  132. static void smp4m_ipi_single(int cpu)
  133. {
  134. set_cpu_int(cpu, IRQ_IPI_SINGLE);
  135. }
  136. static void smp4m_ipi_mask_one(int cpu)
  137. {
  138. set_cpu_int(cpu, IRQ_IPI_MASK);
  139. }
  140. static struct smp_funcall {
  141. smpfunc_t func;
  142. unsigned long arg1;
  143. unsigned long arg2;
  144. unsigned long arg3;
  145. unsigned long arg4;
  146. unsigned long arg5;
  147. unsigned long processors_in[SUN4M_NCPUS]; /* Set when ipi entered. */
  148. unsigned long processors_out[SUN4M_NCPUS]; /* Set when ipi exited. */
  149. } ccall_info;
  150. static DEFINE_SPINLOCK(cross_call_lock);
  151. /* Cross calls must be serialized, at least currently. */
  152. static void smp4m_cross_call(smpfunc_t func, cpumask_t mask, unsigned long arg1,
  153. unsigned long arg2, unsigned long arg3,
  154. unsigned long arg4)
  155. {
  156. register int ncpus = SUN4M_NCPUS;
  157. unsigned long flags;
  158. spin_lock_irqsave(&cross_call_lock, flags);
  159. /* Init function glue. */
  160. ccall_info.func = func;
  161. ccall_info.arg1 = arg1;
  162. ccall_info.arg2 = arg2;
  163. ccall_info.arg3 = arg3;
  164. ccall_info.arg4 = arg4;
  165. ccall_info.arg5 = 0;
  166. /* Init receive/complete mapping, plus fire the IPI's off. */
  167. {
  168. register int i;
  169. cpumask_clear_cpu(smp_processor_id(), &mask);
  170. cpumask_and(&mask, cpu_online_mask, &mask);
  171. for (i = 0; i < ncpus; i++) {
  172. if (cpumask_test_cpu(i, &mask)) {
  173. ccall_info.processors_in[i] = 0;
  174. ccall_info.processors_out[i] = 0;
  175. set_cpu_int(i, IRQ_CROSS_CALL);
  176. } else {
  177. ccall_info.processors_in[i] = 1;
  178. ccall_info.processors_out[i] = 1;
  179. }
  180. }
  181. }
  182. {
  183. register int i;
  184. i = 0;
  185. do {
  186. if (!cpumask_test_cpu(i, &mask))
  187. continue;
  188. while (!ccall_info.processors_in[i])
  189. barrier();
  190. } while (++i < ncpus);
  191. i = 0;
  192. do {
  193. if (!cpumask_test_cpu(i, &mask))
  194. continue;
  195. while (!ccall_info.processors_out[i])
  196. barrier();
  197. } while (++i < ncpus);
  198. }
  199. spin_unlock_irqrestore(&cross_call_lock, flags);
  200. }
  201. /* Running cross calls. */
  202. void smp4m_cross_call_irq(void)
  203. {
  204. int i = smp_processor_id();
  205. ccall_info.processors_in[i] = 1;
  206. ccall_info.func(ccall_info.arg1, ccall_info.arg2, ccall_info.arg3,
  207. ccall_info.arg4, ccall_info.arg5);
  208. ccall_info.processors_out[i] = 1;
  209. }
  210. void smp4m_percpu_timer_interrupt(struct pt_regs *regs)
  211. {
  212. struct pt_regs *old_regs;
  213. int cpu = smp_processor_id();
  214. old_regs = set_irq_regs(regs);
  215. sun4m_clear_profile_irq(cpu);
  216. profile_tick(CPU_PROFILING);
  217. if (!--prof_counter(cpu)) {
  218. int user = user_mode(regs);
  219. irq_enter();
  220. update_process_times(user);
  221. irq_exit();
  222. prof_counter(cpu) = prof_multiplier(cpu);
  223. }
  224. set_irq_regs(old_regs);
  225. }
  226. static void __cpuinit smp_setup_percpu_timer(void)
  227. {
  228. int cpu = smp_processor_id();
  229. prof_counter(cpu) = prof_multiplier(cpu) = 1;
  230. load_profile_irq(cpu, lvl14_resolution);
  231. if (cpu == boot_cpu_id)
  232. sun4m_unmask_profile_irq();
  233. }
  234. static void __init smp4m_blackbox_id(unsigned *addr)
  235. {
  236. int rd = *addr & 0x3e000000;
  237. int rs1 = rd >> 11;
  238. addr[0] = 0x81580000 | rd; /* rd %tbr, reg */
  239. addr[1] = 0x8130200c | rd | rs1; /* srl reg, 0xc, reg */
  240. addr[2] = 0x80082003 | rd | rs1; /* and reg, 3, reg */
  241. }
  242. static void __init smp4m_blackbox_current(unsigned *addr)
  243. {
  244. int rd = *addr & 0x3e000000;
  245. int rs1 = rd >> 11;
  246. addr[0] = 0x81580000 | rd; /* rd %tbr, reg */
  247. addr[2] = 0x8130200a | rd | rs1; /* srl reg, 0xa, reg */
  248. addr[4] = 0x8008200c | rd | rs1; /* and reg, 0xc, reg */
  249. }
  250. void __init sun4m_init_smp(void)
  251. {
  252. BTFIXUPSET_BLACKBOX(hard_smp_processor_id, smp4m_blackbox_id);
  253. BTFIXUPSET_BLACKBOX(load_current, smp4m_blackbox_current);
  254. BTFIXUPSET_CALL(smp_cross_call, smp4m_cross_call, BTFIXUPCALL_NORM);
  255. BTFIXUPSET_CALL(__hard_smp_processor_id, __smp4m_processor_id, BTFIXUPCALL_NORM);
  256. BTFIXUPSET_CALL(smp_ipi_resched, smp4m_ipi_resched, BTFIXUPCALL_NORM);
  257. BTFIXUPSET_CALL(smp_ipi_single, smp4m_ipi_single, BTFIXUPCALL_NORM);
  258. BTFIXUPSET_CALL(smp_ipi_mask_one, smp4m_ipi_mask_one, BTFIXUPCALL_NORM);
  259. }