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s390
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kernel
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reipl64.S

reipl64.S 4.7 KB
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  1. /*
    2. 

  2.  *    Copyright IBM Corp 2000,2011
    3. 

  3.  *    Author(s): Holger Smolinski <Holger.Smolinski@de.ibm.com>,
    4. 

  4.  *		 Denis Joseph Barrow,
    5. 

  5.  */
    6. 

  6. 

  7. #include <linux/linkage.h>
    8. 

  8. #include <asm/asm-offsets.h>
    9. 

  9. 

  10. #
    11. 

  11. # store_status
    12. 

  12. #
    13. 

  13. # Prerequisites to run this function:
    14. 

  14. # - Prefix register is set to zero
    15. 

  15. # - Original prefix register is stored in "dump_prefix_page"
    16. 

  16. # - Lowcore protection is off
    17. 

  17. #
    18. 

  18. ENTRY(store_status)
    19. 

  19. 	/* Save register one and load save area base */
    20. 

  20. 	stg	%r1,__LC_SAVE_AREA_64(%r0)
    21. 

  21. 	lghi	%r1,SAVE_AREA_BASE
    22. 

  22. 	/* General purpose registers */
    23. 

  23. 	stmg	%r0,%r15,__LC_GPREGS_SAVE_AREA-SAVE_AREA_BASE(%r1)
    24. 

  24. 	lg	%r2,__LC_SAVE_AREA_64(%r0)
    25. 

  25. 	stg	%r2,__LC_GPREGS_SAVE_AREA-SAVE_AREA_BASE+8(%r1)
    26. 

  26. 	/* Control registers */
    27. 

  27. 	stctg	%c0,%c15,__LC_CREGS_SAVE_AREA-SAVE_AREA_BASE(%r1)
    28. 

  28. 	/* Access registers */
    29. 

  29. 	stam	%a0,%a15,__LC_AREGS_SAVE_AREA-SAVE_AREA_BASE(%r1)
    30. 

  30. 	/* Floating point registers */
    31. 

  31. 	std	%f0, 0x00 + __LC_FPREGS_SAVE_AREA-SAVE_AREA_BASE(%r1)
    32. 

  32. 	std	%f1, 0x08 + __LC_FPREGS_SAVE_AREA-SAVE_AREA_BASE(%r1)
    33. 

  33. 	std	%f2, 0x10 + __LC_FPREGS_SAVE_AREA-SAVE_AREA_BASE(%r1)
    34. 

  34. 	std	%f3, 0x18 + __LC_FPREGS_SAVE_AREA-SAVE_AREA_BASE(%r1)
    35. 

  35. 	std	%f4, 0x20 + __LC_FPREGS_SAVE_AREA-SAVE_AREA_BASE(%r1)
    36. 

  36. 	std	%f5, 0x28 + __LC_FPREGS_SAVE_AREA-SAVE_AREA_BASE(%r1)
    37. 

  37. 	std	%f6, 0x30 + __LC_FPREGS_SAVE_AREA-SAVE_AREA_BASE(%r1)
    38. 

  38. 	std	%f7, 0x38 + __LC_FPREGS_SAVE_AREA-SAVE_AREA_BASE(%r1)
    39. 

  39. 	std	%f8, 0x40 + __LC_FPREGS_SAVE_AREA-SAVE_AREA_BASE(%r1)
    40. 

  40. 	std	%f9, 0x48 + __LC_FPREGS_SAVE_AREA-SAVE_AREA_BASE(%r1)
    41. 

  41. 	std	%f10,0x50 + __LC_FPREGS_SAVE_AREA-SAVE_AREA_BASE(%r1)
    42. 

  42. 	std	%f11,0x58 + __LC_FPREGS_SAVE_AREA-SAVE_AREA_BASE(%r1)
    43. 

  43. 	std	%f12,0x60 + __LC_FPREGS_SAVE_AREA-SAVE_AREA_BASE(%r1)
    44. 

  44. 	std	%f13,0x68 + __LC_FPREGS_SAVE_AREA-SAVE_AREA_BASE(%r1)
    45. 

  45. 	std	%f14,0x70 + __LC_FPREGS_SAVE_AREA-SAVE_AREA_BASE(%r1)
    46. 

  46. 	std	%f15,0x78 + __LC_FPREGS_SAVE_AREA-SAVE_AREA_BASE(%r1)
    47. 

  47. 	/* Floating point control register */
    48. 

  48. 	stfpc	__LC_FP_CREG_SAVE_AREA-SAVE_AREA_BASE(%r1)
    49. 

  49. 	/* CPU timer */
    50. 

  50. 	stpt	__LC_CPU_TIMER_SAVE_AREA-SAVE_AREA_BASE(%r1)
    51. 

  51. 	/* Saved prefix register */
    52. 

  52. 	larl	%r2,dump_prefix_page
    53. 

  53. 	mvc	__LC_PREFIX_SAVE_AREA-SAVE_AREA_BASE(4,%r1),0(%r2)
    54. 

  54. 	/* Clock comparator - seven bytes */
    55. 

  55. 	larl	%r2,.Lclkcmp
    56. 

  56. 	stckc	0(%r2)
    57. 

  57. 	mvc	__LC_CLOCK_COMP_SAVE_AREA-SAVE_AREA_BASE + 1(7,%r1),1(%r2)
    58. 

  58. 	/* Program status word */
    59. 

  59. 	epsw	%r2,%r3
    60. 

  60. 	st	%r2,__LC_PSW_SAVE_AREA-SAVE_AREA_BASE + 0(%r1)
    61. 

  61. 	st	%r3,__LC_PSW_SAVE_AREA-SAVE_AREA_BASE + 4(%r1)
    62. 

  62. 	larl	%r2,store_status
    63. 

  63. 	stg	%r2,__LC_PSW_SAVE_AREA-SAVE_AREA_BASE + 8(%r1)
    64. 

  64. 	br	%r14
    65. 

  65. .align	8
    66. 

  66. .Lclkcmp:	.quad	0x0000000000000000
    67. 

  67. 

  68. #
    69. 

  69. # do_reipl_asm
    70. 

  70. # Parameter: r2 = schid of reipl device
    71. 

  71. #
    72. 

  72. 

  73. ENTRY(do_reipl_asm)
    74. 

  74. 		basr	%r13,0
    75. 

  75. .Lpg0:		lpswe	.Lnewpsw-.Lpg0(%r13)
    76. 

  76. .Lpg1:		brasl	%r14,store_status
    77. 

  77. 

  78. 		lctlg	%c6,%c6,.Lall-.Lpg0(%r13)
    79. 

  79. 		lgr	%r1,%r2
    80. 

  80. 		mvc	__LC_PGM_NEW_PSW(16),.Lpcnew-.Lpg0(%r13)
    81. 

  81. 		stsch	.Lschib-.Lpg0(%r13)
    82. 

  82. 		oi	.Lschib+5-.Lpg0(%r13),0x84
    83. 

  83. .Lecs:  	xi	.Lschib+27-.Lpg0(%r13),0x01
    84. 

  84. 		msch	.Lschib-.Lpg0(%r13)
    85. 

  85. 		lghi	%r0,5
    86. 

  86. .Lssch:		ssch	.Liplorb-.Lpg0(%r13)
    87. 

  87. 		jz	.L001
    88. 

  88. 		brct	%r0,.Lssch
    89. 

  89. 		bas	%r14,.Ldisab-.Lpg0(%r13)
    90. 

  90. .L001:		mvc	__LC_IO_NEW_PSW(16),.Lionew-.Lpg0(%r13)
    91. 

  91. .Ltpi:		lpswe	.Lwaitpsw-.Lpg0(%r13)
    92. 

  92. .Lcont:		c	%r1,__LC_SUBCHANNEL_ID
    93. 

  93. 		jnz	.Ltpi
    94. 

  94. 		clc	__LC_IO_INT_PARM(4),.Liplorb-.Lpg0(%r13)
    95. 

  95. 		jnz	.Ltpi
    96. 

  96. 		tsch	.Liplirb-.Lpg0(%r13)
    97. 

  97. 		tm	.Liplirb+9-.Lpg0(%r13),0xbf
    98. 

  98. 		jz	.L002
    99. 

  99. 		bas	%r14,.Ldisab-.Lpg0(%r13)
    100. 

  100. .L002:		tm	.Liplirb+8-.Lpg0(%r13),0xf3
    101. 

  101. 		jz	.L003
    102. 

  102. 		bas	%r14,.Ldisab-.Lpg0(%r13)
    103. 

  103. .L003:		st	%r1,__LC_SUBCHANNEL_ID
    104. 

  104. 		lhi	%r1,0		 # mode 0 = esa
    105. 

  105. 		slr	%r0,%r0 	 # set cpuid to zero
    106. 

  106. 		sigp	%r1,%r0,0x12	 # switch to esa mode
    107. 

  107. 		lpsw	0
    108. 

  108. .Ldisab:	sll	%r14,1
    109. 

  109. 		srl	%r14,1		 # need to kill hi bit to avoid specification exceptions.
    110. 

  110. 		st	%r14,.Ldispsw+12-.Lpg0(%r13)
    111. 

  111. 		lpswe	.Ldispsw-.Lpg0(%r13)
    112. 

  112. 		.align	8
    113. 

  113. .Lall:		.quad	0x00000000ff000000
    114. 

  114. 		.align	16
    115. 

  115. /*
    116. 

  116.  * These addresses have to be 31 bit otherwise
    117. 

  117.  * the sigp will throw a specifcation exception
    118. 

  118.  * when switching to ESA mode as bit 31 be set
    119. 

  119.  * in the ESA psw.
    120. 

  120.  * Bit 31 of the addresses has to be 0 for the
    121. 

  121.  * 31bit lpswe instruction a fact they appear to have
    122. 

  122.  * omitted from the pop.
    123. 

  123.  */
    124. 

  124. .Lnewpsw:	.quad	0x0000000080000000
    125. 

  125. 		.quad	.Lpg1
    126. 

  126. .Lpcnew:	.quad	0x0000000080000000
    127. 

  127. 		.quad	.Lecs
    128. 

  128. .Lionew:	.quad	0x0000000080000000
    129. 

  129. 		.quad	.Lcont
    130. 

  130. .Lwaitpsw:	.quad	0x0202000080000000
    131. 

  131. 		.quad	.Ltpi
    132. 

  132. .Ldispsw:	.quad	0x0002000080000000
    133. 

  133. 		.quad	0x0000000000000000
    134. 

  134. .Liplccws:	.long	0x02000000,0x60000018
    135. 

  135. 		.long	0x08000008,0x20000001
    136. 

  136. .Liplorb:	.long	0x0049504c,0x0040ff80
    137. 

  137. 		.long	0x00000000+.Liplccws
    138. 

  138. .Lschib:	.long	0x00000000,0x00000000
    139. 

  139. 		.long	0x00000000,0x00000000
    140. 

  140. 		.long	0x00000000,0x00000000
    141. 

  141. 		.long	0x00000000,0x00000000
    142. 

  142. 		.long	0x00000000,0x00000000
    143. 

  143. 		.long	0x00000000,0x00000000
    144. 

  144. .Liplirb:	.long	0x00000000,0x00000000
    145. 

  145. 		.long	0x00000000,0x00000000
    146. 

  146. 		.long	0x00000000,0x00000000
    147. 

  147. 		.long	0x00000000,0x00000000
    148. 

  148. 		.long	0x00000000,0x00000000
    149. 

  149. 		.long	0x00000000,0x00000000
    150. 

  150. 		.long	0x00000000,0x00000000
    151. 

  151. 		.long	0x00000000,0x00000000
    152.