cputable.c 64 KB

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  1. /*
  2. * Copyright (C) 2001 Ben. Herrenschmidt (benh@kernel.crashing.org)
  3. *
  4. * Modifications for ppc64:
  5. * Copyright (C) 2003 Dave Engebretsen <engebret@us.ibm.com>
  6. *
  7. * This program is free software; you can redistribute it and/or
  8. * modify it under the terms of the GNU General Public License
  9. * as published by the Free Software Foundation; either version
  10. * 2 of the License, or (at your option) any later version.
  11. */
  12. #include <linux/string.h>
  13. #include <linux/sched.h>
  14. #include <linux/threads.h>
  15. #include <linux/init.h>
  16. #include <linux/module.h>
  17. #include <asm/oprofile_impl.h>
  18. #include <asm/cputable.h>
  19. #include <asm/prom.h> /* for PTRRELOC on ARCH=ppc */
  20. #include <asm/mmu.h>
  21. struct cpu_spec* cur_cpu_spec = NULL;
  22. EXPORT_SYMBOL(cur_cpu_spec);
  23. /* The platform string corresponding to the real PVR */
  24. const char *powerpc_base_platform;
  25. /* NOTE:
  26. * Unlike ppc32, ppc64 will only call this once for the boot CPU, it's
  27. * the responsibility of the appropriate CPU save/restore functions to
  28. * eventually copy these settings over. Those save/restore aren't yet
  29. * part of the cputable though. That has to be fixed for both ppc32
  30. * and ppc64
  31. */
  32. #ifdef CONFIG_PPC32
  33. extern void __setup_cpu_e200(unsigned long offset, struct cpu_spec* spec);
  34. extern void __setup_cpu_e500v1(unsigned long offset, struct cpu_spec* spec);
  35. extern void __setup_cpu_e500v2(unsigned long offset, struct cpu_spec* spec);
  36. extern void __setup_cpu_e500mc(unsigned long offset, struct cpu_spec* spec);
  37. extern void __setup_cpu_440ep(unsigned long offset, struct cpu_spec* spec);
  38. extern void __setup_cpu_440epx(unsigned long offset, struct cpu_spec* spec);
  39. extern void __setup_cpu_440gx(unsigned long offset, struct cpu_spec* spec);
  40. extern void __setup_cpu_440grx(unsigned long offset, struct cpu_spec* spec);
  41. extern void __setup_cpu_440spe(unsigned long offset, struct cpu_spec* spec);
  42. extern void __setup_cpu_440x5(unsigned long offset, struct cpu_spec* spec);
  43. extern void __setup_cpu_460ex(unsigned long offset, struct cpu_spec* spec);
  44. extern void __setup_cpu_460gt(unsigned long offset, struct cpu_spec* spec);
  45. extern void __setup_cpu_460sx(unsigned long offset, struct cpu_spec *spec);
  46. extern void __setup_cpu_apm821xx(unsigned long offset, struct cpu_spec *spec);
  47. extern void __setup_cpu_603(unsigned long offset, struct cpu_spec* spec);
  48. extern void __setup_cpu_604(unsigned long offset, struct cpu_spec* spec);
  49. extern void __setup_cpu_750(unsigned long offset, struct cpu_spec* spec);
  50. extern void __setup_cpu_750cx(unsigned long offset, struct cpu_spec* spec);
  51. extern void __setup_cpu_750fx(unsigned long offset, struct cpu_spec* spec);
  52. extern void __setup_cpu_7400(unsigned long offset, struct cpu_spec* spec);
  53. extern void __setup_cpu_7410(unsigned long offset, struct cpu_spec* spec);
  54. extern void __setup_cpu_745x(unsigned long offset, struct cpu_spec* spec);
  55. #endif /* CONFIG_PPC32 */
  56. #ifdef CONFIG_PPC64
  57. extern void __setup_cpu_ppc970(unsigned long offset, struct cpu_spec* spec);
  58. extern void __setup_cpu_ppc970MP(unsigned long offset, struct cpu_spec* spec);
  59. extern void __setup_cpu_pa6t(unsigned long offset, struct cpu_spec* spec);
  60. extern void __setup_cpu_a2(unsigned long offset, struct cpu_spec* spec);
  61. extern void __restore_cpu_pa6t(void);
  62. extern void __restore_cpu_ppc970(void);
  63. extern void __setup_cpu_power7(unsigned long offset, struct cpu_spec* spec);
  64. extern void __restore_cpu_power7(void);
  65. extern void __restore_cpu_a2(void);
  66. #endif /* CONFIG_PPC64 */
  67. #if defined(CONFIG_E500)
  68. extern void __setup_cpu_e5500(unsigned long offset, struct cpu_spec* spec);
  69. extern void __restore_cpu_e5500(void);
  70. #endif /* CONFIG_E500 */
  71. /* This table only contains "desktop" CPUs, it need to be filled with embedded
  72. * ones as well...
  73. */
  74. #define COMMON_USER (PPC_FEATURE_32 | PPC_FEATURE_HAS_FPU | \
  75. PPC_FEATURE_HAS_MMU)
  76. #define COMMON_USER_PPC64 (COMMON_USER | PPC_FEATURE_64)
  77. #define COMMON_USER_POWER4 (COMMON_USER_PPC64 | PPC_FEATURE_POWER4)
  78. #define COMMON_USER_POWER5 (COMMON_USER_PPC64 | PPC_FEATURE_POWER5 |\
  79. PPC_FEATURE_SMT | PPC_FEATURE_ICACHE_SNOOP)
  80. #define COMMON_USER_POWER5_PLUS (COMMON_USER_PPC64 | PPC_FEATURE_POWER5_PLUS|\
  81. PPC_FEATURE_SMT | PPC_FEATURE_ICACHE_SNOOP)
  82. #define COMMON_USER_POWER6 (COMMON_USER_PPC64 | PPC_FEATURE_ARCH_2_05 |\
  83. PPC_FEATURE_SMT | PPC_FEATURE_ICACHE_SNOOP | \
  84. PPC_FEATURE_TRUE_LE | \
  85. PPC_FEATURE_PSERIES_PERFMON_COMPAT)
  86. #define COMMON_USER_POWER7 (COMMON_USER_PPC64 | PPC_FEATURE_ARCH_2_06 |\
  87. PPC_FEATURE_SMT | PPC_FEATURE_ICACHE_SNOOP | \
  88. PPC_FEATURE_TRUE_LE | \
  89. PPC_FEATURE_PSERIES_PERFMON_COMPAT)
  90. #define COMMON_USER_PA6T (COMMON_USER_PPC64 | PPC_FEATURE_PA6T |\
  91. PPC_FEATURE_TRUE_LE | \
  92. PPC_FEATURE_HAS_ALTIVEC_COMP)
  93. #ifdef CONFIG_PPC_BOOK3E_64
  94. #define COMMON_USER_BOOKE (COMMON_USER_PPC64 | PPC_FEATURE_BOOKE)
  95. #else
  96. #define COMMON_USER_BOOKE (PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU | \
  97. PPC_FEATURE_BOOKE)
  98. #endif
  99. static struct cpu_spec __initdata cpu_specs[] = {
  100. #ifdef CONFIG_PPC_BOOK3S_64
  101. { /* Power3 */
  102. .pvr_mask = 0xffff0000,
  103. .pvr_value = 0x00400000,
  104. .cpu_name = "POWER3 (630)",
  105. .cpu_features = CPU_FTRS_POWER3,
  106. .cpu_user_features = COMMON_USER_PPC64|PPC_FEATURE_PPC_LE,
  107. .mmu_features = MMU_FTR_HPTE_TABLE,
  108. .icache_bsize = 128,
  109. .dcache_bsize = 128,
  110. .num_pmcs = 8,
  111. .pmc_type = PPC_PMC_IBM,
  112. .oprofile_cpu_type = "ppc64/power3",
  113. .oprofile_type = PPC_OPROFILE_RS64,
  114. .platform = "power3",
  115. },
  116. { /* Power3+ */
  117. .pvr_mask = 0xffff0000,
  118. .pvr_value = 0x00410000,
  119. .cpu_name = "POWER3 (630+)",
  120. .cpu_features = CPU_FTRS_POWER3,
  121. .cpu_user_features = COMMON_USER_PPC64|PPC_FEATURE_PPC_LE,
  122. .mmu_features = MMU_FTR_HPTE_TABLE,
  123. .icache_bsize = 128,
  124. .dcache_bsize = 128,
  125. .num_pmcs = 8,
  126. .pmc_type = PPC_PMC_IBM,
  127. .oprofile_cpu_type = "ppc64/power3",
  128. .oprofile_type = PPC_OPROFILE_RS64,
  129. .platform = "power3",
  130. },
  131. { /* Northstar */
  132. .pvr_mask = 0xffff0000,
  133. .pvr_value = 0x00330000,
  134. .cpu_name = "RS64-II (northstar)",
  135. .cpu_features = CPU_FTRS_RS64,
  136. .cpu_user_features = COMMON_USER_PPC64,
  137. .mmu_features = MMU_FTR_HPTE_TABLE,
  138. .icache_bsize = 128,
  139. .dcache_bsize = 128,
  140. .num_pmcs = 8,
  141. .pmc_type = PPC_PMC_IBM,
  142. .oprofile_cpu_type = "ppc64/rs64",
  143. .oprofile_type = PPC_OPROFILE_RS64,
  144. .platform = "rs64",
  145. },
  146. { /* Pulsar */
  147. .pvr_mask = 0xffff0000,
  148. .pvr_value = 0x00340000,
  149. .cpu_name = "RS64-III (pulsar)",
  150. .cpu_features = CPU_FTRS_RS64,
  151. .cpu_user_features = COMMON_USER_PPC64,
  152. .mmu_features = MMU_FTR_HPTE_TABLE,
  153. .icache_bsize = 128,
  154. .dcache_bsize = 128,
  155. .num_pmcs = 8,
  156. .pmc_type = PPC_PMC_IBM,
  157. .oprofile_cpu_type = "ppc64/rs64",
  158. .oprofile_type = PPC_OPROFILE_RS64,
  159. .platform = "rs64",
  160. },
  161. { /* I-star */
  162. .pvr_mask = 0xffff0000,
  163. .pvr_value = 0x00360000,
  164. .cpu_name = "RS64-III (icestar)",
  165. .cpu_features = CPU_FTRS_RS64,
  166. .cpu_user_features = COMMON_USER_PPC64,
  167. .mmu_features = MMU_FTR_HPTE_TABLE,
  168. .icache_bsize = 128,
  169. .dcache_bsize = 128,
  170. .num_pmcs = 8,
  171. .pmc_type = PPC_PMC_IBM,
  172. .oprofile_cpu_type = "ppc64/rs64",
  173. .oprofile_type = PPC_OPROFILE_RS64,
  174. .platform = "rs64",
  175. },
  176. { /* S-star */
  177. .pvr_mask = 0xffff0000,
  178. .pvr_value = 0x00370000,
  179. .cpu_name = "RS64-IV (sstar)",
  180. .cpu_features = CPU_FTRS_RS64,
  181. .cpu_user_features = COMMON_USER_PPC64,
  182. .mmu_features = MMU_FTR_HPTE_TABLE,
  183. .icache_bsize = 128,
  184. .dcache_bsize = 128,
  185. .num_pmcs = 8,
  186. .pmc_type = PPC_PMC_IBM,
  187. .oprofile_cpu_type = "ppc64/rs64",
  188. .oprofile_type = PPC_OPROFILE_RS64,
  189. .platform = "rs64",
  190. },
  191. { /* Power4 */
  192. .pvr_mask = 0xffff0000,
  193. .pvr_value = 0x00350000,
  194. .cpu_name = "POWER4 (gp)",
  195. .cpu_features = CPU_FTRS_POWER4,
  196. .cpu_user_features = COMMON_USER_POWER4,
  197. .mmu_features = MMU_FTRS_POWER4,
  198. .icache_bsize = 128,
  199. .dcache_bsize = 128,
  200. .num_pmcs = 8,
  201. .pmc_type = PPC_PMC_IBM,
  202. .oprofile_cpu_type = "ppc64/power4",
  203. .oprofile_type = PPC_OPROFILE_POWER4,
  204. .platform = "power4",
  205. },
  206. { /* Power4+ */
  207. .pvr_mask = 0xffff0000,
  208. .pvr_value = 0x00380000,
  209. .cpu_name = "POWER4+ (gq)",
  210. .cpu_features = CPU_FTRS_POWER4,
  211. .cpu_user_features = COMMON_USER_POWER4,
  212. .mmu_features = MMU_FTRS_POWER4,
  213. .icache_bsize = 128,
  214. .dcache_bsize = 128,
  215. .num_pmcs = 8,
  216. .pmc_type = PPC_PMC_IBM,
  217. .oprofile_cpu_type = "ppc64/power4",
  218. .oprofile_type = PPC_OPROFILE_POWER4,
  219. .platform = "power4",
  220. },
  221. { /* PPC970 */
  222. .pvr_mask = 0xffff0000,
  223. .pvr_value = 0x00390000,
  224. .cpu_name = "PPC970",
  225. .cpu_features = CPU_FTRS_PPC970,
  226. .cpu_user_features = COMMON_USER_POWER4 |
  227. PPC_FEATURE_HAS_ALTIVEC_COMP,
  228. .mmu_features = MMU_FTRS_PPC970,
  229. .icache_bsize = 128,
  230. .dcache_bsize = 128,
  231. .num_pmcs = 8,
  232. .pmc_type = PPC_PMC_IBM,
  233. .cpu_setup = __setup_cpu_ppc970,
  234. .cpu_restore = __restore_cpu_ppc970,
  235. .oprofile_cpu_type = "ppc64/970",
  236. .oprofile_type = PPC_OPROFILE_POWER4,
  237. .platform = "ppc970",
  238. },
  239. { /* PPC970FX */
  240. .pvr_mask = 0xffff0000,
  241. .pvr_value = 0x003c0000,
  242. .cpu_name = "PPC970FX",
  243. .cpu_features = CPU_FTRS_PPC970,
  244. .cpu_user_features = COMMON_USER_POWER4 |
  245. PPC_FEATURE_HAS_ALTIVEC_COMP,
  246. .mmu_features = MMU_FTRS_PPC970,
  247. .icache_bsize = 128,
  248. .dcache_bsize = 128,
  249. .num_pmcs = 8,
  250. .pmc_type = PPC_PMC_IBM,
  251. .cpu_setup = __setup_cpu_ppc970,
  252. .cpu_restore = __restore_cpu_ppc970,
  253. .oprofile_cpu_type = "ppc64/970",
  254. .oprofile_type = PPC_OPROFILE_POWER4,
  255. .platform = "ppc970",
  256. },
  257. { /* PPC970MP DD1.0 - no DEEPNAP, use regular 970 init */
  258. .pvr_mask = 0xffffffff,
  259. .pvr_value = 0x00440100,
  260. .cpu_name = "PPC970MP",
  261. .cpu_features = CPU_FTRS_PPC970,
  262. .cpu_user_features = COMMON_USER_POWER4 |
  263. PPC_FEATURE_HAS_ALTIVEC_COMP,
  264. .mmu_features = MMU_FTR_HPTE_TABLE,
  265. .icache_bsize = 128,
  266. .dcache_bsize = 128,
  267. .num_pmcs = 8,
  268. .pmc_type = PPC_PMC_IBM,
  269. .cpu_setup = __setup_cpu_ppc970,
  270. .cpu_restore = __restore_cpu_ppc970,
  271. .oprofile_cpu_type = "ppc64/970MP",
  272. .oprofile_type = PPC_OPROFILE_POWER4,
  273. .platform = "ppc970",
  274. },
  275. { /* PPC970MP */
  276. .pvr_mask = 0xffff0000,
  277. .pvr_value = 0x00440000,
  278. .cpu_name = "PPC970MP",
  279. .cpu_features = CPU_FTRS_PPC970,
  280. .cpu_user_features = COMMON_USER_POWER4 |
  281. PPC_FEATURE_HAS_ALTIVEC_COMP,
  282. .mmu_features = MMU_FTRS_PPC970,
  283. .icache_bsize = 128,
  284. .dcache_bsize = 128,
  285. .num_pmcs = 8,
  286. .pmc_type = PPC_PMC_IBM,
  287. .cpu_setup = __setup_cpu_ppc970MP,
  288. .cpu_restore = __restore_cpu_ppc970,
  289. .oprofile_cpu_type = "ppc64/970MP",
  290. .oprofile_type = PPC_OPROFILE_POWER4,
  291. .platform = "ppc970",
  292. },
  293. { /* PPC970GX */
  294. .pvr_mask = 0xffff0000,
  295. .pvr_value = 0x00450000,
  296. .cpu_name = "PPC970GX",
  297. .cpu_features = CPU_FTRS_PPC970,
  298. .cpu_user_features = COMMON_USER_POWER4 |
  299. PPC_FEATURE_HAS_ALTIVEC_COMP,
  300. .mmu_features = MMU_FTRS_PPC970,
  301. .icache_bsize = 128,
  302. .dcache_bsize = 128,
  303. .num_pmcs = 8,
  304. .pmc_type = PPC_PMC_IBM,
  305. .cpu_setup = __setup_cpu_ppc970,
  306. .oprofile_cpu_type = "ppc64/970",
  307. .oprofile_type = PPC_OPROFILE_POWER4,
  308. .platform = "ppc970",
  309. },
  310. { /* Power5 GR */
  311. .pvr_mask = 0xffff0000,
  312. .pvr_value = 0x003a0000,
  313. .cpu_name = "POWER5 (gr)",
  314. .cpu_features = CPU_FTRS_POWER5,
  315. .cpu_user_features = COMMON_USER_POWER5,
  316. .mmu_features = MMU_FTRS_POWER5,
  317. .icache_bsize = 128,
  318. .dcache_bsize = 128,
  319. .num_pmcs = 6,
  320. .pmc_type = PPC_PMC_IBM,
  321. .oprofile_cpu_type = "ppc64/power5",
  322. .oprofile_type = PPC_OPROFILE_POWER4,
  323. /* SIHV / SIPR bits are implemented on POWER4+ (GQ)
  324. * and above but only works on POWER5 and above
  325. */
  326. .oprofile_mmcra_sihv = MMCRA_SIHV,
  327. .oprofile_mmcra_sipr = MMCRA_SIPR,
  328. .platform = "power5",
  329. },
  330. { /* Power5++ */
  331. .pvr_mask = 0xffffff00,
  332. .pvr_value = 0x003b0300,
  333. .cpu_name = "POWER5+ (gs)",
  334. .cpu_features = CPU_FTRS_POWER5,
  335. .cpu_user_features = COMMON_USER_POWER5_PLUS,
  336. .mmu_features = MMU_FTRS_POWER5,
  337. .icache_bsize = 128,
  338. .dcache_bsize = 128,
  339. .num_pmcs = 6,
  340. .oprofile_cpu_type = "ppc64/power5++",
  341. .oprofile_type = PPC_OPROFILE_POWER4,
  342. .oprofile_mmcra_sihv = MMCRA_SIHV,
  343. .oprofile_mmcra_sipr = MMCRA_SIPR,
  344. .platform = "power5+",
  345. },
  346. { /* Power5 GS */
  347. .pvr_mask = 0xffff0000,
  348. .pvr_value = 0x003b0000,
  349. .cpu_name = "POWER5+ (gs)",
  350. .cpu_features = CPU_FTRS_POWER5,
  351. .cpu_user_features = COMMON_USER_POWER5_PLUS,
  352. .mmu_features = MMU_FTRS_POWER5,
  353. .icache_bsize = 128,
  354. .dcache_bsize = 128,
  355. .num_pmcs = 6,
  356. .pmc_type = PPC_PMC_IBM,
  357. .oprofile_cpu_type = "ppc64/power5+",
  358. .oprofile_type = PPC_OPROFILE_POWER4,
  359. .oprofile_mmcra_sihv = MMCRA_SIHV,
  360. .oprofile_mmcra_sipr = MMCRA_SIPR,
  361. .platform = "power5+",
  362. },
  363. { /* POWER6 in P5+ mode; 2.04-compliant processor */
  364. .pvr_mask = 0xffffffff,
  365. .pvr_value = 0x0f000001,
  366. .cpu_name = "POWER5+",
  367. .cpu_features = CPU_FTRS_POWER5,
  368. .cpu_user_features = COMMON_USER_POWER5_PLUS,
  369. .mmu_features = MMU_FTRS_POWER5,
  370. .icache_bsize = 128,
  371. .dcache_bsize = 128,
  372. .oprofile_cpu_type = "ppc64/ibm-compat-v1",
  373. .oprofile_type = PPC_OPROFILE_POWER4,
  374. .platform = "power5+",
  375. },
  376. { /* Power6 */
  377. .pvr_mask = 0xffff0000,
  378. .pvr_value = 0x003e0000,
  379. .cpu_name = "POWER6 (raw)",
  380. .cpu_features = CPU_FTRS_POWER6,
  381. .cpu_user_features = COMMON_USER_POWER6 |
  382. PPC_FEATURE_POWER6_EXT,
  383. .mmu_features = MMU_FTRS_POWER6,
  384. .icache_bsize = 128,
  385. .dcache_bsize = 128,
  386. .num_pmcs = 6,
  387. .pmc_type = PPC_PMC_IBM,
  388. .oprofile_cpu_type = "ppc64/power6",
  389. .oprofile_type = PPC_OPROFILE_POWER4,
  390. .oprofile_mmcra_sihv = POWER6_MMCRA_SIHV,
  391. .oprofile_mmcra_sipr = POWER6_MMCRA_SIPR,
  392. .oprofile_mmcra_clear = POWER6_MMCRA_THRM |
  393. POWER6_MMCRA_OTHER,
  394. .platform = "power6x",
  395. },
  396. { /* 2.05-compliant processor, i.e. Power6 "architected" mode */
  397. .pvr_mask = 0xffffffff,
  398. .pvr_value = 0x0f000002,
  399. .cpu_name = "POWER6 (architected)",
  400. .cpu_features = CPU_FTRS_POWER6,
  401. .cpu_user_features = COMMON_USER_POWER6,
  402. .mmu_features = MMU_FTRS_POWER6,
  403. .icache_bsize = 128,
  404. .dcache_bsize = 128,
  405. .oprofile_cpu_type = "ppc64/ibm-compat-v1",
  406. .oprofile_type = PPC_OPROFILE_POWER4,
  407. .platform = "power6",
  408. },
  409. { /* 2.06-compliant processor, i.e. Power7 "architected" mode */
  410. .pvr_mask = 0xffffffff,
  411. .pvr_value = 0x0f000003,
  412. .cpu_name = "POWER7 (architected)",
  413. .cpu_features = CPU_FTRS_POWER7,
  414. .cpu_user_features = COMMON_USER_POWER7,
  415. .mmu_features = MMU_FTRS_POWER7,
  416. .icache_bsize = 128,
  417. .dcache_bsize = 128,
  418. .oprofile_type = PPC_OPROFILE_POWER4,
  419. .oprofile_cpu_type = "ppc64/ibm-compat-v1",
  420. .cpu_setup = __setup_cpu_power7,
  421. .cpu_restore = __restore_cpu_power7,
  422. .platform = "power7",
  423. },
  424. { /* Power7 */
  425. .pvr_mask = 0xffff0000,
  426. .pvr_value = 0x003f0000,
  427. .cpu_name = "POWER7 (raw)",
  428. .cpu_features = CPU_FTRS_POWER7,
  429. .cpu_user_features = COMMON_USER_POWER7,
  430. .mmu_features = MMU_FTRS_POWER7,
  431. .icache_bsize = 128,
  432. .dcache_bsize = 128,
  433. .num_pmcs = 6,
  434. .pmc_type = PPC_PMC_IBM,
  435. .oprofile_cpu_type = "ppc64/power7",
  436. .oprofile_type = PPC_OPROFILE_POWER4,
  437. .cpu_setup = __setup_cpu_power7,
  438. .cpu_restore = __restore_cpu_power7,
  439. .platform = "power7",
  440. },
  441. { /* Power7+ */
  442. .pvr_mask = 0xffff0000,
  443. .pvr_value = 0x004A0000,
  444. .cpu_name = "POWER7+ (raw)",
  445. .cpu_features = CPU_FTRS_POWER7,
  446. .cpu_user_features = COMMON_USER_POWER7,
  447. .mmu_features = MMU_FTRS_POWER7,
  448. .icache_bsize = 128,
  449. .dcache_bsize = 128,
  450. .num_pmcs = 6,
  451. .pmc_type = PPC_PMC_IBM,
  452. .oprofile_cpu_type = "ppc64/power7",
  453. .oprofile_type = PPC_OPROFILE_POWER4,
  454. .cpu_setup = __setup_cpu_power7,
  455. .cpu_restore = __restore_cpu_power7,
  456. .platform = "power7+",
  457. },
  458. { /* Cell Broadband Engine */
  459. .pvr_mask = 0xffff0000,
  460. .pvr_value = 0x00700000,
  461. .cpu_name = "Cell Broadband Engine",
  462. .cpu_features = CPU_FTRS_CELL,
  463. .cpu_user_features = COMMON_USER_PPC64 |
  464. PPC_FEATURE_CELL | PPC_FEATURE_HAS_ALTIVEC_COMP |
  465. PPC_FEATURE_SMT,
  466. .mmu_features = MMU_FTRS_CELL,
  467. .icache_bsize = 128,
  468. .dcache_bsize = 128,
  469. .num_pmcs = 4,
  470. .pmc_type = PPC_PMC_IBM,
  471. .oprofile_cpu_type = "ppc64/cell-be",
  472. .oprofile_type = PPC_OPROFILE_CELL,
  473. .platform = "ppc-cell-be",
  474. },
  475. { /* PA Semi PA6T */
  476. .pvr_mask = 0x7fff0000,
  477. .pvr_value = 0x00900000,
  478. .cpu_name = "PA6T",
  479. .cpu_features = CPU_FTRS_PA6T,
  480. .cpu_user_features = COMMON_USER_PA6T,
  481. .mmu_features = MMU_FTRS_PA6T,
  482. .icache_bsize = 64,
  483. .dcache_bsize = 64,
  484. .num_pmcs = 6,
  485. .pmc_type = PPC_PMC_PA6T,
  486. .cpu_setup = __setup_cpu_pa6t,
  487. .cpu_restore = __restore_cpu_pa6t,
  488. .oprofile_cpu_type = "ppc64/pa6t",
  489. .oprofile_type = PPC_OPROFILE_PA6T,
  490. .platform = "pa6t",
  491. },
  492. { /* default match */
  493. .pvr_mask = 0x00000000,
  494. .pvr_value = 0x00000000,
  495. .cpu_name = "POWER4 (compatible)",
  496. .cpu_features = CPU_FTRS_COMPATIBLE,
  497. .cpu_user_features = COMMON_USER_PPC64,
  498. .mmu_features = MMU_FTRS_DEFAULT_HPTE_ARCH_V2,
  499. .icache_bsize = 128,
  500. .dcache_bsize = 128,
  501. .num_pmcs = 6,
  502. .pmc_type = PPC_PMC_IBM,
  503. .platform = "power4",
  504. }
  505. #endif /* CONFIG_PPC_BOOK3S_64 */
  506. #ifdef CONFIG_PPC32
  507. #if CLASSIC_PPC
  508. { /* 601 */
  509. .pvr_mask = 0xffff0000,
  510. .pvr_value = 0x00010000,
  511. .cpu_name = "601",
  512. .cpu_features = CPU_FTRS_PPC601,
  513. .cpu_user_features = COMMON_USER | PPC_FEATURE_601_INSTR |
  514. PPC_FEATURE_UNIFIED_CACHE | PPC_FEATURE_NO_TB,
  515. .mmu_features = MMU_FTR_HPTE_TABLE,
  516. .icache_bsize = 32,
  517. .dcache_bsize = 32,
  518. .machine_check = machine_check_generic,
  519. .platform = "ppc601",
  520. },
  521. { /* 603 */
  522. .pvr_mask = 0xffff0000,
  523. .pvr_value = 0x00030000,
  524. .cpu_name = "603",
  525. .cpu_features = CPU_FTRS_603,
  526. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  527. .mmu_features = 0,
  528. .icache_bsize = 32,
  529. .dcache_bsize = 32,
  530. .cpu_setup = __setup_cpu_603,
  531. .machine_check = machine_check_generic,
  532. .platform = "ppc603",
  533. },
  534. { /* 603e */
  535. .pvr_mask = 0xffff0000,
  536. .pvr_value = 0x00060000,
  537. .cpu_name = "603e",
  538. .cpu_features = CPU_FTRS_603,
  539. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  540. .mmu_features = 0,
  541. .icache_bsize = 32,
  542. .dcache_bsize = 32,
  543. .cpu_setup = __setup_cpu_603,
  544. .machine_check = machine_check_generic,
  545. .platform = "ppc603",
  546. },
  547. { /* 603ev */
  548. .pvr_mask = 0xffff0000,
  549. .pvr_value = 0x00070000,
  550. .cpu_name = "603ev",
  551. .cpu_features = CPU_FTRS_603,
  552. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  553. .mmu_features = 0,
  554. .icache_bsize = 32,
  555. .dcache_bsize = 32,
  556. .cpu_setup = __setup_cpu_603,
  557. .machine_check = machine_check_generic,
  558. .platform = "ppc603",
  559. },
  560. { /* 604 */
  561. .pvr_mask = 0xffff0000,
  562. .pvr_value = 0x00040000,
  563. .cpu_name = "604",
  564. .cpu_features = CPU_FTRS_604,
  565. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  566. .mmu_features = MMU_FTR_HPTE_TABLE,
  567. .icache_bsize = 32,
  568. .dcache_bsize = 32,
  569. .num_pmcs = 2,
  570. .cpu_setup = __setup_cpu_604,
  571. .machine_check = machine_check_generic,
  572. .platform = "ppc604",
  573. },
  574. { /* 604e */
  575. .pvr_mask = 0xfffff000,
  576. .pvr_value = 0x00090000,
  577. .cpu_name = "604e",
  578. .cpu_features = CPU_FTRS_604,
  579. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  580. .mmu_features = MMU_FTR_HPTE_TABLE,
  581. .icache_bsize = 32,
  582. .dcache_bsize = 32,
  583. .num_pmcs = 4,
  584. .cpu_setup = __setup_cpu_604,
  585. .machine_check = machine_check_generic,
  586. .platform = "ppc604",
  587. },
  588. { /* 604r */
  589. .pvr_mask = 0xffff0000,
  590. .pvr_value = 0x00090000,
  591. .cpu_name = "604r",
  592. .cpu_features = CPU_FTRS_604,
  593. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  594. .mmu_features = MMU_FTR_HPTE_TABLE,
  595. .icache_bsize = 32,
  596. .dcache_bsize = 32,
  597. .num_pmcs = 4,
  598. .cpu_setup = __setup_cpu_604,
  599. .machine_check = machine_check_generic,
  600. .platform = "ppc604",
  601. },
  602. { /* 604ev */
  603. .pvr_mask = 0xffff0000,
  604. .pvr_value = 0x000a0000,
  605. .cpu_name = "604ev",
  606. .cpu_features = CPU_FTRS_604,
  607. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  608. .mmu_features = MMU_FTR_HPTE_TABLE,
  609. .icache_bsize = 32,
  610. .dcache_bsize = 32,
  611. .num_pmcs = 4,
  612. .cpu_setup = __setup_cpu_604,
  613. .machine_check = machine_check_generic,
  614. .platform = "ppc604",
  615. },
  616. { /* 740/750 (0x4202, don't support TAU ?) */
  617. .pvr_mask = 0xffffffff,
  618. .pvr_value = 0x00084202,
  619. .cpu_name = "740/750",
  620. .cpu_features = CPU_FTRS_740_NOTAU,
  621. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  622. .mmu_features = MMU_FTR_HPTE_TABLE,
  623. .icache_bsize = 32,
  624. .dcache_bsize = 32,
  625. .num_pmcs = 4,
  626. .cpu_setup = __setup_cpu_750,
  627. .machine_check = machine_check_generic,
  628. .platform = "ppc750",
  629. },
  630. { /* 750CX (80100 and 8010x?) */
  631. .pvr_mask = 0xfffffff0,
  632. .pvr_value = 0x00080100,
  633. .cpu_name = "750CX",
  634. .cpu_features = CPU_FTRS_750,
  635. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  636. .mmu_features = MMU_FTR_HPTE_TABLE,
  637. .icache_bsize = 32,
  638. .dcache_bsize = 32,
  639. .num_pmcs = 4,
  640. .cpu_setup = __setup_cpu_750cx,
  641. .machine_check = machine_check_generic,
  642. .platform = "ppc750",
  643. },
  644. { /* 750CX (82201 and 82202) */
  645. .pvr_mask = 0xfffffff0,
  646. .pvr_value = 0x00082200,
  647. .cpu_name = "750CX",
  648. .cpu_features = CPU_FTRS_750,
  649. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  650. .mmu_features = MMU_FTR_HPTE_TABLE,
  651. .icache_bsize = 32,
  652. .dcache_bsize = 32,
  653. .num_pmcs = 4,
  654. .pmc_type = PPC_PMC_IBM,
  655. .cpu_setup = __setup_cpu_750cx,
  656. .machine_check = machine_check_generic,
  657. .platform = "ppc750",
  658. },
  659. { /* 750CXe (82214) */
  660. .pvr_mask = 0xfffffff0,
  661. .pvr_value = 0x00082210,
  662. .cpu_name = "750CXe",
  663. .cpu_features = CPU_FTRS_750,
  664. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  665. .mmu_features = MMU_FTR_HPTE_TABLE,
  666. .icache_bsize = 32,
  667. .dcache_bsize = 32,
  668. .num_pmcs = 4,
  669. .pmc_type = PPC_PMC_IBM,
  670. .cpu_setup = __setup_cpu_750cx,
  671. .machine_check = machine_check_generic,
  672. .platform = "ppc750",
  673. },
  674. { /* 750CXe "Gekko" (83214) */
  675. .pvr_mask = 0xffffffff,
  676. .pvr_value = 0x00083214,
  677. .cpu_name = "750CXe",
  678. .cpu_features = CPU_FTRS_750,
  679. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  680. .mmu_features = MMU_FTR_HPTE_TABLE,
  681. .icache_bsize = 32,
  682. .dcache_bsize = 32,
  683. .num_pmcs = 4,
  684. .pmc_type = PPC_PMC_IBM,
  685. .cpu_setup = __setup_cpu_750cx,
  686. .machine_check = machine_check_generic,
  687. .platform = "ppc750",
  688. },
  689. { /* 750CL (and "Broadway") */
  690. .pvr_mask = 0xfffff0e0,
  691. .pvr_value = 0x00087000,
  692. .cpu_name = "750CL",
  693. .cpu_features = CPU_FTRS_750CL,
  694. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  695. .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS,
  696. .icache_bsize = 32,
  697. .dcache_bsize = 32,
  698. .num_pmcs = 4,
  699. .pmc_type = PPC_PMC_IBM,
  700. .cpu_setup = __setup_cpu_750,
  701. .machine_check = machine_check_generic,
  702. .platform = "ppc750",
  703. .oprofile_cpu_type = "ppc/750",
  704. .oprofile_type = PPC_OPROFILE_G4,
  705. },
  706. { /* 745/755 */
  707. .pvr_mask = 0xfffff000,
  708. .pvr_value = 0x00083000,
  709. .cpu_name = "745/755",
  710. .cpu_features = CPU_FTRS_750,
  711. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  712. .mmu_features = MMU_FTR_HPTE_TABLE,
  713. .icache_bsize = 32,
  714. .dcache_bsize = 32,
  715. .num_pmcs = 4,
  716. .pmc_type = PPC_PMC_IBM,
  717. .cpu_setup = __setup_cpu_750,
  718. .machine_check = machine_check_generic,
  719. .platform = "ppc750",
  720. },
  721. { /* 750FX rev 1.x */
  722. .pvr_mask = 0xffffff00,
  723. .pvr_value = 0x70000100,
  724. .cpu_name = "750FX",
  725. .cpu_features = CPU_FTRS_750FX1,
  726. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  727. .mmu_features = MMU_FTR_HPTE_TABLE,
  728. .icache_bsize = 32,
  729. .dcache_bsize = 32,
  730. .num_pmcs = 4,
  731. .pmc_type = PPC_PMC_IBM,
  732. .cpu_setup = __setup_cpu_750,
  733. .machine_check = machine_check_generic,
  734. .platform = "ppc750",
  735. .oprofile_cpu_type = "ppc/750",
  736. .oprofile_type = PPC_OPROFILE_G4,
  737. },
  738. { /* 750FX rev 2.0 must disable HID0[DPM] */
  739. .pvr_mask = 0xffffffff,
  740. .pvr_value = 0x70000200,
  741. .cpu_name = "750FX",
  742. .cpu_features = CPU_FTRS_750FX2,
  743. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  744. .mmu_features = MMU_FTR_HPTE_TABLE,
  745. .icache_bsize = 32,
  746. .dcache_bsize = 32,
  747. .num_pmcs = 4,
  748. .pmc_type = PPC_PMC_IBM,
  749. .cpu_setup = __setup_cpu_750,
  750. .machine_check = machine_check_generic,
  751. .platform = "ppc750",
  752. .oprofile_cpu_type = "ppc/750",
  753. .oprofile_type = PPC_OPROFILE_G4,
  754. },
  755. { /* 750FX (All revs except 2.0) */
  756. .pvr_mask = 0xffff0000,
  757. .pvr_value = 0x70000000,
  758. .cpu_name = "750FX",
  759. .cpu_features = CPU_FTRS_750FX,
  760. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  761. .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS,
  762. .icache_bsize = 32,
  763. .dcache_bsize = 32,
  764. .num_pmcs = 4,
  765. .pmc_type = PPC_PMC_IBM,
  766. .cpu_setup = __setup_cpu_750fx,
  767. .machine_check = machine_check_generic,
  768. .platform = "ppc750",
  769. .oprofile_cpu_type = "ppc/750",
  770. .oprofile_type = PPC_OPROFILE_G4,
  771. },
  772. { /* 750GX */
  773. .pvr_mask = 0xffff0000,
  774. .pvr_value = 0x70020000,
  775. .cpu_name = "750GX",
  776. .cpu_features = CPU_FTRS_750GX,
  777. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  778. .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS,
  779. .icache_bsize = 32,
  780. .dcache_bsize = 32,
  781. .num_pmcs = 4,
  782. .pmc_type = PPC_PMC_IBM,
  783. .cpu_setup = __setup_cpu_750fx,
  784. .machine_check = machine_check_generic,
  785. .platform = "ppc750",
  786. .oprofile_cpu_type = "ppc/750",
  787. .oprofile_type = PPC_OPROFILE_G4,
  788. },
  789. { /* 740/750 (L2CR bit need fixup for 740) */
  790. .pvr_mask = 0xffff0000,
  791. .pvr_value = 0x00080000,
  792. .cpu_name = "740/750",
  793. .cpu_features = CPU_FTRS_740,
  794. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  795. .mmu_features = MMU_FTR_HPTE_TABLE,
  796. .icache_bsize = 32,
  797. .dcache_bsize = 32,
  798. .num_pmcs = 4,
  799. .pmc_type = PPC_PMC_IBM,
  800. .cpu_setup = __setup_cpu_750,
  801. .machine_check = machine_check_generic,
  802. .platform = "ppc750",
  803. },
  804. { /* 7400 rev 1.1 ? (no TAU) */
  805. .pvr_mask = 0xffffffff,
  806. .pvr_value = 0x000c1101,
  807. .cpu_name = "7400 (1.1)",
  808. .cpu_features = CPU_FTRS_7400_NOTAU,
  809. .cpu_user_features = COMMON_USER |
  810. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  811. .mmu_features = MMU_FTR_HPTE_TABLE,
  812. .icache_bsize = 32,
  813. .dcache_bsize = 32,
  814. .num_pmcs = 4,
  815. .pmc_type = PPC_PMC_G4,
  816. .cpu_setup = __setup_cpu_7400,
  817. .machine_check = machine_check_generic,
  818. .platform = "ppc7400",
  819. },
  820. { /* 7400 */
  821. .pvr_mask = 0xffff0000,
  822. .pvr_value = 0x000c0000,
  823. .cpu_name = "7400",
  824. .cpu_features = CPU_FTRS_7400,
  825. .cpu_user_features = COMMON_USER |
  826. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  827. .mmu_features = MMU_FTR_HPTE_TABLE,
  828. .icache_bsize = 32,
  829. .dcache_bsize = 32,
  830. .num_pmcs = 4,
  831. .pmc_type = PPC_PMC_G4,
  832. .cpu_setup = __setup_cpu_7400,
  833. .machine_check = machine_check_generic,
  834. .platform = "ppc7400",
  835. },
  836. { /* 7410 */
  837. .pvr_mask = 0xffff0000,
  838. .pvr_value = 0x800c0000,
  839. .cpu_name = "7410",
  840. .cpu_features = CPU_FTRS_7400,
  841. .cpu_user_features = COMMON_USER |
  842. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  843. .mmu_features = MMU_FTR_HPTE_TABLE,
  844. .icache_bsize = 32,
  845. .dcache_bsize = 32,
  846. .num_pmcs = 4,
  847. .pmc_type = PPC_PMC_G4,
  848. .cpu_setup = __setup_cpu_7410,
  849. .machine_check = machine_check_generic,
  850. .platform = "ppc7400",
  851. },
  852. { /* 7450 2.0 - no doze/nap */
  853. .pvr_mask = 0xffffffff,
  854. .pvr_value = 0x80000200,
  855. .cpu_name = "7450",
  856. .cpu_features = CPU_FTRS_7450_20,
  857. .cpu_user_features = COMMON_USER |
  858. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  859. .mmu_features = MMU_FTR_HPTE_TABLE,
  860. .icache_bsize = 32,
  861. .dcache_bsize = 32,
  862. .num_pmcs = 6,
  863. .pmc_type = PPC_PMC_G4,
  864. .cpu_setup = __setup_cpu_745x,
  865. .oprofile_cpu_type = "ppc/7450",
  866. .oprofile_type = PPC_OPROFILE_G4,
  867. .machine_check = machine_check_generic,
  868. .platform = "ppc7450",
  869. },
  870. { /* 7450 2.1 */
  871. .pvr_mask = 0xffffffff,
  872. .pvr_value = 0x80000201,
  873. .cpu_name = "7450",
  874. .cpu_features = CPU_FTRS_7450_21,
  875. .cpu_user_features = COMMON_USER |
  876. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  877. .mmu_features = MMU_FTR_HPTE_TABLE,
  878. .icache_bsize = 32,
  879. .dcache_bsize = 32,
  880. .num_pmcs = 6,
  881. .pmc_type = PPC_PMC_G4,
  882. .cpu_setup = __setup_cpu_745x,
  883. .oprofile_cpu_type = "ppc/7450",
  884. .oprofile_type = PPC_OPROFILE_G4,
  885. .machine_check = machine_check_generic,
  886. .platform = "ppc7450",
  887. },
  888. { /* 7450 2.3 and newer */
  889. .pvr_mask = 0xffff0000,
  890. .pvr_value = 0x80000000,
  891. .cpu_name = "7450",
  892. .cpu_features = CPU_FTRS_7450_23,
  893. .cpu_user_features = COMMON_USER |
  894. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  895. .mmu_features = MMU_FTR_HPTE_TABLE,
  896. .icache_bsize = 32,
  897. .dcache_bsize = 32,
  898. .num_pmcs = 6,
  899. .pmc_type = PPC_PMC_G4,
  900. .cpu_setup = __setup_cpu_745x,
  901. .oprofile_cpu_type = "ppc/7450",
  902. .oprofile_type = PPC_OPROFILE_G4,
  903. .machine_check = machine_check_generic,
  904. .platform = "ppc7450",
  905. },
  906. { /* 7455 rev 1.x */
  907. .pvr_mask = 0xffffff00,
  908. .pvr_value = 0x80010100,
  909. .cpu_name = "7455",
  910. .cpu_features = CPU_FTRS_7455_1,
  911. .cpu_user_features = COMMON_USER |
  912. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  913. .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS,
  914. .icache_bsize = 32,
  915. .dcache_bsize = 32,
  916. .num_pmcs = 6,
  917. .pmc_type = PPC_PMC_G4,
  918. .cpu_setup = __setup_cpu_745x,
  919. .oprofile_cpu_type = "ppc/7450",
  920. .oprofile_type = PPC_OPROFILE_G4,
  921. .machine_check = machine_check_generic,
  922. .platform = "ppc7450",
  923. },
  924. { /* 7455 rev 2.0 */
  925. .pvr_mask = 0xffffffff,
  926. .pvr_value = 0x80010200,
  927. .cpu_name = "7455",
  928. .cpu_features = CPU_FTRS_7455_20,
  929. .cpu_user_features = COMMON_USER |
  930. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  931. .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS,
  932. .icache_bsize = 32,
  933. .dcache_bsize = 32,
  934. .num_pmcs = 6,
  935. .pmc_type = PPC_PMC_G4,
  936. .cpu_setup = __setup_cpu_745x,
  937. .oprofile_cpu_type = "ppc/7450",
  938. .oprofile_type = PPC_OPROFILE_G4,
  939. .machine_check = machine_check_generic,
  940. .platform = "ppc7450",
  941. },
  942. { /* 7455 others */
  943. .pvr_mask = 0xffff0000,
  944. .pvr_value = 0x80010000,
  945. .cpu_name = "7455",
  946. .cpu_features = CPU_FTRS_7455,
  947. .cpu_user_features = COMMON_USER |
  948. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  949. .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS,
  950. .icache_bsize = 32,
  951. .dcache_bsize = 32,
  952. .num_pmcs = 6,
  953. .pmc_type = PPC_PMC_G4,
  954. .cpu_setup = __setup_cpu_745x,
  955. .oprofile_cpu_type = "ppc/7450",
  956. .oprofile_type = PPC_OPROFILE_G4,
  957. .machine_check = machine_check_generic,
  958. .platform = "ppc7450",
  959. },
  960. { /* 7447/7457 Rev 1.0 */
  961. .pvr_mask = 0xffffffff,
  962. .pvr_value = 0x80020100,
  963. .cpu_name = "7447/7457",
  964. .cpu_features = CPU_FTRS_7447_10,
  965. .cpu_user_features = COMMON_USER |
  966. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  967. .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS,
  968. .icache_bsize = 32,
  969. .dcache_bsize = 32,
  970. .num_pmcs = 6,
  971. .pmc_type = PPC_PMC_G4,
  972. .cpu_setup = __setup_cpu_745x,
  973. .oprofile_cpu_type = "ppc/7450",
  974. .oprofile_type = PPC_OPROFILE_G4,
  975. .machine_check = machine_check_generic,
  976. .platform = "ppc7450",
  977. },
  978. { /* 7447/7457 Rev 1.1 */
  979. .pvr_mask = 0xffffffff,
  980. .pvr_value = 0x80020101,
  981. .cpu_name = "7447/7457",
  982. .cpu_features = CPU_FTRS_7447_10,
  983. .cpu_user_features = COMMON_USER |
  984. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  985. .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS,
  986. .icache_bsize = 32,
  987. .dcache_bsize = 32,
  988. .num_pmcs = 6,
  989. .pmc_type = PPC_PMC_G4,
  990. .cpu_setup = __setup_cpu_745x,
  991. .oprofile_cpu_type = "ppc/7450",
  992. .oprofile_type = PPC_OPROFILE_G4,
  993. .machine_check = machine_check_generic,
  994. .platform = "ppc7450",
  995. },
  996. { /* 7447/7457 Rev 1.2 and later */
  997. .pvr_mask = 0xffff0000,
  998. .pvr_value = 0x80020000,
  999. .cpu_name = "7447/7457",
  1000. .cpu_features = CPU_FTRS_7447,
  1001. .cpu_user_features = COMMON_USER | PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  1002. .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS,
  1003. .icache_bsize = 32,
  1004. .dcache_bsize = 32,
  1005. .num_pmcs = 6,
  1006. .pmc_type = PPC_PMC_G4,
  1007. .cpu_setup = __setup_cpu_745x,
  1008. .oprofile_cpu_type = "ppc/7450",
  1009. .oprofile_type = PPC_OPROFILE_G4,
  1010. .machine_check = machine_check_generic,
  1011. .platform = "ppc7450",
  1012. },
  1013. { /* 7447A */
  1014. .pvr_mask = 0xffff0000,
  1015. .pvr_value = 0x80030000,
  1016. .cpu_name = "7447A",
  1017. .cpu_features = CPU_FTRS_7447A,
  1018. .cpu_user_features = COMMON_USER |
  1019. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  1020. .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS,
  1021. .icache_bsize = 32,
  1022. .dcache_bsize = 32,
  1023. .num_pmcs = 6,
  1024. .pmc_type = PPC_PMC_G4,
  1025. .cpu_setup = __setup_cpu_745x,
  1026. .oprofile_cpu_type = "ppc/7450",
  1027. .oprofile_type = PPC_OPROFILE_G4,
  1028. .machine_check = machine_check_generic,
  1029. .platform = "ppc7450",
  1030. },
  1031. { /* 7448 */
  1032. .pvr_mask = 0xffff0000,
  1033. .pvr_value = 0x80040000,
  1034. .cpu_name = "7448",
  1035. .cpu_features = CPU_FTRS_7448,
  1036. .cpu_user_features = COMMON_USER |
  1037. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  1038. .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS,
  1039. .icache_bsize = 32,
  1040. .dcache_bsize = 32,
  1041. .num_pmcs = 6,
  1042. .pmc_type = PPC_PMC_G4,
  1043. .cpu_setup = __setup_cpu_745x,
  1044. .oprofile_cpu_type = "ppc/7450",
  1045. .oprofile_type = PPC_OPROFILE_G4,
  1046. .machine_check = machine_check_generic,
  1047. .platform = "ppc7450",
  1048. },
  1049. { /* 82xx (8240, 8245, 8260 are all 603e cores) */
  1050. .pvr_mask = 0x7fff0000,
  1051. .pvr_value = 0x00810000,
  1052. .cpu_name = "82xx",
  1053. .cpu_features = CPU_FTRS_82XX,
  1054. .cpu_user_features = COMMON_USER,
  1055. .mmu_features = 0,
  1056. .icache_bsize = 32,
  1057. .dcache_bsize = 32,
  1058. .cpu_setup = __setup_cpu_603,
  1059. .machine_check = machine_check_generic,
  1060. .platform = "ppc603",
  1061. },
  1062. { /* All G2_LE (603e core, plus some) have the same pvr */
  1063. .pvr_mask = 0x7fff0000,
  1064. .pvr_value = 0x00820000,
  1065. .cpu_name = "G2_LE",
  1066. .cpu_features = CPU_FTRS_G2_LE,
  1067. .cpu_user_features = COMMON_USER,
  1068. .mmu_features = MMU_FTR_USE_HIGH_BATS,
  1069. .icache_bsize = 32,
  1070. .dcache_bsize = 32,
  1071. .cpu_setup = __setup_cpu_603,
  1072. .machine_check = machine_check_generic,
  1073. .platform = "ppc603",
  1074. },
  1075. { /* e300c1 (a 603e core, plus some) on 83xx */
  1076. .pvr_mask = 0x7fff0000,
  1077. .pvr_value = 0x00830000,
  1078. .cpu_name = "e300c1",
  1079. .cpu_features = CPU_FTRS_E300,
  1080. .cpu_user_features = COMMON_USER,
  1081. .mmu_features = MMU_FTR_USE_HIGH_BATS,
  1082. .icache_bsize = 32,
  1083. .dcache_bsize = 32,
  1084. .cpu_setup = __setup_cpu_603,
  1085. .machine_check = machine_check_generic,
  1086. .platform = "ppc603",
  1087. },
  1088. { /* e300c2 (an e300c1 core, plus some, minus FPU) on 83xx */
  1089. .pvr_mask = 0x7fff0000,
  1090. .pvr_value = 0x00840000,
  1091. .cpu_name = "e300c2",
  1092. .cpu_features = CPU_FTRS_E300C2,
  1093. .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
  1094. .mmu_features = MMU_FTR_USE_HIGH_BATS |
  1095. MMU_FTR_NEED_DTLB_SW_LRU,
  1096. .icache_bsize = 32,
  1097. .dcache_bsize = 32,
  1098. .cpu_setup = __setup_cpu_603,
  1099. .machine_check = machine_check_generic,
  1100. .platform = "ppc603",
  1101. },
  1102. { /* e300c3 (e300c1, plus one IU, half cache size) on 83xx */
  1103. .pvr_mask = 0x7fff0000,
  1104. .pvr_value = 0x00850000,
  1105. .cpu_name = "e300c3",
  1106. .cpu_features = CPU_FTRS_E300,
  1107. .cpu_user_features = COMMON_USER,
  1108. .mmu_features = MMU_FTR_USE_HIGH_BATS |
  1109. MMU_FTR_NEED_DTLB_SW_LRU,
  1110. .icache_bsize = 32,
  1111. .dcache_bsize = 32,
  1112. .cpu_setup = __setup_cpu_603,
  1113. .num_pmcs = 4,
  1114. .oprofile_cpu_type = "ppc/e300",
  1115. .oprofile_type = PPC_OPROFILE_FSL_EMB,
  1116. .platform = "ppc603",
  1117. },
  1118. { /* e300c4 (e300c1, plus one IU) */
  1119. .pvr_mask = 0x7fff0000,
  1120. .pvr_value = 0x00860000,
  1121. .cpu_name = "e300c4",
  1122. .cpu_features = CPU_FTRS_E300,
  1123. .cpu_user_features = COMMON_USER,
  1124. .mmu_features = MMU_FTR_USE_HIGH_BATS |
  1125. MMU_FTR_NEED_DTLB_SW_LRU,
  1126. .icache_bsize = 32,
  1127. .dcache_bsize = 32,
  1128. .cpu_setup = __setup_cpu_603,
  1129. .machine_check = machine_check_generic,
  1130. .num_pmcs = 4,
  1131. .oprofile_cpu_type = "ppc/e300",
  1132. .oprofile_type = PPC_OPROFILE_FSL_EMB,
  1133. .platform = "ppc603",
  1134. },
  1135. { /* default match, we assume split I/D cache & TB (non-601)... */
  1136. .pvr_mask = 0x00000000,
  1137. .pvr_value = 0x00000000,
  1138. .cpu_name = "(generic PPC)",
  1139. .cpu_features = CPU_FTRS_CLASSIC32,
  1140. .cpu_user_features = COMMON_USER,
  1141. .mmu_features = MMU_FTR_HPTE_TABLE,
  1142. .icache_bsize = 32,
  1143. .dcache_bsize = 32,
  1144. .machine_check = machine_check_generic,
  1145. .platform = "ppc603",
  1146. },
  1147. #endif /* CLASSIC_PPC */
  1148. #ifdef CONFIG_8xx
  1149. { /* 8xx */
  1150. .pvr_mask = 0xffff0000,
  1151. .pvr_value = 0x00500000,
  1152. .cpu_name = "8xx",
  1153. /* CPU_FTR_MAYBE_CAN_DOZE is possible,
  1154. * if the 8xx code is there.... */
  1155. .cpu_features = CPU_FTRS_8XX,
  1156. .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
  1157. .mmu_features = MMU_FTR_TYPE_8xx,
  1158. .icache_bsize = 16,
  1159. .dcache_bsize = 16,
  1160. .platform = "ppc823",
  1161. },
  1162. #endif /* CONFIG_8xx */
  1163. #ifdef CONFIG_40x
  1164. { /* 403GC */
  1165. .pvr_mask = 0xffffff00,
  1166. .pvr_value = 0x00200200,
  1167. .cpu_name = "403GC",
  1168. .cpu_features = CPU_FTRS_40X,
  1169. .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
  1170. .mmu_features = MMU_FTR_TYPE_40x,
  1171. .icache_bsize = 16,
  1172. .dcache_bsize = 16,
  1173. .machine_check = machine_check_4xx,
  1174. .platform = "ppc403",
  1175. },
  1176. { /* 403GCX */
  1177. .pvr_mask = 0xffffff00,
  1178. .pvr_value = 0x00201400,
  1179. .cpu_name = "403GCX",
  1180. .cpu_features = CPU_FTRS_40X,
  1181. .cpu_user_features = PPC_FEATURE_32 |
  1182. PPC_FEATURE_HAS_MMU | PPC_FEATURE_NO_TB,
  1183. .mmu_features = MMU_FTR_TYPE_40x,
  1184. .icache_bsize = 16,
  1185. .dcache_bsize = 16,
  1186. .machine_check = machine_check_4xx,
  1187. .platform = "ppc403",
  1188. },
  1189. { /* 403G ?? */
  1190. .pvr_mask = 0xffff0000,
  1191. .pvr_value = 0x00200000,
  1192. .cpu_name = "403G ??",
  1193. .cpu_features = CPU_FTRS_40X,
  1194. .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
  1195. .mmu_features = MMU_FTR_TYPE_40x,
  1196. .icache_bsize = 16,
  1197. .dcache_bsize = 16,
  1198. .machine_check = machine_check_4xx,
  1199. .platform = "ppc403",
  1200. },
  1201. { /* 405GP */
  1202. .pvr_mask = 0xffff0000,
  1203. .pvr_value = 0x40110000,
  1204. .cpu_name = "405GP",
  1205. .cpu_features = CPU_FTRS_40X,
  1206. .cpu_user_features = PPC_FEATURE_32 |
  1207. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1208. .mmu_features = MMU_FTR_TYPE_40x,
  1209. .icache_bsize = 32,
  1210. .dcache_bsize = 32,
  1211. .machine_check = machine_check_4xx,
  1212. .platform = "ppc405",
  1213. },
  1214. { /* STB 03xxx */
  1215. .pvr_mask = 0xffff0000,
  1216. .pvr_value = 0x40130000,
  1217. .cpu_name = "STB03xxx",
  1218. .cpu_features = CPU_FTRS_40X,
  1219. .cpu_user_features = PPC_FEATURE_32 |
  1220. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1221. .mmu_features = MMU_FTR_TYPE_40x,
  1222. .icache_bsize = 32,
  1223. .dcache_bsize = 32,
  1224. .machine_check = machine_check_4xx,
  1225. .platform = "ppc405",
  1226. },
  1227. { /* STB 04xxx */
  1228. .pvr_mask = 0xffff0000,
  1229. .pvr_value = 0x41810000,
  1230. .cpu_name = "STB04xxx",
  1231. .cpu_features = CPU_FTRS_40X,
  1232. .cpu_user_features = PPC_FEATURE_32 |
  1233. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1234. .mmu_features = MMU_FTR_TYPE_40x,
  1235. .icache_bsize = 32,
  1236. .dcache_bsize = 32,
  1237. .machine_check = machine_check_4xx,
  1238. .platform = "ppc405",
  1239. },
  1240. { /* NP405L */
  1241. .pvr_mask = 0xffff0000,
  1242. .pvr_value = 0x41610000,
  1243. .cpu_name = "NP405L",
  1244. .cpu_features = CPU_FTRS_40X,
  1245. .cpu_user_features = PPC_FEATURE_32 |
  1246. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1247. .mmu_features = MMU_FTR_TYPE_40x,
  1248. .icache_bsize = 32,
  1249. .dcache_bsize = 32,
  1250. .machine_check = machine_check_4xx,
  1251. .platform = "ppc405",
  1252. },
  1253. { /* NP4GS3 */
  1254. .pvr_mask = 0xffff0000,
  1255. .pvr_value = 0x40B10000,
  1256. .cpu_name = "NP4GS3",
  1257. .cpu_features = CPU_FTRS_40X,
  1258. .cpu_user_features = PPC_FEATURE_32 |
  1259. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1260. .mmu_features = MMU_FTR_TYPE_40x,
  1261. .icache_bsize = 32,
  1262. .dcache_bsize = 32,
  1263. .machine_check = machine_check_4xx,
  1264. .platform = "ppc405",
  1265. },
  1266. { /* NP405H */
  1267. .pvr_mask = 0xffff0000,
  1268. .pvr_value = 0x41410000,
  1269. .cpu_name = "NP405H",
  1270. .cpu_features = CPU_FTRS_40X,
  1271. .cpu_user_features = PPC_FEATURE_32 |
  1272. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1273. .mmu_features = MMU_FTR_TYPE_40x,
  1274. .icache_bsize = 32,
  1275. .dcache_bsize = 32,
  1276. .machine_check = machine_check_4xx,
  1277. .platform = "ppc405",
  1278. },
  1279. { /* 405GPr */
  1280. .pvr_mask = 0xffff0000,
  1281. .pvr_value = 0x50910000,
  1282. .cpu_name = "405GPr",
  1283. .cpu_features = CPU_FTRS_40X,
  1284. .cpu_user_features = PPC_FEATURE_32 |
  1285. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1286. .mmu_features = MMU_FTR_TYPE_40x,
  1287. .icache_bsize = 32,
  1288. .dcache_bsize = 32,
  1289. .machine_check = machine_check_4xx,
  1290. .platform = "ppc405",
  1291. },
  1292. { /* STBx25xx */
  1293. .pvr_mask = 0xffff0000,
  1294. .pvr_value = 0x51510000,
  1295. .cpu_name = "STBx25xx",
  1296. .cpu_features = CPU_FTRS_40X,
  1297. .cpu_user_features = PPC_FEATURE_32 |
  1298. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1299. .mmu_features = MMU_FTR_TYPE_40x,
  1300. .icache_bsize = 32,
  1301. .dcache_bsize = 32,
  1302. .machine_check = machine_check_4xx,
  1303. .platform = "ppc405",
  1304. },
  1305. { /* 405LP */
  1306. .pvr_mask = 0xffff0000,
  1307. .pvr_value = 0x41F10000,
  1308. .cpu_name = "405LP",
  1309. .cpu_features = CPU_FTRS_40X,
  1310. .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
  1311. .mmu_features = MMU_FTR_TYPE_40x,
  1312. .icache_bsize = 32,
  1313. .dcache_bsize = 32,
  1314. .machine_check = machine_check_4xx,
  1315. .platform = "ppc405",
  1316. },
  1317. { /* Xilinx Virtex-II Pro */
  1318. .pvr_mask = 0xfffff000,
  1319. .pvr_value = 0x20010000,
  1320. .cpu_name = "Virtex-II Pro",
  1321. .cpu_features = CPU_FTRS_40X,
  1322. .cpu_user_features = PPC_FEATURE_32 |
  1323. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1324. .mmu_features = MMU_FTR_TYPE_40x,
  1325. .icache_bsize = 32,
  1326. .dcache_bsize = 32,
  1327. .machine_check = machine_check_4xx,
  1328. .platform = "ppc405",
  1329. },
  1330. { /* Xilinx Virtex-4 FX */
  1331. .pvr_mask = 0xfffff000,
  1332. .pvr_value = 0x20011000,
  1333. .cpu_name = "Virtex-4 FX",
  1334. .cpu_features = CPU_FTRS_40X,
  1335. .cpu_user_features = PPC_FEATURE_32 |
  1336. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1337. .mmu_features = MMU_FTR_TYPE_40x,
  1338. .icache_bsize = 32,
  1339. .dcache_bsize = 32,
  1340. .machine_check = machine_check_4xx,
  1341. .platform = "ppc405",
  1342. },
  1343. { /* 405EP */
  1344. .pvr_mask = 0xffff0000,
  1345. .pvr_value = 0x51210000,
  1346. .cpu_name = "405EP",
  1347. .cpu_features = CPU_FTRS_40X,
  1348. .cpu_user_features = PPC_FEATURE_32 |
  1349. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1350. .mmu_features = MMU_FTR_TYPE_40x,
  1351. .icache_bsize = 32,
  1352. .dcache_bsize = 32,
  1353. .machine_check = machine_check_4xx,
  1354. .platform = "ppc405",
  1355. },
  1356. { /* 405EX Rev. A/B with Security */
  1357. .pvr_mask = 0xffff000f,
  1358. .pvr_value = 0x12910007,
  1359. .cpu_name = "405EX Rev. A/B",
  1360. .cpu_features = CPU_FTRS_40X,
  1361. .cpu_user_features = PPC_FEATURE_32 |
  1362. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1363. .mmu_features = MMU_FTR_TYPE_40x,
  1364. .icache_bsize = 32,
  1365. .dcache_bsize = 32,
  1366. .machine_check = machine_check_4xx,
  1367. .platform = "ppc405",
  1368. },
  1369. { /* 405EX Rev. C without Security */
  1370. .pvr_mask = 0xffff000f,
  1371. .pvr_value = 0x1291000d,
  1372. .cpu_name = "405EX Rev. C",
  1373. .cpu_features = CPU_FTRS_40X,
  1374. .cpu_user_features = PPC_FEATURE_32 |
  1375. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1376. .mmu_features = MMU_FTR_TYPE_40x,
  1377. .icache_bsize = 32,
  1378. .dcache_bsize = 32,
  1379. .machine_check = machine_check_4xx,
  1380. .platform = "ppc405",
  1381. },
  1382. { /* 405EX Rev. C with Security */
  1383. .pvr_mask = 0xffff000f,
  1384. .pvr_value = 0x1291000f,
  1385. .cpu_name = "405EX Rev. C",
  1386. .cpu_features = CPU_FTRS_40X,
  1387. .cpu_user_features = PPC_FEATURE_32 |
  1388. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1389. .mmu_features = MMU_FTR_TYPE_40x,
  1390. .icache_bsize = 32,
  1391. .dcache_bsize = 32,
  1392. .machine_check = machine_check_4xx,
  1393. .platform = "ppc405",
  1394. },
  1395. { /* 405EX Rev. D without Security */
  1396. .pvr_mask = 0xffff000f,
  1397. .pvr_value = 0x12910003,
  1398. .cpu_name = "405EX Rev. D",
  1399. .cpu_features = CPU_FTRS_40X,
  1400. .cpu_user_features = PPC_FEATURE_32 |
  1401. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1402. .mmu_features = MMU_FTR_TYPE_40x,
  1403. .icache_bsize = 32,
  1404. .dcache_bsize = 32,
  1405. .machine_check = machine_check_4xx,
  1406. .platform = "ppc405",
  1407. },
  1408. { /* 405EX Rev. D with Security */
  1409. .pvr_mask = 0xffff000f,
  1410. .pvr_value = 0x12910005,
  1411. .cpu_name = "405EX Rev. D",
  1412. .cpu_features = CPU_FTRS_40X,
  1413. .cpu_user_features = PPC_FEATURE_32 |
  1414. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1415. .mmu_features = MMU_FTR_TYPE_40x,
  1416. .icache_bsize = 32,
  1417. .dcache_bsize = 32,
  1418. .machine_check = machine_check_4xx,
  1419. .platform = "ppc405",
  1420. },
  1421. { /* 405EXr Rev. A/B without Security */
  1422. .pvr_mask = 0xffff000f,
  1423. .pvr_value = 0x12910001,
  1424. .cpu_name = "405EXr Rev. A/B",
  1425. .cpu_features = CPU_FTRS_40X,
  1426. .cpu_user_features = PPC_FEATURE_32 |
  1427. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1428. .mmu_features = MMU_FTR_TYPE_40x,
  1429. .icache_bsize = 32,
  1430. .dcache_bsize = 32,
  1431. .machine_check = machine_check_4xx,
  1432. .platform = "ppc405",
  1433. },
  1434. { /* 405EXr Rev. C without Security */
  1435. .pvr_mask = 0xffff000f,
  1436. .pvr_value = 0x12910009,
  1437. .cpu_name = "405EXr Rev. C",
  1438. .cpu_features = CPU_FTRS_40X,
  1439. .cpu_user_features = PPC_FEATURE_32 |
  1440. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1441. .mmu_features = MMU_FTR_TYPE_40x,
  1442. .icache_bsize = 32,
  1443. .dcache_bsize = 32,
  1444. .machine_check = machine_check_4xx,
  1445. .platform = "ppc405",
  1446. },
  1447. { /* 405EXr Rev. C with Security */
  1448. .pvr_mask = 0xffff000f,
  1449. .pvr_value = 0x1291000b,
  1450. .cpu_name = "405EXr Rev. C",
  1451. .cpu_features = CPU_FTRS_40X,
  1452. .cpu_user_features = PPC_FEATURE_32 |
  1453. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1454. .mmu_features = MMU_FTR_TYPE_40x,
  1455. .icache_bsize = 32,
  1456. .dcache_bsize = 32,
  1457. .machine_check = machine_check_4xx,
  1458. .platform = "ppc405",
  1459. },
  1460. { /* 405EXr Rev. D without Security */
  1461. .pvr_mask = 0xffff000f,
  1462. .pvr_value = 0x12910000,
  1463. .cpu_name = "405EXr Rev. D",
  1464. .cpu_features = CPU_FTRS_40X,
  1465. .cpu_user_features = PPC_FEATURE_32 |
  1466. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1467. .mmu_features = MMU_FTR_TYPE_40x,
  1468. .icache_bsize = 32,
  1469. .dcache_bsize = 32,
  1470. .machine_check = machine_check_4xx,
  1471. .platform = "ppc405",
  1472. },
  1473. { /* 405EXr Rev. D with Security */
  1474. .pvr_mask = 0xffff000f,
  1475. .pvr_value = 0x12910002,
  1476. .cpu_name = "405EXr Rev. D",
  1477. .cpu_features = CPU_FTRS_40X,
  1478. .cpu_user_features = PPC_FEATURE_32 |
  1479. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1480. .mmu_features = MMU_FTR_TYPE_40x,
  1481. .icache_bsize = 32,
  1482. .dcache_bsize = 32,
  1483. .machine_check = machine_check_4xx,
  1484. .platform = "ppc405",
  1485. },
  1486. {
  1487. /* 405EZ */
  1488. .pvr_mask = 0xffff0000,
  1489. .pvr_value = 0x41510000,
  1490. .cpu_name = "405EZ",
  1491. .cpu_features = CPU_FTRS_40X,
  1492. .cpu_user_features = PPC_FEATURE_32 |
  1493. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1494. .mmu_features = MMU_FTR_TYPE_40x,
  1495. .icache_bsize = 32,
  1496. .dcache_bsize = 32,
  1497. .machine_check = machine_check_4xx,
  1498. .platform = "ppc405",
  1499. },
  1500. { /* default match */
  1501. .pvr_mask = 0x00000000,
  1502. .pvr_value = 0x00000000,
  1503. .cpu_name = "(generic 40x PPC)",
  1504. .cpu_features = CPU_FTRS_40X,
  1505. .cpu_user_features = PPC_FEATURE_32 |
  1506. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1507. .mmu_features = MMU_FTR_TYPE_40x,
  1508. .icache_bsize = 32,
  1509. .dcache_bsize = 32,
  1510. .machine_check = machine_check_4xx,
  1511. .platform = "ppc405",
  1512. }
  1513. #endif /* CONFIG_40x */
  1514. #ifdef CONFIG_44x
  1515. {
  1516. .pvr_mask = 0xf0000fff,
  1517. .pvr_value = 0x40000850,
  1518. .cpu_name = "440GR Rev. A",
  1519. .cpu_features = CPU_FTRS_44X,
  1520. .cpu_user_features = COMMON_USER_BOOKE,
  1521. .mmu_features = MMU_FTR_TYPE_44x,
  1522. .icache_bsize = 32,
  1523. .dcache_bsize = 32,
  1524. .machine_check = machine_check_4xx,
  1525. .platform = "ppc440",
  1526. },
  1527. { /* Use logical PVR for 440EP (logical pvr = pvr | 0x8) */
  1528. .pvr_mask = 0xf0000fff,
  1529. .pvr_value = 0x40000858,
  1530. .cpu_name = "440EP Rev. A",
  1531. .cpu_features = CPU_FTRS_44X,
  1532. .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
  1533. .mmu_features = MMU_FTR_TYPE_44x,
  1534. .icache_bsize = 32,
  1535. .dcache_bsize = 32,
  1536. .cpu_setup = __setup_cpu_440ep,
  1537. .machine_check = machine_check_4xx,
  1538. .platform = "ppc440",
  1539. },
  1540. {
  1541. .pvr_mask = 0xf0000fff,
  1542. .pvr_value = 0x400008d3,
  1543. .cpu_name = "440GR Rev. B",
  1544. .cpu_features = CPU_FTRS_44X,
  1545. .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
  1546. .mmu_features = MMU_FTR_TYPE_44x,
  1547. .icache_bsize = 32,
  1548. .dcache_bsize = 32,
  1549. .machine_check = machine_check_4xx,
  1550. .platform = "ppc440",
  1551. },
  1552. { /* Matches both physical and logical PVR for 440EP (logical pvr = pvr | 0x8) */
  1553. .pvr_mask = 0xf0000ff7,
  1554. .pvr_value = 0x400008d4,
  1555. .cpu_name = "440EP Rev. C",
  1556. .cpu_features = CPU_FTRS_44X,
  1557. .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
  1558. .mmu_features = MMU_FTR_TYPE_44x,
  1559. .icache_bsize = 32,
  1560. .dcache_bsize = 32,
  1561. .cpu_setup = __setup_cpu_440ep,
  1562. .machine_check = machine_check_4xx,
  1563. .platform = "ppc440",
  1564. },
  1565. { /* Use logical PVR for 440EP (logical pvr = pvr | 0x8) */
  1566. .pvr_mask = 0xf0000fff,
  1567. .pvr_value = 0x400008db,
  1568. .cpu_name = "440EP Rev. B",
  1569. .cpu_features = CPU_FTRS_44X,
  1570. .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
  1571. .mmu_features = MMU_FTR_TYPE_44x,
  1572. .icache_bsize = 32,
  1573. .dcache_bsize = 32,
  1574. .cpu_setup = __setup_cpu_440ep,
  1575. .machine_check = machine_check_4xx,
  1576. .platform = "ppc440",
  1577. },
  1578. { /* 440GRX */
  1579. .pvr_mask = 0xf0000ffb,
  1580. .pvr_value = 0x200008D0,
  1581. .cpu_name = "440GRX",
  1582. .cpu_features = CPU_FTRS_44X,
  1583. .cpu_user_features = COMMON_USER_BOOKE,
  1584. .mmu_features = MMU_FTR_TYPE_44x,
  1585. .icache_bsize = 32,
  1586. .dcache_bsize = 32,
  1587. .cpu_setup = __setup_cpu_440grx,
  1588. .machine_check = machine_check_440A,
  1589. .platform = "ppc440",
  1590. },
  1591. { /* Use logical PVR for 440EPx (logical pvr = pvr | 0x8) */
  1592. .pvr_mask = 0xf0000ffb,
  1593. .pvr_value = 0x200008D8,
  1594. .cpu_name = "440EPX",
  1595. .cpu_features = CPU_FTRS_44X,
  1596. .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
  1597. .mmu_features = MMU_FTR_TYPE_44x,
  1598. .icache_bsize = 32,
  1599. .dcache_bsize = 32,
  1600. .cpu_setup = __setup_cpu_440epx,
  1601. .machine_check = machine_check_440A,
  1602. .platform = "ppc440",
  1603. },
  1604. { /* 440GP Rev. B */
  1605. .pvr_mask = 0xf0000fff,
  1606. .pvr_value = 0x40000440,
  1607. .cpu_name = "440GP Rev. B",
  1608. .cpu_features = CPU_FTRS_44X,
  1609. .cpu_user_features = COMMON_USER_BOOKE,
  1610. .mmu_features = MMU_FTR_TYPE_44x,
  1611. .icache_bsize = 32,
  1612. .dcache_bsize = 32,
  1613. .machine_check = machine_check_4xx,
  1614. .platform = "ppc440gp",
  1615. },
  1616. { /* 440GP Rev. C */
  1617. .pvr_mask = 0xf0000fff,
  1618. .pvr_value = 0x40000481,
  1619. .cpu_name = "440GP Rev. C",
  1620. .cpu_features = CPU_FTRS_44X,
  1621. .cpu_user_features = COMMON_USER_BOOKE,
  1622. .mmu_features = MMU_FTR_TYPE_44x,
  1623. .icache_bsize = 32,
  1624. .dcache_bsize = 32,
  1625. .machine_check = machine_check_4xx,
  1626. .platform = "ppc440gp",
  1627. },
  1628. { /* 440GX Rev. A */
  1629. .pvr_mask = 0xf0000fff,
  1630. .pvr_value = 0x50000850,
  1631. .cpu_name = "440GX Rev. A",
  1632. .cpu_features = CPU_FTRS_44X,
  1633. .cpu_user_features = COMMON_USER_BOOKE,
  1634. .mmu_features = MMU_FTR_TYPE_44x,
  1635. .icache_bsize = 32,
  1636. .dcache_bsize = 32,
  1637. .cpu_setup = __setup_cpu_440gx,
  1638. .machine_check = machine_check_440A,
  1639. .platform = "ppc440",
  1640. },
  1641. { /* 440GX Rev. B */
  1642. .pvr_mask = 0xf0000fff,
  1643. .pvr_value = 0x50000851,
  1644. .cpu_name = "440GX Rev. B",
  1645. .cpu_features = CPU_FTRS_44X,
  1646. .cpu_user_features = COMMON_USER_BOOKE,
  1647. .mmu_features = MMU_FTR_TYPE_44x,
  1648. .icache_bsize = 32,
  1649. .dcache_bsize = 32,
  1650. .cpu_setup = __setup_cpu_440gx,
  1651. .machine_check = machine_check_440A,
  1652. .platform = "ppc440",
  1653. },
  1654. { /* 440GX Rev. C */
  1655. .pvr_mask = 0xf0000fff,
  1656. .pvr_value = 0x50000892,
  1657. .cpu_name = "440GX Rev. C",
  1658. .cpu_features = CPU_FTRS_44X,
  1659. .cpu_user_features = COMMON_USER_BOOKE,
  1660. .mmu_features = MMU_FTR_TYPE_44x,
  1661. .icache_bsize = 32,
  1662. .dcache_bsize = 32,
  1663. .cpu_setup = __setup_cpu_440gx,
  1664. .machine_check = machine_check_440A,
  1665. .platform = "ppc440",
  1666. },
  1667. { /* 440GX Rev. F */
  1668. .pvr_mask = 0xf0000fff,
  1669. .pvr_value = 0x50000894,
  1670. .cpu_name = "440GX Rev. F",
  1671. .cpu_features = CPU_FTRS_44X,
  1672. .cpu_user_features = COMMON_USER_BOOKE,
  1673. .mmu_features = MMU_FTR_TYPE_44x,
  1674. .icache_bsize = 32,
  1675. .dcache_bsize = 32,
  1676. .cpu_setup = __setup_cpu_440gx,
  1677. .machine_check = machine_check_440A,
  1678. .platform = "ppc440",
  1679. },
  1680. { /* 440SP Rev. A */
  1681. .pvr_mask = 0xfff00fff,
  1682. .pvr_value = 0x53200891,
  1683. .cpu_name = "440SP Rev. A",
  1684. .cpu_features = CPU_FTRS_44X,
  1685. .cpu_user_features = COMMON_USER_BOOKE,
  1686. .mmu_features = MMU_FTR_TYPE_44x,
  1687. .icache_bsize = 32,
  1688. .dcache_bsize = 32,
  1689. .machine_check = machine_check_4xx,
  1690. .platform = "ppc440",
  1691. },
  1692. { /* 440SPe Rev. A */
  1693. .pvr_mask = 0xfff00fff,
  1694. .pvr_value = 0x53400890,
  1695. .cpu_name = "440SPe Rev. A",
  1696. .cpu_features = CPU_FTRS_44X,
  1697. .cpu_user_features = COMMON_USER_BOOKE,
  1698. .mmu_features = MMU_FTR_TYPE_44x,
  1699. .icache_bsize = 32,
  1700. .dcache_bsize = 32,
  1701. .cpu_setup = __setup_cpu_440spe,
  1702. .machine_check = machine_check_440A,
  1703. .platform = "ppc440",
  1704. },
  1705. { /* 440SPe Rev. B */
  1706. .pvr_mask = 0xfff00fff,
  1707. .pvr_value = 0x53400891,
  1708. .cpu_name = "440SPe Rev. B",
  1709. .cpu_features = CPU_FTRS_44X,
  1710. .cpu_user_features = COMMON_USER_BOOKE,
  1711. .mmu_features = MMU_FTR_TYPE_44x,
  1712. .icache_bsize = 32,
  1713. .dcache_bsize = 32,
  1714. .cpu_setup = __setup_cpu_440spe,
  1715. .machine_check = machine_check_440A,
  1716. .platform = "ppc440",
  1717. },
  1718. { /* 440 in Xilinx Virtex-5 FXT */
  1719. .pvr_mask = 0xfffffff0,
  1720. .pvr_value = 0x7ff21910,
  1721. .cpu_name = "440 in Virtex-5 FXT",
  1722. .cpu_features = CPU_FTRS_44X,
  1723. .cpu_user_features = COMMON_USER_BOOKE,
  1724. .mmu_features = MMU_FTR_TYPE_44x,
  1725. .icache_bsize = 32,
  1726. .dcache_bsize = 32,
  1727. .cpu_setup = __setup_cpu_440x5,
  1728. .machine_check = machine_check_440A,
  1729. .platform = "ppc440",
  1730. },
  1731. { /* 460EX */
  1732. .pvr_mask = 0xffff0006,
  1733. .pvr_value = 0x13020002,
  1734. .cpu_name = "460EX",
  1735. .cpu_features = CPU_FTRS_440x6,
  1736. .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
  1737. .mmu_features = MMU_FTR_TYPE_44x,
  1738. .icache_bsize = 32,
  1739. .dcache_bsize = 32,
  1740. .cpu_setup = __setup_cpu_460ex,
  1741. .machine_check = machine_check_440A,
  1742. .platform = "ppc440",
  1743. },
  1744. { /* 460EX Rev B */
  1745. .pvr_mask = 0xffff0007,
  1746. .pvr_value = 0x13020004,
  1747. .cpu_name = "460EX Rev. B",
  1748. .cpu_features = CPU_FTRS_440x6,
  1749. .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
  1750. .mmu_features = MMU_FTR_TYPE_44x,
  1751. .icache_bsize = 32,
  1752. .dcache_bsize = 32,
  1753. .cpu_setup = __setup_cpu_460ex,
  1754. .machine_check = machine_check_440A,
  1755. .platform = "ppc440",
  1756. },
  1757. { /* 460GT */
  1758. .pvr_mask = 0xffff0006,
  1759. .pvr_value = 0x13020000,
  1760. .cpu_name = "460GT",
  1761. .cpu_features = CPU_FTRS_440x6,
  1762. .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
  1763. .mmu_features = MMU_FTR_TYPE_44x,
  1764. .icache_bsize = 32,
  1765. .dcache_bsize = 32,
  1766. .cpu_setup = __setup_cpu_460gt,
  1767. .machine_check = machine_check_440A,
  1768. .platform = "ppc440",
  1769. },
  1770. { /* 460GT Rev B */
  1771. .pvr_mask = 0xffff0007,
  1772. .pvr_value = 0x13020005,
  1773. .cpu_name = "460GT Rev. B",
  1774. .cpu_features = CPU_FTRS_440x6,
  1775. .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
  1776. .mmu_features = MMU_FTR_TYPE_44x,
  1777. .icache_bsize = 32,
  1778. .dcache_bsize = 32,
  1779. .cpu_setup = __setup_cpu_460gt,
  1780. .machine_check = machine_check_440A,
  1781. .platform = "ppc440",
  1782. },
  1783. { /* 460SX */
  1784. .pvr_mask = 0xffffff00,
  1785. .pvr_value = 0x13541800,
  1786. .cpu_name = "460SX",
  1787. .cpu_features = CPU_FTRS_44X,
  1788. .cpu_user_features = COMMON_USER_BOOKE,
  1789. .mmu_features = MMU_FTR_TYPE_44x,
  1790. .icache_bsize = 32,
  1791. .dcache_bsize = 32,
  1792. .cpu_setup = __setup_cpu_460sx,
  1793. .machine_check = machine_check_440A,
  1794. .platform = "ppc440",
  1795. },
  1796. { /* 464 in APM821xx */
  1797. .pvr_mask = 0xffffff00,
  1798. .pvr_value = 0x12C41C80,
  1799. .cpu_name = "APM821XX",
  1800. .cpu_features = CPU_FTRS_44X,
  1801. .cpu_user_features = COMMON_USER_BOOKE |
  1802. PPC_FEATURE_HAS_FPU,
  1803. .mmu_features = MMU_FTR_TYPE_44x,
  1804. .icache_bsize = 32,
  1805. .dcache_bsize = 32,
  1806. .cpu_setup = __setup_cpu_apm821xx,
  1807. .machine_check = machine_check_440A,
  1808. .platform = "ppc440",
  1809. },
  1810. { /* 476 DD2 core */
  1811. .pvr_mask = 0xffffffff,
  1812. .pvr_value = 0x11a52080,
  1813. .cpu_name = "476",
  1814. .cpu_features = CPU_FTRS_47X | CPU_FTR_476_DD2,
  1815. .cpu_user_features = COMMON_USER_BOOKE |
  1816. PPC_FEATURE_HAS_FPU,
  1817. .mmu_features = MMU_FTR_TYPE_47x |
  1818. MMU_FTR_USE_TLBIVAX_BCAST | MMU_FTR_LOCK_BCAST_INVAL,
  1819. .icache_bsize = 32,
  1820. .dcache_bsize = 128,
  1821. .machine_check = machine_check_47x,
  1822. .platform = "ppc470",
  1823. },
  1824. { /* 476 iss */
  1825. .pvr_mask = 0xffff0000,
  1826. .pvr_value = 0x00050000,
  1827. .cpu_name = "476",
  1828. .cpu_features = CPU_FTRS_47X,
  1829. .cpu_user_features = COMMON_USER_BOOKE |
  1830. PPC_FEATURE_HAS_FPU,
  1831. .mmu_features = MMU_FTR_TYPE_47x |
  1832. MMU_FTR_USE_TLBIVAX_BCAST | MMU_FTR_LOCK_BCAST_INVAL,
  1833. .icache_bsize = 32,
  1834. .dcache_bsize = 128,
  1835. .machine_check = machine_check_47x,
  1836. .platform = "ppc470",
  1837. },
  1838. { /* 476 others */
  1839. .pvr_mask = 0xffff0000,
  1840. .pvr_value = 0x11a50000,
  1841. .cpu_name = "476",
  1842. .cpu_features = CPU_FTRS_47X,
  1843. .cpu_user_features = COMMON_USER_BOOKE |
  1844. PPC_FEATURE_HAS_FPU,
  1845. .mmu_features = MMU_FTR_TYPE_47x |
  1846. MMU_FTR_USE_TLBIVAX_BCAST | MMU_FTR_LOCK_BCAST_INVAL,
  1847. .icache_bsize = 32,
  1848. .dcache_bsize = 128,
  1849. .machine_check = machine_check_47x,
  1850. .platform = "ppc470",
  1851. },
  1852. { /* default match */
  1853. .pvr_mask = 0x00000000,
  1854. .pvr_value = 0x00000000,
  1855. .cpu_name = "(generic 44x PPC)",
  1856. .cpu_features = CPU_FTRS_44X,
  1857. .cpu_user_features = COMMON_USER_BOOKE,
  1858. .mmu_features = MMU_FTR_TYPE_44x,
  1859. .icache_bsize = 32,
  1860. .dcache_bsize = 32,
  1861. .machine_check = machine_check_4xx,
  1862. .platform = "ppc440",
  1863. }
  1864. #endif /* CONFIG_44x */
  1865. #ifdef CONFIG_E200
  1866. { /* e200z5 */
  1867. .pvr_mask = 0xfff00000,
  1868. .pvr_value = 0x81000000,
  1869. .cpu_name = "e200z5",
  1870. /* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */
  1871. .cpu_features = CPU_FTRS_E200,
  1872. .cpu_user_features = COMMON_USER_BOOKE |
  1873. PPC_FEATURE_HAS_EFP_SINGLE |
  1874. PPC_FEATURE_UNIFIED_CACHE,
  1875. .mmu_features = MMU_FTR_TYPE_FSL_E,
  1876. .dcache_bsize = 32,
  1877. .machine_check = machine_check_e200,
  1878. .platform = "ppc5554",
  1879. },
  1880. { /* e200z6 */
  1881. .pvr_mask = 0xfff00000,
  1882. .pvr_value = 0x81100000,
  1883. .cpu_name = "e200z6",
  1884. /* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */
  1885. .cpu_features = CPU_FTRS_E200,
  1886. .cpu_user_features = COMMON_USER_BOOKE |
  1887. PPC_FEATURE_HAS_SPE_COMP |
  1888. PPC_FEATURE_HAS_EFP_SINGLE_COMP |
  1889. PPC_FEATURE_UNIFIED_CACHE,
  1890. .mmu_features = MMU_FTR_TYPE_FSL_E,
  1891. .dcache_bsize = 32,
  1892. .machine_check = machine_check_e200,
  1893. .platform = "ppc5554",
  1894. },
  1895. { /* default match */
  1896. .pvr_mask = 0x00000000,
  1897. .pvr_value = 0x00000000,
  1898. .cpu_name = "(generic E200 PPC)",
  1899. .cpu_features = CPU_FTRS_E200,
  1900. .cpu_user_features = COMMON_USER_BOOKE |
  1901. PPC_FEATURE_HAS_EFP_SINGLE |
  1902. PPC_FEATURE_UNIFIED_CACHE,
  1903. .mmu_features = MMU_FTR_TYPE_FSL_E,
  1904. .dcache_bsize = 32,
  1905. .cpu_setup = __setup_cpu_e200,
  1906. .machine_check = machine_check_e200,
  1907. .platform = "ppc5554",
  1908. }
  1909. #endif /* CONFIG_E200 */
  1910. #endif /* CONFIG_PPC32 */
  1911. #ifdef CONFIG_E500
  1912. #ifdef CONFIG_PPC32
  1913. { /* e500 */
  1914. .pvr_mask = 0xffff0000,
  1915. .pvr_value = 0x80200000,
  1916. .cpu_name = "e500",
  1917. .cpu_features = CPU_FTRS_E500,
  1918. .cpu_user_features = COMMON_USER_BOOKE |
  1919. PPC_FEATURE_HAS_SPE_COMP |
  1920. PPC_FEATURE_HAS_EFP_SINGLE_COMP,
  1921. .mmu_features = MMU_FTR_TYPE_FSL_E,
  1922. .icache_bsize = 32,
  1923. .dcache_bsize = 32,
  1924. .num_pmcs = 4,
  1925. .oprofile_cpu_type = "ppc/e500",
  1926. .oprofile_type = PPC_OPROFILE_FSL_EMB,
  1927. .cpu_setup = __setup_cpu_e500v1,
  1928. .machine_check = machine_check_e500,
  1929. .platform = "ppc8540",
  1930. },
  1931. { /* e500v2 */
  1932. .pvr_mask = 0xffff0000,
  1933. .pvr_value = 0x80210000,
  1934. .cpu_name = "e500v2",
  1935. .cpu_features = CPU_FTRS_E500_2,
  1936. .cpu_user_features = COMMON_USER_BOOKE |
  1937. PPC_FEATURE_HAS_SPE_COMP |
  1938. PPC_FEATURE_HAS_EFP_SINGLE_COMP |
  1939. PPC_FEATURE_HAS_EFP_DOUBLE_COMP,
  1940. .mmu_features = MMU_FTR_TYPE_FSL_E | MMU_FTR_BIG_PHYS,
  1941. .icache_bsize = 32,
  1942. .dcache_bsize = 32,
  1943. .num_pmcs = 4,
  1944. .oprofile_cpu_type = "ppc/e500",
  1945. .oprofile_type = PPC_OPROFILE_FSL_EMB,
  1946. .cpu_setup = __setup_cpu_e500v2,
  1947. .machine_check = machine_check_e500,
  1948. .platform = "ppc8548",
  1949. },
  1950. { /* e500mc */
  1951. .pvr_mask = 0xffff0000,
  1952. .pvr_value = 0x80230000,
  1953. .cpu_name = "e500mc",
  1954. .cpu_features = CPU_FTRS_E500MC,
  1955. .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
  1956. .mmu_features = MMU_FTR_TYPE_FSL_E | MMU_FTR_BIG_PHYS |
  1957. MMU_FTR_USE_TLBILX,
  1958. .icache_bsize = 64,
  1959. .dcache_bsize = 64,
  1960. .num_pmcs = 4,
  1961. .oprofile_cpu_type = "ppc/e500mc",
  1962. .oprofile_type = PPC_OPROFILE_FSL_EMB,
  1963. .cpu_setup = __setup_cpu_e500mc,
  1964. .machine_check = machine_check_e500mc,
  1965. .platform = "ppce500mc",
  1966. },
  1967. #endif /* CONFIG_PPC32 */
  1968. { /* e5500 */
  1969. .pvr_mask = 0xffff0000,
  1970. .pvr_value = 0x80240000,
  1971. .cpu_name = "e5500",
  1972. .cpu_features = CPU_FTRS_E5500,
  1973. .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
  1974. .mmu_features = MMU_FTR_TYPE_FSL_E | MMU_FTR_BIG_PHYS |
  1975. MMU_FTR_USE_TLBILX,
  1976. .icache_bsize = 64,
  1977. .dcache_bsize = 64,
  1978. .num_pmcs = 4,
  1979. .oprofile_cpu_type = "ppc/e500mc",
  1980. .oprofile_type = PPC_OPROFILE_FSL_EMB,
  1981. .cpu_setup = __setup_cpu_e5500,
  1982. .cpu_restore = __restore_cpu_e5500,
  1983. .machine_check = machine_check_e500mc,
  1984. .platform = "ppce5500",
  1985. },
  1986. #ifdef CONFIG_PPC32
  1987. { /* default match */
  1988. .pvr_mask = 0x00000000,
  1989. .pvr_value = 0x00000000,
  1990. .cpu_name = "(generic E500 PPC)",
  1991. .cpu_features = CPU_FTRS_E500,
  1992. .cpu_user_features = COMMON_USER_BOOKE |
  1993. PPC_FEATURE_HAS_SPE_COMP |
  1994. PPC_FEATURE_HAS_EFP_SINGLE_COMP,
  1995. .mmu_features = MMU_FTR_TYPE_FSL_E,
  1996. .icache_bsize = 32,
  1997. .dcache_bsize = 32,
  1998. .machine_check = machine_check_e500,
  1999. .platform = "powerpc",
  2000. }
  2001. #endif /* CONFIG_PPC32 */
  2002. #endif /* CONFIG_E500 */
  2003. #ifdef CONFIG_PPC_A2
  2004. { /* Standard A2 (>= DD2) + FPU core */
  2005. .pvr_mask = 0xffff0000,
  2006. .pvr_value = 0x00480000,
  2007. .cpu_name = "A2 (>= DD2)",
  2008. .cpu_features = CPU_FTRS_A2,
  2009. .cpu_user_features = COMMON_USER_PPC64,
  2010. .mmu_features = MMU_FTRS_A2,
  2011. .icache_bsize = 64,
  2012. .dcache_bsize = 64,
  2013. .num_pmcs = 0,
  2014. .cpu_setup = __setup_cpu_a2,
  2015. .cpu_restore = __restore_cpu_a2,
  2016. .machine_check = machine_check_generic,
  2017. .platform = "ppca2",
  2018. },
  2019. { /* This is a default entry to get going, to be replaced by
  2020. * a real one at some stage
  2021. */
  2022. #define CPU_FTRS_BASE_BOOK3E (CPU_FTR_USE_TB | \
  2023. CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_SMT | \
  2024. CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)
  2025. .pvr_mask = 0x00000000,
  2026. .pvr_value = 0x00000000,
  2027. .cpu_name = "Book3E",
  2028. .cpu_features = CPU_FTRS_BASE_BOOK3E,
  2029. .cpu_user_features = COMMON_USER_PPC64,
  2030. .mmu_features = MMU_FTR_TYPE_3E | MMU_FTR_USE_TLBILX |
  2031. MMU_FTR_USE_TLBIVAX_BCAST |
  2032. MMU_FTR_LOCK_BCAST_INVAL,
  2033. .icache_bsize = 64,
  2034. .dcache_bsize = 64,
  2035. .num_pmcs = 0,
  2036. .machine_check = machine_check_generic,
  2037. .platform = "power6",
  2038. },
  2039. #endif /* CONFIG_PPC_A2 */
  2040. };
  2041. static struct cpu_spec the_cpu_spec;
  2042. static void __init setup_cpu_spec(unsigned long offset, struct cpu_spec *s)
  2043. {
  2044. struct cpu_spec *t = &the_cpu_spec;
  2045. struct cpu_spec old;
  2046. t = PTRRELOC(t);
  2047. old = *t;
  2048. /* Copy everything, then do fixups */
  2049. *t = *s;
  2050. /*
  2051. * If we are overriding a previous value derived from the real
  2052. * PVR with a new value obtained using a logical PVR value,
  2053. * don't modify the performance monitor fields.
  2054. */
  2055. if (old.num_pmcs && !s->num_pmcs) {
  2056. t->num_pmcs = old.num_pmcs;
  2057. t->pmc_type = old.pmc_type;
  2058. t->oprofile_type = old.oprofile_type;
  2059. t->oprofile_mmcra_sihv = old.oprofile_mmcra_sihv;
  2060. t->oprofile_mmcra_sipr = old.oprofile_mmcra_sipr;
  2061. t->oprofile_mmcra_clear = old.oprofile_mmcra_clear;
  2062. /*
  2063. * If we have passed through this logic once before and
  2064. * have pulled the default case because the real PVR was
  2065. * not found inside cpu_specs[], then we are possibly
  2066. * running in compatibility mode. In that case, let the
  2067. * oprofiler know which set of compatibility counters to
  2068. * pull from by making sure the oprofile_cpu_type string
  2069. * is set to that of compatibility mode. If the
  2070. * oprofile_cpu_type already has a value, then we are
  2071. * possibly overriding a real PVR with a logical one,
  2072. * and, in that case, keep the current value for
  2073. * oprofile_cpu_type.
  2074. */
  2075. if (old.oprofile_cpu_type != NULL) {
  2076. t->oprofile_cpu_type = old.oprofile_cpu_type;
  2077. t->oprofile_type = old.oprofile_type;
  2078. }
  2079. }
  2080. *PTRRELOC(&cur_cpu_spec) = &the_cpu_spec;
  2081. /*
  2082. * Set the base platform string once; assumes
  2083. * we're called with real pvr first.
  2084. */
  2085. if (*PTRRELOC(&powerpc_base_platform) == NULL)
  2086. *PTRRELOC(&powerpc_base_platform) = t->platform;
  2087. #if defined(CONFIG_PPC64) || defined(CONFIG_BOOKE)
  2088. /* ppc64 and booke expect identify_cpu to also call setup_cpu for
  2089. * that processor. I will consolidate that at a later time, for now,
  2090. * just use #ifdef. We also don't need to PTRRELOC the function
  2091. * pointer on ppc64 and booke as we are running at 0 in real mode
  2092. * on ppc64 and reloc_offset is always 0 on booke.
  2093. */
  2094. if (t->cpu_setup) {
  2095. t->cpu_setup(offset, t);
  2096. }
  2097. #endif /* CONFIG_PPC64 || CONFIG_BOOKE */
  2098. }
  2099. struct cpu_spec * __init identify_cpu(unsigned long offset, unsigned int pvr)
  2100. {
  2101. struct cpu_spec *s = cpu_specs;
  2102. int i;
  2103. s = PTRRELOC(s);
  2104. for (i = 0; i < ARRAY_SIZE(cpu_specs); i++,s++) {
  2105. if ((pvr & s->pvr_mask) == s->pvr_value) {
  2106. setup_cpu_spec(offset, s);
  2107. return s;
  2108. }
  2109. }
  2110. BUG();
  2111. return NULL;
  2112. }