p5020si.dtsi 15 KB

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  1. /*
  2. * P5020 Silicon Device Tree Source
  3. *
  4. * Copyright 2010-2011 Freescale Semiconductor Inc.
  5. *
  6. * Redistribution and use in source and binary forms, with or without
  7. * modification, are permitted provided that the following conditions are met:
  8. * * Redistributions of source code must retain the above copyright
  9. * notice, this list of conditions and the following disclaimer.
  10. * * Redistributions in binary form must reproduce the above copyright
  11. * notice, this list of conditions and the following disclaimer in the
  12. * documentation and/or other materials provided with the distribution.
  13. * * Neither the name of Freescale Semiconductor nor the
  14. * names of its contributors may be used to endorse or promote products
  15. * derived from this software without specific prior written permission.
  16. *
  17. *
  18. * ALTERNATIVELY, this software may be distributed under the terms of the
  19. * GNU General Public License ("GPL") as published by the Free Software
  20. * Foundation, either version 2 of that License or (at your option) any
  21. * later version.
  22. *
  23. * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
  24. * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  25. * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  26. * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
  27. * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  28. * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  29. * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  30. * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  31. * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  32. * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  33. */
  34. /dts-v1/;
  35. / {
  36. compatible = "fsl,P5020";
  37. #address-cells = <2>;
  38. #size-cells = <2>;
  39. interrupt-parent = <&mpic>;
  40. aliases {
  41. ccsr = &soc;
  42. serial0 = &serial0;
  43. serial1 = &serial1;
  44. serial2 = &serial2;
  45. serial3 = &serial3;
  46. pci0 = &pci0;
  47. pci1 = &pci1;
  48. pci2 = &pci2;
  49. pci3 = &pci3;
  50. usb0 = &usb0;
  51. usb1 = &usb1;
  52. dma0 = &dma0;
  53. dma1 = &dma1;
  54. sdhc = &sdhc;
  55. msi0 = &msi0;
  56. msi1 = &msi1;
  57. msi2 = &msi2;
  58. crypto = &crypto;
  59. sec_jr0 = &sec_jr0;
  60. sec_jr1 = &sec_jr1;
  61. sec_jr2 = &sec_jr2;
  62. sec_jr3 = &sec_jr3;
  63. rtic_a = &rtic_a;
  64. rtic_b = &rtic_b;
  65. rtic_c = &rtic_c;
  66. rtic_d = &rtic_d;
  67. sec_mon = &sec_mon;
  68. /*
  69. rio0 = &rapidio0;
  70. */
  71. };
  72. cpus {
  73. #address-cells = <1>;
  74. #size-cells = <0>;
  75. cpu0: PowerPC,e5500@0 {
  76. device_type = "cpu";
  77. reg = <0>;
  78. next-level-cache = <&L2_0>;
  79. L2_0: l2-cache {
  80. next-level-cache = <&cpc>;
  81. };
  82. };
  83. cpu1: PowerPC,e5500@1 {
  84. device_type = "cpu";
  85. reg = <1>;
  86. next-level-cache = <&L2_1>;
  87. L2_1: l2-cache {
  88. next-level-cache = <&cpc>;
  89. };
  90. };
  91. };
  92. soc: soc@ffe000000 {
  93. #address-cells = <1>;
  94. #size-cells = <1>;
  95. device_type = "soc";
  96. compatible = "simple-bus";
  97. ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
  98. reg = <0xf 0xfe000000 0 0x00001000>;
  99. soc-sram-error {
  100. compatible = "fsl,soc-sram-error";
  101. interrupts = <16 2 1 29>;
  102. };
  103. corenet-law@0 {
  104. compatible = "fsl,corenet-law";
  105. reg = <0x0 0x1000>;
  106. fsl,num-laws = <32>;
  107. };
  108. memory-controller@8000 {
  109. compatible = "fsl,qoriq-memory-controller-v4.5", "fsl,qoriq-memory-controller";
  110. reg = <0x8000 0x1000>;
  111. interrupts = <16 2 1 23>;
  112. };
  113. memory-controller@9000 {
  114. compatible = "fsl,qoriq-memory-controller-v4.5", "fsl,qoriq-memory-controller";
  115. reg = <0x9000 0x1000>;
  116. interrupts = <16 2 1 22>;
  117. };
  118. cpc: l3-cache-controller@10000 {
  119. compatible = "fsl,p5020-l3-cache-controller", "fsl,p4080-l3-cache-controller", "cache";
  120. reg = <0x10000 0x1000
  121. 0x11000 0x1000>;
  122. interrupts = <16 2 1 27
  123. 16 2 1 26>;
  124. };
  125. corenet-cf@18000 {
  126. compatible = "fsl,corenet-cf";
  127. reg = <0x18000 0x1000>;
  128. interrupts = <16 2 1 31>;
  129. fsl,ccf-num-csdids = <32>;
  130. fsl,ccf-num-snoopids = <32>;
  131. };
  132. iommu@20000 {
  133. compatible = "fsl,pamu-v1.0", "fsl,pamu";
  134. reg = <0x20000 0x4000>;
  135. interrupts = <
  136. 24 2 0 0
  137. 16 2 1 30>;
  138. };
  139. mpic: pic@40000 {
  140. clock-frequency = <0>;
  141. interrupt-controller;
  142. #address-cells = <0>;
  143. #interrupt-cells = <4>;
  144. reg = <0x40000 0x40000>;
  145. compatible = "fsl,mpic", "chrp,open-pic";
  146. device_type = "open-pic";
  147. };
  148. msi0: msi@41600 {
  149. compatible = "fsl,mpic-msi";
  150. reg = <0x41600 0x200>;
  151. msi-available-ranges = <0 0x100>;
  152. interrupts = <
  153. 0xe0 0 0 0
  154. 0xe1 0 0 0
  155. 0xe2 0 0 0
  156. 0xe3 0 0 0
  157. 0xe4 0 0 0
  158. 0xe5 0 0 0
  159. 0xe6 0 0 0
  160. 0xe7 0 0 0>;
  161. };
  162. msi1: msi@41800 {
  163. compatible = "fsl,mpic-msi";
  164. reg = <0x41800 0x200>;
  165. msi-available-ranges = <0 0x100>;
  166. interrupts = <
  167. 0xe8 0 0 0
  168. 0xe9 0 0 0
  169. 0xea 0 0 0
  170. 0xeb 0 0 0
  171. 0xec 0 0 0
  172. 0xed 0 0 0
  173. 0xee 0 0 0
  174. 0xef 0 0 0>;
  175. };
  176. msi2: msi@41a00 {
  177. compatible = "fsl,mpic-msi";
  178. reg = <0x41a00 0x200>;
  179. msi-available-ranges = <0 0x100>;
  180. interrupts = <
  181. 0xf0 0 0 0
  182. 0xf1 0 0 0
  183. 0xf2 0 0 0
  184. 0xf3 0 0 0
  185. 0xf4 0 0 0
  186. 0xf5 0 0 0
  187. 0xf6 0 0 0
  188. 0xf7 0 0 0>;
  189. };
  190. guts: global-utilities@e0000 {
  191. compatible = "fsl,qoriq-device-config-1.0";
  192. reg = <0xe0000 0xe00>;
  193. fsl,has-rstcr;
  194. #sleep-cells = <1>;
  195. fsl,liodn-bits = <12>;
  196. };
  197. pins: global-utilities@e0e00 {
  198. compatible = "fsl,qoriq-pin-control-1.0";
  199. reg = <0xe0e00 0x200>;
  200. #sleep-cells = <2>;
  201. };
  202. clockgen: global-utilities@e1000 {
  203. compatible = "fsl,p5020-clockgen", "fsl,qoriq-clockgen-1.0";
  204. reg = <0xe1000 0x1000>;
  205. clock-frequency = <0>;
  206. };
  207. rcpm: global-utilities@e2000 {
  208. compatible = "fsl,qoriq-rcpm-1.0";
  209. reg = <0xe2000 0x1000>;
  210. #sleep-cells = <1>;
  211. };
  212. sfp: sfp@e8000 {
  213. compatible = "fsl,p5020-sfp", "fsl,qoriq-sfp-1.0";
  214. reg = <0xe8000 0x1000>;
  215. };
  216. serdes: serdes@ea000 {
  217. compatible = "fsl,p5020-serdes";
  218. reg = <0xea000 0x1000>;
  219. };
  220. dma0: dma@100300 {
  221. #address-cells = <1>;
  222. #size-cells = <1>;
  223. compatible = "fsl,p5020-dma", "fsl,eloplus-dma";
  224. reg = <0x100300 0x4>;
  225. ranges = <0x0 0x100100 0x200>;
  226. cell-index = <0>;
  227. dma-channel@0 {
  228. compatible = "fsl,p5020-dma-channel",
  229. "fsl,eloplus-dma-channel";
  230. reg = <0x0 0x80>;
  231. cell-index = <0>;
  232. interrupts = <28 2 0 0>;
  233. };
  234. dma-channel@80 {
  235. compatible = "fsl,p5020-dma-channel",
  236. "fsl,eloplus-dma-channel";
  237. reg = <0x80 0x80>;
  238. cell-index = <1>;
  239. interrupts = <29 2 0 0>;
  240. };
  241. dma-channel@100 {
  242. compatible = "fsl,p5020-dma-channel",
  243. "fsl,eloplus-dma-channel";
  244. reg = <0x100 0x80>;
  245. cell-index = <2>;
  246. interrupts = <30 2 0 0>;
  247. };
  248. dma-channel@180 {
  249. compatible = "fsl,p5020-dma-channel",
  250. "fsl,eloplus-dma-channel";
  251. reg = <0x180 0x80>;
  252. cell-index = <3>;
  253. interrupts = <31 2 0 0>;
  254. };
  255. };
  256. dma1: dma@101300 {
  257. #address-cells = <1>;
  258. #size-cells = <1>;
  259. compatible = "fsl,p5020-dma", "fsl,eloplus-dma";
  260. reg = <0x101300 0x4>;
  261. ranges = <0x0 0x101100 0x200>;
  262. cell-index = <1>;
  263. dma-channel@0 {
  264. compatible = "fsl,p5020-dma-channel",
  265. "fsl,eloplus-dma-channel";
  266. reg = <0x0 0x80>;
  267. cell-index = <0>;
  268. interrupts = <32 2 0 0>;
  269. };
  270. dma-channel@80 {
  271. compatible = "fsl,p5020-dma-channel",
  272. "fsl,eloplus-dma-channel";
  273. reg = <0x80 0x80>;
  274. cell-index = <1>;
  275. interrupts = <33 2 0 0>;
  276. };
  277. dma-channel@100 {
  278. compatible = "fsl,p5020-dma-channel",
  279. "fsl,eloplus-dma-channel";
  280. reg = <0x100 0x80>;
  281. cell-index = <2>;
  282. interrupts = <34 2 0 0>;
  283. };
  284. dma-channel@180 {
  285. compatible = "fsl,p5020-dma-channel",
  286. "fsl,eloplus-dma-channel";
  287. reg = <0x180 0x80>;
  288. cell-index = <3>;
  289. interrupts = <35 2 0 0>;
  290. };
  291. };
  292. spi@110000 {
  293. #address-cells = <1>;
  294. #size-cells = <0>;
  295. compatible = "fsl,p5020-espi", "fsl,mpc8536-espi";
  296. reg = <0x110000 0x1000>;
  297. interrupts = <53 0x2 0 0>;
  298. fsl,espi-num-chipselects = <4>;
  299. };
  300. sdhc: sdhc@114000 {
  301. compatible = "fsl,p5020-esdhc", "fsl,esdhc";
  302. reg = <0x114000 0x1000>;
  303. interrupts = <48 2 0 0>;
  304. sdhci,auto-cmd12;
  305. clock-frequency = <0>;
  306. };
  307. i2c@118000 {
  308. #address-cells = <1>;
  309. #size-cells = <0>;
  310. cell-index = <0>;
  311. compatible = "fsl-i2c";
  312. reg = <0x118000 0x100>;
  313. interrupts = <38 2 0 0>;
  314. dfsrr;
  315. };
  316. i2c@118100 {
  317. #address-cells = <1>;
  318. #size-cells = <0>;
  319. cell-index = <1>;
  320. compatible = "fsl-i2c";
  321. reg = <0x118100 0x100>;
  322. interrupts = <38 2 0 0>;
  323. dfsrr;
  324. };
  325. i2c@119000 {
  326. #address-cells = <1>;
  327. #size-cells = <0>;
  328. cell-index = <2>;
  329. compatible = "fsl-i2c";
  330. reg = <0x119000 0x100>;
  331. interrupts = <39 2 0 0>;
  332. dfsrr;
  333. };
  334. i2c@119100 {
  335. #address-cells = <1>;
  336. #size-cells = <0>;
  337. cell-index = <3>;
  338. compatible = "fsl-i2c";
  339. reg = <0x119100 0x100>;
  340. interrupts = <39 2 0 0>;
  341. dfsrr;
  342. };
  343. serial0: serial@11c500 {
  344. cell-index = <0>;
  345. device_type = "serial";
  346. compatible = "ns16550";
  347. reg = <0x11c500 0x100>;
  348. clock-frequency = <0>;
  349. interrupts = <36 2 0 0>;
  350. };
  351. serial1: serial@11c600 {
  352. cell-index = <1>;
  353. device_type = "serial";
  354. compatible = "ns16550";
  355. reg = <0x11c600 0x100>;
  356. clock-frequency = <0>;
  357. interrupts = <36 2 0 0>;
  358. };
  359. serial2: serial@11d500 {
  360. cell-index = <2>;
  361. device_type = "serial";
  362. compatible = "ns16550";
  363. reg = <0x11d500 0x100>;
  364. clock-frequency = <0>;
  365. interrupts = <37 2 0 0>;
  366. };
  367. serial3: serial@11d600 {
  368. cell-index = <3>;
  369. device_type = "serial";
  370. compatible = "ns16550";
  371. reg = <0x11d600 0x100>;
  372. clock-frequency = <0>;
  373. interrupts = <37 2 0 0>;
  374. };
  375. gpio0: gpio@130000 {
  376. compatible = "fsl,p5020-gpio", "fsl,qoriq-gpio";
  377. reg = <0x130000 0x1000>;
  378. interrupts = <55 2 0 0>;
  379. #gpio-cells = <2>;
  380. gpio-controller;
  381. };
  382. usb0: usb@210000 {
  383. compatible = "fsl,p5020-usb2-mph",
  384. "fsl,mpc85xx-usb2-mph", "fsl-usb2-mph";
  385. reg = <0x210000 0x1000>;
  386. #address-cells = <1>;
  387. #size-cells = <0>;
  388. interrupts = <44 0x2 0 0>;
  389. phy_type = "utmi";
  390. port0;
  391. };
  392. usb1: usb@211000 {
  393. compatible = "fsl,p5020-usb2-dr",
  394. "fsl,mpc85xx-usb2-dr", "fsl-usb2-dr";
  395. reg = <0x211000 0x1000>;
  396. #address-cells = <1>;
  397. #size-cells = <0>;
  398. interrupts = <45 0x2 0 0>;
  399. dr_mode = "host";
  400. phy_type = "utmi";
  401. };
  402. sata@220000 {
  403. compatible = "fsl,p5020-sata", "fsl,pq-sata-v2";
  404. reg = <0x220000 0x1000>;
  405. interrupts = <68 0x2 0 0>;
  406. };
  407. sata@221000 {
  408. compatible = "fsl,p5020-sata", "fsl,pq-sata-v2";
  409. reg = <0x221000 0x1000>;
  410. interrupts = <69 0x2 0 0>;
  411. };
  412. crypto: crypto@300000 {
  413. compatible = "fsl,sec-v4.2", "fsl,sec-v4.0";
  414. #address-cells = <1>;
  415. #size-cells = <1>;
  416. reg = <0x300000 0x10000>;
  417. ranges = <0 0x300000 0x10000>;
  418. interrupts = <92 2 0 0>;
  419. sec_jr0: jr@1000 {
  420. compatible = "fsl,sec-v4.2-job-ring",
  421. "fsl,sec-v4.0-job-ring";
  422. reg = <0x1000 0x1000>;
  423. interrupts = <88 2 0 0>;
  424. };
  425. sec_jr1: jr@2000 {
  426. compatible = "fsl,sec-v4.2-job-ring",
  427. "fsl,sec-v4.0-job-ring";
  428. reg = <0x2000 0x1000>;
  429. interrupts = <89 2 0 0>;
  430. };
  431. sec_jr2: jr@3000 {
  432. compatible = "fsl,sec-v4.2-job-ring",
  433. "fsl,sec-v4.0-job-ring";
  434. reg = <0x3000 0x1000>;
  435. interrupts = <90 2 0 0>;
  436. };
  437. sec_jr3: jr@4000 {
  438. compatible = "fsl,sec-v4.2-job-ring",
  439. "fsl,sec-v4.0-job-ring";
  440. reg = <0x4000 0x1000>;
  441. interrupts = <91 2 0 0>;
  442. };
  443. rtic@6000 {
  444. compatible = "fsl,sec-v4.2-rtic",
  445. "fsl,sec-v4.0-rtic";
  446. #address-cells = <1>;
  447. #size-cells = <1>;
  448. reg = <0x6000 0x100>;
  449. ranges = <0x0 0x6100 0xe00>;
  450. rtic_a: rtic-a@0 {
  451. compatible = "fsl,sec-v4.2-rtic-memory",
  452. "fsl,sec-v4.0-rtic-memory";
  453. reg = <0x00 0x20 0x100 0x80>;
  454. };
  455. rtic_b: rtic-b@20 {
  456. compatible = "fsl,sec-v4.2-rtic-memory",
  457. "fsl,sec-v4.0-rtic-memory";
  458. reg = <0x20 0x20 0x200 0x80>;
  459. };
  460. rtic_c: rtic-c@40 {
  461. compatible = "fsl,sec-v4.2-rtic-memory",
  462. "fsl,sec-v4.0-rtic-memory";
  463. reg = <0x40 0x20 0x300 0x80>;
  464. };
  465. rtic_d: rtic-d@60 {
  466. compatible = "fsl,sec-v4.2-rtic-memory",
  467. "fsl,sec-v4.0-rtic-memory";
  468. reg = <0x60 0x20 0x500 0x80>;
  469. };
  470. };
  471. };
  472. sec_mon: sec_mon@314000 {
  473. compatible = "fsl,sec-v4.2-mon", "fsl,sec-v4.0-mon";
  474. reg = <0x314000 0x1000>;
  475. interrupts = <93 2 0 0>;
  476. };
  477. };
  478. /*
  479. rapidio0: rapidio@ffe0c0000
  480. */
  481. localbus@ffe124000 {
  482. compatible = "fsl,p5020-elbc", "fsl,elbc", "simple-bus";
  483. interrupts = <25 2 0 0>;
  484. #address-cells = <2>;
  485. #size-cells = <1>;
  486. };
  487. pci0: pcie@ffe200000 {
  488. compatible = "fsl,p5020-pcie", "fsl,qoriq-pcie-v2.2";
  489. device_type = "pci";
  490. #size-cells = <2>;
  491. #address-cells = <3>;
  492. bus-range = <0x0 0xff>;
  493. clock-frequency = <0x1fca055>;
  494. fsl,msi = <&msi0>;
  495. interrupts = <16 2 1 15>;
  496. pcie@0 {
  497. reg = <0 0 0 0 0>;
  498. #interrupt-cells = <1>;
  499. #size-cells = <2>;
  500. #address-cells = <3>;
  501. device_type = "pci";
  502. interrupts = <16 2 1 15>;
  503. interrupt-map-mask = <0xf800 0 0 7>;
  504. interrupt-map = <
  505. /* IDSEL 0x0 */
  506. 0000 0 0 1 &mpic 40 1 0 0
  507. 0000 0 0 2 &mpic 1 1 0 0
  508. 0000 0 0 3 &mpic 2 1 0 0
  509. 0000 0 0 4 &mpic 3 1 0 0
  510. >;
  511. };
  512. };
  513. pci1: pcie@ffe201000 {
  514. compatible = "fsl,p5020-pcie", "fsl,qoriq-pcie-v2.2";
  515. device_type = "pci";
  516. #size-cells = <2>;
  517. #address-cells = <3>;
  518. bus-range = <0 0xff>;
  519. clock-frequency = <0x1fca055>;
  520. fsl,msi = <&msi1>;
  521. interrupts = <16 2 1 14>;
  522. pcie@0 {
  523. reg = <0 0 0 0 0>;
  524. #interrupt-cells = <1>;
  525. #size-cells = <2>;
  526. #address-cells = <3>;
  527. device_type = "pci";
  528. interrupts = <16 2 1 14>;
  529. interrupt-map-mask = <0xf800 0 0 7>;
  530. interrupt-map = <
  531. /* IDSEL 0x0 */
  532. 0000 0 0 1 &mpic 41 1 0 0
  533. 0000 0 0 2 &mpic 5 1 0 0
  534. 0000 0 0 3 &mpic 6 1 0 0
  535. 0000 0 0 4 &mpic 7 1 0 0
  536. >;
  537. };
  538. };
  539. pci2: pcie@ffe202000 {
  540. compatible = "fsl,p5020-pcie", "fsl,qoriq-pcie-v2.2";
  541. device_type = "pci";
  542. #size-cells = <2>;
  543. #address-cells = <3>;
  544. bus-range = <0x0 0xff>;
  545. clock-frequency = <0x1fca055>;
  546. fsl,msi = <&msi2>;
  547. interrupts = <16 2 1 13>;
  548. pcie@0 {
  549. reg = <0 0 0 0 0>;
  550. #interrupt-cells = <1>;
  551. #size-cells = <2>;
  552. #address-cells = <3>;
  553. device_type = "pci";
  554. interrupts = <16 2 1 13>;
  555. interrupt-map-mask = <0xf800 0 0 7>;
  556. interrupt-map = <
  557. /* IDSEL 0x0 */
  558. 0000 0 0 1 &mpic 42 1 0 0
  559. 0000 0 0 2 &mpic 9 1 0 0
  560. 0000 0 0 3 &mpic 10 1 0 0
  561. 0000 0 0 4 &mpic 11 1 0 0
  562. >;
  563. };
  564. };
  565. pci3: pcie@ffe203000 {
  566. compatible = "fsl,p5020-pcie", "fsl,qoriq-pcie-v2.2";
  567. device_type = "pci";
  568. #size-cells = <2>;
  569. #address-cells = <3>;
  570. bus-range = <0x0 0xff>;
  571. clock-frequency = <0x1fca055>;
  572. fsl,msi = <&msi2>;
  573. interrupts = <16 2 1 12>;
  574. pcie@0 {
  575. reg = <0 0 0 0 0>;
  576. #interrupt-cells = <1>;
  577. #size-cells = <2>;
  578. #address-cells = <3>;
  579. device_type = "pci";
  580. interrupts = <16 2 1 12>;
  581. interrupt-map-mask = <0xf800 0 0 7>;
  582. interrupt-map = <
  583. /* IDSEL 0x0 */
  584. 0000 0 0 1 &mpic 43 1 0 0
  585. 0000 0 0 2 &mpic 0 1 0 0
  586. 0000 0 0 3 &mpic 4 1 0 0
  587. 0000 0 0 4 &mpic 8 1 0 0
  588. >;
  589. };
  590. };
  591. };