irq.c 4.2 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175
  1. /*
  2. * Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
  3. * JZ4740 platform IRQ support
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms of the GNU General Public License as published by the
  7. * Free Software Foundation; either version 2 of the License, or (at your
  8. * option) any later version.
  9. *
  10. * You should have received a copy of the GNU General Public License along
  11. * with this program; if not, write to the Free Software Foundation, Inc.,
  12. * 675 Mass Ave, Cambridge, MA 02139, USA.
  13. *
  14. */
  15. #include <linux/errno.h>
  16. #include <linux/init.h>
  17. #include <linux/types.h>
  18. #include <linux/interrupt.h>
  19. #include <linux/ioport.h>
  20. #include <linux/timex.h>
  21. #include <linux/slab.h>
  22. #include <linux/delay.h>
  23. #include <linux/debugfs.h>
  24. #include <linux/seq_file.h>
  25. #include <asm/io.h>
  26. #include <asm/mipsregs.h>
  27. #include <asm/irq_cpu.h>
  28. #include <asm/mach-jz4740/base.h>
  29. static void __iomem *jz_intc_base;
  30. static uint32_t jz_intc_wakeup;
  31. static uint32_t jz_intc_saved;
  32. #define JZ_REG_INTC_STATUS 0x00
  33. #define JZ_REG_INTC_MASK 0x04
  34. #define JZ_REG_INTC_SET_MASK 0x08
  35. #define JZ_REG_INTC_CLEAR_MASK 0x0c
  36. #define JZ_REG_INTC_PENDING 0x10
  37. #define IRQ_BIT(x) BIT((x) - JZ4740_IRQ_BASE)
  38. static inline unsigned long intc_irq_bit(struct irq_data *data)
  39. {
  40. return (unsigned long)irq_data_get_irq_chip_data(data);
  41. }
  42. static void intc_irq_unmask(struct irq_data *data)
  43. {
  44. writel(intc_irq_bit(data), jz_intc_base + JZ_REG_INTC_CLEAR_MASK);
  45. }
  46. static void intc_irq_mask(struct irq_data *data)
  47. {
  48. writel(intc_irq_bit(data), jz_intc_base + JZ_REG_INTC_SET_MASK);
  49. }
  50. static int intc_irq_set_wake(struct irq_data *data, unsigned int on)
  51. {
  52. if (on)
  53. jz_intc_wakeup |= intc_irq_bit(data);
  54. else
  55. jz_intc_wakeup &= ~intc_irq_bit(data);
  56. return 0;
  57. }
  58. static struct irq_chip intc_irq_type = {
  59. .name = "INTC",
  60. .irq_mask = intc_irq_mask,
  61. .irq_mask_ack = intc_irq_mask,
  62. .irq_unmask = intc_irq_unmask,
  63. .irq_set_wake = intc_irq_set_wake,
  64. };
  65. static irqreturn_t jz4740_cascade(int irq, void *data)
  66. {
  67. uint32_t irq_reg;
  68. irq_reg = readl(jz_intc_base + JZ_REG_INTC_PENDING);
  69. if (irq_reg)
  70. generic_handle_irq(__fls(irq_reg) + JZ4740_IRQ_BASE);
  71. return IRQ_HANDLED;
  72. }
  73. static struct irqaction jz4740_cascade_action = {
  74. .handler = jz4740_cascade,
  75. .name = "JZ4740 cascade interrupt",
  76. };
  77. void __init arch_init_irq(void)
  78. {
  79. int i;
  80. mips_cpu_irq_init();
  81. jz_intc_base = ioremap(JZ4740_INTC_BASE_ADDR, 0x14);
  82. /* Mask all irqs */
  83. writel(0xffffffff, jz_intc_base + JZ_REG_INTC_SET_MASK);
  84. for (i = JZ4740_IRQ_BASE; i < JZ4740_IRQ_BASE + 32; i++) {
  85. irq_set_chip_data(i, (void *)IRQ_BIT(i));
  86. irq_set_chip_and_handler(i, &intc_irq_type, handle_level_irq);
  87. }
  88. setup_irq(2, &jz4740_cascade_action);
  89. }
  90. asmlinkage void plat_irq_dispatch(void)
  91. {
  92. unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
  93. if (pending & STATUSF_IP2)
  94. do_IRQ(2);
  95. else if (pending & STATUSF_IP3)
  96. do_IRQ(3);
  97. else
  98. spurious_interrupt();
  99. }
  100. void jz4740_intc_suspend(void)
  101. {
  102. jz_intc_saved = readl(jz_intc_base + JZ_REG_INTC_MASK);
  103. writel(~jz_intc_wakeup, jz_intc_base + JZ_REG_INTC_SET_MASK);
  104. writel(jz_intc_wakeup, jz_intc_base + JZ_REG_INTC_CLEAR_MASK);
  105. }
  106. void jz4740_intc_resume(void)
  107. {
  108. writel(~jz_intc_saved, jz_intc_base + JZ_REG_INTC_CLEAR_MASK);
  109. writel(jz_intc_saved, jz_intc_base + JZ_REG_INTC_SET_MASK);
  110. }
  111. #ifdef CONFIG_DEBUG_FS
  112. static inline void intc_seq_reg(struct seq_file *s, const char *name,
  113. unsigned int reg)
  114. {
  115. seq_printf(s, "%s:\t\t%08x\n", name, readl(jz_intc_base + reg));
  116. }
  117. static int intc_regs_show(struct seq_file *s, void *unused)
  118. {
  119. intc_seq_reg(s, "Status", JZ_REG_INTC_STATUS);
  120. intc_seq_reg(s, "Mask", JZ_REG_INTC_MASK);
  121. intc_seq_reg(s, "Pending", JZ_REG_INTC_PENDING);
  122. return 0;
  123. }
  124. static int intc_regs_open(struct inode *inode, struct file *file)
  125. {
  126. return single_open(file, intc_regs_show, NULL);
  127. }
  128. static const struct file_operations intc_regs_operations = {
  129. .open = intc_regs_open,
  130. .read = seq_read,
  131. .llseek = seq_lseek,
  132. .release = single_release,
  133. };
  134. static int __init intc_debugfs_init(void)
  135. {
  136. (void) debugfs_create_file("jz_regs_intc", S_IFREG | S_IRUGO,
  137. NULL, NULL, &intc_regs_operations);
  138. return 0;
  139. }
  140. subsys_initcall(intc_debugfs_init);
  141. #endif