head-ram.S 2.5 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141
  1. .global __main
  2. .global __rom_start
  3. .global _rambase
  4. .global _ramstart
  5. .global splash_bits
  6. .global _start
  7. .global _stext
  8. .global _edata
  9. #define DEBUG
  10. #define ROM_OFFSET 0x10C00000
  11. #define STACK_GAURD 0x10
  12. .text
  13. _start:
  14. _stext:
  15. movew #0x2700, %sr /* Exceptions off! */
  16. #if 0
  17. /* Init chip registers. uCsimm specific */
  18. moveb #0x00, 0xfffffb0b /* Watchdog off */
  19. moveb #0x10, 0xfffff000 /* SCR */
  20. movew #0x2400, 0xfffff200 /* PLLCR */
  21. movew #0x0123, 0xfffff202 /* PLLFSR */
  22. moveb #0x00, 0xfffff40b /* enable chip select */
  23. moveb #0x00, 0xfffff423 /* enable /DWE */
  24. moveb #0x08, 0xfffffd0d /* disable hardmap */
  25. moveb #0x07, 0xfffffd0e /* level 7 interrupt clear */
  26. movew #0x8600, 0xfffff100 /* FLASH at 0x10c00000 */
  27. movew #0x018b, 0xfffff110 /* 2Meg, enable, 0ws */
  28. movew #0x8f00, 0xfffffc00 /* DRAM configuration */
  29. movew #0x9667, 0xfffffc02 /* DRAM control */
  30. movew #0x0000, 0xfffff106 /* DRAM at 0x00000000 */
  31. movew #0x068f, 0xfffff116 /* 8Meg, enable, 0ws */
  32. moveb #0x40, 0xfffff300 /* IVR */
  33. movel #0x007FFFFF, %d0 /* IMR */
  34. movel %d0, 0xfffff304
  35. moveb 0xfffff42b, %d0
  36. andb #0xe0, %d0
  37. moveb %d0, 0xfffff42b
  38. moveb #0x08, 0xfffff907 /* Ignore CTS */
  39. movew #0x010b, 0xfffff902 /* BAUD to 9600 */
  40. movew #0xe100, 0xfffff900 /* enable */
  41. #endif
  42. movew #16384, %d0 /* PLL settle wait loop */
  43. L0:
  44. subw #1, %d0
  45. bne L0
  46. #ifdef DEBUG
  47. moveq #70, %d7 /* 'F' */
  48. moveb %d7,0xfffff907 /* No absolute addresses */
  49. pclp1:
  50. movew 0xfffff906, %d7
  51. andw #0x2000, %d7
  52. beq pclp1
  53. #endif /* DEBUG */
  54. #ifdef DEBUG
  55. moveq #82, %d7 /* 'R' */
  56. moveb %d7,0xfffff907 /* No absolute addresses */
  57. pclp3:
  58. movew 0xfffff906, %d7
  59. andw #0x2000, %d7
  60. beq pclp3
  61. #endif /* DEBUG */
  62. moveal #0x007ffff0, %ssp
  63. moveal #_sbss, %a0
  64. moveal #_ebss, %a1
  65. /* Copy 0 to %a0 until %a0 >= %a1 */
  66. L1:
  67. movel #0, %a0@+
  68. cmpal %a0, %a1
  69. bhi L1
  70. #ifdef DEBUG
  71. moveq #67, %d7 /* 'C' */
  72. jsr putc
  73. #endif /* DEBUG */
  74. pea 0
  75. pea env
  76. pea %sp@(4)
  77. pea 0
  78. #ifdef DEBUG
  79. moveq #70, %d7 /* 'F' */
  80. jsr putc
  81. #endif /* DEBUG */
  82. lp:
  83. jsr start_kernel
  84. jmp lp
  85. _exit:
  86. jmp _exit
  87. __main:
  88. /* nothing */
  89. rts
  90. #ifdef DEBUG
  91. putc:
  92. moveb %d7,0xfffff907
  93. pclp:
  94. movew 0xfffff906, %d7
  95. andw #0x2000, %d7
  96. beq pclp
  97. rts
  98. #endif /* DEBUG */
  99. .data
  100. /*
  101. * Set up the usable of RAM stuff. Size of RAM is determined then
  102. * an initial stack set up at the end.
  103. */
  104. .align 4
  105. _ramvec:
  106. .long 0
  107. _rambase:
  108. .long 0
  109. _ramstart:
  110. .long 0
  111. _ramend:
  112. .long 0
  113. env:
  114. .long 0