adc.c 12 KB

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  1. /* arch/arm/plat-samsung/adc.c
  2. *
  3. * Copyright (c) 2008 Simtec Electronics
  4. * http://armlinux.simtec.co.uk/
  5. * Ben Dooks <ben@simtec.co.uk>, <ben-linux@fluff.org>
  6. *
  7. * Samsung ADC device core
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License as published by
  11. * the Free Software Foundation; either version 2 of the License.
  12. */
  13. #include <linux/module.h>
  14. #include <linux/kernel.h>
  15. #include <linux/platform_device.h>
  16. #include <linux/sched.h>
  17. #include <linux/list.h>
  18. #include <linux/slab.h>
  19. #include <linux/err.h>
  20. #include <linux/clk.h>
  21. #include <linux/interrupt.h>
  22. #include <linux/io.h>
  23. #include <linux/regulator/consumer.h>
  24. #include <plat/regs-adc.h>
  25. #include <plat/adc.h>
  26. /* This driver is designed to control the usage of the ADC block between
  27. * the touchscreen and any other drivers that may need to use it, such as
  28. * the hwmon driver.
  29. *
  30. * Priority will be given to the touchscreen driver, but as this itself is
  31. * rate limited it should not starve other requests which are processed in
  32. * order that they are received.
  33. *
  34. * Each user registers to get a client block which uniquely identifies it
  35. * and stores information such as the necessary functions to callback when
  36. * action is required.
  37. */
  38. enum s3c_cpu_type {
  39. TYPE_ADCV1, /* S3C24XX */
  40. TYPE_ADCV2, /* S3C64XX, S5P64X0, S5PC100 */
  41. TYPE_ADCV3, /* S5PV210, S5PC110, EXYNOS4210 */
  42. };
  43. struct s3c_adc_client {
  44. struct platform_device *pdev;
  45. struct list_head pend;
  46. wait_queue_head_t *wait;
  47. unsigned int nr_samples;
  48. int result;
  49. unsigned char is_ts;
  50. unsigned char channel;
  51. void (*select_cb)(struct s3c_adc_client *c, unsigned selected);
  52. void (*convert_cb)(struct s3c_adc_client *c,
  53. unsigned val1, unsigned val2,
  54. unsigned *samples_left);
  55. };
  56. struct adc_device {
  57. struct platform_device *pdev;
  58. struct platform_device *owner;
  59. struct clk *clk;
  60. struct s3c_adc_client *cur;
  61. struct s3c_adc_client *ts_pend;
  62. void __iomem *regs;
  63. spinlock_t lock;
  64. unsigned int prescale;
  65. int irq;
  66. struct regulator *vdd;
  67. };
  68. static struct adc_device *adc_dev;
  69. static LIST_HEAD(adc_pending); /* protected by adc_device.lock */
  70. #define adc_dbg(_adc, msg...) dev_dbg(&(_adc)->pdev->dev, msg)
  71. static inline void s3c_adc_convert(struct adc_device *adc)
  72. {
  73. unsigned con = readl(adc->regs + S3C2410_ADCCON);
  74. con |= S3C2410_ADCCON_ENABLE_START;
  75. writel(con, adc->regs + S3C2410_ADCCON);
  76. }
  77. static inline void s3c_adc_select(struct adc_device *adc,
  78. struct s3c_adc_client *client)
  79. {
  80. unsigned con = readl(adc->regs + S3C2410_ADCCON);
  81. enum s3c_cpu_type cpu = platform_get_device_id(adc->pdev)->driver_data;
  82. client->select_cb(client, 1);
  83. con &= ~S3C2410_ADCCON_MUXMASK;
  84. con &= ~S3C2410_ADCCON_STDBM;
  85. con &= ~S3C2410_ADCCON_STARTMASK;
  86. if (!client->is_ts) {
  87. if (cpu == TYPE_ADCV3)
  88. writel(client->channel & 0xf, adc->regs + S5P_ADCMUX);
  89. else
  90. con |= S3C2410_ADCCON_SELMUX(client->channel);
  91. }
  92. writel(con, adc->regs + S3C2410_ADCCON);
  93. }
  94. static void s3c_adc_dbgshow(struct adc_device *adc)
  95. {
  96. adc_dbg(adc, "CON=%08x, TSC=%08x, DLY=%08x\n",
  97. readl(adc->regs + S3C2410_ADCCON),
  98. readl(adc->regs + S3C2410_ADCTSC),
  99. readl(adc->regs + S3C2410_ADCDLY));
  100. }
  101. static void s3c_adc_try(struct adc_device *adc)
  102. {
  103. struct s3c_adc_client *next = adc->ts_pend;
  104. if (!next && !list_empty(&adc_pending)) {
  105. next = list_first_entry(&adc_pending,
  106. struct s3c_adc_client, pend);
  107. list_del(&next->pend);
  108. } else
  109. adc->ts_pend = NULL;
  110. if (next) {
  111. adc_dbg(adc, "new client is %p\n", next);
  112. adc->cur = next;
  113. s3c_adc_select(adc, next);
  114. s3c_adc_convert(adc);
  115. s3c_adc_dbgshow(adc);
  116. }
  117. }
  118. int s3c_adc_start(struct s3c_adc_client *client,
  119. unsigned int channel, unsigned int nr_samples)
  120. {
  121. struct adc_device *adc = adc_dev;
  122. unsigned long flags;
  123. if (!adc) {
  124. printk(KERN_ERR "%s: failed to find adc\n", __func__);
  125. return -EINVAL;
  126. }
  127. if (client->is_ts && adc->ts_pend)
  128. return -EAGAIN;
  129. spin_lock_irqsave(&adc->lock, flags);
  130. client->channel = channel;
  131. client->nr_samples = nr_samples;
  132. if (client->is_ts)
  133. adc->ts_pend = client;
  134. else
  135. list_add_tail(&client->pend, &adc_pending);
  136. if (!adc->cur)
  137. s3c_adc_try(adc);
  138. spin_unlock_irqrestore(&adc->lock, flags);
  139. return 0;
  140. }
  141. EXPORT_SYMBOL_GPL(s3c_adc_start);
  142. static void s3c_convert_done(struct s3c_adc_client *client,
  143. unsigned v, unsigned u, unsigned *left)
  144. {
  145. client->result = v;
  146. wake_up(client->wait);
  147. }
  148. int s3c_adc_read(struct s3c_adc_client *client, unsigned int ch)
  149. {
  150. DECLARE_WAIT_QUEUE_HEAD_ONSTACK(wake);
  151. int ret;
  152. client->convert_cb = s3c_convert_done;
  153. client->wait = &wake;
  154. client->result = -1;
  155. ret = s3c_adc_start(client, ch, 1);
  156. if (ret < 0)
  157. goto err;
  158. ret = wait_event_timeout(wake, client->result >= 0, HZ / 2);
  159. if (client->result < 0) {
  160. ret = -ETIMEDOUT;
  161. goto err;
  162. }
  163. client->convert_cb = NULL;
  164. return client->result;
  165. err:
  166. return ret;
  167. }
  168. EXPORT_SYMBOL_GPL(s3c_adc_read);
  169. static void s3c_adc_default_select(struct s3c_adc_client *client,
  170. unsigned select)
  171. {
  172. }
  173. struct s3c_adc_client *s3c_adc_register(struct platform_device *pdev,
  174. void (*select)(struct s3c_adc_client *client,
  175. unsigned int selected),
  176. void (*conv)(struct s3c_adc_client *client,
  177. unsigned d0, unsigned d1,
  178. unsigned *samples_left),
  179. unsigned int is_ts)
  180. {
  181. struct s3c_adc_client *client;
  182. WARN_ON(!pdev);
  183. if (!select)
  184. select = s3c_adc_default_select;
  185. if (!pdev)
  186. return ERR_PTR(-EINVAL);
  187. client = kzalloc(sizeof(struct s3c_adc_client), GFP_KERNEL);
  188. if (!client) {
  189. dev_err(&pdev->dev, "no memory for adc client\n");
  190. return ERR_PTR(-ENOMEM);
  191. }
  192. client->pdev = pdev;
  193. client->is_ts = is_ts;
  194. client->select_cb = select;
  195. client->convert_cb = conv;
  196. return client;
  197. }
  198. EXPORT_SYMBOL_GPL(s3c_adc_register);
  199. void s3c_adc_release(struct s3c_adc_client *client)
  200. {
  201. unsigned long flags;
  202. spin_lock_irqsave(&adc_dev->lock, flags);
  203. /* We should really check that nothing is in progress. */
  204. if (adc_dev->cur == client)
  205. adc_dev->cur = NULL;
  206. if (adc_dev->ts_pend == client)
  207. adc_dev->ts_pend = NULL;
  208. else {
  209. struct list_head *p, *n;
  210. struct s3c_adc_client *tmp;
  211. list_for_each_safe(p, n, &adc_pending) {
  212. tmp = list_entry(p, struct s3c_adc_client, pend);
  213. if (tmp == client)
  214. list_del(&tmp->pend);
  215. }
  216. }
  217. if (adc_dev->cur == NULL)
  218. s3c_adc_try(adc_dev);
  219. spin_unlock_irqrestore(&adc_dev->lock, flags);
  220. kfree(client);
  221. }
  222. EXPORT_SYMBOL_GPL(s3c_adc_release);
  223. static irqreturn_t s3c_adc_irq(int irq, void *pw)
  224. {
  225. struct adc_device *adc = pw;
  226. struct s3c_adc_client *client = adc->cur;
  227. enum s3c_cpu_type cpu = platform_get_device_id(adc->pdev)->driver_data;
  228. unsigned data0, data1;
  229. if (!client) {
  230. dev_warn(&adc->pdev->dev, "%s: no adc pending\n", __func__);
  231. goto exit;
  232. }
  233. data0 = readl(adc->regs + S3C2410_ADCDAT0);
  234. data1 = readl(adc->regs + S3C2410_ADCDAT1);
  235. adc_dbg(adc, "read %d: 0x%04x, 0x%04x\n", client->nr_samples, data0, data1);
  236. client->nr_samples--;
  237. if (cpu != TYPE_ADCV1) {
  238. /* S3C64XX/S5P ADC resolution is 12-bit */
  239. data0 &= 0xfff;
  240. data1 &= 0xfff;
  241. } else {
  242. data0 &= 0x3ff;
  243. data1 &= 0x3ff;
  244. }
  245. if (client->convert_cb)
  246. (client->convert_cb)(client, data0, data1, &client->nr_samples);
  247. if (client->nr_samples > 0) {
  248. /* fire another conversion for this */
  249. client->select_cb(client, 1);
  250. s3c_adc_convert(adc);
  251. } else {
  252. spin_lock(&adc->lock);
  253. (client->select_cb)(client, 0);
  254. adc->cur = NULL;
  255. s3c_adc_try(adc);
  256. spin_unlock(&adc->lock);
  257. }
  258. exit:
  259. if (cpu != TYPE_ADCV1) {
  260. /* Clear ADC interrupt */
  261. writel(0, adc->regs + S3C64XX_ADCCLRINT);
  262. }
  263. return IRQ_HANDLED;
  264. }
  265. static int s3c_adc_probe(struct platform_device *pdev)
  266. {
  267. struct device *dev = &pdev->dev;
  268. struct adc_device *adc;
  269. struct resource *regs;
  270. int ret;
  271. unsigned tmp;
  272. adc = kzalloc(sizeof(struct adc_device), GFP_KERNEL);
  273. if (adc == NULL) {
  274. dev_err(dev, "failed to allocate adc_device\n");
  275. return -ENOMEM;
  276. }
  277. spin_lock_init(&adc->lock);
  278. adc->pdev = pdev;
  279. adc->prescale = S3C2410_ADCCON_PRSCVL(49);
  280. adc->vdd = regulator_get(dev, "vdd");
  281. if (IS_ERR(adc->vdd)) {
  282. dev_err(dev, "operating without regulator \"vdd\" .\n");
  283. ret = PTR_ERR(adc->vdd);
  284. goto err_alloc;
  285. }
  286. adc->irq = platform_get_irq(pdev, 1);
  287. if (adc->irq <= 0) {
  288. dev_err(dev, "failed to get adc irq\n");
  289. ret = -ENOENT;
  290. goto err_reg;
  291. }
  292. ret = request_irq(adc->irq, s3c_adc_irq, 0, dev_name(dev), adc);
  293. if (ret < 0) {
  294. dev_err(dev, "failed to attach adc irq\n");
  295. goto err_reg;
  296. }
  297. adc->clk = clk_get(dev, "adc");
  298. if (IS_ERR(adc->clk)) {
  299. dev_err(dev, "failed to get adc clock\n");
  300. ret = PTR_ERR(adc->clk);
  301. goto err_irq;
  302. }
  303. regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  304. if (!regs) {
  305. dev_err(dev, "failed to find registers\n");
  306. ret = -ENXIO;
  307. goto err_clk;
  308. }
  309. adc->regs = ioremap(regs->start, resource_size(regs));
  310. if (!adc->regs) {
  311. dev_err(dev, "failed to map registers\n");
  312. ret = -ENXIO;
  313. goto err_clk;
  314. }
  315. ret = regulator_enable(adc->vdd);
  316. if (ret)
  317. goto err_ioremap;
  318. clk_enable(adc->clk);
  319. tmp = adc->prescale | S3C2410_ADCCON_PRSCEN;
  320. if (platform_get_device_id(pdev)->driver_data != TYPE_ADCV1) {
  321. /* Enable 12-bit ADC resolution */
  322. tmp |= S3C64XX_ADCCON_RESSEL;
  323. }
  324. writel(tmp, adc->regs + S3C2410_ADCCON);
  325. dev_info(dev, "attached adc driver\n");
  326. platform_set_drvdata(pdev, adc);
  327. adc_dev = adc;
  328. return 0;
  329. err_ioremap:
  330. iounmap(adc->regs);
  331. err_clk:
  332. clk_put(adc->clk);
  333. err_irq:
  334. free_irq(adc->irq, adc);
  335. err_reg:
  336. regulator_put(adc->vdd);
  337. err_alloc:
  338. kfree(adc);
  339. return ret;
  340. }
  341. static int __devexit s3c_adc_remove(struct platform_device *pdev)
  342. {
  343. struct adc_device *adc = platform_get_drvdata(pdev);
  344. iounmap(adc->regs);
  345. free_irq(adc->irq, adc);
  346. clk_disable(adc->clk);
  347. regulator_disable(adc->vdd);
  348. regulator_put(adc->vdd);
  349. clk_put(adc->clk);
  350. kfree(adc);
  351. return 0;
  352. }
  353. #ifdef CONFIG_PM
  354. static int s3c_adc_suspend(struct device *dev)
  355. {
  356. struct platform_device *pdev = container_of(dev,
  357. struct platform_device, dev);
  358. struct adc_device *adc = platform_get_drvdata(pdev);
  359. unsigned long flags;
  360. u32 con;
  361. spin_lock_irqsave(&adc->lock, flags);
  362. con = readl(adc->regs + S3C2410_ADCCON);
  363. con |= S3C2410_ADCCON_STDBM;
  364. writel(con, adc->regs + S3C2410_ADCCON);
  365. disable_irq(adc->irq);
  366. spin_unlock_irqrestore(&adc->lock, flags);
  367. clk_disable(adc->clk);
  368. regulator_disable(adc->vdd);
  369. return 0;
  370. }
  371. static int s3c_adc_resume(struct device *dev)
  372. {
  373. struct platform_device *pdev = container_of(dev,
  374. struct platform_device, dev);
  375. struct adc_device *adc = platform_get_drvdata(pdev);
  376. int ret;
  377. unsigned long tmp;
  378. ret = regulator_enable(adc->vdd);
  379. if (ret)
  380. return ret;
  381. clk_enable(adc->clk);
  382. enable_irq(adc->irq);
  383. tmp = adc->prescale | S3C2410_ADCCON_PRSCEN;
  384. /* Enable 12-bit ADC resolution */
  385. if (platform_get_device_id(pdev)->driver_data != TYPE_ADCV1)
  386. tmp |= S3C64XX_ADCCON_RESSEL;
  387. writel(tmp, adc->regs + S3C2410_ADCCON);
  388. return 0;
  389. }
  390. #else
  391. #define s3c_adc_suspend NULL
  392. #define s3c_adc_resume NULL
  393. #endif
  394. static struct platform_device_id s3c_adc_driver_ids[] = {
  395. {
  396. .name = "s3c24xx-adc",
  397. .driver_data = TYPE_ADCV1,
  398. }, {
  399. .name = "s3c64xx-adc",
  400. .driver_data = TYPE_ADCV2,
  401. }, {
  402. .name = "samsung-adc-v3",
  403. .driver_data = TYPE_ADCV3,
  404. },
  405. { }
  406. };
  407. MODULE_DEVICE_TABLE(platform, s3c_adc_driver_ids);
  408. static const struct dev_pm_ops adc_pm_ops = {
  409. .suspend = s3c_adc_suspend,
  410. .resume = s3c_adc_resume,
  411. };
  412. static struct platform_driver s3c_adc_driver = {
  413. .id_table = s3c_adc_driver_ids,
  414. .driver = {
  415. .name = "s3c-adc",
  416. .owner = THIS_MODULE,
  417. .pm = &adc_pm_ops,
  418. },
  419. .probe = s3c_adc_probe,
  420. .remove = __devexit_p(s3c_adc_remove),
  421. };
  422. static int __init adc_init(void)
  423. {
  424. int ret;
  425. ret = platform_driver_register(&s3c_adc_driver);
  426. if (ret)
  427. printk(KERN_ERR "%s: failed to add adc driver\n", __func__);
  428. return ret;
  429. }
  430. module_init(adc_init);