time.c 4.0 KB

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  1. /*
  2. * linux/arch/arm/mach-w90x900/time.c
  3. *
  4. * Based on linux/arch/arm/plat-s3c24xx/time.c by Ben Dooks
  5. *
  6. * Copyright (c) 2009 Nuvoton technology corporation
  7. * All rights reserved.
  8. *
  9. * Wan ZongShun <mcuos.com@gmail.com>
  10. *
  11. * This program is free software; you can redistribute it and/or modify
  12. * it under the terms of the GNU General Public License as published by
  13. * the Free Software Foundation; either version 2 of the License, or
  14. * (at your option) any later version.
  15. *
  16. */
  17. #include <linux/kernel.h>
  18. #include <linux/sched.h>
  19. #include <linux/init.h>
  20. #include <linux/interrupt.h>
  21. #include <linux/err.h>
  22. #include <linux/clk.h>
  23. #include <linux/io.h>
  24. #include <linux/leds.h>
  25. #include <linux/clocksource.h>
  26. #include <linux/clockchips.h>
  27. #include <asm/mach-types.h>
  28. #include <asm/mach/irq.h>
  29. #include <asm/mach/time.h>
  30. #include <mach/map.h>
  31. #include <mach/regs-timer.h>
  32. #define RESETINT 0x1f
  33. #define PERIOD (0x01 << 27)
  34. #define ONESHOT (0x00 << 27)
  35. #define COUNTEN (0x01 << 30)
  36. #define INTEN (0x01 << 29)
  37. #define TICKS_PER_SEC 100
  38. #define PRESCALE 0x63 /* Divider = prescale + 1 */
  39. #define TDR_SHIFT 24
  40. static unsigned int timer0_load;
  41. static void nuc900_clockevent_setmode(enum clock_event_mode mode,
  42. struct clock_event_device *clk)
  43. {
  44. unsigned int val;
  45. val = __raw_readl(REG_TCSR0);
  46. val &= ~(0x03 << 27);
  47. switch (mode) {
  48. case CLOCK_EVT_MODE_PERIODIC:
  49. __raw_writel(timer0_load, REG_TICR0);
  50. val |= (PERIOD | COUNTEN | INTEN | PRESCALE);
  51. break;
  52. case CLOCK_EVT_MODE_ONESHOT:
  53. val |= (ONESHOT | COUNTEN | INTEN | PRESCALE);
  54. break;
  55. case CLOCK_EVT_MODE_UNUSED:
  56. case CLOCK_EVT_MODE_SHUTDOWN:
  57. case CLOCK_EVT_MODE_RESUME:
  58. break;
  59. }
  60. __raw_writel(val, REG_TCSR0);
  61. }
  62. static int nuc900_clockevent_setnextevent(unsigned long evt,
  63. struct clock_event_device *clk)
  64. {
  65. unsigned int val;
  66. __raw_writel(evt, REG_TICR0);
  67. val = __raw_readl(REG_TCSR0);
  68. val |= (COUNTEN | INTEN | PRESCALE);
  69. __raw_writel(val, REG_TCSR0);
  70. return 0;
  71. }
  72. static struct clock_event_device nuc900_clockevent_device = {
  73. .name = "nuc900-timer0",
  74. .shift = 32,
  75. .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
  76. .set_mode = nuc900_clockevent_setmode,
  77. .set_next_event = nuc900_clockevent_setnextevent,
  78. .rating = 300,
  79. };
  80. /*IRQ handler for the timer*/
  81. static irqreturn_t nuc900_timer0_interrupt(int irq, void *dev_id)
  82. {
  83. struct clock_event_device *evt = &nuc900_clockevent_device;
  84. __raw_writel(0x01, REG_TISR); /* clear TIF0 */
  85. evt->event_handler(evt);
  86. return IRQ_HANDLED;
  87. }
  88. static struct irqaction nuc900_timer0_irq = {
  89. .name = "nuc900-timer0",
  90. .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
  91. .handler = nuc900_timer0_interrupt,
  92. };
  93. static void __init nuc900_clockevents_init(void)
  94. {
  95. unsigned int rate;
  96. struct clk *clk = clk_get(NULL, "timer0");
  97. BUG_ON(IS_ERR(clk));
  98. __raw_writel(0x00, REG_TCSR0);
  99. clk_enable(clk);
  100. rate = clk_get_rate(clk) / (PRESCALE + 1);
  101. timer0_load = (rate / TICKS_PER_SEC);
  102. __raw_writel(RESETINT, REG_TISR);
  103. setup_irq(IRQ_TIMER0, &nuc900_timer0_irq);
  104. nuc900_clockevent_device.mult = div_sc(rate, NSEC_PER_SEC,
  105. nuc900_clockevent_device.shift);
  106. nuc900_clockevent_device.max_delta_ns = clockevent_delta2ns(0xffffffff,
  107. &nuc900_clockevent_device);
  108. nuc900_clockevent_device.min_delta_ns = clockevent_delta2ns(0xf,
  109. &nuc900_clockevent_device);
  110. nuc900_clockevent_device.cpumask = cpumask_of(0);
  111. clockevents_register_device(&nuc900_clockevent_device);
  112. }
  113. static void __init nuc900_clocksource_init(void)
  114. {
  115. unsigned int val;
  116. unsigned int rate;
  117. struct clk *clk = clk_get(NULL, "timer1");
  118. BUG_ON(IS_ERR(clk));
  119. __raw_writel(0x00, REG_TCSR1);
  120. clk_enable(clk);
  121. rate = clk_get_rate(clk) / (PRESCALE + 1);
  122. __raw_writel(0xffffffff, REG_TICR1);
  123. val = __raw_readl(REG_TCSR1);
  124. val |= (COUNTEN | PERIOD | PRESCALE);
  125. __raw_writel(val, REG_TCSR1);
  126. clocksource_mmio_init(REG_TDR1, "nuc900-timer1", rate, 200,
  127. TDR_SHIFT, clocksource_mmio_readl_down);
  128. }
  129. static void __init nuc900_timer_init(void)
  130. {
  131. nuc900_clocksource_init();
  132. nuc900_clockevents_init();
  133. }
  134. struct sys_timer nuc900_timer = {
  135. .init = nuc900_timer_init,
  136. };