irq.c 1.9 KB

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  1. /* arch/arm/plat-s3c64xx/irq.c
  2. *
  3. * Copyright 2008 Openmoko, Inc.
  4. * Copyright 2008 Simtec Electronics
  5. * Ben Dooks <ben@simtec.co.uk>
  6. * http://armlinux.simtec.co.uk/
  7. *
  8. * S3C64XX - Interrupt handling
  9. *
  10. * This program is free software; you can redistribute it and/or modify
  11. * it under the terms of the GNU General Public License version 2 as
  12. * published by the Free Software Foundation.
  13. */
  14. #include <linux/kernel.h>
  15. #include <linux/interrupt.h>
  16. #include <linux/serial_core.h>
  17. #include <linux/irq.h>
  18. #include <linux/io.h>
  19. #include <asm/hardware/vic.h>
  20. #include <mach/map.h>
  21. #include <plat/irq-vic-timer.h>
  22. #include <plat/irq-uart.h>
  23. #include <plat/cpu.h>
  24. static struct s3c_uart_irq uart_irqs[] = {
  25. [0] = {
  26. .regs = S3C_VA_UART0,
  27. .base_irq = IRQ_S3CUART_BASE0,
  28. .parent_irq = IRQ_UART0,
  29. },
  30. [1] = {
  31. .regs = S3C_VA_UART1,
  32. .base_irq = IRQ_S3CUART_BASE1,
  33. .parent_irq = IRQ_UART1,
  34. },
  35. [2] = {
  36. .regs = S3C_VA_UART2,
  37. .base_irq = IRQ_S3CUART_BASE2,
  38. .parent_irq = IRQ_UART2,
  39. },
  40. [3] = {
  41. .regs = S3C_VA_UART3,
  42. .base_irq = IRQ_S3CUART_BASE3,
  43. .parent_irq = IRQ_UART3,
  44. },
  45. };
  46. /* setup the sources the vic should advertise resume for, even though it
  47. * is not doing the wake (set_irq_wake needs to be valid) */
  48. #define IRQ_VIC0_RESUME (1 << (IRQ_RTC_TIC - IRQ_VIC0_BASE))
  49. #define IRQ_VIC1_RESUME (1 << (IRQ_RTC_ALARM - IRQ_VIC1_BASE) | \
  50. 1 << (IRQ_PENDN - IRQ_VIC1_BASE) | \
  51. 1 << (IRQ_HSMMC0 - IRQ_VIC1_BASE) | \
  52. 1 << (IRQ_HSMMC1 - IRQ_VIC1_BASE) | \
  53. 1 << (IRQ_HSMMC2 - IRQ_VIC1_BASE))
  54. void __init s3c64xx_init_irq(u32 vic0_valid, u32 vic1_valid)
  55. {
  56. printk(KERN_DEBUG "%s: initialising interrupts\n", __func__);
  57. /* initialise the pair of VICs */
  58. vic_init(VA_VIC0, IRQ_VIC0_BASE, vic0_valid, IRQ_VIC0_RESUME);
  59. vic_init(VA_VIC1, IRQ_VIC1_BASE, vic1_valid, IRQ_VIC1_RESUME);
  60. /* add the timer sub-irqs */
  61. s3c_init_vic_timer_irq(5, IRQ_TIMER0);
  62. s3c_init_uart_irqs(uart_irqs, ARRAY_SIZE(uart_irqs));
  63. }