devices.c 21 KB

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  1. #include <linux/module.h>
  2. #include <linux/kernel.h>
  3. #include <linux/init.h>
  4. #include <linux/platform_device.h>
  5. #include <linux/dma-mapping.h>
  6. #include <linux/spi/pxa2xx_spi.h>
  7. #include <linux/i2c/pxa-i2c.h>
  8. #include <asm/pmu.h>
  9. #include <mach/udc.h>
  10. #include <mach/pxa3xx-u2d.h>
  11. #include <mach/pxafb.h>
  12. #include <mach/mmc.h>
  13. #include <mach/irda.h>
  14. #include <mach/ohci.h>
  15. #include <plat/pxa27x_keypad.h>
  16. #include <mach/camera.h>
  17. #include <mach/audio.h>
  18. #include <mach/hardware.h>
  19. #include <plat/pxa3xx_nand.h>
  20. #include "devices.h"
  21. #include "generic.h"
  22. void __init pxa_register_device(struct platform_device *dev, void *data)
  23. {
  24. int ret;
  25. dev->dev.platform_data = data;
  26. ret = platform_device_register(dev);
  27. if (ret)
  28. dev_err(&dev->dev, "unable to register device: %d\n", ret);
  29. }
  30. static struct resource pxa_resource_pmu = {
  31. .start = IRQ_PMU,
  32. .end = IRQ_PMU,
  33. .flags = IORESOURCE_IRQ,
  34. };
  35. struct platform_device pxa_device_pmu = {
  36. .name = "arm-pmu",
  37. .id = ARM_PMU_DEVICE_CPU,
  38. .resource = &pxa_resource_pmu,
  39. .num_resources = 1,
  40. };
  41. static struct resource pxamci_resources[] = {
  42. [0] = {
  43. .start = 0x41100000,
  44. .end = 0x41100fff,
  45. .flags = IORESOURCE_MEM,
  46. },
  47. [1] = {
  48. .start = IRQ_MMC,
  49. .end = IRQ_MMC,
  50. .flags = IORESOURCE_IRQ,
  51. },
  52. [2] = {
  53. .start = 21,
  54. .end = 21,
  55. .flags = IORESOURCE_DMA,
  56. },
  57. [3] = {
  58. .start = 22,
  59. .end = 22,
  60. .flags = IORESOURCE_DMA,
  61. },
  62. };
  63. static u64 pxamci_dmamask = 0xffffffffUL;
  64. struct platform_device pxa_device_mci = {
  65. .name = "pxa2xx-mci",
  66. .id = 0,
  67. .dev = {
  68. .dma_mask = &pxamci_dmamask,
  69. .coherent_dma_mask = 0xffffffff,
  70. },
  71. .num_resources = ARRAY_SIZE(pxamci_resources),
  72. .resource = pxamci_resources,
  73. };
  74. void __init pxa_set_mci_info(struct pxamci_platform_data *info)
  75. {
  76. pxa_register_device(&pxa_device_mci, info);
  77. }
  78. static struct pxa2xx_udc_mach_info pxa_udc_info = {
  79. .gpio_pullup = -1,
  80. };
  81. void __init pxa_set_udc_info(struct pxa2xx_udc_mach_info *info)
  82. {
  83. memcpy(&pxa_udc_info, info, sizeof *info);
  84. }
  85. static struct resource pxa2xx_udc_resources[] = {
  86. [0] = {
  87. .start = 0x40600000,
  88. .end = 0x4060ffff,
  89. .flags = IORESOURCE_MEM,
  90. },
  91. [1] = {
  92. .start = IRQ_USB,
  93. .end = IRQ_USB,
  94. .flags = IORESOURCE_IRQ,
  95. },
  96. };
  97. static u64 udc_dma_mask = ~(u32)0;
  98. struct platform_device pxa25x_device_udc = {
  99. .name = "pxa25x-udc",
  100. .id = -1,
  101. .resource = pxa2xx_udc_resources,
  102. .num_resources = ARRAY_SIZE(pxa2xx_udc_resources),
  103. .dev = {
  104. .platform_data = &pxa_udc_info,
  105. .dma_mask = &udc_dma_mask,
  106. }
  107. };
  108. struct platform_device pxa27x_device_udc = {
  109. .name = "pxa27x-udc",
  110. .id = -1,
  111. .resource = pxa2xx_udc_resources,
  112. .num_resources = ARRAY_SIZE(pxa2xx_udc_resources),
  113. .dev = {
  114. .platform_data = &pxa_udc_info,
  115. .dma_mask = &udc_dma_mask,
  116. }
  117. };
  118. #ifdef CONFIG_PXA3xx
  119. static struct resource pxa3xx_u2d_resources[] = {
  120. [0] = {
  121. .start = 0x54100000,
  122. .end = 0x54100fff,
  123. .flags = IORESOURCE_MEM,
  124. },
  125. [1] = {
  126. .start = IRQ_USB2,
  127. .end = IRQ_USB2,
  128. .flags = IORESOURCE_IRQ,
  129. },
  130. };
  131. struct platform_device pxa3xx_device_u2d = {
  132. .name = "pxa3xx-u2d",
  133. .id = -1,
  134. .resource = pxa3xx_u2d_resources,
  135. .num_resources = ARRAY_SIZE(pxa3xx_u2d_resources),
  136. };
  137. void __init pxa3xx_set_u2d_info(struct pxa3xx_u2d_platform_data *info)
  138. {
  139. pxa_register_device(&pxa3xx_device_u2d, info);
  140. }
  141. #endif /* CONFIG_PXA3xx */
  142. static struct resource pxafb_resources[] = {
  143. [0] = {
  144. .start = 0x44000000,
  145. .end = 0x4400ffff,
  146. .flags = IORESOURCE_MEM,
  147. },
  148. [1] = {
  149. .start = IRQ_LCD,
  150. .end = IRQ_LCD,
  151. .flags = IORESOURCE_IRQ,
  152. },
  153. };
  154. static u64 fb_dma_mask = ~(u64)0;
  155. struct platform_device pxa_device_fb = {
  156. .name = "pxa2xx-fb",
  157. .id = -1,
  158. .dev = {
  159. .dma_mask = &fb_dma_mask,
  160. .coherent_dma_mask = 0xffffffff,
  161. },
  162. .num_resources = ARRAY_SIZE(pxafb_resources),
  163. .resource = pxafb_resources,
  164. };
  165. void __init pxa_set_fb_info(struct device *parent, struct pxafb_mach_info *info)
  166. {
  167. pxa_device_fb.dev.parent = parent;
  168. pxa_register_device(&pxa_device_fb, info);
  169. }
  170. static struct resource pxa_resource_ffuart[] = {
  171. {
  172. .start = 0x40100000,
  173. .end = 0x40100023,
  174. .flags = IORESOURCE_MEM,
  175. }, {
  176. .start = IRQ_FFUART,
  177. .end = IRQ_FFUART,
  178. .flags = IORESOURCE_IRQ,
  179. }
  180. };
  181. struct platform_device pxa_device_ffuart = {
  182. .name = "pxa2xx-uart",
  183. .id = 0,
  184. .resource = pxa_resource_ffuart,
  185. .num_resources = ARRAY_SIZE(pxa_resource_ffuart),
  186. };
  187. void __init pxa_set_ffuart_info(void *info)
  188. {
  189. pxa_register_device(&pxa_device_ffuart, info);
  190. }
  191. static struct resource pxa_resource_btuart[] = {
  192. {
  193. .start = 0x40200000,
  194. .end = 0x40200023,
  195. .flags = IORESOURCE_MEM,
  196. }, {
  197. .start = IRQ_BTUART,
  198. .end = IRQ_BTUART,
  199. .flags = IORESOURCE_IRQ,
  200. }
  201. };
  202. struct platform_device pxa_device_btuart = {
  203. .name = "pxa2xx-uart",
  204. .id = 1,
  205. .resource = pxa_resource_btuart,
  206. .num_resources = ARRAY_SIZE(pxa_resource_btuart),
  207. };
  208. void __init pxa_set_btuart_info(void *info)
  209. {
  210. pxa_register_device(&pxa_device_btuart, info);
  211. }
  212. static struct resource pxa_resource_stuart[] = {
  213. {
  214. .start = 0x40700000,
  215. .end = 0x40700023,
  216. .flags = IORESOURCE_MEM,
  217. }, {
  218. .start = IRQ_STUART,
  219. .end = IRQ_STUART,
  220. .flags = IORESOURCE_IRQ,
  221. }
  222. };
  223. struct platform_device pxa_device_stuart = {
  224. .name = "pxa2xx-uart",
  225. .id = 2,
  226. .resource = pxa_resource_stuart,
  227. .num_resources = ARRAY_SIZE(pxa_resource_stuart),
  228. };
  229. void __init pxa_set_stuart_info(void *info)
  230. {
  231. pxa_register_device(&pxa_device_stuart, info);
  232. }
  233. static struct resource pxa_resource_hwuart[] = {
  234. {
  235. .start = 0x41600000,
  236. .end = 0x4160002F,
  237. .flags = IORESOURCE_MEM,
  238. }, {
  239. .start = IRQ_HWUART,
  240. .end = IRQ_HWUART,
  241. .flags = IORESOURCE_IRQ,
  242. }
  243. };
  244. struct platform_device pxa_device_hwuart = {
  245. .name = "pxa2xx-uart",
  246. .id = 3,
  247. .resource = pxa_resource_hwuart,
  248. .num_resources = ARRAY_SIZE(pxa_resource_hwuart),
  249. };
  250. void __init pxa_set_hwuart_info(void *info)
  251. {
  252. if (cpu_is_pxa255())
  253. pxa_register_device(&pxa_device_hwuart, info);
  254. else
  255. pr_info("UART: Ignoring attempt to register HWUART on non-PXA255 hardware");
  256. }
  257. static struct resource pxai2c_resources[] = {
  258. {
  259. .start = 0x40301680,
  260. .end = 0x403016a3,
  261. .flags = IORESOURCE_MEM,
  262. }, {
  263. .start = IRQ_I2C,
  264. .end = IRQ_I2C,
  265. .flags = IORESOURCE_IRQ,
  266. },
  267. };
  268. struct platform_device pxa_device_i2c = {
  269. .name = "pxa2xx-i2c",
  270. .id = 0,
  271. .resource = pxai2c_resources,
  272. .num_resources = ARRAY_SIZE(pxai2c_resources),
  273. };
  274. void __init pxa_set_i2c_info(struct i2c_pxa_platform_data *info)
  275. {
  276. pxa_register_device(&pxa_device_i2c, info);
  277. }
  278. #ifdef CONFIG_PXA27x
  279. static struct resource pxa27x_resources_i2c_power[] = {
  280. {
  281. .start = 0x40f00180,
  282. .end = 0x40f001a3,
  283. .flags = IORESOURCE_MEM,
  284. }, {
  285. .start = IRQ_PWRI2C,
  286. .end = IRQ_PWRI2C,
  287. .flags = IORESOURCE_IRQ,
  288. },
  289. };
  290. struct platform_device pxa27x_device_i2c_power = {
  291. .name = "pxa2xx-i2c",
  292. .id = 1,
  293. .resource = pxa27x_resources_i2c_power,
  294. .num_resources = ARRAY_SIZE(pxa27x_resources_i2c_power),
  295. };
  296. #endif
  297. static struct resource pxai2s_resources[] = {
  298. {
  299. .start = 0x40400000,
  300. .end = 0x40400083,
  301. .flags = IORESOURCE_MEM,
  302. }, {
  303. .start = IRQ_I2S,
  304. .end = IRQ_I2S,
  305. .flags = IORESOURCE_IRQ,
  306. },
  307. };
  308. struct platform_device pxa_device_i2s = {
  309. .name = "pxa2xx-i2s",
  310. .id = -1,
  311. .resource = pxai2s_resources,
  312. .num_resources = ARRAY_SIZE(pxai2s_resources),
  313. };
  314. struct platform_device pxa_device_asoc_ssp1 = {
  315. .name = "pxa-ssp-dai",
  316. .id = 0,
  317. };
  318. struct platform_device pxa_device_asoc_ssp2= {
  319. .name = "pxa-ssp-dai",
  320. .id = 1,
  321. };
  322. struct platform_device pxa_device_asoc_ssp3 = {
  323. .name = "pxa-ssp-dai",
  324. .id = 2,
  325. };
  326. struct platform_device pxa_device_asoc_ssp4 = {
  327. .name = "pxa-ssp-dai",
  328. .id = 3,
  329. };
  330. struct platform_device pxa_device_asoc_platform = {
  331. .name = "pxa-pcm-audio",
  332. .id = -1,
  333. };
  334. static u64 pxaficp_dmamask = ~(u32)0;
  335. struct platform_device pxa_device_ficp = {
  336. .name = "pxa2xx-ir",
  337. .id = -1,
  338. .dev = {
  339. .dma_mask = &pxaficp_dmamask,
  340. .coherent_dma_mask = 0xffffffff,
  341. },
  342. };
  343. void __init pxa_set_ficp_info(struct pxaficp_platform_data *info)
  344. {
  345. pxa_register_device(&pxa_device_ficp, info);
  346. }
  347. static struct resource pxa_rtc_resources[] = {
  348. [0] = {
  349. .start = 0x40900000,
  350. .end = 0x40900000 + 0x3b,
  351. .flags = IORESOURCE_MEM,
  352. },
  353. [1] = {
  354. .start = IRQ_RTC1Hz,
  355. .end = IRQ_RTC1Hz,
  356. .flags = IORESOURCE_IRQ,
  357. },
  358. [2] = {
  359. .start = IRQ_RTCAlrm,
  360. .end = IRQ_RTCAlrm,
  361. .flags = IORESOURCE_IRQ,
  362. },
  363. };
  364. struct platform_device sa1100_device_rtc = {
  365. .name = "sa1100-rtc",
  366. .id = -1,
  367. };
  368. struct platform_device pxa_device_rtc = {
  369. .name = "pxa-rtc",
  370. .id = -1,
  371. .num_resources = ARRAY_SIZE(pxa_rtc_resources),
  372. .resource = pxa_rtc_resources,
  373. };
  374. static struct resource pxa_ac97_resources[] = {
  375. [0] = {
  376. .start = 0x40500000,
  377. .end = 0x40500000 + 0xfff,
  378. .flags = IORESOURCE_MEM,
  379. },
  380. [1] = {
  381. .start = IRQ_AC97,
  382. .end = IRQ_AC97,
  383. .flags = IORESOURCE_IRQ,
  384. },
  385. };
  386. static u64 pxa_ac97_dmamask = 0xffffffffUL;
  387. struct platform_device pxa_device_ac97 = {
  388. .name = "pxa2xx-ac97",
  389. .id = -1,
  390. .dev = {
  391. .dma_mask = &pxa_ac97_dmamask,
  392. .coherent_dma_mask = 0xffffffff,
  393. },
  394. .num_resources = ARRAY_SIZE(pxa_ac97_resources),
  395. .resource = pxa_ac97_resources,
  396. };
  397. void __init pxa_set_ac97_info(pxa2xx_audio_ops_t *ops)
  398. {
  399. pxa_register_device(&pxa_device_ac97, ops);
  400. }
  401. #ifdef CONFIG_PXA25x
  402. static struct resource pxa25x_resource_pwm0[] = {
  403. [0] = {
  404. .start = 0x40b00000,
  405. .end = 0x40b0000f,
  406. .flags = IORESOURCE_MEM,
  407. },
  408. };
  409. struct platform_device pxa25x_device_pwm0 = {
  410. .name = "pxa25x-pwm",
  411. .id = 0,
  412. .resource = pxa25x_resource_pwm0,
  413. .num_resources = ARRAY_SIZE(pxa25x_resource_pwm0),
  414. };
  415. static struct resource pxa25x_resource_pwm1[] = {
  416. [0] = {
  417. .start = 0x40c00000,
  418. .end = 0x40c0000f,
  419. .flags = IORESOURCE_MEM,
  420. },
  421. };
  422. struct platform_device pxa25x_device_pwm1 = {
  423. .name = "pxa25x-pwm",
  424. .id = 1,
  425. .resource = pxa25x_resource_pwm1,
  426. .num_resources = ARRAY_SIZE(pxa25x_resource_pwm1),
  427. };
  428. static u64 pxa25x_ssp_dma_mask = DMA_BIT_MASK(32);
  429. static struct resource pxa25x_resource_ssp[] = {
  430. [0] = {
  431. .start = 0x41000000,
  432. .end = 0x4100001f,
  433. .flags = IORESOURCE_MEM,
  434. },
  435. [1] = {
  436. .start = IRQ_SSP,
  437. .end = IRQ_SSP,
  438. .flags = IORESOURCE_IRQ,
  439. },
  440. [2] = {
  441. /* DRCMR for RX */
  442. .start = 13,
  443. .end = 13,
  444. .flags = IORESOURCE_DMA,
  445. },
  446. [3] = {
  447. /* DRCMR for TX */
  448. .start = 14,
  449. .end = 14,
  450. .flags = IORESOURCE_DMA,
  451. },
  452. };
  453. struct platform_device pxa25x_device_ssp = {
  454. .name = "pxa25x-ssp",
  455. .id = 0,
  456. .dev = {
  457. .dma_mask = &pxa25x_ssp_dma_mask,
  458. .coherent_dma_mask = DMA_BIT_MASK(32),
  459. },
  460. .resource = pxa25x_resource_ssp,
  461. .num_resources = ARRAY_SIZE(pxa25x_resource_ssp),
  462. };
  463. static u64 pxa25x_nssp_dma_mask = DMA_BIT_MASK(32);
  464. static struct resource pxa25x_resource_nssp[] = {
  465. [0] = {
  466. .start = 0x41400000,
  467. .end = 0x4140002f,
  468. .flags = IORESOURCE_MEM,
  469. },
  470. [1] = {
  471. .start = IRQ_NSSP,
  472. .end = IRQ_NSSP,
  473. .flags = IORESOURCE_IRQ,
  474. },
  475. [2] = {
  476. /* DRCMR for RX */
  477. .start = 15,
  478. .end = 15,
  479. .flags = IORESOURCE_DMA,
  480. },
  481. [3] = {
  482. /* DRCMR for TX */
  483. .start = 16,
  484. .end = 16,
  485. .flags = IORESOURCE_DMA,
  486. },
  487. };
  488. struct platform_device pxa25x_device_nssp = {
  489. .name = "pxa25x-nssp",
  490. .id = 1,
  491. .dev = {
  492. .dma_mask = &pxa25x_nssp_dma_mask,
  493. .coherent_dma_mask = DMA_BIT_MASK(32),
  494. },
  495. .resource = pxa25x_resource_nssp,
  496. .num_resources = ARRAY_SIZE(pxa25x_resource_nssp),
  497. };
  498. static u64 pxa25x_assp_dma_mask = DMA_BIT_MASK(32);
  499. static struct resource pxa25x_resource_assp[] = {
  500. [0] = {
  501. .start = 0x41500000,
  502. .end = 0x4150002f,
  503. .flags = IORESOURCE_MEM,
  504. },
  505. [1] = {
  506. .start = IRQ_ASSP,
  507. .end = IRQ_ASSP,
  508. .flags = IORESOURCE_IRQ,
  509. },
  510. [2] = {
  511. /* DRCMR for RX */
  512. .start = 23,
  513. .end = 23,
  514. .flags = IORESOURCE_DMA,
  515. },
  516. [3] = {
  517. /* DRCMR for TX */
  518. .start = 24,
  519. .end = 24,
  520. .flags = IORESOURCE_DMA,
  521. },
  522. };
  523. struct platform_device pxa25x_device_assp = {
  524. /* ASSP is basically equivalent to NSSP */
  525. .name = "pxa25x-nssp",
  526. .id = 2,
  527. .dev = {
  528. .dma_mask = &pxa25x_assp_dma_mask,
  529. .coherent_dma_mask = DMA_BIT_MASK(32),
  530. },
  531. .resource = pxa25x_resource_assp,
  532. .num_resources = ARRAY_SIZE(pxa25x_resource_assp),
  533. };
  534. #endif /* CONFIG_PXA25x */
  535. #if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
  536. static struct resource pxa27x_resource_camera[] = {
  537. [0] = {
  538. .start = 0x50000000,
  539. .end = 0x50000fff,
  540. .flags = IORESOURCE_MEM,
  541. },
  542. [1] = {
  543. .start = IRQ_CAMERA,
  544. .end = IRQ_CAMERA,
  545. .flags = IORESOURCE_IRQ,
  546. },
  547. };
  548. static u64 pxa27x_dma_mask_camera = DMA_BIT_MASK(32);
  549. static struct platform_device pxa27x_device_camera = {
  550. .name = "pxa27x-camera",
  551. .id = 0, /* This is used to put cameras on this interface */
  552. .dev = {
  553. .dma_mask = &pxa27x_dma_mask_camera,
  554. .coherent_dma_mask = 0xffffffff,
  555. },
  556. .num_resources = ARRAY_SIZE(pxa27x_resource_camera),
  557. .resource = pxa27x_resource_camera,
  558. };
  559. void __init pxa_set_camera_info(struct pxacamera_platform_data *info)
  560. {
  561. pxa_register_device(&pxa27x_device_camera, info);
  562. }
  563. static u64 pxa27x_ohci_dma_mask = DMA_BIT_MASK(32);
  564. static struct resource pxa27x_resource_ohci[] = {
  565. [0] = {
  566. .start = 0x4C000000,
  567. .end = 0x4C00ff6f,
  568. .flags = IORESOURCE_MEM,
  569. },
  570. [1] = {
  571. .start = IRQ_USBH1,
  572. .end = IRQ_USBH1,
  573. .flags = IORESOURCE_IRQ,
  574. },
  575. };
  576. struct platform_device pxa27x_device_ohci = {
  577. .name = "pxa27x-ohci",
  578. .id = -1,
  579. .dev = {
  580. .dma_mask = &pxa27x_ohci_dma_mask,
  581. .coherent_dma_mask = DMA_BIT_MASK(32),
  582. },
  583. .num_resources = ARRAY_SIZE(pxa27x_resource_ohci),
  584. .resource = pxa27x_resource_ohci,
  585. };
  586. void __init pxa_set_ohci_info(struct pxaohci_platform_data *info)
  587. {
  588. pxa_register_device(&pxa27x_device_ohci, info);
  589. }
  590. #endif /* CONFIG_PXA27x || CONFIG_PXA3xx */
  591. #if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx) || defined(CONFIG_PXA95x)
  592. static struct resource pxa27x_resource_keypad[] = {
  593. [0] = {
  594. .start = 0x41500000,
  595. .end = 0x4150004c,
  596. .flags = IORESOURCE_MEM,
  597. },
  598. [1] = {
  599. .start = IRQ_KEYPAD,
  600. .end = IRQ_KEYPAD,
  601. .flags = IORESOURCE_IRQ,
  602. },
  603. };
  604. struct platform_device pxa27x_device_keypad = {
  605. .name = "pxa27x-keypad",
  606. .id = -1,
  607. .resource = pxa27x_resource_keypad,
  608. .num_resources = ARRAY_SIZE(pxa27x_resource_keypad),
  609. };
  610. void __init pxa_set_keypad_info(struct pxa27x_keypad_platform_data *info)
  611. {
  612. pxa_register_device(&pxa27x_device_keypad, info);
  613. }
  614. static u64 pxa27x_ssp1_dma_mask = DMA_BIT_MASK(32);
  615. static struct resource pxa27x_resource_ssp1[] = {
  616. [0] = {
  617. .start = 0x41000000,
  618. .end = 0x4100003f,
  619. .flags = IORESOURCE_MEM,
  620. },
  621. [1] = {
  622. .start = IRQ_SSP,
  623. .end = IRQ_SSP,
  624. .flags = IORESOURCE_IRQ,
  625. },
  626. [2] = {
  627. /* DRCMR for RX */
  628. .start = 13,
  629. .end = 13,
  630. .flags = IORESOURCE_DMA,
  631. },
  632. [3] = {
  633. /* DRCMR for TX */
  634. .start = 14,
  635. .end = 14,
  636. .flags = IORESOURCE_DMA,
  637. },
  638. };
  639. struct platform_device pxa27x_device_ssp1 = {
  640. .name = "pxa27x-ssp",
  641. .id = 0,
  642. .dev = {
  643. .dma_mask = &pxa27x_ssp1_dma_mask,
  644. .coherent_dma_mask = DMA_BIT_MASK(32),
  645. },
  646. .resource = pxa27x_resource_ssp1,
  647. .num_resources = ARRAY_SIZE(pxa27x_resource_ssp1),
  648. };
  649. static u64 pxa27x_ssp2_dma_mask = DMA_BIT_MASK(32);
  650. static struct resource pxa27x_resource_ssp2[] = {
  651. [0] = {
  652. .start = 0x41700000,
  653. .end = 0x4170003f,
  654. .flags = IORESOURCE_MEM,
  655. },
  656. [1] = {
  657. .start = IRQ_SSP2,
  658. .end = IRQ_SSP2,
  659. .flags = IORESOURCE_IRQ,
  660. },
  661. [2] = {
  662. /* DRCMR for RX */
  663. .start = 15,
  664. .end = 15,
  665. .flags = IORESOURCE_DMA,
  666. },
  667. [3] = {
  668. /* DRCMR for TX */
  669. .start = 16,
  670. .end = 16,
  671. .flags = IORESOURCE_DMA,
  672. },
  673. };
  674. struct platform_device pxa27x_device_ssp2 = {
  675. .name = "pxa27x-ssp",
  676. .id = 1,
  677. .dev = {
  678. .dma_mask = &pxa27x_ssp2_dma_mask,
  679. .coherent_dma_mask = DMA_BIT_MASK(32),
  680. },
  681. .resource = pxa27x_resource_ssp2,
  682. .num_resources = ARRAY_SIZE(pxa27x_resource_ssp2),
  683. };
  684. static u64 pxa27x_ssp3_dma_mask = DMA_BIT_MASK(32);
  685. static struct resource pxa27x_resource_ssp3[] = {
  686. [0] = {
  687. .start = 0x41900000,
  688. .end = 0x4190003f,
  689. .flags = IORESOURCE_MEM,
  690. },
  691. [1] = {
  692. .start = IRQ_SSP3,
  693. .end = IRQ_SSP3,
  694. .flags = IORESOURCE_IRQ,
  695. },
  696. [2] = {
  697. /* DRCMR for RX */
  698. .start = 66,
  699. .end = 66,
  700. .flags = IORESOURCE_DMA,
  701. },
  702. [3] = {
  703. /* DRCMR for TX */
  704. .start = 67,
  705. .end = 67,
  706. .flags = IORESOURCE_DMA,
  707. },
  708. };
  709. struct platform_device pxa27x_device_ssp3 = {
  710. .name = "pxa27x-ssp",
  711. .id = 2,
  712. .dev = {
  713. .dma_mask = &pxa27x_ssp3_dma_mask,
  714. .coherent_dma_mask = DMA_BIT_MASK(32),
  715. },
  716. .resource = pxa27x_resource_ssp3,
  717. .num_resources = ARRAY_SIZE(pxa27x_resource_ssp3),
  718. };
  719. static struct resource pxa27x_resource_pwm0[] = {
  720. [0] = {
  721. .start = 0x40b00000,
  722. .end = 0x40b0001f,
  723. .flags = IORESOURCE_MEM,
  724. },
  725. };
  726. struct platform_device pxa27x_device_pwm0 = {
  727. .name = "pxa27x-pwm",
  728. .id = 0,
  729. .resource = pxa27x_resource_pwm0,
  730. .num_resources = ARRAY_SIZE(pxa27x_resource_pwm0),
  731. };
  732. static struct resource pxa27x_resource_pwm1[] = {
  733. [0] = {
  734. .start = 0x40c00000,
  735. .end = 0x40c0001f,
  736. .flags = IORESOURCE_MEM,
  737. },
  738. };
  739. struct platform_device pxa27x_device_pwm1 = {
  740. .name = "pxa27x-pwm",
  741. .id = 1,
  742. .resource = pxa27x_resource_pwm1,
  743. .num_resources = ARRAY_SIZE(pxa27x_resource_pwm1),
  744. };
  745. #endif /* CONFIG_PXA27x || CONFIG_PXA3xx || CONFIG_PXA95x*/
  746. #ifdef CONFIG_PXA3xx
  747. static struct resource pxa3xx_resources_mci2[] = {
  748. [0] = {
  749. .start = 0x42000000,
  750. .end = 0x42000fff,
  751. .flags = IORESOURCE_MEM,
  752. },
  753. [1] = {
  754. .start = IRQ_MMC2,
  755. .end = IRQ_MMC2,
  756. .flags = IORESOURCE_IRQ,
  757. },
  758. [2] = {
  759. .start = 93,
  760. .end = 93,
  761. .flags = IORESOURCE_DMA,
  762. },
  763. [3] = {
  764. .start = 94,
  765. .end = 94,
  766. .flags = IORESOURCE_DMA,
  767. },
  768. };
  769. struct platform_device pxa3xx_device_mci2 = {
  770. .name = "pxa2xx-mci",
  771. .id = 1,
  772. .dev = {
  773. .dma_mask = &pxamci_dmamask,
  774. .coherent_dma_mask = 0xffffffff,
  775. },
  776. .num_resources = ARRAY_SIZE(pxa3xx_resources_mci2),
  777. .resource = pxa3xx_resources_mci2,
  778. };
  779. void __init pxa3xx_set_mci2_info(struct pxamci_platform_data *info)
  780. {
  781. pxa_register_device(&pxa3xx_device_mci2, info);
  782. }
  783. static struct resource pxa3xx_resources_mci3[] = {
  784. [0] = {
  785. .start = 0x42500000,
  786. .end = 0x42500fff,
  787. .flags = IORESOURCE_MEM,
  788. },
  789. [1] = {
  790. .start = IRQ_MMC3,
  791. .end = IRQ_MMC3,
  792. .flags = IORESOURCE_IRQ,
  793. },
  794. [2] = {
  795. .start = 100,
  796. .end = 100,
  797. .flags = IORESOURCE_DMA,
  798. },
  799. [3] = {
  800. .start = 101,
  801. .end = 101,
  802. .flags = IORESOURCE_DMA,
  803. },
  804. };
  805. struct platform_device pxa3xx_device_mci3 = {
  806. .name = "pxa2xx-mci",
  807. .id = 2,
  808. .dev = {
  809. .dma_mask = &pxamci_dmamask,
  810. .coherent_dma_mask = 0xffffffff,
  811. },
  812. .num_resources = ARRAY_SIZE(pxa3xx_resources_mci3),
  813. .resource = pxa3xx_resources_mci3,
  814. };
  815. void __init pxa3xx_set_mci3_info(struct pxamci_platform_data *info)
  816. {
  817. pxa_register_device(&pxa3xx_device_mci3, info);
  818. }
  819. static struct resource pxa3xx_resources_gcu[] = {
  820. {
  821. .start = 0x54000000,
  822. .end = 0x54000fff,
  823. .flags = IORESOURCE_MEM,
  824. },
  825. {
  826. .start = IRQ_GCU,
  827. .end = IRQ_GCU,
  828. .flags = IORESOURCE_IRQ,
  829. },
  830. };
  831. static u64 pxa3xx_gcu_dmamask = DMA_BIT_MASK(32);
  832. struct platform_device pxa3xx_device_gcu = {
  833. .name = "pxa3xx-gcu",
  834. .id = -1,
  835. .num_resources = ARRAY_SIZE(pxa3xx_resources_gcu),
  836. .resource = pxa3xx_resources_gcu,
  837. .dev = {
  838. .dma_mask = &pxa3xx_gcu_dmamask,
  839. .coherent_dma_mask = 0xffffffff,
  840. },
  841. };
  842. #endif /* CONFIG_PXA3xx */
  843. #if defined(CONFIG_PXA3xx) || defined(CONFIG_PXA95x)
  844. static struct resource pxa3xx_resources_i2c_power[] = {
  845. {
  846. .start = 0x40f500c0,
  847. .end = 0x40f500d3,
  848. .flags = IORESOURCE_MEM,
  849. }, {
  850. .start = IRQ_PWRI2C,
  851. .end = IRQ_PWRI2C,
  852. .flags = IORESOURCE_IRQ,
  853. },
  854. };
  855. struct platform_device pxa3xx_device_i2c_power = {
  856. .name = "pxa3xx-pwri2c",
  857. .id = 1,
  858. .resource = pxa3xx_resources_i2c_power,
  859. .num_resources = ARRAY_SIZE(pxa3xx_resources_i2c_power),
  860. };
  861. static struct resource pxa3xx_resources_nand[] = {
  862. [0] = {
  863. .start = 0x43100000,
  864. .end = 0x43100053,
  865. .flags = IORESOURCE_MEM,
  866. },
  867. [1] = {
  868. .start = IRQ_NAND,
  869. .end = IRQ_NAND,
  870. .flags = IORESOURCE_IRQ,
  871. },
  872. [2] = {
  873. /* DRCMR for Data DMA */
  874. .start = 97,
  875. .end = 97,
  876. .flags = IORESOURCE_DMA,
  877. },
  878. [3] = {
  879. /* DRCMR for Command DMA */
  880. .start = 99,
  881. .end = 99,
  882. .flags = IORESOURCE_DMA,
  883. },
  884. };
  885. static u64 pxa3xx_nand_dma_mask = DMA_BIT_MASK(32);
  886. struct platform_device pxa3xx_device_nand = {
  887. .name = "pxa3xx-nand",
  888. .id = -1,
  889. .dev = {
  890. .dma_mask = &pxa3xx_nand_dma_mask,
  891. .coherent_dma_mask = DMA_BIT_MASK(32),
  892. },
  893. .num_resources = ARRAY_SIZE(pxa3xx_resources_nand),
  894. .resource = pxa3xx_resources_nand,
  895. };
  896. void __init pxa3xx_set_nand_info(struct pxa3xx_nand_platform_data *info)
  897. {
  898. pxa_register_device(&pxa3xx_device_nand, info);
  899. }
  900. static u64 pxa3xx_ssp4_dma_mask = DMA_BIT_MASK(32);
  901. static struct resource pxa3xx_resource_ssp4[] = {
  902. [0] = {
  903. .start = 0x41a00000,
  904. .end = 0x41a0003f,
  905. .flags = IORESOURCE_MEM,
  906. },
  907. [1] = {
  908. .start = IRQ_SSP4,
  909. .end = IRQ_SSP4,
  910. .flags = IORESOURCE_IRQ,
  911. },
  912. [2] = {
  913. /* DRCMR for RX */
  914. .start = 2,
  915. .end = 2,
  916. .flags = IORESOURCE_DMA,
  917. },
  918. [3] = {
  919. /* DRCMR for TX */
  920. .start = 3,
  921. .end = 3,
  922. .flags = IORESOURCE_DMA,
  923. },
  924. };
  925. struct platform_device pxa3xx_device_ssp4 = {
  926. /* PXA3xx SSP is basically equivalent to PXA27x */
  927. .name = "pxa27x-ssp",
  928. .id = 3,
  929. .dev = {
  930. .dma_mask = &pxa3xx_ssp4_dma_mask,
  931. .coherent_dma_mask = DMA_BIT_MASK(32),
  932. },
  933. .resource = pxa3xx_resource_ssp4,
  934. .num_resources = ARRAY_SIZE(pxa3xx_resource_ssp4),
  935. };
  936. #endif /* CONFIG_PXA3xx || CONFIG_PXA95x */
  937. /* pxa2xx-spi platform-device ID equals respective SSP platform-device ID + 1.
  938. * See comment in arch/arm/mach-pxa/ssp.c::ssp_probe() */
  939. void __init pxa2xx_set_spi_info(unsigned id, struct pxa2xx_spi_master *info)
  940. {
  941. struct platform_device *pd;
  942. pd = platform_device_alloc("pxa2xx-spi", id);
  943. if (pd == NULL) {
  944. printk(KERN_ERR "pxa2xx-spi: failed to allocate device id %d\n",
  945. id);
  946. return;
  947. }
  948. pd->dev.platform_data = info;
  949. platform_device_add(pd);
  950. }