rstc.c 1.6 KB

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  1. /*
  2. * reset controller for CSR SiRFprimaII
  3. *
  4. * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
  5. *
  6. * Licensed under GPLv2 or later.
  7. */
  8. #include <linux/kernel.h>
  9. #include <linux/mutex.h>
  10. #include <linux/io.h>
  11. #include <linux/delay.h>
  12. #include <linux/device.h>
  13. #include <linux/of.h>
  14. #include <linux/of_address.h>
  15. void __iomem *sirfsoc_rstc_base;
  16. static DEFINE_MUTEX(rstc_lock);
  17. static struct of_device_id rstc_ids[] = {
  18. { .compatible = "sirf,prima2-rstc" },
  19. };
  20. static int __init sirfsoc_of_rstc_init(void)
  21. {
  22. struct device_node *np;
  23. np = of_find_matching_node(NULL, rstc_ids);
  24. if (!np)
  25. panic("unable to find compatible rstc node in dtb\n");
  26. sirfsoc_rstc_base = of_iomap(np, 0);
  27. if (!sirfsoc_rstc_base)
  28. panic("unable to map rstc cpu registers\n");
  29. of_node_put(np);
  30. return 0;
  31. }
  32. early_initcall(sirfsoc_of_rstc_init);
  33. int sirfsoc_reset_device(struct device *dev)
  34. {
  35. const unsigned int *prop = of_get_property(dev->of_node, "reset-bit", NULL);
  36. unsigned int reset_bit;
  37. if (!prop)
  38. return -ENODEV;
  39. reset_bit = be32_to_cpup(prop);
  40. mutex_lock(&rstc_lock);
  41. /*
  42. * Writing 1 to this bit resets corresponding block. Writing 0 to this
  43. * bit de-asserts reset signal of the corresponding block.
  44. * datasheet doesn't require explicit delay between the set and clear
  45. * of reset bit. it could be shorter if tests pass.
  46. */
  47. writel(readl(sirfsoc_rstc_base + (reset_bit / 32) * 4) | reset_bit,
  48. sirfsoc_rstc_base + (reset_bit / 32) * 4);
  49. msleep(10);
  50. writel(readl(sirfsoc_rstc_base + (reset_bit / 32) * 4) & ~reset_bit,
  51. sirfsoc_rstc_base + (reset_bit / 32) * 4);
  52. mutex_unlock(&rstc_lock);
  53. return 0;
  54. }