pmu.c 4.9 KB

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  1. /* linux/arch/arm/mach-exynos4/pmu.c
  2. *
  3. * Copyright (c) 2011 Samsung Electronics Co., Ltd.
  4. * http://www.samsung.com/
  5. *
  6. * EXYNOS4210 - CPU PMU(Power Management Unit) support
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License version 2 as
  10. * published by the Free Software Foundation.
  11. */
  12. #include <linux/io.h>
  13. #include <linux/kernel.h>
  14. #include <mach/regs-clock.h>
  15. #include <mach/pmu.h>
  16. static void __iomem *sys_powerdown_reg[] = {
  17. S5P_ARM_CORE0_LOWPWR,
  18. S5P_DIS_IRQ_CORE0,
  19. S5P_DIS_IRQ_CENTRAL0,
  20. S5P_ARM_CORE1_LOWPWR,
  21. S5P_DIS_IRQ_CORE1,
  22. S5P_DIS_IRQ_CENTRAL1,
  23. S5P_ARM_COMMON_LOWPWR,
  24. S5P_L2_0_LOWPWR,
  25. S5P_L2_1_LOWPWR,
  26. S5P_CMU_ACLKSTOP_LOWPWR,
  27. S5P_CMU_SCLKSTOP_LOWPWR,
  28. S5P_CMU_RESET_LOWPWR,
  29. S5P_APLL_SYSCLK_LOWPWR,
  30. S5P_MPLL_SYSCLK_LOWPWR,
  31. S5P_VPLL_SYSCLK_LOWPWR,
  32. S5P_EPLL_SYSCLK_LOWPWR,
  33. S5P_CMU_CLKSTOP_GPS_ALIVE_LOWPWR,
  34. S5P_CMU_RESET_GPSALIVE_LOWPWR,
  35. S5P_CMU_CLKSTOP_CAM_LOWPWR,
  36. S5P_CMU_CLKSTOP_TV_LOWPWR,
  37. S5P_CMU_CLKSTOP_MFC_LOWPWR,
  38. S5P_CMU_CLKSTOP_G3D_LOWPWR,
  39. S5P_CMU_CLKSTOP_LCD0_LOWPWR,
  40. S5P_CMU_CLKSTOP_LCD1_LOWPWR,
  41. S5P_CMU_CLKSTOP_MAUDIO_LOWPWR,
  42. S5P_CMU_CLKSTOP_GPS_LOWPWR,
  43. S5P_CMU_RESET_CAM_LOWPWR,
  44. S5P_CMU_RESET_TV_LOWPWR,
  45. S5P_CMU_RESET_MFC_LOWPWR,
  46. S5P_CMU_RESET_G3D_LOWPWR,
  47. S5P_CMU_RESET_LCD0_LOWPWR,
  48. S5P_CMU_RESET_LCD1_LOWPWR,
  49. S5P_CMU_RESET_MAUDIO_LOWPWR,
  50. S5P_CMU_RESET_GPS_LOWPWR,
  51. S5P_TOP_BUS_LOWPWR,
  52. S5P_TOP_RETENTION_LOWPWR,
  53. S5P_TOP_PWR_LOWPWR,
  54. S5P_LOGIC_RESET_LOWPWR,
  55. S5P_ONENAND_MEM_LOWPWR,
  56. S5P_MODIMIF_MEM_LOWPWR,
  57. S5P_G2D_ACP_MEM_LOWPWR,
  58. S5P_USBOTG_MEM_LOWPWR,
  59. S5P_HSMMC_MEM_LOWPWR,
  60. S5P_CSSYS_MEM_LOWPWR,
  61. S5P_SECSS_MEM_LOWPWR,
  62. S5P_PCIE_MEM_LOWPWR,
  63. S5P_SATA_MEM_LOWPWR,
  64. S5P_PAD_RETENTION_DRAM_LOWPWR,
  65. S5P_PAD_RETENTION_MAUDIO_LOWPWR,
  66. S5P_PAD_RETENTION_GPIO_LOWPWR,
  67. S5P_PAD_RETENTION_UART_LOWPWR,
  68. S5P_PAD_RETENTION_MMCA_LOWPWR,
  69. S5P_PAD_RETENTION_MMCB_LOWPWR,
  70. S5P_PAD_RETENTION_EBIA_LOWPWR,
  71. S5P_PAD_RETENTION_EBIB_LOWPWR,
  72. S5P_PAD_RETENTION_ISOLATION_LOWPWR,
  73. S5P_PAD_RETENTION_ALV_SEL_LOWPWR,
  74. S5P_XUSBXTI_LOWPWR,
  75. S5P_XXTI_LOWPWR,
  76. S5P_EXT_REGULATOR_LOWPWR,
  77. S5P_GPIO_MODE_LOWPWR,
  78. S5P_GPIO_MODE_MAUDIO_LOWPWR,
  79. S5P_CAM_LOWPWR,
  80. S5P_TV_LOWPWR,
  81. S5P_MFC_LOWPWR,
  82. S5P_G3D_LOWPWR,
  83. S5P_LCD0_LOWPWR,
  84. S5P_LCD1_LOWPWR,
  85. S5P_MAUDIO_LOWPWR,
  86. S5P_GPS_LOWPWR,
  87. S5P_GPS_ALIVE_LOWPWR,
  88. };
  89. static const unsigned int sys_powerdown_val[][NUM_SYS_POWERDOWN] = {
  90. /* { AFTR, LPA, SLEEP }*/
  91. { 0, 0, 2 }, /* ARM_CORE0 */
  92. { 0, 0, 0 }, /* ARM_DIS_IRQ_CORE0 */
  93. { 0, 0, 0 }, /* ARM_DIS_IRQ_CENTRAL0 */
  94. { 0, 0, 2 }, /* ARM_CORE1 */
  95. { 0, 0, 0 }, /* ARM_DIS_IRQ_CORE1 */
  96. { 0, 0, 0 }, /* ARM_DIS_IRQ_CENTRAL1 */
  97. { 0, 0, 2 }, /* ARM_COMMON */
  98. { 2, 2, 3 }, /* ARM_CPU_L2_0 */
  99. { 2, 2, 3 }, /* ARM_CPU_L2_1 */
  100. { 1, 0, 0 }, /* CMU_ACLKSTOP */
  101. { 1, 0, 0 }, /* CMU_SCLKSTOP */
  102. { 1, 1, 0 }, /* CMU_RESET */
  103. { 1, 0, 0 }, /* APLL_SYSCLK */
  104. { 1, 0, 0 }, /* MPLL_SYSCLK */
  105. { 1, 0, 0 }, /* VPLL_SYSCLK */
  106. { 1, 1, 0 }, /* EPLL_SYSCLK */
  107. { 1, 1, 0 }, /* CMU_CLKSTOP_GPS_ALIVE */
  108. { 1, 1, 0 }, /* CMU_RESET_GPS_ALIVE */
  109. { 1, 1, 0 }, /* CMU_CLKSTOP_CAM */
  110. { 1, 1, 0 }, /* CMU_CLKSTOP_TV */
  111. { 1, 1, 0 }, /* CMU_CLKSTOP_MFC */
  112. { 1, 1, 0 }, /* CMU_CLKSTOP_G3D */
  113. { 1, 1, 0 }, /* CMU_CLKSTOP_LCD0 */
  114. { 1, 1, 0 }, /* CMU_CLKSTOP_LCD1 */
  115. { 1, 1, 0 }, /* CMU_CLKSTOP_MAUDIO */
  116. { 1, 1, 0 }, /* CMU_CLKSTOP_GPS */
  117. { 1, 1, 0 }, /* CMU_RESET_CAM */
  118. { 1, 1, 0 }, /* CMU_RESET_TV */
  119. { 1, 1, 0 }, /* CMU_RESET_MFC */
  120. { 1, 1, 0 }, /* CMU_RESET_G3D */
  121. { 1, 1, 0 }, /* CMU_RESET_LCD0 */
  122. { 1, 1, 0 }, /* CMU_RESET_LCD1 */
  123. { 1, 1, 0 }, /* CMU_RESET_MAUDIO */
  124. { 1, 1, 0 }, /* CMU_RESET_GPS */
  125. { 3, 0, 0 }, /* TOP_BUS */
  126. { 1, 0, 1 }, /* TOP_RETENTION */
  127. { 3, 0, 3 }, /* TOP_PWR */
  128. { 1, 1, 0 }, /* LOGIC_RESET */
  129. { 3, 0, 0 }, /* ONENAND_MEM */
  130. { 3, 0, 0 }, /* MODIMIF_MEM */
  131. { 3, 0, 0 }, /* G2D_ACP_MEM */
  132. { 3, 0, 0 }, /* USBOTG_MEM */
  133. { 3, 0, 0 }, /* HSMMC_MEM */
  134. { 3, 0, 0 }, /* CSSYS_MEM */
  135. { 3, 0, 0 }, /* SECSS_MEM */
  136. { 3, 0, 0 }, /* PCIE_MEM */
  137. { 3, 0, 0 }, /* SATA_MEM */
  138. { 1, 0, 0 }, /* PAD_RETENTION_DRAM */
  139. { 1, 1, 0 }, /* PAD_RETENTION_MAUDIO */
  140. { 1, 0, 0 }, /* PAD_RETENTION_GPIO */
  141. { 1, 0, 0 }, /* PAD_RETENTION_UART */
  142. { 1, 0, 0 }, /* PAD_RETENTION_MMCA */
  143. { 1, 0, 0 }, /* PAD_RETENTION_MMCB */
  144. { 1, 0, 0 }, /* PAD_RETENTION_EBIA */
  145. { 1, 0, 0 }, /* PAD_RETENTION_EBIB */
  146. { 1, 0, 0 }, /* PAD_RETENTION_ISOLATION */
  147. { 1, 0, 0 }, /* PAD_RETENTION_ALV_SEL */
  148. { 1, 1, 0 }, /* XUSBXTI */
  149. { 1, 1, 0 }, /* XXTI */
  150. { 1, 1, 0 }, /* EXT_REGULATOR */
  151. { 1, 0, 0 }, /* GPIO_MODE */
  152. { 1, 1, 0 }, /* GPIO_MODE_MAUDIO */
  153. { 7, 0, 0 }, /* CAM */
  154. { 7, 0, 0 }, /* TV */
  155. { 7, 0, 0 }, /* MFC */
  156. { 7, 0, 0 }, /* G3D */
  157. { 7, 0, 0 }, /* LCD0 */
  158. { 7, 0, 0 }, /* LCD1 */
  159. { 7, 7, 0 }, /* MAUDIO */
  160. { 7, 0, 0 }, /* GPS */
  161. { 7, 0, 0 }, /* GPS_ALIVE */
  162. };
  163. void exynos4_sys_powerdown_conf(enum sys_powerdown mode)
  164. {
  165. unsigned int count = ARRAY_SIZE(sys_powerdown_reg);
  166. for (; count > 0; count--)
  167. __raw_writel(sys_powerdown_val[count - 1][mode],
  168. sys_powerdown_reg[count - 1]);
  169. }