dma.c 4.2 KB

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  1. /* linux/arch/arm/mach-exynos4/dma.c
  2. *
  3. * Copyright (c) 2011 Samsung Electronics Co., Ltd.
  4. * http://www.samsung.com
  5. *
  6. * Copyright (C) 2010 Samsung Electronics Co. Ltd.
  7. * Jaswinder Singh <jassi.brar@samsung.com>
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License as published by
  11. * the Free Software Foundation; either version 2 of the License, or
  12. * (at your option) any later version.
  13. *
  14. * This program is distributed in the hope that it will be useful,
  15. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17. * GNU General Public License for more details.
  18. *
  19. * You should have received a copy of the GNU General Public License
  20. * along with this program; if not, write to the Free Software
  21. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  22. */
  23. #include <linux/platform_device.h>
  24. #include <linux/dma-mapping.h>
  25. #include <plat/devs.h>
  26. #include <plat/irqs.h>
  27. #include <mach/map.h>
  28. #include <mach/irqs.h>
  29. #include <plat/s3c-pl330-pdata.h>
  30. static u64 dma_dmamask = DMA_BIT_MASK(32);
  31. static struct resource exynos4_pdma0_resource[] = {
  32. [0] = {
  33. .start = EXYNOS4_PA_PDMA0,
  34. .end = EXYNOS4_PA_PDMA0 + SZ_4K,
  35. .flags = IORESOURCE_MEM,
  36. },
  37. [1] = {
  38. .start = IRQ_PDMA0,
  39. .end = IRQ_PDMA0,
  40. .flags = IORESOURCE_IRQ,
  41. },
  42. };
  43. static struct s3c_pl330_platdata exynos4_pdma0_pdata = {
  44. .peri = {
  45. [0] = DMACH_PCM0_RX,
  46. [1] = DMACH_PCM0_TX,
  47. [2] = DMACH_PCM2_RX,
  48. [3] = DMACH_PCM2_TX,
  49. [4] = DMACH_MSM_REQ0,
  50. [5] = DMACH_MSM_REQ2,
  51. [6] = DMACH_SPI0_RX,
  52. [7] = DMACH_SPI0_TX,
  53. [8] = DMACH_SPI2_RX,
  54. [9] = DMACH_SPI2_TX,
  55. [10] = DMACH_I2S0S_TX,
  56. [11] = DMACH_I2S0_RX,
  57. [12] = DMACH_I2S0_TX,
  58. [13] = DMACH_I2S2_RX,
  59. [14] = DMACH_I2S2_TX,
  60. [15] = DMACH_UART0_RX,
  61. [16] = DMACH_UART0_TX,
  62. [17] = DMACH_UART2_RX,
  63. [18] = DMACH_UART2_TX,
  64. [19] = DMACH_UART4_RX,
  65. [20] = DMACH_UART4_TX,
  66. [21] = DMACH_SLIMBUS0_RX,
  67. [22] = DMACH_SLIMBUS0_TX,
  68. [23] = DMACH_SLIMBUS2_RX,
  69. [24] = DMACH_SLIMBUS2_TX,
  70. [25] = DMACH_SLIMBUS4_RX,
  71. [26] = DMACH_SLIMBUS4_TX,
  72. [27] = DMACH_AC97_MICIN,
  73. [28] = DMACH_AC97_PCMIN,
  74. [29] = DMACH_AC97_PCMOUT,
  75. [30] = DMACH_MAX,
  76. [31] = DMACH_MAX,
  77. },
  78. };
  79. static struct platform_device exynos4_device_pdma0 = {
  80. .name = "s3c-pl330",
  81. .id = 0,
  82. .num_resources = ARRAY_SIZE(exynos4_pdma0_resource),
  83. .resource = exynos4_pdma0_resource,
  84. .dev = {
  85. .dma_mask = &dma_dmamask,
  86. .coherent_dma_mask = DMA_BIT_MASK(32),
  87. .platform_data = &exynos4_pdma0_pdata,
  88. },
  89. };
  90. static struct resource exynos4_pdma1_resource[] = {
  91. [0] = {
  92. .start = EXYNOS4_PA_PDMA1,
  93. .end = EXYNOS4_PA_PDMA1 + SZ_4K,
  94. .flags = IORESOURCE_MEM,
  95. },
  96. [1] = {
  97. .start = IRQ_PDMA1,
  98. .end = IRQ_PDMA1,
  99. .flags = IORESOURCE_IRQ,
  100. },
  101. };
  102. static struct s3c_pl330_platdata exynos4_pdma1_pdata = {
  103. .peri = {
  104. [0] = DMACH_PCM0_RX,
  105. [1] = DMACH_PCM0_TX,
  106. [2] = DMACH_PCM1_RX,
  107. [3] = DMACH_PCM1_TX,
  108. [4] = DMACH_MSM_REQ1,
  109. [5] = DMACH_MSM_REQ3,
  110. [6] = DMACH_SPI1_RX,
  111. [7] = DMACH_SPI1_TX,
  112. [8] = DMACH_I2S0S_TX,
  113. [9] = DMACH_I2S0_RX,
  114. [10] = DMACH_I2S0_TX,
  115. [11] = DMACH_I2S1_RX,
  116. [12] = DMACH_I2S1_TX,
  117. [13] = DMACH_UART0_RX,
  118. [14] = DMACH_UART0_TX,
  119. [15] = DMACH_UART1_RX,
  120. [16] = DMACH_UART1_TX,
  121. [17] = DMACH_UART3_RX,
  122. [18] = DMACH_UART3_TX,
  123. [19] = DMACH_SLIMBUS1_RX,
  124. [20] = DMACH_SLIMBUS1_TX,
  125. [21] = DMACH_SLIMBUS3_RX,
  126. [22] = DMACH_SLIMBUS3_TX,
  127. [23] = DMACH_SLIMBUS5_RX,
  128. [24] = DMACH_SLIMBUS5_TX,
  129. [25] = DMACH_SLIMBUS0AUX_RX,
  130. [26] = DMACH_SLIMBUS0AUX_TX,
  131. [27] = DMACH_SPDIF,
  132. [28] = DMACH_MAX,
  133. [29] = DMACH_MAX,
  134. [30] = DMACH_MAX,
  135. [31] = DMACH_MAX,
  136. },
  137. };
  138. static struct platform_device exynos4_device_pdma1 = {
  139. .name = "s3c-pl330",
  140. .id = 1,
  141. .num_resources = ARRAY_SIZE(exynos4_pdma1_resource),
  142. .resource = exynos4_pdma1_resource,
  143. .dev = {
  144. .dma_mask = &dma_dmamask,
  145. .coherent_dma_mask = DMA_BIT_MASK(32),
  146. .platform_data = &exynos4_pdma1_pdata,
  147. },
  148. };
  149. static struct platform_device *exynos4_dmacs[] __initdata = {
  150. &exynos4_device_pdma0,
  151. &exynos4_device_pdma1,
  152. };
  153. static int __init exynos4_dma_init(void)
  154. {
  155. platform_add_devices(exynos4_dmacs, ARRAY_SIZE(exynos4_dmacs));
  156. return 0;
  157. }
  158. arch_initcall(exynos4_dma_init);