entry_64.txt 3.7 KB

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  1. This file documents some of the kernel entries in
  2. arch/x86/kernel/entry_64.S. A lot of this explanation is adapted from
  3. an email from Ingo Molnar:
  4. http://lkml.kernel.org/r/<20110529191055.GC9835%40elte.hu>
  5. The x86 architecture has quite a few different ways to jump into
  6. kernel code. Most of these entry points are registered in
  7. arch/x86/kernel/traps.c and implemented in arch/x86/kernel/entry_64.S
  8. and arch/x86/ia32/ia32entry.S.
  9. The IDT vector assignments are listed in arch/x86/include/irq_vectors.h.
  10. Some of these entries are:
  11. - system_call: syscall instruction from 64-bit code.
  12. - ia32_syscall: int 0x80 from 32-bit or 64-bit code; compat syscall
  13. either way.
  14. - ia32_syscall, ia32_sysenter: syscall and sysenter from 32-bit
  15. code
  16. - interrupt: An array of entries. Every IDT vector that doesn't
  17. explicitly point somewhere else gets set to the corresponding
  18. value in interrupts. These point to a whole array of
  19. magically-generated functions that make their way to do_IRQ with
  20. the interrupt number as a parameter.
  21. - emulate_vsyscall: int 0xcc, a special non-ABI entry used by
  22. vsyscall emulation.
  23. - APIC interrupts: Various special-purpose interrupts for things
  24. like TLB shootdown.
  25. - Architecturally-defined exceptions like divide_error.
  26. There are a few complexities here. The different x86-64 entries
  27. have different calling conventions. The syscall and sysenter
  28. instructions have their own peculiar calling conventions. Some of
  29. the IDT entries push an error code onto the stack; others don't.
  30. IDT entries using the IST alternative stack mechanism need their own
  31. magic to get the stack frames right. (You can find some
  32. documentation in the AMD APM, Volume 2, Chapter 8 and the Intel SDM,
  33. Volume 3, Chapter 6.)
  34. Dealing with the swapgs instruction is especially tricky. Swapgs
  35. toggles whether gs is the kernel gs or the user gs. The swapgs
  36. instruction is rather fragile: it must nest perfectly and only in
  37. single depth, it should only be used if entering from user mode to
  38. kernel mode and then when returning to user-space, and precisely
  39. so. If we mess that up even slightly, we crash.
  40. So when we have a secondary entry, already in kernel mode, we *must
  41. not* use SWAPGS blindly - nor must we forget doing a SWAPGS when it's
  42. not switched/swapped yet.
  43. Now, there's a secondary complication: there's a cheap way to test
  44. which mode the CPU is in and an expensive way.
  45. The cheap way is to pick this info off the entry frame on the kernel
  46. stack, from the CS of the ptregs area of the kernel stack:
  47. xorl %ebx,%ebx
  48. testl $3,CS+8(%rsp)
  49. je error_kernelspace
  50. SWAPGS
  51. The expensive (paranoid) way is to read back the MSR_GS_BASE value
  52. (which is what SWAPGS modifies):
  53. movl $1,%ebx
  54. movl $MSR_GS_BASE,%ecx
  55. rdmsr
  56. testl %edx,%edx
  57. js 1f /* negative -> in kernel */
  58. SWAPGS
  59. xorl %ebx,%ebx
  60. 1: ret
  61. and the whole paranoid non-paranoid macro complexity is about whether
  62. to suffer that RDMSR cost.
  63. If we are at an interrupt or user-trap/gate-alike boundary then we can
  64. use the faster check: the stack will be a reliable indicator of
  65. whether SWAPGS was already done: if we see that we are a secondary
  66. entry interrupting kernel mode execution, then we know that the GS
  67. base has already been switched. If it says that we interrupted
  68. user-space execution then we must do the SWAPGS.
  69. But if we are in an NMI/MCE/DEBUG/whatever super-atomic entry context,
  70. which might have triggered right after a normal entry wrote CS to the
  71. stack but before we executed SWAPGS, then the only safe way to check
  72. for GS is the slower method: the RDMSR.
  73. So we try only to mark those entry methods 'paranoid' that absolutely
  74. need the more expensive check for the GS base - and we generate all
  75. 'normal' entry points with the regular (faster) entry macros.